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r600g: remove the workaround for quads and provoking vertex
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_blitter.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38 #include "util/u_surface.h"
39 #include "util/u_pack_color.h"
40 #include "util/u_memory.h"
41 #include "util/u_inlines.h"
42 #include "util/u_framebuffer.h"
43 #include "pipebuffer/pb_buffer.h"
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t eg_num_banks(uint32_t nbanks)
52 {
53 switch (nbanks) {
54 case 2:
55 return 0;
56 case 4:
57 return 1;
58 case 8:
59 default:
60 return 2;
61 case 16:
62 return 3;
63 }
64 }
65
66
67 static unsigned eg_tile_split(unsigned tile_split)
68 {
69 switch (tile_split) {
70 case 64: tile_split = 0; break;
71 case 128: tile_split = 1; break;
72 case 256: tile_split = 2; break;
73 case 512: tile_split = 3; break;
74 default:
75 case 1024: tile_split = 4; break;
76 case 2048: tile_split = 5; break;
77 case 4096: tile_split = 6; break;
78 }
79 return tile_split;
80 }
81
82 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
83 {
84 switch (macro_tile_aspect) {
85 default:
86 case 1: macro_tile_aspect = 0; break;
87 case 2: macro_tile_aspect = 1; break;
88 case 4: macro_tile_aspect = 2; break;
89 case 8: macro_tile_aspect = 3; break;
90 }
91 return macro_tile_aspect;
92 }
93
94 static unsigned eg_bank_wh(unsigned bankwh)
95 {
96 switch (bankwh) {
97 default:
98 case 1: bankwh = 0; break;
99 case 2: bankwh = 1; break;
100 case 4: bankwh = 2; break;
101 case 8: bankwh = 3; break;
102 }
103 return bankwh;
104 }
105
106 static uint32_t r600_translate_blend_function(int blend_func)
107 {
108 switch (blend_func) {
109 case PIPE_BLEND_ADD:
110 return V_028780_COMB_DST_PLUS_SRC;
111 case PIPE_BLEND_SUBTRACT:
112 return V_028780_COMB_SRC_MINUS_DST;
113 case PIPE_BLEND_REVERSE_SUBTRACT:
114 return V_028780_COMB_DST_MINUS_SRC;
115 case PIPE_BLEND_MIN:
116 return V_028780_COMB_MIN_DST_SRC;
117 case PIPE_BLEND_MAX:
118 return V_028780_COMB_MAX_DST_SRC;
119 default:
120 R600_ERR("Unknown blend function %d\n", blend_func);
121 assert(0);
122 break;
123 }
124 return 0;
125 }
126
127 static uint32_t r600_translate_blend_factor(int blend_fact)
128 {
129 switch (blend_fact) {
130 case PIPE_BLENDFACTOR_ONE:
131 return V_028780_BLEND_ONE;
132 case PIPE_BLENDFACTOR_SRC_COLOR:
133 return V_028780_BLEND_SRC_COLOR;
134 case PIPE_BLENDFACTOR_SRC_ALPHA:
135 return V_028780_BLEND_SRC_ALPHA;
136 case PIPE_BLENDFACTOR_DST_ALPHA:
137 return V_028780_BLEND_DST_ALPHA;
138 case PIPE_BLENDFACTOR_DST_COLOR:
139 return V_028780_BLEND_DST_COLOR;
140 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
141 return V_028780_BLEND_SRC_ALPHA_SATURATE;
142 case PIPE_BLENDFACTOR_CONST_COLOR:
143 return V_028780_BLEND_CONST_COLOR;
144 case PIPE_BLENDFACTOR_CONST_ALPHA:
145 return V_028780_BLEND_CONST_ALPHA;
146 case PIPE_BLENDFACTOR_ZERO:
147 return V_028780_BLEND_ZERO;
148 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
149 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
150 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
151 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
152 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
153 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
154 case PIPE_BLENDFACTOR_INV_DST_COLOR:
155 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
156 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
157 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
158 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
159 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
160 case PIPE_BLENDFACTOR_SRC1_COLOR:
161 return V_028780_BLEND_SRC1_COLOR;
162 case PIPE_BLENDFACTOR_SRC1_ALPHA:
163 return V_028780_BLEND_SRC1_ALPHA;
164 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
165 return V_028780_BLEND_INV_SRC1_COLOR;
166 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
167 return V_028780_BLEND_INV_SRC1_ALPHA;
168 default:
169 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
170 assert(0);
171 break;
172 }
173 return 0;
174 }
175
176 static unsigned r600_tex_dim(unsigned dim)
177 {
178 switch (dim) {
179 default:
180 case PIPE_TEXTURE_1D:
181 return V_030000_SQ_TEX_DIM_1D;
182 case PIPE_TEXTURE_1D_ARRAY:
183 return V_030000_SQ_TEX_DIM_1D_ARRAY;
184 case PIPE_TEXTURE_2D:
185 case PIPE_TEXTURE_RECT:
186 return V_030000_SQ_TEX_DIM_2D;
187 case PIPE_TEXTURE_2D_ARRAY:
188 return V_030000_SQ_TEX_DIM_2D_ARRAY;
189 case PIPE_TEXTURE_3D:
190 return V_030000_SQ_TEX_DIM_3D;
191 case PIPE_TEXTURE_CUBE:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 return V_028040_Z_24;
204 case PIPE_FORMAT_Z32_FLOAT:
205 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
206 return V_028040_Z_32_FLOAT;
207 default:
208 return ~0U;
209 }
210 }
211
212 static uint32_t r600_translate_colorswap(enum pipe_format format)
213 {
214 switch (format) {
215 /* 8-bit buffers. */
216 case PIPE_FORMAT_L4A4_UNORM:
217 case PIPE_FORMAT_A4R4_UNORM:
218 return V_028C70_SWAP_ALT;
219
220 case PIPE_FORMAT_A8_UNORM:
221 case PIPE_FORMAT_A8_UINT:
222 case PIPE_FORMAT_A8_SINT:
223 case PIPE_FORMAT_R4A4_UNORM:
224 return V_028C70_SWAP_ALT_REV;
225 case PIPE_FORMAT_I8_UNORM:
226 case PIPE_FORMAT_L8_UNORM:
227 case PIPE_FORMAT_I8_UINT:
228 case PIPE_FORMAT_I8_SINT:
229 case PIPE_FORMAT_L8_UINT:
230 case PIPE_FORMAT_L8_SINT:
231 case PIPE_FORMAT_L8_SRGB:
232 case PIPE_FORMAT_R8_UNORM:
233 case PIPE_FORMAT_R8_SNORM:
234 case PIPE_FORMAT_R8_UINT:
235 case PIPE_FORMAT_R8_SINT:
236 return V_028C70_SWAP_STD;
237
238 /* 16-bit buffers. */
239 case PIPE_FORMAT_B5G6R5_UNORM:
240 return V_028C70_SWAP_STD_REV;
241
242 case PIPE_FORMAT_B5G5R5A1_UNORM:
243 case PIPE_FORMAT_B5G5R5X1_UNORM:
244 return V_028C70_SWAP_ALT;
245
246 case PIPE_FORMAT_B4G4R4A4_UNORM:
247 case PIPE_FORMAT_B4G4R4X4_UNORM:
248 return V_028C70_SWAP_ALT;
249
250 case PIPE_FORMAT_Z16_UNORM:
251 return V_028C70_SWAP_STD;
252
253 case PIPE_FORMAT_L8A8_UNORM:
254 case PIPE_FORMAT_L8A8_UINT:
255 case PIPE_FORMAT_L8A8_SINT:
256 case PIPE_FORMAT_L8A8_SRGB:
257 return V_028C70_SWAP_ALT;
258 case PIPE_FORMAT_R8G8_UNORM:
259 case PIPE_FORMAT_R8G8_UINT:
260 case PIPE_FORMAT_R8G8_SINT:
261 return V_028C70_SWAP_STD;
262
263 case PIPE_FORMAT_R16_UNORM:
264 case PIPE_FORMAT_R16_UINT:
265 case PIPE_FORMAT_R16_SINT:
266 case PIPE_FORMAT_R16_FLOAT:
267 return V_028C70_SWAP_STD;
268
269 /* 32-bit buffers. */
270 case PIPE_FORMAT_A8B8G8R8_SRGB:
271 return V_028C70_SWAP_STD_REV;
272 case PIPE_FORMAT_B8G8R8A8_SRGB:
273 return V_028C70_SWAP_ALT;
274
275 case PIPE_FORMAT_B8G8R8A8_UNORM:
276 case PIPE_FORMAT_B8G8R8X8_UNORM:
277 return V_028C70_SWAP_ALT;
278
279 case PIPE_FORMAT_A8R8G8B8_UNORM:
280 case PIPE_FORMAT_X8R8G8B8_UNORM:
281 return V_028C70_SWAP_ALT_REV;
282 case PIPE_FORMAT_R8G8B8A8_SNORM:
283 case PIPE_FORMAT_R8G8B8A8_UNORM:
284 case PIPE_FORMAT_R8G8B8A8_SSCALED:
285 case PIPE_FORMAT_R8G8B8A8_USCALED:
286 case PIPE_FORMAT_R8G8B8A8_SINT:
287 case PIPE_FORMAT_R8G8B8A8_UINT:
288 case PIPE_FORMAT_R8G8B8X8_UNORM:
289 return V_028C70_SWAP_STD;
290
291 case PIPE_FORMAT_A8B8G8R8_UNORM:
292 case PIPE_FORMAT_X8B8G8R8_UNORM:
293 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
294 return V_028C70_SWAP_STD_REV;
295
296 case PIPE_FORMAT_Z24X8_UNORM:
297 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
298 return V_028C70_SWAP_STD;
299
300 case PIPE_FORMAT_X8Z24_UNORM:
301 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
302 return V_028C70_SWAP_STD;
303
304 case PIPE_FORMAT_R10G10B10A2_UNORM:
305 case PIPE_FORMAT_R10G10B10X2_SNORM:
306 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
307 return V_028C70_SWAP_STD;
308
309 case PIPE_FORMAT_B10G10R10A2_UNORM:
310 case PIPE_FORMAT_B10G10R10A2_UINT:
311 return V_028C70_SWAP_ALT;
312
313 case PIPE_FORMAT_R11G11B10_FLOAT:
314 case PIPE_FORMAT_R32_FLOAT:
315 case PIPE_FORMAT_R32_UINT:
316 case PIPE_FORMAT_R32_SINT:
317 case PIPE_FORMAT_Z32_FLOAT:
318 case PIPE_FORMAT_R16G16_FLOAT:
319 case PIPE_FORMAT_R16G16_UNORM:
320 case PIPE_FORMAT_R16G16_UINT:
321 case PIPE_FORMAT_R16G16_SINT:
322 return V_028C70_SWAP_STD;
323
324 /* 64-bit buffers. */
325 case PIPE_FORMAT_R32G32_FLOAT:
326 case PIPE_FORMAT_R32G32_UINT:
327 case PIPE_FORMAT_R32G32_SINT:
328 case PIPE_FORMAT_R16G16B16A16_UNORM:
329 case PIPE_FORMAT_R16G16B16A16_SNORM:
330 case PIPE_FORMAT_R16G16B16A16_USCALED:
331 case PIPE_FORMAT_R16G16B16A16_SSCALED:
332 case PIPE_FORMAT_R16G16B16A16_UINT:
333 case PIPE_FORMAT_R16G16B16A16_SINT:
334 case PIPE_FORMAT_R16G16B16A16_FLOAT:
335 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
336
337 /* 128-bit buffers. */
338 case PIPE_FORMAT_R32G32B32A32_FLOAT:
339 case PIPE_FORMAT_R32G32B32A32_SNORM:
340 case PIPE_FORMAT_R32G32B32A32_UNORM:
341 case PIPE_FORMAT_R32G32B32A32_SSCALED:
342 case PIPE_FORMAT_R32G32B32A32_USCALED:
343 case PIPE_FORMAT_R32G32B32A32_SINT:
344 case PIPE_FORMAT_R32G32B32A32_UINT:
345 return V_028C70_SWAP_STD;
346 default:
347 R600_ERR("unsupported colorswap format %d\n", format);
348 return ~0U;
349 }
350 return ~0U;
351 }
352
353 static uint32_t r600_translate_colorformat(enum pipe_format format)
354 {
355 switch (format) {
356 /* 8-bit buffers. */
357 case PIPE_FORMAT_A8_UNORM:
358 case PIPE_FORMAT_A8_UINT:
359 case PIPE_FORMAT_A8_SINT:
360 case PIPE_FORMAT_I8_UNORM:
361 case PIPE_FORMAT_I8_UINT:
362 case PIPE_FORMAT_I8_SINT:
363 case PIPE_FORMAT_L8_UNORM:
364 case PIPE_FORMAT_L8_UINT:
365 case PIPE_FORMAT_L8_SINT:
366 case PIPE_FORMAT_L8_SRGB:
367 case PIPE_FORMAT_R8_UNORM:
368 case PIPE_FORMAT_R8_SNORM:
369 case PIPE_FORMAT_R8_UINT:
370 case PIPE_FORMAT_R8_SINT:
371 return V_028C70_COLOR_8;
372
373 /* 16-bit buffers. */
374 case PIPE_FORMAT_B5G6R5_UNORM:
375 return V_028C70_COLOR_5_6_5;
376
377 case PIPE_FORMAT_B5G5R5A1_UNORM:
378 case PIPE_FORMAT_B5G5R5X1_UNORM:
379 return V_028C70_COLOR_1_5_5_5;
380
381 case PIPE_FORMAT_B4G4R4A4_UNORM:
382 case PIPE_FORMAT_B4G4R4X4_UNORM:
383 return V_028C70_COLOR_4_4_4_4;
384
385 case PIPE_FORMAT_Z16_UNORM:
386 return V_028C70_COLOR_16;
387
388 case PIPE_FORMAT_L8A8_UNORM:
389 case PIPE_FORMAT_L8A8_UINT:
390 case PIPE_FORMAT_L8A8_SINT:
391 case PIPE_FORMAT_L8A8_SRGB:
392 case PIPE_FORMAT_R8G8_UNORM:
393 case PIPE_FORMAT_R8G8_UINT:
394 case PIPE_FORMAT_R8G8_SINT:
395 return V_028C70_COLOR_8_8;
396
397 case PIPE_FORMAT_R16_UNORM:
398 case PIPE_FORMAT_R16_UINT:
399 case PIPE_FORMAT_R16_SINT:
400 return V_028C70_COLOR_16;
401
402 case PIPE_FORMAT_R16_FLOAT:
403 return V_028C70_COLOR_16_FLOAT;
404
405 /* 32-bit buffers. */
406 case PIPE_FORMAT_A8B8G8R8_SRGB:
407 case PIPE_FORMAT_A8B8G8R8_UNORM:
408 case PIPE_FORMAT_A8R8G8B8_UNORM:
409 case PIPE_FORMAT_B8G8R8A8_SRGB:
410 case PIPE_FORMAT_B8G8R8A8_UNORM:
411 case PIPE_FORMAT_B8G8R8X8_UNORM:
412 case PIPE_FORMAT_R8G8B8A8_SNORM:
413 case PIPE_FORMAT_R8G8B8A8_UNORM:
414 case PIPE_FORMAT_R8G8B8X8_UNORM:
415 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
416 case PIPE_FORMAT_X8B8G8R8_UNORM:
417 case PIPE_FORMAT_X8R8G8B8_UNORM:
418 case PIPE_FORMAT_R8G8B8_UNORM:
419 case PIPE_FORMAT_R8G8B8A8_SSCALED:
420 case PIPE_FORMAT_R8G8B8A8_USCALED:
421 case PIPE_FORMAT_R8G8B8A8_SINT:
422 case PIPE_FORMAT_R8G8B8A8_UINT:
423 return V_028C70_COLOR_8_8_8_8;
424
425 case PIPE_FORMAT_R10G10B10A2_UNORM:
426 case PIPE_FORMAT_R10G10B10X2_SNORM:
427 case PIPE_FORMAT_B10G10R10A2_UNORM:
428 case PIPE_FORMAT_B10G10R10A2_UINT:
429 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
430 return V_028C70_COLOR_2_10_10_10;
431
432 case PIPE_FORMAT_Z24X8_UNORM:
433 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
434 return V_028C70_COLOR_8_24;
435
436 case PIPE_FORMAT_X8Z24_UNORM:
437 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
438 return V_028C70_COLOR_24_8;
439
440 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
441 return V_028C70_COLOR_X24_8_32_FLOAT;
442
443 case PIPE_FORMAT_R32_UINT:
444 case PIPE_FORMAT_R32_SINT:
445 return V_028C70_COLOR_32;
446
447 case PIPE_FORMAT_R32_FLOAT:
448 case PIPE_FORMAT_Z32_FLOAT:
449 return V_028C70_COLOR_32_FLOAT;
450
451 case PIPE_FORMAT_R16G16_FLOAT:
452 return V_028C70_COLOR_16_16_FLOAT;
453
454 case PIPE_FORMAT_R16G16_SSCALED:
455 case PIPE_FORMAT_R16G16_UNORM:
456 case PIPE_FORMAT_R16G16_UINT:
457 case PIPE_FORMAT_R16G16_SINT:
458 return V_028C70_COLOR_16_16;
459
460 case PIPE_FORMAT_R11G11B10_FLOAT:
461 return V_028C70_COLOR_10_11_11_FLOAT;
462
463 /* 64-bit buffers. */
464 case PIPE_FORMAT_R16G16B16_USCALED:
465 case PIPE_FORMAT_R16G16B16_SSCALED:
466 case PIPE_FORMAT_R16G16B16A16_UINT:
467 case PIPE_FORMAT_R16G16B16A16_SINT:
468 case PIPE_FORMAT_R16G16B16A16_USCALED:
469 case PIPE_FORMAT_R16G16B16A16_SSCALED:
470 case PIPE_FORMAT_R16G16B16A16_UNORM:
471 case PIPE_FORMAT_R16G16B16A16_SNORM:
472 return V_028C70_COLOR_16_16_16_16;
473
474 case PIPE_FORMAT_R16G16B16_FLOAT:
475 case PIPE_FORMAT_R16G16B16A16_FLOAT:
476 return V_028C70_COLOR_16_16_16_16_FLOAT;
477
478 case PIPE_FORMAT_R32G32_FLOAT:
479 return V_028C70_COLOR_32_32_FLOAT;
480
481 case PIPE_FORMAT_R32G32_USCALED:
482 case PIPE_FORMAT_R32G32_SSCALED:
483 case PIPE_FORMAT_R32G32_SINT:
484 case PIPE_FORMAT_R32G32_UINT:
485 return V_028C70_COLOR_32_32;
486
487 /* 96-bit buffers. */
488 case PIPE_FORMAT_R32G32B32_FLOAT:
489 return V_028C70_COLOR_32_32_32_FLOAT;
490
491 /* 128-bit buffers. */
492 case PIPE_FORMAT_R32G32B32A32_SNORM:
493 case PIPE_FORMAT_R32G32B32A32_UNORM:
494 case PIPE_FORMAT_R32G32B32A32_SSCALED:
495 case PIPE_FORMAT_R32G32B32A32_USCALED:
496 case PIPE_FORMAT_R32G32B32A32_SINT:
497 case PIPE_FORMAT_R32G32B32A32_UINT:
498 return V_028C70_COLOR_32_32_32_32;
499 case PIPE_FORMAT_R32G32B32A32_FLOAT:
500 return V_028C70_COLOR_32_32_32_32_FLOAT;
501
502 /* YUV buffers. */
503 case PIPE_FORMAT_UYVY:
504 case PIPE_FORMAT_YUYV:
505 default:
506 return ~0U; /* Unsupported. */
507 }
508 }
509
510 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
511 {
512 if (R600_BIG_ENDIAN) {
513 switch(colorformat) {
514
515 /* 8-bit buffers. */
516 case V_028C70_COLOR_8:
517 return ENDIAN_NONE;
518
519 /* 16-bit buffers. */
520 case V_028C70_COLOR_5_6_5:
521 case V_028C70_COLOR_1_5_5_5:
522 case V_028C70_COLOR_4_4_4_4:
523 case V_028C70_COLOR_16:
524 case V_028C70_COLOR_8_8:
525 return ENDIAN_8IN16;
526
527 /* 32-bit buffers. */
528 case V_028C70_COLOR_8_8_8_8:
529 case V_028C70_COLOR_2_10_10_10:
530 case V_028C70_COLOR_8_24:
531 case V_028C70_COLOR_24_8:
532 case V_028C70_COLOR_32_FLOAT:
533 case V_028C70_COLOR_16_16_FLOAT:
534 case V_028C70_COLOR_16_16:
535 return ENDIAN_8IN32;
536
537 /* 64-bit buffers. */
538 case V_028C70_COLOR_16_16_16_16:
539 case V_028C70_COLOR_16_16_16_16_FLOAT:
540 return ENDIAN_8IN16;
541
542 case V_028C70_COLOR_32_32_FLOAT:
543 case V_028C70_COLOR_32_32:
544 case V_028C70_COLOR_X24_8_32_FLOAT:
545 return ENDIAN_8IN32;
546
547 /* 96-bit buffers. */
548 case V_028C70_COLOR_32_32_32_FLOAT:
549 /* 128-bit buffers. */
550 case V_028C70_COLOR_32_32_32_32_FLOAT:
551 case V_028C70_COLOR_32_32_32_32:
552 return ENDIAN_8IN32;
553 default:
554 return ENDIAN_NONE; /* Unsupported. */
555 }
556 } else {
557 return ENDIAN_NONE;
558 }
559 }
560
561 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
562 {
563 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
564 }
565
566 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
567 {
568 return r600_translate_colorformat(format) != ~0U &&
569 r600_translate_colorswap(format) != ~0U;
570 }
571
572 static bool r600_is_zs_format_supported(enum pipe_format format)
573 {
574 return r600_translate_dbformat(format) != ~0U;
575 }
576
577 boolean evergreen_is_format_supported(struct pipe_screen *screen,
578 enum pipe_format format,
579 enum pipe_texture_target target,
580 unsigned sample_count,
581 unsigned usage)
582 {
583 unsigned retval = 0;
584
585 if (target >= PIPE_MAX_TEXTURE_TYPES) {
586 R600_ERR("r600: unsupported texture type %d\n", target);
587 return FALSE;
588 }
589
590 if (!util_format_is_supported(format, usage))
591 return FALSE;
592
593 /* Multisample */
594 if (sample_count > 1)
595 return FALSE;
596
597 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
598 r600_is_sampler_format_supported(screen, format)) {
599 retval |= PIPE_BIND_SAMPLER_VIEW;
600 }
601
602 if ((usage & (PIPE_BIND_RENDER_TARGET |
603 PIPE_BIND_DISPLAY_TARGET |
604 PIPE_BIND_SCANOUT |
605 PIPE_BIND_SHARED)) &&
606 r600_is_colorbuffer_format_supported(format)) {
607 retval |= usage &
608 (PIPE_BIND_RENDER_TARGET |
609 PIPE_BIND_DISPLAY_TARGET |
610 PIPE_BIND_SCANOUT |
611 PIPE_BIND_SHARED);
612 }
613
614 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
615 r600_is_zs_format_supported(format)) {
616 retval |= PIPE_BIND_DEPTH_STENCIL;
617 }
618
619 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
620 r600_is_vertex_format_supported(format)) {
621 retval |= PIPE_BIND_VERTEX_BUFFER;
622 }
623
624 if (usage & PIPE_BIND_TRANSFER_READ)
625 retval |= PIPE_BIND_TRANSFER_READ;
626 if (usage & PIPE_BIND_TRANSFER_WRITE)
627 retval |= PIPE_BIND_TRANSFER_WRITE;
628
629 return retval == usage;
630 }
631
632 static void *evergreen_create_blend_state(struct pipe_context *ctx,
633 const struct pipe_blend_state *state)
634 {
635 struct r600_context *rctx = (struct r600_context *)ctx;
636 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
637 struct r600_pipe_state *rstate;
638 uint32_t color_control, target_mask;
639 /* FIXME there is more then 8 framebuffer */
640 unsigned blend_cntl[8];
641
642 if (blend == NULL) {
643 return NULL;
644 }
645
646 rstate = &blend->rstate;
647
648 rstate->id = R600_PIPE_STATE_BLEND;
649
650 target_mask = 0;
651 color_control = S_028808_MODE(1);
652 if (state->logicop_enable) {
653 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
654 } else {
655 color_control |= (0xcc << 16);
656 }
657 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
658 if (state->independent_blend_enable) {
659 for (int i = 0; i < 8; i++) {
660 target_mask |= (state->rt[i].colormask << (4 * i));
661 }
662 } else {
663 for (int i = 0; i < 8; i++) {
664 target_mask |= (state->rt[0].colormask << (4 * i));
665 }
666 }
667 blend->cb_target_mask = target_mask;
668
669 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
670 color_control, NULL, 0);
671
672 if (rctx->chip_class != CAYMAN)
673 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, ~0, NULL, 0);
674 else {
675 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0);
676 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0);
677 }
678
679 for (int i = 0; i < 8; i++) {
680 /* state->rt entries > 0 only written if independent blending */
681 const int j = state->independent_blend_enable ? i : 0;
682
683 unsigned eqRGB = state->rt[j].rgb_func;
684 unsigned srcRGB = state->rt[j].rgb_src_factor;
685 unsigned dstRGB = state->rt[j].rgb_dst_factor;
686 unsigned eqA = state->rt[j].alpha_func;
687 unsigned srcA = state->rt[j].alpha_src_factor;
688 unsigned dstA = state->rt[j].alpha_dst_factor;
689
690 blend_cntl[i] = 0;
691 if (!state->rt[j].blend_enable)
692 continue;
693
694 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
695 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
696 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
697 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
698
699 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
700 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
701 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
702 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
703 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
704 }
705 }
706 for (int i = 0; i < 8; i++) {
707 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
708 }
709
710 return rstate;
711 }
712
713 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
714 const struct pipe_depth_stencil_alpha_state *state)
715 {
716 struct r600_context *rctx = (struct r600_context *)ctx;
717 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
718 unsigned db_depth_control, alpha_test_control, alpha_ref;
719 unsigned db_render_override, db_render_control;
720 struct r600_pipe_state *rstate;
721
722 if (dsa == NULL) {
723 return NULL;
724 }
725
726 dsa->valuemask[0] = state->stencil[0].valuemask;
727 dsa->valuemask[1] = state->stencil[1].valuemask;
728 dsa->writemask[0] = state->stencil[0].writemask;
729 dsa->writemask[1] = state->stencil[1].writemask;
730
731 rstate = &dsa->rstate;
732
733 rstate->id = R600_PIPE_STATE_DSA;
734 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
735 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
736 S_028800_ZFUNC(state->depth.func);
737
738 /* stencil */
739 if (state->stencil[0].enabled) {
740 db_depth_control |= S_028800_STENCIL_ENABLE(1);
741 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
742 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
743 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
744 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
745
746 if (state->stencil[1].enabled) {
747 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
748 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
749 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
750 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
751 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
752 }
753 }
754
755 /* alpha */
756 alpha_test_control = 0;
757 alpha_ref = 0;
758 if (state->alpha.enabled) {
759 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
760 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
761 alpha_ref = fui(state->alpha.ref_value);
762 }
763 dsa->alpha_ref = alpha_ref;
764
765 /* misc */
766 db_render_control = 0;
767 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
768 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
769 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
770 /* TODO db_render_override depends on query */
771 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
772 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
773 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
774 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
775 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
776 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
777 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
778 * evergreen_pipe_shader_ps().*/
779 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
780 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
781 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
782 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
783 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
784 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
785 dsa->db_render_override = db_render_override;
786
787 return rstate;
788 }
789
790 static void *evergreen_create_rs_state(struct pipe_context *ctx,
791 const struct pipe_rasterizer_state *state)
792 {
793 struct r600_context *rctx = (struct r600_context *)ctx;
794 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
795 struct r600_pipe_state *rstate;
796 unsigned tmp;
797 unsigned prov_vtx = 1, polygon_dual_mode;
798 unsigned clip_rule;
799 float psize_min, psize_max;
800
801 if (rs == NULL) {
802 return NULL;
803 }
804
805 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
806 state->fill_back != PIPE_POLYGON_MODE_FILL);
807
808 if (state->flatshade_first)
809 prov_vtx = 0;
810
811 rstate = &rs->rstate;
812 rs->flatshade = state->flatshade;
813 rs->sprite_coord_enable = state->sprite_coord_enable;
814 rs->two_side = state->light_twoside;
815 rs->clip_plane_enable = state->clip_plane_enable;
816 rs->pa_sc_line_stipple = state->line_stipple_enable ?
817 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
818 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
819 rs->pa_cl_clip_cntl =
820 S_028810_PS_UCP_MODE(3) |
821 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
822 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
823 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
824
825 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
826
827 /* offset */
828 rs->offset_units = state->offset_units;
829 rs->offset_scale = state->offset_scale * 12.0f;
830
831 rstate->id = R600_PIPE_STATE_RASTERIZER;
832 tmp = S_0286D4_FLAT_SHADE_ENA(1);
833 if (state->sprite_coord_enable) {
834 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
835 S_0286D4_PNT_SPRITE_OVRD_X(2) |
836 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
837 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
838 S_0286D4_PNT_SPRITE_OVRD_W(1);
839 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
840 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
841 }
842 }
843 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
844
845 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
846 /* point size 12.4 fixed point */
847 tmp = (unsigned)(state->point_size * 8.0);
848 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
849
850 if (state->point_size_per_vertex) {
851 psize_min = util_get_min_point_size(state);
852 psize_max = 8192;
853 } else {
854 /* Force the point size to be as if the vertex output was disabled. */
855 psize_min = state->point_size;
856 psize_max = state->point_size;
857 }
858 /* Divide by two, because 0.5 = 1 pixel. */
859 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
860 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
861 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
862 NULL, 0);
863
864 tmp = (unsigned)state->line_width * 8;
865 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
866 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
867 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
868 NULL, 0);
869
870 if (rctx->chip_class == CAYMAN) {
871 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
872 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
873 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
874 NULL, 0);
875 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
876 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
877 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
878 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
879
880
881 } else {
882 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
883
884 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
885 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
886 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
887 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
888
889 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
890 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
891 NULL, 0);
892 }
893 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
894 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
895 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
896 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
897 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
898 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
899 S_028814_FACE(!state->front_ccw) |
900 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
901 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
902 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
903 S_028814_POLY_MODE(polygon_dual_mode) |
904 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
905 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
906 NULL, 0);
907 return rstate;
908 }
909
910 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
911 const struct pipe_sampler_state *state)
912 {
913 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
914 union util_color uc;
915 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
916
917 if (rstate == NULL) {
918 return NULL;
919 }
920
921 rstate->id = R600_PIPE_STATE_SAMPLER;
922 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
923 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
924 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
925 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
926 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
927 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
928 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
929 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
930 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
931 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
932 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
933 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
934 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
935 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
936 NULL, 0);
937 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
938 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
939 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
940 S_03C008_TYPE(1),
941 NULL, 0);
942
943 if (uc.ui) {
944 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
945 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
946 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
947 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
948 }
949 return rstate;
950 }
951
952 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
953 struct pipe_resource *texture,
954 const struct pipe_sampler_view *state)
955 {
956 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
957 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
958 struct r600_pipe_resource_state *rstate;
959 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
960 unsigned format, endian;
961 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
962 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
963 unsigned height, depth, width;
964 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
965
966 if (view == NULL)
967 return NULL;
968 rstate = &view->state;
969
970 /* initialize base object */
971 view->base = *state;
972 view->base.texture = NULL;
973 pipe_reference(NULL, &texture->reference);
974 view->base.texture = texture;
975 view->base.reference.count = 1;
976 view->base.context = ctx;
977
978 swizzle[0] = state->swizzle_r;
979 swizzle[1] = state->swizzle_g;
980 swizzle[2] = state->swizzle_b;
981 swizzle[3] = state->swizzle_a;
982
983 format = r600_translate_texformat(ctx->screen, state->format,
984 swizzle,
985 &word4, &yuv_format);
986 if (format == ~0) {
987 format = 0;
988 }
989
990 if (tmp->depth && !tmp->is_flushing_texture) {
991 r600_texture_depth_flush(ctx, texture, TRUE);
992 tmp = tmp->flushed_depth_texture;
993 }
994
995 endian = r600_colorformat_endian_swap(format);
996
997 if (!rscreen->use_surface) {
998 height = texture->height0;
999 depth = texture->depth0;
1000 width = texture->width0;
1001 pitch = align(tmp->pitch_in_blocks[0] *
1002 util_format_get_blockwidth(state->format), 8);
1003 array_mode = tmp->array_mode[0];
1004 tile_type = tmp->tile_type;
1005 tile_split = 0;
1006 macro_aspect = 0;
1007 bankw = 0;
1008 bankh = 0;
1009 } else {
1010 width = tmp->surface.level[0].npix_x;
1011 height = tmp->surface.level[0].npix_y;
1012 depth = tmp->surface.level[0].npix_z;
1013 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1014 tile_type = tmp->tile_type;
1015
1016 switch (tmp->surface.level[0].mode) {
1017 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1018 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1019 break;
1020 case RADEON_SURF_MODE_2D:
1021 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1022 break;
1023 case RADEON_SURF_MODE_1D:
1024 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1025 break;
1026 case RADEON_SURF_MODE_LINEAR:
1027 default:
1028 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1029 break;
1030 }
1031 tile_split = tmp->surface.tile_split;
1032 macro_aspect = tmp->surface.mtilea;
1033 bankw = tmp->surface.bankw;
1034 bankh = tmp->surface.bankh;
1035 tile_split = eg_tile_split(tile_split);
1036 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1037 bankw = eg_bank_wh(bankw);
1038 bankh = eg_bank_wh(bankh);
1039 }
1040 /* 128 bit formats require tile type = 1 */
1041 if (rscreen->chip_class == CAYMAN) {
1042 if (util_format_get_blocksize(state->format) >= 16)
1043 tile_type = 1;
1044 }
1045 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1046
1047 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1048 height = 1;
1049 depth = texture->array_size;
1050 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1051 depth = texture->array_size;
1052 }
1053
1054 rstate->bo[0] = &tmp->resource;
1055 rstate->bo[1] = &tmp->resource;
1056 rstate->bo_usage[0] = RADEON_USAGE_READ;
1057 rstate->bo_usage[1] = RADEON_USAGE_READ;
1058
1059 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1060 S_030000_PITCH((pitch / 8) - 1) |
1061 S_030000_TEX_WIDTH(width - 1));
1062 if (rscreen->chip_class == CAYMAN)
1063 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1064 else
1065 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1066 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1067 S_030004_TEX_DEPTH(depth - 1) |
1068 S_030004_ARRAY_MODE(array_mode));
1069 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1070 if (state->u.tex.last_level) {
1071 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1072 } else {
1073 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1074 }
1075 rstate->val[4] = (word4 |
1076 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1077 S_030010_ENDIAN_SWAP(endian) |
1078 S_030010_BASE_LEVEL(state->u.tex.first_level));
1079 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1080 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1081 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1082 /* aniso max 16 samples */
1083 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1084 (S_030018_TILE_SPLIT(tile_split));
1085 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1086 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1087 S_03001C_BANK_WIDTH(bankw) |
1088 S_03001C_BANK_HEIGHT(bankh) |
1089 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1090 S_03001C_NUM_BANKS(nbanks);
1091
1092 return &view->base;
1093 }
1094
1095 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1096 struct pipe_sampler_view **views)
1097 {
1098 struct r600_context *rctx = (struct r600_context *)ctx;
1099 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1100
1101 for (int i = 0; i < count; i++) {
1102 if (resource[i]) {
1103 evergreen_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1104 i + R600_MAX_CONST_BUFFERS);
1105 }
1106 }
1107 }
1108
1109 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1110 struct pipe_sampler_view **views)
1111 {
1112 struct r600_context *rctx = (struct r600_context *)ctx;
1113 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1114 int i;
1115 int has_depth = 0;
1116
1117 for (i = 0; i < count; i++) {
1118 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1119 if (resource[i]) {
1120 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1121 has_depth = 1;
1122 evergreen_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1123 i + R600_MAX_CONST_BUFFERS);
1124 } else
1125 evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1126 i + R600_MAX_CONST_BUFFERS);
1127
1128 pipe_sampler_view_reference(
1129 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1130 views[i]);
1131 } else {
1132 if (resource[i]) {
1133 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1134 has_depth = 1;
1135 }
1136 }
1137 }
1138 for (i = count; i < NUM_TEX_UNITS; i++) {
1139 if (rctx->ps_samplers.views[i]) {
1140 evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1141 i + R600_MAX_CONST_BUFFERS);
1142 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1143 }
1144 }
1145 rctx->have_depth_texture = has_depth;
1146 rctx->ps_samplers.n_views = count;
1147 }
1148
1149 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1150 {
1151 struct r600_context *rctx = (struct r600_context *)ctx;
1152 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1153
1154 if (count)
1155 r600_inval_texture_cache(rctx);
1156
1157 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1158 rctx->ps_samplers.n_samplers = count;
1159
1160 for (int i = 0; i < count; i++) {
1161 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1162 }
1163 }
1164
1165 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1166 {
1167 struct r600_context *rctx = (struct r600_context *)ctx;
1168 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1169
1170 if (count)
1171 r600_inval_texture_cache(rctx);
1172
1173 for (int i = 0; i < count; i++) {
1174 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1175 }
1176 }
1177
1178 static void evergreen_set_clip_state(struct pipe_context *ctx,
1179 const struct pipe_clip_state *state)
1180 {
1181 struct r600_context *rctx = (struct r600_context *)ctx;
1182 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1183 struct pipe_resource *cbuf;
1184
1185 if (rstate == NULL)
1186 return;
1187
1188 rctx->clip = *state;
1189 rstate->id = R600_PIPE_STATE_CLIP;
1190 for (int i = 0; i < 6; i++) {
1191 r600_pipe_state_add_reg(rstate,
1192 R_0285BC_PA_CL_UCP0_X + i * 16,
1193 fui(state->ucp[i][0]), NULL, 0);
1194 r600_pipe_state_add_reg(rstate,
1195 R_0285C0_PA_CL_UCP0_Y + i * 16,
1196 fui(state->ucp[i][1]) , NULL, 0);
1197 r600_pipe_state_add_reg(rstate,
1198 R_0285C4_PA_CL_UCP0_Z + i * 16,
1199 fui(state->ucp[i][2]), NULL, 0);
1200 r600_pipe_state_add_reg(rstate,
1201 R_0285C8_PA_CL_UCP0_W + i * 16,
1202 fui(state->ucp[i][3]), NULL, 0);
1203 }
1204
1205 free(rctx->states[R600_PIPE_STATE_CLIP]);
1206 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1207 r600_context_pipe_state_set(rctx, rstate);
1208
1209 cbuf = pipe_user_buffer_create(ctx->screen,
1210 state->ucp,
1211 4*4*8, /* 8*4 floats */
1212 PIPE_BIND_CONSTANT_BUFFER);
1213 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1214 pipe_resource_reference(&cbuf, NULL);
1215 }
1216
1217 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1218 const struct pipe_poly_stipple *state)
1219 {
1220 }
1221
1222 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1223 {
1224 }
1225
1226 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1227 const struct pipe_scissor_state *state)
1228 {
1229 struct r600_context *rctx = (struct r600_context *)ctx;
1230 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1231 uint32_t tl, br;
1232
1233 if (rstate == NULL)
1234 return;
1235
1236 rstate->id = R600_PIPE_STATE_SCISSOR;
1237 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1238 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1239 r600_pipe_state_add_reg(rstate,
1240 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1241 NULL, 0);
1242 r600_pipe_state_add_reg(rstate,
1243 R_028214_PA_SC_CLIPRECT_0_BR, br,
1244 NULL, 0);
1245 r600_pipe_state_add_reg(rstate,
1246 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1247 NULL, 0);
1248 r600_pipe_state_add_reg(rstate,
1249 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1250 NULL, 0);
1251 r600_pipe_state_add_reg(rstate,
1252 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1253 NULL, 0);
1254 r600_pipe_state_add_reg(rstate,
1255 R_028224_PA_SC_CLIPRECT_2_BR, br,
1256 NULL, 0);
1257 r600_pipe_state_add_reg(rstate,
1258 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1259 NULL, 0);
1260 r600_pipe_state_add_reg(rstate,
1261 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1262 NULL, 0);
1263
1264 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1265 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1266 r600_context_pipe_state_set(rctx, rstate);
1267 }
1268
1269 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1270 const struct pipe_viewport_state *state)
1271 {
1272 struct r600_context *rctx = (struct r600_context *)ctx;
1273 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1274
1275 if (rstate == NULL)
1276 return;
1277
1278 rctx->viewport = *state;
1279 rstate->id = R600_PIPE_STATE_VIEWPORT;
1280 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1281 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1282 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1283 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1284 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1285 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1286 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1287 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1288 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1289
1290 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1291 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1292 r600_context_pipe_state_set(rctx, rstate);
1293 }
1294
1295 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1296 const struct pipe_framebuffer_state *state, int cb)
1297 {
1298 struct r600_screen *rscreen = rctx->screen;
1299 struct r600_resource_texture *rtex;
1300 struct r600_surface *surf;
1301 unsigned level = state->cbufs[cb]->u.tex.level;
1302 unsigned pitch, slice;
1303 unsigned color_info, color_attrib;
1304 unsigned format, swap, ntype, endian;
1305 uint64_t offset;
1306 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1307 const struct util_format_description *desc;
1308 int i;
1309 unsigned blend_clamp = 0, blend_bypass = 0;
1310
1311 surf = (struct r600_surface *)state->cbufs[cb];
1312 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1313
1314 if (rtex->depth)
1315 rctx->have_depth_fb = TRUE;
1316
1317 if (rtex->depth && !rtex->is_flushing_texture) {
1318 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1319 rtex = rtex->flushed_depth_texture;
1320 }
1321
1322 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1323 if (!rscreen->use_surface) {
1324 offset = r600_texture_get_offset(rtex,
1325 level, state->cbufs[cb]->u.tex.first_layer);
1326 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1327 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1328 if (slice) {
1329 slice = slice - 1;
1330 }
1331 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1332 tile_split = 0;
1333 macro_aspect = 0;
1334 bankw = 0;
1335 bankh = 0;
1336 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1337 tile_type = rtex->tile_type;
1338 } else {
1339 /* workaround for linear buffers */
1340 tile_type = 1;
1341 }
1342 } else {
1343 offset = rtex->surface.level[level].offset;
1344 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1345 offset += rtex->surface.level[level].slice_size *
1346 state->cbufs[cb]->u.tex.first_layer;
1347 }
1348 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1349 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1350 if (slice) {
1351 slice = slice - 1;
1352 }
1353 color_info = 0;
1354 switch (rtex->surface.level[level].mode) {
1355 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1356 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1357 tile_type = 1;
1358 break;
1359 case RADEON_SURF_MODE_1D:
1360 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1361 tile_type = rtex->tile_type;
1362 break;
1363 case RADEON_SURF_MODE_2D:
1364 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1365 tile_type = rtex->tile_type;
1366 break;
1367 case RADEON_SURF_MODE_LINEAR:
1368 default:
1369 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1370 tile_type = 1;
1371 break;
1372 }
1373 tile_split = rtex->surface.tile_split;
1374 macro_aspect = rtex->surface.mtilea;
1375 bankw = rtex->surface.bankw;
1376 bankh = rtex->surface.bankh;
1377 tile_split = eg_tile_split(tile_split);
1378 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1379 bankw = eg_bank_wh(bankw);
1380 bankh = eg_bank_wh(bankh);
1381 }
1382 /* 128 bit formats require tile type = 1 */
1383 if (rscreen->chip_class == CAYMAN) {
1384 if (util_format_get_blocksize(surf->base.format) >= 16)
1385 tile_type = 1;
1386 }
1387 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1388 desc = util_format_description(surf->base.format);
1389 for (i = 0; i < 4; i++) {
1390 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1391 break;
1392 }
1393 }
1394
1395 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1396 S_028C74_NUM_BANKS(nbanks) |
1397 S_028C74_BANK_WIDTH(bankw) |
1398 S_028C74_BANK_HEIGHT(bankh) |
1399 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1400 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1401
1402 ntype = V_028C70_NUMBER_UNORM;
1403 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1404 ntype = V_028C70_NUMBER_SRGB;
1405 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1406 if (desc->channel[i].normalized)
1407 ntype = V_028C70_NUMBER_SNORM;
1408 else if (desc->channel[i].pure_integer)
1409 ntype = V_028C70_NUMBER_SINT;
1410 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1411 if (desc->channel[i].normalized)
1412 ntype = V_028C70_NUMBER_UNORM;
1413 else if (desc->channel[i].pure_integer)
1414 ntype = V_028C70_NUMBER_UINT;
1415 }
1416
1417 format = r600_translate_colorformat(surf->base.format);
1418 swap = r600_translate_colorswap(surf->base.format);
1419 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1420 endian = ENDIAN_NONE;
1421 } else {
1422 endian = r600_colorformat_endian_swap(format);
1423 }
1424
1425 /* blend clamp should be set for all NORM/SRGB types */
1426 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1427 ntype == V_028C70_NUMBER_SRGB)
1428 blend_clamp = 1;
1429
1430 /* set blend bypass according to docs if SINT/UINT or
1431 8/24 COLOR variants */
1432 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1433 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1434 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1435 blend_clamp = 0;
1436 blend_bypass = 1;
1437 }
1438
1439 color_info |= S_028C70_FORMAT(format) |
1440 S_028C70_COMP_SWAP(swap) |
1441 S_028C70_BLEND_CLAMP(blend_clamp) |
1442 S_028C70_BLEND_BYPASS(blend_bypass) |
1443 S_028C70_NUMBER_TYPE(ntype) |
1444 S_028C70_ENDIAN(endian);
1445
1446 /* EXPORT_NORM is an optimzation that can be enabled for better
1447 * performance in certain cases.
1448 * EXPORT_NORM can be enabled if:
1449 * - 11-bit or smaller UNORM/SNORM/SRGB
1450 * - 16-bit or smaller FLOAT
1451 */
1452 /* FIXME: This should probably be the same for all CBs if we want
1453 * useful alpha tests. */
1454 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1455 ((desc->channel[i].size < 12 &&
1456 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1457 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1458 (desc->channel[i].size < 17 &&
1459 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1460 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1461 rctx->export_16bpc = true;
1462 } else {
1463 rctx->export_16bpc = false;
1464 }
1465 rctx->alpha_ref_dirty = true;
1466
1467
1468 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1469 offset >>= 8;
1470
1471 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1472 r600_pipe_state_add_reg(rstate,
1473 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1474 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1475 r600_pipe_state_add_reg(rstate,
1476 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1477 0x0, NULL, 0);
1478 r600_pipe_state_add_reg(rstate,
1479 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1480 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1481 r600_pipe_state_add_reg(rstate,
1482 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1483 S_028C64_PITCH_TILE_MAX(pitch),
1484 NULL, 0);
1485 r600_pipe_state_add_reg(rstate,
1486 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1487 S_028C68_SLICE_TILE_MAX(slice),
1488 NULL, 0);
1489 if (!rscreen->use_surface) {
1490 r600_pipe_state_add_reg(rstate,
1491 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1492 0x00000000, NULL, 0);
1493 } else {
1494 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1495 r600_pipe_state_add_reg(rstate,
1496 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1497 0x00000000, NULL, 0);
1498 } else {
1499 r600_pipe_state_add_reg(rstate,
1500 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1501 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1502 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1503 NULL, 0);
1504 }
1505 }
1506 r600_pipe_state_add_reg(rstate,
1507 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1508 color_attrib,
1509 &rtex->resource, RADEON_USAGE_READWRITE);
1510 }
1511
1512 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1513 const struct pipe_framebuffer_state *state)
1514 {
1515 struct r600_screen *rscreen = rctx->screen;
1516 struct r600_resource_texture *rtex;
1517 struct r600_surface *surf;
1518 uint64_t offset;
1519 unsigned level, first_layer, pitch, slice, format, array_mode;
1520 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1521
1522 if (state->zsbuf == NULL)
1523 return;
1524
1525 surf = (struct r600_surface *)state->zsbuf;
1526 level = surf->base.u.tex.level;
1527 rtex = (struct r600_resource_texture*)surf->base.texture;
1528 first_layer = surf->base.u.tex.first_layer;
1529 format = r600_translate_dbformat(rtex->real_format);
1530
1531 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1532 /* XXX remove this once tiling is properly supported */
1533 if (!rscreen->use_surface) {
1534 /* XXX remove this once tiling is properly supported */
1535 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1536 V_028C70_ARRAY_1D_TILED_THIN1;
1537
1538 offset += r600_texture_get_offset(rtex, level, first_layer);
1539 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1540 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1541 if (slice) {
1542 slice = slice - 1;
1543 }
1544 tile_split = 0;
1545 macro_aspect = 0;
1546 bankw = 0;
1547 bankh = 0;
1548 } else {
1549 offset += rtex->surface.level[level].offset;
1550 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1551 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1552 if (slice) {
1553 slice = slice - 1;
1554 }
1555 switch (rtex->surface.level[level].mode) {
1556 case RADEON_SURF_MODE_2D:
1557 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1558 break;
1559 case RADEON_SURF_MODE_1D:
1560 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1561 case RADEON_SURF_MODE_LINEAR:
1562 default:
1563 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1564 break;
1565 }
1566 tile_split = rtex->surface.tile_split;
1567 macro_aspect = rtex->surface.mtilea;
1568 bankw = rtex->surface.bankw;
1569 bankh = rtex->surface.bankh;
1570 tile_split = eg_tile_split(tile_split);
1571 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1572 bankw = eg_bank_wh(bankw);
1573 bankh = eg_bank_wh(bankh);
1574 }
1575 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1576 offset >>= 8;
1577
1578 z_info = S_028040_ARRAY_MODE(array_mode) |
1579 S_028040_FORMAT(format) |
1580 S_028040_TILE_SPLIT(tile_split)|
1581 S_028040_NUM_BANKS(nbanks) |
1582 S_028040_BANK_WIDTH(bankw) |
1583 S_028040_BANK_HEIGHT(bankh) |
1584 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1585
1586 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1587 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1588 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1589 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1590 if (!rscreen->use_surface) {
1591 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1592 0x00000000, NULL, 0);
1593 } else {
1594 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1595 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1596 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1597 NULL, 0);
1598 }
1599
1600 if (rtex->stencil) {
1601 uint64_t stencil_offset =
1602 r600_texture_get_offset(rtex->stencil, level, first_layer);
1603 unsigned stile_split;
1604
1605 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1606 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1607 stencil_offset >>= 8;
1608
1609 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1610 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1611 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1612 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1613 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1614 1 | S_028044_TILE_SPLIT(stile_split),
1615 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1616 } else {
1617 if (rscreen->use_surface && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1618 uint64_t stencil_offset = rtex->surface.stencil_offset;
1619 unsigned stile_split = rtex->surface.stencil_tile_split;
1620
1621 stile_split = eg_tile_split(stile_split);
1622 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1623 stencil_offset += rtex->surface.level[level].offset / 4;
1624 stencil_offset >>= 8;
1625
1626 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1627 stencil_offset, &rtex->resource,
1628 RADEON_USAGE_READWRITE);
1629 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1630 stencil_offset, &rtex->resource,
1631 RADEON_USAGE_READWRITE);
1632 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1633 1 | S_028044_TILE_SPLIT(stile_split),
1634 &rtex->resource,
1635 RADEON_USAGE_READWRITE);
1636 } else {
1637 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1638 offset, &rtex->resource,
1639 RADEON_USAGE_READWRITE);
1640 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1641 offset, &rtex->resource,
1642 RADEON_USAGE_READWRITE);
1643 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1644 0, NULL, RADEON_USAGE_READWRITE);
1645 }
1646 }
1647
1648 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1649 &rtex->resource, RADEON_USAGE_READWRITE);
1650 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1651 S_028058_PITCH_TILE_MAX(pitch),
1652 NULL, 0);
1653 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1654 S_02805C_SLICE_TILE_MAX(slice),
1655 NULL, 0);
1656 }
1657
1658 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1659 const struct pipe_framebuffer_state *state)
1660 {
1661 struct r600_context *rctx = (struct r600_context *)ctx;
1662 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1663 uint32_t shader_mask, tl, br;
1664 int tl_x, tl_y, br_x, br_y;
1665
1666 if (rstate == NULL)
1667 return;
1668
1669 r600_flush_framebuffer(rctx, false);
1670
1671 /* unreference old buffer and reference new one */
1672 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1673
1674 util_copy_framebuffer_state(&rctx->framebuffer, state);
1675
1676 /* build states */
1677 rctx->have_depth_fb = 0;
1678 rctx->nr_cbufs = state->nr_cbufs;
1679 for (int i = 0; i < state->nr_cbufs; i++) {
1680 evergreen_cb(rctx, rstate, state, i);
1681 }
1682 if (state->zsbuf) {
1683 evergreen_db(rctx, rstate, state);
1684 }
1685
1686 shader_mask = 0;
1687 for (int i = 0; i < state->nr_cbufs; i++) {
1688 shader_mask |= 0xf << (i * 4);
1689 }
1690 tl_x = 0;
1691 tl_y = 0;
1692 br_x = state->width;
1693 br_y = state->height;
1694 /* EG hw workaround */
1695 if (br_x == 0)
1696 tl_x = 1;
1697 if (br_y == 0)
1698 tl_y = 1;
1699 /* cayman hw workaround */
1700 if (rctx->chip_class == CAYMAN) {
1701 if (br_x == 1 && br_y == 1)
1702 br_x = 2;
1703 }
1704 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1705 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1706
1707 r600_pipe_state_add_reg(rstate,
1708 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1709 NULL, 0);
1710 r600_pipe_state_add_reg(rstate,
1711 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1712 NULL, 0);
1713 r600_pipe_state_add_reg(rstate,
1714 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1715 NULL, 0);
1716 r600_pipe_state_add_reg(rstate,
1717 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1718 NULL, 0);
1719 r600_pipe_state_add_reg(rstate,
1720 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1721 NULL, 0);
1722 r600_pipe_state_add_reg(rstate,
1723 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1724 NULL, 0);
1725 r600_pipe_state_add_reg(rstate,
1726 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1727 NULL, 0);
1728 r600_pipe_state_add_reg(rstate,
1729 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1730 NULL, 0);
1731 r600_pipe_state_add_reg(rstate,
1732 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1733 NULL, 0);
1734 r600_pipe_state_add_reg(rstate,
1735 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1736 NULL, 0);
1737 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1738 shader_mask, NULL, 0);
1739
1740
1741 if (rctx->chip_class == CAYMAN) {
1742 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1743 0x00000000, NULL, 0);
1744 } else {
1745 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1746 0x00000000, NULL, 0);
1747 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0,
1748 0x00000000, NULL, 0);
1749 }
1750
1751 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1752 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1753 r600_context_pipe_state_set(rctx, rstate);
1754
1755 if (state->zsbuf) {
1756 evergreen_polygon_offset_update(rctx);
1757 }
1758 }
1759
1760 void evergreen_init_state_functions(struct r600_context *rctx)
1761 {
1762 rctx->context.create_blend_state = evergreen_create_blend_state;
1763 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1764 rctx->context.create_fs_state = r600_create_shader_state;
1765 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1766 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1767 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1768 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1769 rctx->context.create_vs_state = r600_create_shader_state;
1770 rctx->context.bind_blend_state = r600_bind_blend_state;
1771 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1772 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1773 rctx->context.bind_fs_state = r600_bind_ps_shader;
1774 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1775 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1776 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1777 rctx->context.bind_vs_state = r600_bind_vs_shader;
1778 rctx->context.delete_blend_state = r600_delete_state;
1779 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1780 rctx->context.delete_fs_state = r600_delete_ps_shader;
1781 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1782 rctx->context.delete_sampler_state = r600_delete_state;
1783 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1784 rctx->context.delete_vs_state = r600_delete_vs_shader;
1785 rctx->context.set_blend_color = r600_set_blend_color;
1786 rctx->context.set_clip_state = evergreen_set_clip_state;
1787 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1788 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1789 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1790 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1791 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1792 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1793 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1794 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1795 rctx->context.set_index_buffer = r600_set_index_buffer;
1796 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1797 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1798 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1799 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1800 rctx->context.texture_barrier = r600_texture_barrier;
1801 rctx->context.create_stream_output_target = r600_create_so_target;
1802 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1803 rctx->context.set_stream_output_targets = r600_set_so_targets;
1804 }
1805
1806 static void cayman_init_config(struct r600_context *rctx)
1807 {
1808 struct r600_pipe_state *rstate = &rctx->config;
1809 unsigned tmp;
1810
1811 tmp = 0x00000000;
1812 tmp |= S_008C00_EXPORT_SRC_C(1);
1813 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
1814
1815 /* always set the temp clauses */
1816 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), NULL, 0);
1817 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
1818 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
1819 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
1820
1821 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1822
1823 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1824 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1825 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1826 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1827 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1828 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1829 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1830 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1831 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1832 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1833 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1834 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1835 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1836 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1837 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1838 r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1839 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1840 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1841 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1842
1843 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
1844 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
1845 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
1846 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
1847 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
1848 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
1849 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
1850 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
1851 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
1852 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
1853 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
1854 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
1855 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
1856 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
1857 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
1858 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
1859 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
1860 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
1861 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
1862 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
1863 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
1864 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
1865 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
1866 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
1867 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
1868 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
1869 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
1870 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
1871 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
1872 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
1873 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
1874 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
1875
1876 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1877
1878 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1879 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1880
1881 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, NULL, 0);
1882 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, NULL, 0);
1883
1884 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, NULL, 0);
1885 r600_context_pipe_state_set(rctx, rstate);
1886 }
1887
1888 void evergreen_init_config(struct r600_context *rctx)
1889 {
1890 struct r600_pipe_state *rstate = &rctx->config;
1891 int ps_prio;
1892 int vs_prio;
1893 int gs_prio;
1894 int es_prio;
1895 int hs_prio, cs_prio, ls_prio;
1896 int num_ps_gprs;
1897 int num_vs_gprs;
1898 int num_gs_gprs;
1899 int num_es_gprs;
1900 int num_hs_gprs;
1901 int num_ls_gprs;
1902 int num_temp_gprs;
1903 int num_ps_threads;
1904 int num_vs_threads;
1905 int num_gs_threads;
1906 int num_es_threads;
1907 int num_hs_threads;
1908 int num_ls_threads;
1909 int num_ps_stack_entries;
1910 int num_vs_stack_entries;
1911 int num_gs_stack_entries;
1912 int num_es_stack_entries;
1913 int num_hs_stack_entries;
1914 int num_ls_stack_entries;
1915 enum radeon_family family;
1916 unsigned tmp;
1917
1918 family = rctx->family;
1919
1920 if (rctx->chip_class == CAYMAN) {
1921 cayman_init_config(rctx);
1922 return;
1923 }
1924
1925 ps_prio = 0;
1926 vs_prio = 1;
1927 gs_prio = 2;
1928 es_prio = 3;
1929 hs_prio = 0;
1930 ls_prio = 0;
1931 cs_prio = 0;
1932
1933 switch (family) {
1934 case CHIP_CEDAR:
1935 default:
1936 num_ps_gprs = 93;
1937 num_vs_gprs = 46;
1938 num_temp_gprs = 4;
1939 num_gs_gprs = 31;
1940 num_es_gprs = 31;
1941 num_hs_gprs = 23;
1942 num_ls_gprs = 23;
1943 num_ps_threads = 96;
1944 num_vs_threads = 16;
1945 num_gs_threads = 16;
1946 num_es_threads = 16;
1947 num_hs_threads = 16;
1948 num_ls_threads = 16;
1949 num_ps_stack_entries = 42;
1950 num_vs_stack_entries = 42;
1951 num_gs_stack_entries = 42;
1952 num_es_stack_entries = 42;
1953 num_hs_stack_entries = 42;
1954 num_ls_stack_entries = 42;
1955 break;
1956 case CHIP_REDWOOD:
1957 num_ps_gprs = 93;
1958 num_vs_gprs = 46;
1959 num_temp_gprs = 4;
1960 num_gs_gprs = 31;
1961 num_es_gprs = 31;
1962 num_hs_gprs = 23;
1963 num_ls_gprs = 23;
1964 num_ps_threads = 128;
1965 num_vs_threads = 20;
1966 num_gs_threads = 20;
1967 num_es_threads = 20;
1968 num_hs_threads = 20;
1969 num_ls_threads = 20;
1970 num_ps_stack_entries = 42;
1971 num_vs_stack_entries = 42;
1972 num_gs_stack_entries = 42;
1973 num_es_stack_entries = 42;
1974 num_hs_stack_entries = 42;
1975 num_ls_stack_entries = 42;
1976 break;
1977 case CHIP_JUNIPER:
1978 num_ps_gprs = 93;
1979 num_vs_gprs = 46;
1980 num_temp_gprs = 4;
1981 num_gs_gprs = 31;
1982 num_es_gprs = 31;
1983 num_hs_gprs = 23;
1984 num_ls_gprs = 23;
1985 num_ps_threads = 128;
1986 num_vs_threads = 20;
1987 num_gs_threads = 20;
1988 num_es_threads = 20;
1989 num_hs_threads = 20;
1990 num_ls_threads = 20;
1991 num_ps_stack_entries = 85;
1992 num_vs_stack_entries = 85;
1993 num_gs_stack_entries = 85;
1994 num_es_stack_entries = 85;
1995 num_hs_stack_entries = 85;
1996 num_ls_stack_entries = 85;
1997 break;
1998 case CHIP_CYPRESS:
1999 case CHIP_HEMLOCK:
2000 num_ps_gprs = 93;
2001 num_vs_gprs = 46;
2002 num_temp_gprs = 4;
2003 num_gs_gprs = 31;
2004 num_es_gprs = 31;
2005 num_hs_gprs = 23;
2006 num_ls_gprs = 23;
2007 num_ps_threads = 128;
2008 num_vs_threads = 20;
2009 num_gs_threads = 20;
2010 num_es_threads = 20;
2011 num_hs_threads = 20;
2012 num_ls_threads = 20;
2013 num_ps_stack_entries = 85;
2014 num_vs_stack_entries = 85;
2015 num_gs_stack_entries = 85;
2016 num_es_stack_entries = 85;
2017 num_hs_stack_entries = 85;
2018 num_ls_stack_entries = 85;
2019 break;
2020 case CHIP_PALM:
2021 num_ps_gprs = 93;
2022 num_vs_gprs = 46;
2023 num_temp_gprs = 4;
2024 num_gs_gprs = 31;
2025 num_es_gprs = 31;
2026 num_hs_gprs = 23;
2027 num_ls_gprs = 23;
2028 num_ps_threads = 96;
2029 num_vs_threads = 16;
2030 num_gs_threads = 16;
2031 num_es_threads = 16;
2032 num_hs_threads = 16;
2033 num_ls_threads = 16;
2034 num_ps_stack_entries = 42;
2035 num_vs_stack_entries = 42;
2036 num_gs_stack_entries = 42;
2037 num_es_stack_entries = 42;
2038 num_hs_stack_entries = 42;
2039 num_ls_stack_entries = 42;
2040 break;
2041 case CHIP_SUMO:
2042 num_ps_gprs = 93;
2043 num_vs_gprs = 46;
2044 num_temp_gprs = 4;
2045 num_gs_gprs = 31;
2046 num_es_gprs = 31;
2047 num_hs_gprs = 23;
2048 num_ls_gprs = 23;
2049 num_ps_threads = 96;
2050 num_vs_threads = 25;
2051 num_gs_threads = 25;
2052 num_es_threads = 25;
2053 num_hs_threads = 25;
2054 num_ls_threads = 25;
2055 num_ps_stack_entries = 42;
2056 num_vs_stack_entries = 42;
2057 num_gs_stack_entries = 42;
2058 num_es_stack_entries = 42;
2059 num_hs_stack_entries = 42;
2060 num_ls_stack_entries = 42;
2061 break;
2062 case CHIP_SUMO2:
2063 num_ps_gprs = 93;
2064 num_vs_gprs = 46;
2065 num_temp_gprs = 4;
2066 num_gs_gprs = 31;
2067 num_es_gprs = 31;
2068 num_hs_gprs = 23;
2069 num_ls_gprs = 23;
2070 num_ps_threads = 96;
2071 num_vs_threads = 25;
2072 num_gs_threads = 25;
2073 num_es_threads = 25;
2074 num_hs_threads = 25;
2075 num_ls_threads = 25;
2076 num_ps_stack_entries = 85;
2077 num_vs_stack_entries = 85;
2078 num_gs_stack_entries = 85;
2079 num_es_stack_entries = 85;
2080 num_hs_stack_entries = 85;
2081 num_ls_stack_entries = 85;
2082 break;
2083 case CHIP_BARTS:
2084 num_ps_gprs = 93;
2085 num_vs_gprs = 46;
2086 num_temp_gprs = 4;
2087 num_gs_gprs = 31;
2088 num_es_gprs = 31;
2089 num_hs_gprs = 23;
2090 num_ls_gprs = 23;
2091 num_ps_threads = 128;
2092 num_vs_threads = 20;
2093 num_gs_threads = 20;
2094 num_es_threads = 20;
2095 num_hs_threads = 20;
2096 num_ls_threads = 20;
2097 num_ps_stack_entries = 85;
2098 num_vs_stack_entries = 85;
2099 num_gs_stack_entries = 85;
2100 num_es_stack_entries = 85;
2101 num_hs_stack_entries = 85;
2102 num_ls_stack_entries = 85;
2103 break;
2104 case CHIP_TURKS:
2105 num_ps_gprs = 93;
2106 num_vs_gprs = 46;
2107 num_temp_gprs = 4;
2108 num_gs_gprs = 31;
2109 num_es_gprs = 31;
2110 num_hs_gprs = 23;
2111 num_ls_gprs = 23;
2112 num_ps_threads = 128;
2113 num_vs_threads = 20;
2114 num_gs_threads = 20;
2115 num_es_threads = 20;
2116 num_hs_threads = 20;
2117 num_ls_threads = 20;
2118 num_ps_stack_entries = 42;
2119 num_vs_stack_entries = 42;
2120 num_gs_stack_entries = 42;
2121 num_es_stack_entries = 42;
2122 num_hs_stack_entries = 42;
2123 num_ls_stack_entries = 42;
2124 break;
2125 case CHIP_CAICOS:
2126 num_ps_gprs = 93;
2127 num_vs_gprs = 46;
2128 num_temp_gprs = 4;
2129 num_gs_gprs = 31;
2130 num_es_gprs = 31;
2131 num_hs_gprs = 23;
2132 num_ls_gprs = 23;
2133 num_ps_threads = 128;
2134 num_vs_threads = 10;
2135 num_gs_threads = 10;
2136 num_es_threads = 10;
2137 num_hs_threads = 10;
2138 num_ls_threads = 10;
2139 num_ps_stack_entries = 42;
2140 num_vs_stack_entries = 42;
2141 num_gs_stack_entries = 42;
2142 num_es_stack_entries = 42;
2143 num_hs_stack_entries = 42;
2144 num_ls_stack_entries = 42;
2145 break;
2146 }
2147
2148 tmp = 0x00000000;
2149 switch (family) {
2150 case CHIP_CEDAR:
2151 case CHIP_PALM:
2152 case CHIP_SUMO:
2153 case CHIP_SUMO2:
2154 case CHIP_CAICOS:
2155 break;
2156 default:
2157 tmp |= S_008C00_VC_ENABLE(1);
2158 break;
2159 }
2160 tmp |= S_008C00_EXPORT_SRC_C(1);
2161 tmp |= S_008C00_CS_PRIO(cs_prio);
2162 tmp |= S_008C00_LS_PRIO(ls_prio);
2163 tmp |= S_008C00_HS_PRIO(hs_prio);
2164 tmp |= S_008C00_PS_PRIO(ps_prio);
2165 tmp |= S_008C00_VS_PRIO(vs_prio);
2166 tmp |= S_008C00_GS_PRIO(gs_prio);
2167 tmp |= S_008C00_ES_PRIO(es_prio);
2168 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
2169
2170 /* enable dynamic GPR resource management */
2171 if (rctx->screen->info.drm_minor >= 7) {
2172 /* always set temp clauses */
2173 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2174 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), NULL, 0);
2175 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
2176 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
2177 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
2178 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2179 S_028838_PS_GPRS(0x1e) |
2180 S_028838_VS_GPRS(0x1e) |
2181 S_028838_GS_GPRS(0x1e) |
2182 S_028838_ES_GPRS(0x1e) |
2183 S_028838_HS_GPRS(0x1e) |
2184 S_028838_LS_GPRS(0x1e), NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2185 } else {
2186 tmp = 0;
2187 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2188 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2189 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2190 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
2191
2192 tmp = 0;
2193 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2194 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2195 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
2196
2197 tmp = 0;
2198 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2199 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2200 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, NULL, 0);
2201 }
2202
2203 tmp = 0;
2204 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2205 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2206 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2207 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2208 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, NULL, 0);
2209
2210 tmp = 0;
2211 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2212 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2213 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, NULL, 0);
2214
2215 tmp = 0;
2216 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2217 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2218 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
2219
2220 tmp = 0;
2221 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2222 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2223 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
2224
2225 tmp = 0;
2226 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2227 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2228 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, NULL, 0);
2229
2230 tmp = 0;
2231 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2232 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2233 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, NULL, 0);
2234
2235 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, NULL, 0);
2236 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), NULL, 0);
2237
2238 #if 0
2239 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, NULL, 0);
2240
2241 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, NULL, 0);
2242 #endif
2243 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
2244
2245 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, NULL, 0);
2246 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, NULL, 0);
2247 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2248 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2249 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2250 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2251
2252 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, NULL, 0);
2253 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, NULL, 0);
2254 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, NULL, 0);
2255 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, NULL, 0);
2256
2257 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
2258 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
2259 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
2260 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
2261 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
2262 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
2263 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
2264 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
2265 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
2266 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
2267 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
2268 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
2269 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
2270 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
2271 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
2272 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
2273 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
2274 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
2275
2276 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
2277 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
2278 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
2279 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
2280 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
2281 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
2282 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
2283 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
2284 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
2285 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
2286 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
2287 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
2288 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
2289 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
2290 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
2291 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
2292 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
2293 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
2294 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
2295 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
2296 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
2297 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
2298 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
2299 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
2300 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
2301 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
2302 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
2303 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
2304 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
2305 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
2306 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
2307 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
2308
2309 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
2310
2311 r600_context_pipe_state_set(rctx, rstate);
2312 }
2313
2314 void evergreen_polygon_offset_update(struct r600_context *rctx)
2315 {
2316 struct r600_pipe_state state;
2317
2318 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2319 state.nregs = 0;
2320 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2321 float offset_units = rctx->rasterizer->offset_units;
2322 unsigned offset_db_fmt_cntl = 0, depth;
2323
2324 switch (rctx->framebuffer.zsbuf->texture->format) {
2325 case PIPE_FORMAT_Z24X8_UNORM:
2326 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2327 depth = -24;
2328 offset_units *= 2.0f;
2329 break;
2330 case PIPE_FORMAT_Z32_FLOAT:
2331 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2332 depth = -23;
2333 offset_units *= 1.0f;
2334 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2335 break;
2336 case PIPE_FORMAT_Z16_UNORM:
2337 depth = -16;
2338 offset_units *= 4.0f;
2339 break;
2340 default:
2341 return;
2342 }
2343 /* FIXME some of those reg can be computed with cso */
2344 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2345 r600_pipe_state_add_reg(&state,
2346 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2347 fui(rctx->rasterizer->offset_scale), NULL, 0);
2348 r600_pipe_state_add_reg(&state,
2349 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2350 fui(offset_units), NULL, 0);
2351 r600_pipe_state_add_reg(&state,
2352 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2353 fui(rctx->rasterizer->offset_scale), NULL, 0);
2354 r600_pipe_state_add_reg(&state,
2355 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2356 fui(offset_units), NULL, 0);
2357 r600_pipe_state_add_reg(&state,
2358 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2359 offset_db_fmt_cntl, NULL, 0);
2360 r600_context_pipe_state_set(rctx, &state);
2361 }
2362 }
2363
2364 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2365 {
2366 struct r600_context *rctx = (struct r600_context *)ctx;
2367 struct r600_pipe_state *rstate = &shader->rstate;
2368 struct r600_shader *rshader = &shader->shader;
2369 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2370 int pos_index = -1, face_index = -1;
2371 int ninterp = 0;
2372 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2373 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2374
2375 rstate->nregs = 0;
2376
2377 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2378 for (i = 0; i < rshader->ninput; i++) {
2379 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2380 POSITION goes via GPRs from the SC so isn't counted */
2381 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2382 pos_index = i;
2383 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2384 face_index = i;
2385 else {
2386 ninterp++;
2387 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2388 have_linear = TRUE;
2389 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2390 have_perspective = TRUE;
2391 if (rshader->input[i].centroid)
2392 have_centroid = TRUE;
2393 }
2394
2395 sid = rshader->input[i].spi_sid;
2396
2397 if (sid) {
2398
2399 tmp = S_028644_SEMANTIC(sid);
2400
2401 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2402 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2403 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2404 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2405 tmp |= S_028644_FLAT_SHADE(1);
2406 }
2407
2408 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2409 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2410 tmp |= S_028644_PT_SPRITE_TEX(1);
2411 }
2412
2413 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2414 tmp, NULL, 0);
2415
2416 idx++;
2417 }
2418 }
2419
2420 for (i = 0; i < rshader->noutput; i++) {
2421 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2422 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2423 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2424 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2425 }
2426 if (rshader->uses_kill)
2427 db_shader_control |= S_02880C_KILL_ENABLE(1);
2428
2429 exports_ps = 0;
2430 num_cout = 0;
2431 for (i = 0; i < rshader->noutput; i++) {
2432 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2433 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2434 exports_ps |= 1;
2435 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2436 if (rshader->fs_write_all)
2437 num_cout = rshader->nr_cbufs;
2438 else
2439 num_cout++;
2440 }
2441 }
2442 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2443 if (!exports_ps) {
2444 /* always at least export 1 component per pixel */
2445 exports_ps = 2;
2446 }
2447
2448 if (ninterp == 0) {
2449 ninterp = 1;
2450 have_perspective = TRUE;
2451 }
2452
2453 if (!have_perspective && !have_linear)
2454 have_perspective = TRUE;
2455
2456 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2457 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2458 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2459 spi_input_z = 0;
2460 if (pos_index != -1) {
2461 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2462 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2463 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2464 spi_input_z |= 1;
2465 }
2466
2467 spi_ps_in_control_1 = 0;
2468 if (face_index != -1) {
2469 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2470 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2471 }
2472
2473 spi_baryc_cntl = 0;
2474 if (have_perspective)
2475 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2476 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2477 if (have_linear)
2478 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2479 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2480
2481 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2482 spi_ps_in_control_0, NULL, 0);
2483 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2484 spi_ps_in_control_1, NULL, 0);
2485 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2486 0, NULL, 0);
2487 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2488 r600_pipe_state_add_reg(rstate,
2489 R_0286E0_SPI_BARYC_CNTL,
2490 spi_baryc_cntl,
2491 NULL, 0);
2492
2493 r600_pipe_state_add_reg(rstate,
2494 R_028840_SQ_PGM_START_PS,
2495 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2496 shader->bo, RADEON_USAGE_READ);
2497 r600_pipe_state_add_reg(rstate,
2498 R_028844_SQ_PGM_RESOURCES_PS,
2499 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2500 S_028844_PRIME_CACHE_ON_DRAW(1) |
2501 S_028844_STACK_SIZE(rshader->bc.nstack),
2502 NULL, 0);
2503 r600_pipe_state_add_reg(rstate,
2504 R_028848_SQ_PGM_RESOURCES_2_PS,
2505 S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2506 NULL, 0);
2507 r600_pipe_state_add_reg(rstate,
2508 R_02884C_SQ_PGM_EXPORTS_PS,
2509 exports_ps, NULL, 0);
2510 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2511 db_shader_control,
2512 NULL, 0);
2513 r600_pipe_state_add_reg(rstate,
2514 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2515 NULL, 0);
2516
2517 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2518 if (rctx->rasterizer)
2519 shader->flatshade = rctx->rasterizer->flatshade;
2520 }
2521
2522 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2523 {
2524 struct r600_context *rctx = (struct r600_context *)ctx;
2525 struct r600_pipe_state *rstate = &shader->rstate;
2526 struct r600_shader *rshader = &shader->shader;
2527 unsigned spi_vs_out_id[10] = {};
2528 unsigned i, tmp, nparams = 0;
2529
2530 /* clear previous register */
2531 rstate->nregs = 0;
2532
2533 for (i = 0; i < rshader->noutput; i++) {
2534 if (rshader->output[i].spi_sid) {
2535 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2536 spi_vs_out_id[nparams / 4] |= tmp;
2537 nparams++;
2538 }
2539 }
2540
2541 for (i = 0; i < 10; i++) {
2542 r600_pipe_state_add_reg(rstate,
2543 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2544 spi_vs_out_id[i], NULL, 0);
2545 }
2546
2547 /* Certain attributes (position, psize, etc.) don't count as params.
2548 * VS is required to export at least one param and r600_shader_from_tgsi()
2549 * takes care of adding a dummy export.
2550 */
2551 if (nparams < 1)
2552 nparams = 1;
2553
2554 r600_pipe_state_add_reg(rstate,
2555 R_0286C4_SPI_VS_OUT_CONFIG,
2556 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2557 NULL, 0);
2558 r600_pipe_state_add_reg(rstate,
2559 R_028860_SQ_PGM_RESOURCES_VS,
2560 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2561 S_028860_STACK_SIZE(rshader->bc.nstack),
2562 NULL, 0);
2563 r600_pipe_state_add_reg(rstate,
2564 R_028864_SQ_PGM_RESOURCES_2_VS,
2565 S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2566 NULL, 0);
2567 r600_pipe_state_add_reg(rstate,
2568 R_02885C_SQ_PGM_START_VS,
2569 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2570 shader->bo, RADEON_USAGE_READ);
2571
2572 r600_pipe_state_add_reg(rstate,
2573 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2574 NULL, 0);
2575
2576 shader->pa_cl_vs_out_cntl =
2577 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2578 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2579 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2580 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2581 }
2582
2583 void evergreen_fetch_shader(struct pipe_context *ctx,
2584 struct r600_vertex_element *ve)
2585 {
2586 struct r600_context *rctx = (struct r600_context *)ctx;
2587 struct r600_pipe_state *rstate = &ve->rstate;
2588 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2589 rstate->nregs = 0;
2590 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2591 0x00000000, NULL, 0);
2592 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2593 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2594 ve->fetch_shader, RADEON_USAGE_READ);
2595 }
2596
2597 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2598 {
2599 struct pipe_depth_stencil_alpha_state dsa;
2600 struct r600_pipe_state *rstate;
2601
2602 memset(&dsa, 0, sizeof(dsa));
2603
2604 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2605 r600_pipe_state_add_reg(rstate,
2606 R_028000_DB_RENDER_CONTROL,
2607 S_028000_DEPTH_COPY_ENABLE(1) |
2608 S_028000_STENCIL_COPY_ENABLE(1) |
2609 S_028000_COPY_CENTROID(1),
2610 NULL, 0);
2611 return rstate;
2612 }
2613
2614 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2615 struct r600_pipe_resource_state *rstate)
2616 {
2617 rstate->id = R600_PIPE_STATE_RESOURCE;
2618
2619 rstate->val[0] = 0;
2620 rstate->bo[0] = NULL;
2621 rstate->val[1] = 0;
2622 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2623 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2624 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2625 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2626 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2627 rstate->val[4] = 0;
2628 rstate->val[5] = 0;
2629 rstate->val[6] = 0;
2630 rstate->val[7] = 0xc0000000;
2631 }
2632
2633
2634 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2635 struct r600_pipe_resource_state *rstate,
2636 struct r600_resource *rbuffer,
2637 unsigned offset, unsigned stride,
2638 enum radeon_bo_usage usage)
2639 {
2640 uint64_t va;
2641
2642 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2643 rstate->bo[0] = rbuffer;
2644 rstate->bo_usage[0] = usage;
2645 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2646 rstate->val[1] = rbuffer->buf->size - offset - 1;
2647 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2648 S_030008_STRIDE(stride) |
2649 (((va + offset) >> 32UL) & 0xFF);
2650 }