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r600g: gpu_shader5 gl_SampleMaskIn support
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
34
35 static INLINE unsigned evergreen_array_mode(unsigned mode)
36 {
37 switch (mode) {
38 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
39 break;
40 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
41 break;
42 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
43 default:
44 case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL;
45 }
46 }
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
184 V_030000_SQ_TEX_DIM_2D;
185 case PIPE_TEXTURE_2D_ARRAY:
186 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
187 V_030000_SQ_TEX_DIM_2D_ARRAY;
188 case PIPE_TEXTURE_3D:
189 return V_030000_SQ_TEX_DIM_3D;
190 case PIPE_TEXTURE_CUBE:
191 case PIPE_TEXTURE_CUBE_ARRAY:
192 return V_030000_SQ_TEX_DIM_CUBEMAP;
193 }
194 }
195
196 static uint32_t r600_translate_dbformat(enum pipe_format format)
197 {
198 switch (format) {
199 case PIPE_FORMAT_Z16_UNORM:
200 return V_028040_Z_16;
201 case PIPE_FORMAT_Z24X8_UNORM:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
203 case PIPE_FORMAT_X8Z24_UNORM:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
205 return V_028040_Z_24;
206 case PIPE_FORMAT_Z32_FLOAT:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
208 return V_028040_Z_32_FLOAT;
209 default:
210 return ~0U;
211 }
212 }
213
214 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
215 {
216 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
217 }
218
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
220 {
221 return r600_translate_colorformat(chip, format) != ~0U &&
222 r600_translate_colorswap(format) != ~0U;
223 }
224
225 static bool r600_is_zs_format_supported(enum pipe_format format)
226 {
227 return r600_translate_dbformat(format) != ~0U;
228 }
229
230 static inline bool r600_is_blending_supported(enum pipe_format format)
231 {
232 return !(util_format_is_pure_integer(format) || util_format_is_depth_or_stencil(format));
233 }
234
235 boolean evergreen_is_format_supported(struct pipe_screen *screen,
236 enum pipe_format format,
237 enum pipe_texture_target target,
238 unsigned sample_count,
239 unsigned usage)
240 {
241 struct r600_screen *rscreen = (struct r600_screen*)screen;
242 unsigned retval = 0;
243
244 if (target >= PIPE_MAX_TEXTURE_TYPES) {
245 R600_ERR("r600: unsupported texture type %d\n", target);
246 return FALSE;
247 }
248
249 if (!util_format_is_supported(format, usage))
250 return FALSE;
251
252 if (sample_count > 1) {
253 if (!rscreen->has_msaa)
254 return FALSE;
255
256 switch (sample_count) {
257 case 2:
258 case 4:
259 case 8:
260 break;
261 default:
262 return FALSE;
263 }
264 }
265
266 if (usage & PIPE_BIND_SAMPLER_VIEW) {
267 if (target == PIPE_BUFFER) {
268 if (r600_is_vertex_format_supported(format))
269 retval |= PIPE_BIND_SAMPLER_VIEW;
270 } else {
271 if (r600_is_sampler_format_supported(screen, format))
272 retval |= PIPE_BIND_SAMPLER_VIEW;
273 }
274 }
275
276 if ((usage & (PIPE_BIND_RENDER_TARGET |
277 PIPE_BIND_DISPLAY_TARGET |
278 PIPE_BIND_SCANOUT |
279 PIPE_BIND_SHARED)) &&
280 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
281 retval |= usage &
282 (PIPE_BIND_RENDER_TARGET |
283 PIPE_BIND_DISPLAY_TARGET |
284 PIPE_BIND_SCANOUT |
285 PIPE_BIND_SHARED);
286 }
287
288 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
289 r600_is_zs_format_supported(format)) {
290 retval |= PIPE_BIND_DEPTH_STENCIL;
291 }
292
293 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
294 r600_is_vertex_format_supported(format)) {
295 retval |= PIPE_BIND_VERTEX_BUFFER;
296 }
297
298 if (usage & PIPE_BIND_TRANSFER_READ)
299 retval |= PIPE_BIND_TRANSFER_READ;
300 if (usage & PIPE_BIND_TRANSFER_WRITE)
301 retval |= PIPE_BIND_TRANSFER_WRITE;
302
303 if ((usage & PIPE_BIND_BLENDABLE) &&
304 r600_is_blending_supported(format))
305 retval |= PIPE_BIND_BLENDABLE;
306
307 return retval == usage;
308 }
309
310 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
311 const struct pipe_blend_state *state, int mode)
312 {
313 uint32_t color_control = 0, target_mask = 0;
314 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
315
316 if (!blend) {
317 return NULL;
318 }
319
320 r600_init_command_buffer(&blend->buffer, 20);
321 r600_init_command_buffer(&blend->buffer_no_blend, 20);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 target_mask |= (state->rt[i].colormask << (4 * i));
332 }
333 } else {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[0].colormask << (4 * i));
336 }
337 }
338
339 /* only have dual source on MRT0 */
340 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
341 blend->cb_target_mask = target_mask;
342 blend->alpha_to_one = state->alpha_to_one;
343
344 if (target_mask)
345 color_control |= S_028808_MODE(mode);
346 else
347 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
348
349
350 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
351 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
358
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
362 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
363
364 for (int i = 0; i < 8; i++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j = state->independent_blend_enable ? i : 0;
367
368 unsigned eqRGB = state->rt[j].rgb_func;
369 unsigned srcRGB = state->rt[j].rgb_src_factor;
370 unsigned dstRGB = state->rt[j].rgb_dst_factor;
371 unsigned eqA = state->rt[j].alpha_func;
372 unsigned srcA = state->rt[j].alpha_src_factor;
373 unsigned dstA = state->rt[j].alpha_dst_factor;
374 uint32_t bc = 0;
375
376 r600_store_value(&blend->buffer_no_blend, 0);
377
378 if (!state->rt[j].blend_enable) {
379 r600_store_value(&blend->buffer, 0);
380 continue;
381 }
382
383 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
385 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
386 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
387
388 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
389 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
391 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
392 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
393 }
394 r600_store_value(&blend->buffer, bc);
395 }
396 return blend;
397 }
398
399 static void *evergreen_create_blend_state(struct pipe_context *ctx,
400 const struct pipe_blend_state *state)
401 {
402
403 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
404 }
405
406 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
407 const struct pipe_depth_stencil_alpha_state *state)
408 {
409 unsigned db_depth_control, alpha_test_control, alpha_ref;
410 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
411
412 if (dsa == NULL) {
413 return NULL;
414 }
415
416 r600_init_command_buffer(&dsa->buffer, 3);
417
418 dsa->valuemask[0] = state->stencil[0].valuemask;
419 dsa->valuemask[1] = state->stencil[1].valuemask;
420 dsa->writemask[0] = state->stencil[0].writemask;
421 dsa->writemask[1] = state->stencil[1].writemask;
422 dsa->zwritemask = state->depth.writemask;
423
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436 if (state->stencil[1].enabled) {
437 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
442 }
443 }
444
445 /* alpha */
446 alpha_test_control = 0;
447 alpha_ref = 0;
448 if (state->alpha.enabled) {
449 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
450 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref = fui(state->alpha.ref_value);
452 }
453 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
454 dsa->alpha_ref = alpha_ref;
455
456 /* misc */
457 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
458 return dsa;
459 }
460
461 static void *evergreen_create_rs_state(struct pipe_context *ctx,
462 const struct pipe_rasterizer_state *state)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465 unsigned tmp, spi_interp;
466 float psize_min, psize_max;
467 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
468
469 if (rs == NULL) {
470 return NULL;
471 }
472
473 r600_init_command_buffer(&rs->buffer, 30);
474
475 rs->flatshade = state->flatshade;
476 rs->sprite_coord_enable = state->sprite_coord_enable;
477 rs->two_side = state->light_twoside;
478 rs->clip_plane_enable = state->clip_plane_enable;
479 rs->pa_sc_line_stipple = state->line_stipple_enable ?
480 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
481 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
482 rs->pa_cl_clip_cntl =
483 S_028810_PS_UCP_MODE(3) |
484 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
485 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
486 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
487 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
488 rs->multisample_enable = state->multisample;
489
490 /* offset */
491 rs->offset_units = state->offset_units;
492 rs->offset_scale = state->offset_scale * 12.0f;
493 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
494
495 if (state->point_size_per_vertex) {
496 psize_min = util_get_min_point_size(state);
497 psize_max = 8192;
498 } else {
499 /* Force the point size to be as if the vertex output was disabled. */
500 psize_min = state->point_size;
501 psize_max = state->point_size;
502 }
503
504 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
505 if (state->sprite_coord_enable) {
506 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
507 S_0286D4_PNT_SPRITE_OVRD_X(2) |
508 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
509 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
510 S_0286D4_PNT_SPRITE_OVRD_W(1);
511 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
512 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
513 }
514 }
515
516 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
517 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
518 tmp = r600_pack_float_12p4(state->point_size/2);
519 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
520 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
521 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
522 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
523 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
524 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
525 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
526
527 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
528 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
529 S_028A48_MSAA_ENABLE(state->multisample) |
530 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
531 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
532
533 if (rctx->b.chip_class == CAYMAN) {
534 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
535 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
536 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
537 } else {
538 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
539 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
540 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
541 }
542
543 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
544 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
545 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
546 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
547 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
548 S_028814_FACE(!state->front_ccw) |
549 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
550 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
551 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
552 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
553 state->fill_back != PIPE_POLYGON_MODE_FILL) |
554 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
555 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
556 return rs;
557 }
558
559 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
560 const struct pipe_sampler_state *state)
561 {
562 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
563 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
564
565 if (ss == NULL) {
566 return NULL;
567 }
568
569 ss->border_color_use = sampler_state_needs_border_color(state);
570
571 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
572 ss->tex_sampler_words[0] =
573 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
574 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
575 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
576 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
577 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
578 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
579 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
580 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
581 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
582 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
583 ss->tex_sampler_words[1] =
584 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
585 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
586 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
587 ss->tex_sampler_words[2] =
588 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
589 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
590 S_03C008_TYPE(1);
591
592 if (ss->border_color_use) {
593 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
594 }
595 return ss;
596 }
597
598 static struct pipe_sampler_view *
599 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
600 unsigned width0, unsigned height0)
601
602 {
603 struct pipe_context *ctx = view->base.context;
604 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
605 uint64_t va;
606 int stride = util_format_get_blocksize(view->base.format);
607 unsigned format, num_format, format_comp, endian;
608 unsigned swizzle_res;
609 unsigned char swizzle[4];
610 const struct util_format_description *desc;
611 unsigned offset = view->base.u.buf.first_element * stride;
612 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
613
614 swizzle[0] = view->base.swizzle_r;
615 swizzle[1] = view->base.swizzle_g;
616 swizzle[2] = view->base.swizzle_b;
617 swizzle[3] = view->base.swizzle_a;
618
619 r600_vertex_data_type(view->base.format,
620 &format, &num_format, &format_comp,
621 &endian);
622
623 desc = util_format_description(view->base.format);
624
625 swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
626
627 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
628 view->tex_resource = &tmp->resource;
629
630 view->skip_mip_address_reloc = true;
631 view->tex_resource_words[0] = va;
632 view->tex_resource_words[1] = size - 1;
633 view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
634 S_030008_STRIDE(stride) |
635 S_030008_DATA_FORMAT(format) |
636 S_030008_NUM_FORMAT_ALL(num_format) |
637 S_030008_FORMAT_COMP_ALL(format_comp) |
638 S_030008_ENDIAN_SWAP(endian);
639 view->tex_resource_words[3] = swizzle_res;
640 /*
641 * in theory dword 4 is for number of elements, for use with resinfo,
642 * but it seems to utterly fail to work, the amd gpu shader analyser
643 * uses a const buffer to store the element sizes for buffer txq
644 */
645 view->tex_resource_words[4] = 0;
646 view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
647 view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
648 return &view->base;
649 }
650
651 struct pipe_sampler_view *
652 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
653 struct pipe_resource *texture,
654 const struct pipe_sampler_view *state,
655 unsigned width0, unsigned height0,
656 unsigned force_level)
657 {
658 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
659 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
660 struct r600_texture *tmp = (struct r600_texture*)texture;
661 unsigned format, endian;
662 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
663 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0;
664 unsigned height, depth, width;
665 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
666 enum pipe_format pipe_format = state->format;
667 struct radeon_surface_level *surflevel;
668 unsigned base_level, first_level, last_level;
669 uint64_t va;
670
671 if (view == NULL)
672 return NULL;
673
674 /* initialize base object */
675 view->base = *state;
676 view->base.texture = NULL;
677 pipe_reference(NULL, &texture->reference);
678 view->base.texture = texture;
679 view->base.reference.count = 1;
680 view->base.context = ctx;
681
682 if (texture->target == PIPE_BUFFER)
683 return texture_buffer_sampler_view(view, width0, height0);
684
685 swizzle[0] = state->swizzle_r;
686 swizzle[1] = state->swizzle_g;
687 swizzle[2] = state->swizzle_b;
688 swizzle[3] = state->swizzle_a;
689
690 tile_split = tmp->surface.tile_split;
691 surflevel = tmp->surface.level;
692
693 /* Texturing with separate depth and stencil. */
694 if (tmp->is_depth && !tmp->is_flushing_texture) {
695 switch (pipe_format) {
696 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
697 pipe_format = PIPE_FORMAT_Z32_FLOAT;
698 break;
699 case PIPE_FORMAT_X8Z24_UNORM:
700 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
701 /* Z24 is always stored like this. */
702 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
703 break;
704 case PIPE_FORMAT_X24S8_UINT:
705 case PIPE_FORMAT_S8X24_UINT:
706 case PIPE_FORMAT_X32_S8X24_UINT:
707 pipe_format = PIPE_FORMAT_S8_UINT;
708 tile_split = tmp->surface.stencil_tile_split;
709 surflevel = tmp->surface.stencil_level;
710 break;
711 default:;
712 }
713 }
714
715 format = r600_translate_texformat(ctx->screen, pipe_format,
716 swizzle,
717 &word4, &yuv_format);
718 assert(format != ~0);
719 if (format == ~0) {
720 FREE(view);
721 return NULL;
722 }
723
724 endian = r600_colorformat_endian_swap(format);
725
726 base_level = 0;
727 first_level = state->u.tex.first_level;
728 last_level = state->u.tex.last_level;
729 width = width0;
730 height = height0;
731 depth = texture->depth0;
732
733 if (force_level) {
734 base_level = force_level;
735 first_level = 0;
736 last_level = 0;
737 width = u_minify(width, force_level);
738 height = u_minify(height, force_level);
739 depth = u_minify(depth, force_level);
740 }
741
742 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
743 non_disp_tiling = tmp->non_disp_tiling;
744
745 switch (surflevel[base_level].mode) {
746 case RADEON_SURF_MODE_LINEAR_ALIGNED:
747 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
748 break;
749 case RADEON_SURF_MODE_2D:
750 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
751 break;
752 case RADEON_SURF_MODE_1D:
753 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
754 break;
755 case RADEON_SURF_MODE_LINEAR:
756 default:
757 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
758 break;
759 }
760 macro_aspect = tmp->surface.mtilea;
761 bankw = tmp->surface.bankw;
762 bankh = tmp->surface.bankh;
763 tile_split = eg_tile_split(tile_split);
764 macro_aspect = eg_macro_tile_aspect(macro_aspect);
765 bankw = eg_bank_wh(bankw);
766 bankh = eg_bank_wh(bankh);
767 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
768
769 /* 128 bit formats require tile type = 1 */
770 if (rscreen->b.chip_class == CAYMAN) {
771 if (util_format_get_blocksize(pipe_format) >= 16)
772 non_disp_tiling = 1;
773 }
774 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
775
776 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
777 height = 1;
778 depth = texture->array_size;
779 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
780 depth = texture->array_size;
781 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
782 depth = texture->array_size / 6;
783
784 va = r600_resource_va(ctx->screen, texture);
785
786 view->tex_resource = &tmp->resource;
787 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
788 S_030000_PITCH((pitch / 8) - 1) |
789 S_030000_TEX_WIDTH(width - 1));
790 if (rscreen->b.chip_class == CAYMAN)
791 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
792 else
793 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
794 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
795 S_030004_TEX_DEPTH(depth - 1) |
796 S_030004_ARRAY_MODE(array_mode));
797 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
798
799 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
800 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
801 if (tmp->is_depth) {
802 /* disable FMASK (0 = disabled) */
803 view->tex_resource_words[3] = 0;
804 view->skip_mip_address_reloc = true;
805 } else {
806 /* FMASK should be in MIP_ADDRESS for multisample textures */
807 view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
808 }
809 } else if (last_level && texture->nr_samples <= 1) {
810 view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
811 } else {
812 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
813 }
814
815 view->tex_resource_words[4] = (word4 |
816 S_030010_ENDIAN_SWAP(endian));
817 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
818 S_030014_LAST_ARRAY(state->u.tex.last_layer);
819 view->tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
820
821 if (texture->nr_samples > 1) {
822 unsigned log_samples = util_logbase2(texture->nr_samples);
823 if (rscreen->b.chip_class == CAYMAN) {
824 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
825 }
826 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
827 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
828 view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
829 } else {
830 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
831 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
832 /* aniso max 16 samples */
833 view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
834 }
835
836 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
837 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
838 S_03001C_BANK_WIDTH(bankw) |
839 S_03001C_BANK_HEIGHT(bankh) |
840 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
841 S_03001C_NUM_BANKS(nbanks) |
842 S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture);
843 return &view->base;
844 }
845
846 static struct pipe_sampler_view *
847 evergreen_create_sampler_view(struct pipe_context *ctx,
848 struct pipe_resource *tex,
849 const struct pipe_sampler_view *state)
850 {
851 return evergreen_create_sampler_view_custom(ctx, tex, state,
852 tex->width0, tex->height0, 0);
853 }
854
855 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
856 {
857 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
858 struct pipe_clip_state *state = &rctx->clip_state.state;
859
860 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
861 radeon_emit_array(cs, (unsigned*)state, 6*4);
862 }
863
864 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
865 const struct pipe_poly_stipple *state)
866 {
867 }
868
869 static void evergreen_get_scissor_rect(struct r600_context *rctx,
870 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
871 uint32_t *tl, uint32_t *br)
872 {
873 /* EG hw workaround */
874 if (br_x == 0)
875 tl_x = 1;
876 if (br_y == 0)
877 tl_y = 1;
878
879 /* cayman hw workaround */
880 if (rctx->b.chip_class == CAYMAN) {
881 if (br_x == 1 && br_y == 1)
882 br_x = 2;
883 }
884
885 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
886 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
887 }
888
889 static void evergreen_set_scissor_states(struct pipe_context *ctx,
890 unsigned start_slot,
891 unsigned num_scissors,
892 const struct pipe_scissor_state *state)
893 {
894 struct r600_context *rctx = (struct r600_context *)ctx;
895 int i;
896
897 for (i = start_slot; i < start_slot + num_scissors; i++) {
898 rctx->scissor[i].scissor = state[i - start_slot];
899 rctx->scissor[i].atom.dirty = true;
900 }
901 }
902
903 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
904 {
905 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
906 struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
907 struct pipe_scissor_state *state = &rstate->scissor;
908 unsigned offset = rstate->idx * 4 * 2;
909 uint32_t tl, br;
910
911 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
912
913 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
914 radeon_emit(cs, tl);
915 radeon_emit(cs, br);
916 }
917
918 /**
919 * This function intializes the CB* register values for RATs. It is meant
920 * to be used for 1D aligned buffers that do not have an associated
921 * radeon_surface.
922 */
923 void evergreen_init_color_surface_rat(struct r600_context *rctx,
924 struct r600_surface *surf)
925 {
926 struct pipe_resource *pipe_buffer = surf->base.texture;
927 unsigned format = r600_translate_colorformat(rctx->b.chip_class,
928 surf->base.format);
929 unsigned endian = r600_colorformat_endian_swap(format);
930 unsigned swap = r600_translate_colorswap(surf->base.format);
931 unsigned block_size =
932 align(util_format_get_blocksize(pipe_buffer->format), 4);
933 unsigned pitch_alignment =
934 MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
935 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
936
937 /* XXX: This is copied from evergreen_init_color_surface(). I don't
938 * know why this is necessary.
939 */
940 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
941 endian = ENDIAN_NONE;
942 }
943
944 surf->cb_color_base =
945 r600_resource_va(rctx->b.b.screen, pipe_buffer) >> 8;
946
947 surf->cb_color_pitch = (pitch / 8) - 1;
948
949 surf->cb_color_slice = 0;
950
951 surf->cb_color_view = 0;
952
953 surf->cb_color_info =
954 S_028C70_ENDIAN(endian)
955 | S_028C70_FORMAT(format)
956 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
957 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
958 | S_028C70_COMP_SWAP(swap)
959 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
960 * are using NUMBER_UINT */
961 | S_028C70_RAT(1)
962 ;
963
964 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
965
966 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
967 * elements. */
968 surf->cb_color_dim = pipe_buffer->width0;
969
970 /* Set the buffer range the GPU will have access to: */
971 util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
972 0, pipe_buffer->width0);
973
974 surf->cb_color_fmask = surf->cb_color_base;
975 surf->cb_color_fmask_slice = 0;
976 }
977
978 void evergreen_init_color_surface(struct r600_context *rctx,
979 struct r600_surface *surf)
980 {
981 struct r600_screen *rscreen = rctx->screen;
982 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
983 struct pipe_resource *pipe_tex = surf->base.texture;
984 unsigned level = surf->base.u.tex.level;
985 unsigned pitch, slice;
986 unsigned color_info, color_attrib, color_dim = 0, color_view;
987 unsigned format, swap, ntype, endian;
988 uint64_t offset, base_offset;
989 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
990 const struct util_format_description *desc;
991 int i;
992 bool blend_clamp = 0, blend_bypass = 0;
993
994 offset = rtex->surface.level[level].offset;
995 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
996 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
997 offset += rtex->surface.level[level].slice_size *
998 surf->base.u.tex.first_layer;
999 color_view = 0;
1000 } else
1001 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1002 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1003
1004 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1005 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1006 if (slice) {
1007 slice = slice - 1;
1008 }
1009 color_info = 0;
1010 switch (rtex->surface.level[level].mode) {
1011 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1012 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1013 non_disp_tiling = 1;
1014 break;
1015 case RADEON_SURF_MODE_1D:
1016 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1017 non_disp_tiling = rtex->non_disp_tiling;
1018 break;
1019 case RADEON_SURF_MODE_2D:
1020 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1021 non_disp_tiling = rtex->non_disp_tiling;
1022 break;
1023 case RADEON_SURF_MODE_LINEAR:
1024 default:
1025 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1026 non_disp_tiling = 1;
1027 break;
1028 }
1029 tile_split = rtex->surface.tile_split;
1030 macro_aspect = rtex->surface.mtilea;
1031 bankw = rtex->surface.bankw;
1032 bankh = rtex->surface.bankh;
1033 fmask_bankh = rtex->fmask.bank_height;
1034 tile_split = eg_tile_split(tile_split);
1035 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1036 bankw = eg_bank_wh(bankw);
1037 bankh = eg_bank_wh(bankh);
1038 fmask_bankh = eg_bank_wh(fmask_bankh);
1039
1040 /* 128 bit formats require tile type = 1 */
1041 if (rscreen->b.chip_class == CAYMAN) {
1042 if (util_format_get_blocksize(surf->base.format) >= 16)
1043 non_disp_tiling = 1;
1044 }
1045 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1046 desc = util_format_description(surf->base.format);
1047 for (i = 0; i < 4; i++) {
1048 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1049 break;
1050 }
1051 }
1052
1053 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1054 S_028C74_NUM_BANKS(nbanks) |
1055 S_028C74_BANK_WIDTH(bankw) |
1056 S_028C74_BANK_HEIGHT(bankh) |
1057 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1058 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1059 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1060
1061 if (rctx->b.chip_class == CAYMAN) {
1062 color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1063 UTIL_FORMAT_SWIZZLE_1);
1064
1065 if (rtex->resource.b.b.nr_samples > 1) {
1066 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1067 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1068 S_028C74_NUM_FRAGMENTS(log_samples);
1069 }
1070 }
1071
1072 ntype = V_028C70_NUMBER_UNORM;
1073 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1074 ntype = V_028C70_NUMBER_SRGB;
1075 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1076 if (desc->channel[i].normalized)
1077 ntype = V_028C70_NUMBER_SNORM;
1078 else if (desc->channel[i].pure_integer)
1079 ntype = V_028C70_NUMBER_SINT;
1080 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1081 if (desc->channel[i].normalized)
1082 ntype = V_028C70_NUMBER_UNORM;
1083 else if (desc->channel[i].pure_integer)
1084 ntype = V_028C70_NUMBER_UINT;
1085 }
1086
1087 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
1088 assert(format != ~0);
1089
1090 swap = r600_translate_colorswap(surf->base.format);
1091 assert(swap != ~0);
1092
1093 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1094 endian = ENDIAN_NONE;
1095 } else {
1096 endian = r600_colorformat_endian_swap(format);
1097 }
1098
1099 /* blend clamp should be set for all NORM/SRGB types */
1100 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1101 ntype == V_028C70_NUMBER_SRGB)
1102 blend_clamp = 1;
1103
1104 /* set blend bypass according to docs if SINT/UINT or
1105 8/24 COLOR variants */
1106 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1107 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1108 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1109 blend_clamp = 0;
1110 blend_bypass = 1;
1111 }
1112
1113 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1114
1115 color_info |= S_028C70_FORMAT(format) |
1116 S_028C70_COMP_SWAP(swap) |
1117 S_028C70_BLEND_CLAMP(blend_clamp) |
1118 S_028C70_BLEND_BYPASS(blend_bypass) |
1119 S_028C70_NUMBER_TYPE(ntype) |
1120 S_028C70_ENDIAN(endian);
1121
1122 /* EXPORT_NORM is an optimzation that can be enabled for better
1123 * performance in certain cases.
1124 * EXPORT_NORM can be enabled if:
1125 * - 11-bit or smaller UNORM/SNORM/SRGB
1126 * - 16-bit or smaller FLOAT
1127 */
1128 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1129 ((desc->channel[i].size < 12 &&
1130 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1131 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1132 (desc->channel[i].size < 17 &&
1133 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1134 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1135 surf->export_16bpc = true;
1136 }
1137
1138 if (rtex->fmask.size) {
1139 color_info |= S_028C70_COMPRESSION(1);
1140 }
1141
1142 base_offset = r600_resource_va(rctx->b.b.screen, pipe_tex);
1143
1144 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1145 surf->cb_color_base = (base_offset + offset) >> 8;
1146 surf->cb_color_dim = color_dim;
1147 surf->cb_color_info = color_info;
1148 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1149 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1150 surf->cb_color_view = color_view;
1151 surf->cb_color_attrib = color_attrib;
1152 if (rtex->fmask.size) {
1153 surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
1154 } else {
1155 surf->cb_color_fmask = surf->cb_color_base;
1156 }
1157 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1158
1159 surf->color_initialized = true;
1160 }
1161
1162 static void evergreen_init_depth_surface(struct r600_context *rctx,
1163 struct r600_surface *surf)
1164 {
1165 struct r600_screen *rscreen = rctx->screen;
1166 struct pipe_screen *screen = &rscreen->b.b;
1167 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1168 uint64_t offset;
1169 unsigned level, pitch, slice, format, array_mode;
1170 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1171
1172 level = surf->base.u.tex.level;
1173 format = r600_translate_dbformat(surf->base.format);
1174 assert(format != ~0);
1175
1176 offset = r600_resource_va(screen, surf->base.texture);
1177 offset += rtex->surface.level[level].offset;
1178 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1179 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1180 if (slice) {
1181 slice = slice - 1;
1182 }
1183 switch (rtex->surface.level[level].mode) {
1184 case RADEON_SURF_MODE_2D:
1185 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1186 break;
1187 case RADEON_SURF_MODE_1D:
1188 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1189 case RADEON_SURF_MODE_LINEAR:
1190 default:
1191 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1192 break;
1193 }
1194 tile_split = rtex->surface.tile_split;
1195 macro_aspect = rtex->surface.mtilea;
1196 bankw = rtex->surface.bankw;
1197 bankh = rtex->surface.bankh;
1198 tile_split = eg_tile_split(tile_split);
1199 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1200 bankw = eg_bank_wh(bankw);
1201 bankh = eg_bank_wh(bankh);
1202 nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
1203 offset >>= 8;
1204
1205 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1206 S_028040_FORMAT(format) |
1207 S_028040_TILE_SPLIT(tile_split)|
1208 S_028040_NUM_BANKS(nbanks) |
1209 S_028040_BANK_WIDTH(bankw) |
1210 S_028040_BANK_HEIGHT(bankh) |
1211 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1212 if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1213 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1214 }
1215 surf->db_depth_base = offset;
1216 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1217 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1218 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1219 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1220
1221 switch (surf->base.format) {
1222 case PIPE_FORMAT_Z24X8_UNORM:
1223 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1224 case PIPE_FORMAT_X8Z24_UNORM:
1225 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1226 surf->pa_su_poly_offset_db_fmt_cntl =
1227 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1228 break;
1229 case PIPE_FORMAT_Z32_FLOAT:
1230 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1231 surf->pa_su_poly_offset_db_fmt_cntl =
1232 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1233 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1234 break;
1235 case PIPE_FORMAT_Z16_UNORM:
1236 surf->pa_su_poly_offset_db_fmt_cntl =
1237 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1238 break;
1239 default:;
1240 }
1241
1242 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1243 uint64_t stencil_offset;
1244 unsigned stile_split = rtex->surface.stencil_tile_split;
1245
1246 stile_split = eg_tile_split(stile_split);
1247
1248 stencil_offset = rtex->surface.stencil_level[level].offset;
1249 stencil_offset += r600_resource_va(screen, surf->base.texture);
1250
1251 surf->db_stencil_base = stencil_offset >> 8;
1252 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1253 S_028044_TILE_SPLIT(stile_split);
1254 } else {
1255 surf->db_stencil_base = offset;
1256 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1257 * Older kernels are out of luck. */
1258 surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
1259 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1260 S_028044_FORMAT(V_028044_STENCIL_8);
1261 }
1262
1263 /* use htile only for first level */
1264 if (rtex->htile_buffer && !level) {
1265 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1266 surf->db_htile_data_base = va >> 8;
1267 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1268 S_028ABC_HTILE_HEIGHT(1) |
1269 S_028ABC_FULL_CACHE(1) |
1270 S_028ABC_LINEAR(1);
1271 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1272 surf->db_preload_control = 0;
1273 }
1274
1275 surf->depth_initialized = true;
1276 }
1277
1278 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1279 const struct pipe_framebuffer_state *state)
1280 {
1281 struct r600_context *rctx = (struct r600_context *)ctx;
1282 struct r600_surface *surf;
1283 struct r600_texture *rtex;
1284 uint32_t i, log_samples;
1285
1286 if (rctx->framebuffer.state.nr_cbufs) {
1287 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1288 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1289 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1290 }
1291 if (rctx->framebuffer.state.zsbuf) {
1292 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1293 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1294
1295 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1296 if (rtex->htile_buffer) {
1297 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1298 }
1299 }
1300
1301 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1302
1303 /* Colorbuffers. */
1304 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1305 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1306 util_format_is_pure_integer(state->cbufs[0]->format);
1307 rctx->framebuffer.compressed_cb_mask = 0;
1308 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1309
1310 for (i = 0; i < state->nr_cbufs; i++) {
1311 surf = (struct r600_surface*)state->cbufs[i];
1312 if (!surf)
1313 continue;
1314
1315 rtex = (struct r600_texture*)surf->base.texture;
1316
1317 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1318
1319 if (!surf->color_initialized) {
1320 evergreen_init_color_surface(rctx, surf);
1321 }
1322
1323 if (!surf->export_16bpc) {
1324 rctx->framebuffer.export_16bpc = false;
1325 }
1326
1327 if (rtex->fmask.size && rtex->cmask.size) {
1328 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1329 }
1330 }
1331
1332 /* Update alpha-test state dependencies.
1333 * Alpha-test is done on the first colorbuffer only. */
1334 if (state->nr_cbufs) {
1335 bool alphatest_bypass = false;
1336 bool export_16bpc = true;
1337
1338 surf = (struct r600_surface*)state->cbufs[0];
1339 if (surf) {
1340 alphatest_bypass = surf->alphatest_bypass;
1341 export_16bpc = surf->export_16bpc;
1342 }
1343
1344 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1345 rctx->alphatest_state.bypass = alphatest_bypass;
1346 rctx->alphatest_state.atom.dirty = true;
1347 }
1348 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1349 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1350 rctx->alphatest_state.atom.dirty = true;
1351 }
1352 }
1353
1354 /* ZS buffer. */
1355 if (state->zsbuf) {
1356 surf = (struct r600_surface*)state->zsbuf;
1357
1358 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1359
1360 if (!surf->depth_initialized) {
1361 evergreen_init_depth_surface(rctx, surf);
1362 }
1363
1364 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1365 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1366 rctx->poly_offset_state.atom.dirty = true;
1367 }
1368
1369 if (rctx->db_state.rsurf != surf) {
1370 rctx->db_state.rsurf = surf;
1371 rctx->db_state.atom.dirty = true;
1372 rctx->db_misc_state.atom.dirty = true;
1373 }
1374 } else if (rctx->db_state.rsurf) {
1375 rctx->db_state.rsurf = NULL;
1376 rctx->db_state.atom.dirty = true;
1377 rctx->db_misc_state.atom.dirty = true;
1378 }
1379
1380 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1381 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1382 rctx->cb_misc_state.atom.dirty = true;
1383 }
1384
1385 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1386 rctx->alphatest_state.bypass = false;
1387 rctx->alphatest_state.atom.dirty = true;
1388 }
1389
1390 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1391 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1392 if ((rctx->b.chip_class == CAYMAN ||
1393 rctx->b.family == CHIP_RV770) &&
1394 rctx->db_misc_state.log_samples != log_samples) {
1395 rctx->db_misc_state.log_samples = log_samples;
1396 rctx->db_misc_state.atom.dirty = true;
1397 }
1398
1399
1400 /* Calculate the CS size. */
1401 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1402
1403 /* MSAA. */
1404 if (rctx->b.chip_class == EVERGREEN)
1405 rctx->framebuffer.atom.num_dw += 14; /* Evergreen */
1406 else
1407 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1408
1409 /* Colorbuffers. */
1410 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1411 if (rctx->keep_tiling_flags)
1412 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1413 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1414
1415 /* ZS buffer. */
1416 if (state->zsbuf) {
1417 rctx->framebuffer.atom.num_dw += 24;
1418 if (rctx->keep_tiling_flags)
1419 rctx->framebuffer.atom.num_dw += 2;
1420 } else if (rctx->screen->b.info.drm_minor >= 18) {
1421 rctx->framebuffer.atom.num_dw += 4;
1422 }
1423
1424 rctx->framebuffer.atom.dirty = true;
1425 }
1426
1427
1428 /* 8xMSAA */
1429 static uint32_t sample_locs_8x[] = {
1430 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1431 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1432 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1433 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1434 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1435 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1436 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1437 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1438 };
1439 static unsigned max_dist_8x = 7;
1440
1441 static void evergreen_get_sample_position(struct pipe_context *ctx,
1442 unsigned sample_count,
1443 unsigned sample_index,
1444 float *out_value)
1445 {
1446 int offset, index;
1447 struct {
1448 int idx:4;
1449 } val;
1450 switch (sample_count) {
1451 case 1:
1452 default:
1453 out_value[0] = out_value[1] = 0.5;
1454 break;
1455 case 2:
1456 offset = 4 * (sample_index * 2);
1457 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1458 out_value[0] = (float)(val.idx + 8) / 16.0f;
1459 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1460 out_value[1] = (float)(val.idx + 8) / 16.0f;
1461 break;
1462 case 4:
1463 offset = 4 * (sample_index * 2);
1464 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1465 out_value[0] = (float)(val.idx + 8) / 16.0f;
1466 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1467 out_value[1] = (float)(val.idx + 8) / 16.0f;
1468 break;
1469 case 8:
1470 offset = 4 * (sample_index % 4 * 2);
1471 index = (sample_index / 4);
1472 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1473 out_value[0] = (float)(val.idx + 8) / 16.0f;
1474 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1475 out_value[1] = (float)(val.idx + 8) / 16.0f;
1476 break;
1477 }
1478 }
1479
1480 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1481 {
1482
1483 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1484 unsigned max_dist = 0;
1485
1486 switch (nr_samples) {
1487 default:
1488 nr_samples = 0;
1489 break;
1490 case 2:
1491 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
1492 radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
1493 max_dist = eg_max_dist_2x;
1494 break;
1495 case 4:
1496 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
1497 radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
1498 max_dist = eg_max_dist_4x;
1499 break;
1500 case 8:
1501 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1502 radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
1503 max_dist = max_dist_8x;
1504 break;
1505 }
1506
1507 if (nr_samples > 1) {
1508 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1509 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1510 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1511 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1512 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1513 } else {
1514 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1515 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1516 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1517 }
1518 }
1519
1520 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1521 {
1522 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1523 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1524 unsigned nr_cbufs = state->nr_cbufs;
1525 unsigned i, tl, br;
1526 struct r600_texture *tex = NULL;
1527 struct r600_surface *cb = NULL;
1528
1529 /* XXX support more colorbuffers once we need them */
1530 assert(nr_cbufs <= 8);
1531 if (nr_cbufs > 8)
1532 nr_cbufs = 8;
1533
1534 /* Colorbuffers. */
1535 for (i = 0; i < nr_cbufs; i++) {
1536 unsigned reloc, cmask_reloc;
1537
1538 cb = (struct r600_surface*)state->cbufs[i];
1539 if (!cb) {
1540 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1541 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1542 continue;
1543 }
1544
1545 tex = (struct r600_texture *)cb->base.texture;
1546 reloc = r600_context_bo_reloc(&rctx->b,
1547 &rctx->b.rings.gfx,
1548 (struct r600_resource*)cb->base.texture,
1549 RADEON_USAGE_READWRITE,
1550 tex->surface.nsamples > 1 ?
1551 RADEON_PRIO_COLOR_BUFFER_MSAA :
1552 RADEON_PRIO_COLOR_BUFFER);
1553
1554 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1555 cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1556 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1557 RADEON_PRIO_COLOR_META);
1558 } else {
1559 cmask_reloc = reloc;
1560 }
1561
1562 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1563 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1564 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1565 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1566 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1567 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1568 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1569 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1570 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1571 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1572 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1573 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1574 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1575 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1576
1577 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1578 radeon_emit(cs, reloc);
1579
1580 if (!rctx->keep_tiling_flags) {
1581 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1582 radeon_emit(cs, reloc);
1583 }
1584
1585 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1586 radeon_emit(cs, reloc);
1587
1588 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1589 radeon_emit(cs, cmask_reloc);
1590
1591 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1592 radeon_emit(cs, reloc);
1593 }
1594 /* set CB_COLOR1_INFO for possible dual-src blending */
1595 if (i == 1 && state->cbufs[0]) {
1596 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1597 cb->cb_color_info | tex->cb_color_info);
1598
1599 if (!rctx->keep_tiling_flags) {
1600 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1601 &rctx->b.rings.gfx,
1602 (struct r600_resource*)state->cbufs[0]->texture,
1603 RADEON_USAGE_READWRITE,
1604 RADEON_PRIO_COLOR_BUFFER);
1605
1606 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1607 radeon_emit(cs, reloc);
1608 }
1609 i++;
1610 }
1611 if (rctx->keep_tiling_flags) {
1612 for (; i < 8 ; i++) {
1613 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1614 }
1615 for (; i < 12; i++) {
1616 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1617 }
1618 }
1619
1620 /* ZS buffer. */
1621 if (state->zsbuf) {
1622 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1623 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1624 &rctx->b.rings.gfx,
1625 (struct r600_resource*)state->zsbuf->texture,
1626 RADEON_USAGE_READWRITE,
1627 zb->base.texture->nr_samples > 1 ?
1628 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1629 RADEON_PRIO_DEPTH_BUFFER);
1630
1631 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1632 zb->pa_su_poly_offset_db_fmt_cntl);
1633 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1634
1635 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1636 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1637 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1638 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1639 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1640 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1641 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1642 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1643 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1644
1645 if (!rctx->keep_tiling_flags) {
1646 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
1647 radeon_emit(cs, reloc);
1648 }
1649
1650 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1651 radeon_emit(cs, reloc);
1652
1653 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1654 radeon_emit(cs, reloc);
1655
1656 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1657 radeon_emit(cs, reloc);
1658
1659 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1660 radeon_emit(cs, reloc);
1661 } else if (rctx->screen->b.info.drm_minor >= 18) {
1662 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1663 * Older kernels are out of luck. */
1664 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1665 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1666 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1667 }
1668
1669 /* Framebuffer dimensions. */
1670 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1671
1672 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1673 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1674 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1675
1676 if (rctx->b.chip_class == EVERGREEN) {
1677 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1678 } else {
1679 cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples);
1680 cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, 1);
1681 }
1682 }
1683
1684 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1685 {
1686 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1687 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1688 float offset_units = state->offset_units;
1689 float offset_scale = state->offset_scale;
1690
1691 switch (state->zs_format) {
1692 case PIPE_FORMAT_Z24X8_UNORM:
1693 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1694 case PIPE_FORMAT_X8Z24_UNORM:
1695 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1696 offset_units *= 2.0f;
1697 break;
1698 case PIPE_FORMAT_Z16_UNORM:
1699 offset_units *= 4.0f;
1700 break;
1701 default:;
1702 }
1703
1704 r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1705 radeon_emit(cs, fui(offset_scale));
1706 radeon_emit(cs, fui(offset_units));
1707 radeon_emit(cs, fui(offset_scale));
1708 radeon_emit(cs, fui(offset_units));
1709 }
1710
1711 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1712 {
1713 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1714 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1715 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1716 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1717
1718 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1719 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1720 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1721 * will assure that the alpha-test will work even if there is
1722 * no colorbuffer bound. */
1723 radeon_emit(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1724 }
1725
1726 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1727 {
1728 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1729 struct r600_db_state *a = (struct r600_db_state*)atom;
1730
1731 if (a->rsurf && a->rsurf->db_htile_surface) {
1732 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1733 unsigned reloc_idx;
1734
1735 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1736 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1737 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
1738 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1739 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1740 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1741 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1742 cs->buf[cs->cdw++] = reloc_idx;
1743 } else {
1744 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
1745 r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
1746 }
1747 }
1748
1749 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1750 {
1751 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1752 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1753 unsigned db_render_control = 0;
1754 unsigned db_count_control = 0;
1755 unsigned db_render_override =
1756 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1757 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1758
1759 if (a->occlusion_query_enabled) {
1760 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1761 if (rctx->b.chip_class == CAYMAN) {
1762 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1763 }
1764 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1765 }
1766 /* FIXME we should be able to use hyperz even if we are not writing to
1767 * zbuffer but somehow this trigger GPU lockup. See :
1768 *
1769 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
1770 *
1771 * Disable hyperz for now if not writing to zbuffer.
1772 */
1773 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface && rctx->zwritemask) {
1774 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1775 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
1776 /* This is to fix a lockup when hyperz and alpha test are enabled at
1777 * the same time somehow GPU get confuse on which order to pick for
1778 * z test
1779 */
1780 if (rctx->alphatest_state.sx_alpha_test_control) {
1781 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
1782 }
1783 } else {
1784 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
1785 }
1786 if (a->flush_depthstencil_through_cb) {
1787 assert(a->copy_depth || a->copy_stencil);
1788
1789 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1790 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1791 S_028000_COPY_CENTROID(1) |
1792 S_028000_COPY_SAMPLE(a->copy_sample);
1793 } else if (a->flush_depthstencil_in_place) {
1794 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(1) |
1795 S_028000_STENCIL_COMPRESS_DISABLE(1);
1796 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1797 }
1798 if (a->htile_clear) {
1799 /* FIXME we might want to disable cliprect here */
1800 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
1801 }
1802
1803 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1804 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1805 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1806 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1807 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1808 }
1809
1810 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1811 struct r600_vertexbuf_state *state,
1812 unsigned resource_offset,
1813 unsigned pkt_flags)
1814 {
1815 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1816 uint32_t dirty_mask = state->dirty_mask;
1817
1818 while (dirty_mask) {
1819 struct pipe_vertex_buffer *vb;
1820 struct r600_resource *rbuffer;
1821 uint64_t va;
1822 unsigned buffer_index = u_bit_scan(&dirty_mask);
1823
1824 vb = &state->vb[buffer_index];
1825 rbuffer = (struct r600_resource*)vb->buffer;
1826 assert(rbuffer);
1827
1828 va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
1829 va += vb->buffer_offset;
1830
1831 /* fetch resources start at index 992 */
1832 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1833 radeon_emit(cs, (resource_offset + buffer_index) * 8);
1834 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1835 radeon_emit(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1836 radeon_emit(cs, /* RESOURCEi_WORD2 */
1837 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1838 S_030008_STRIDE(vb->stride) |
1839 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1840 radeon_emit(cs, /* RESOURCEi_WORD3 */
1841 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1842 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1843 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1844 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1845 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1846 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1847 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1848 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1849
1850 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1851 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1852 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1853 }
1854 state->dirty_mask = 0;
1855 }
1856
1857 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1858 {
1859 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1860 }
1861
1862 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1863 {
1864 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1865 RADEON_CP_PACKET3_COMPUTE_MODE);
1866 }
1867
1868 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1869 struct r600_constbuf_state *state,
1870 unsigned buffer_id_base,
1871 unsigned reg_alu_constbuf_size,
1872 unsigned reg_alu_const_cache,
1873 unsigned pkt_flags)
1874 {
1875 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1876 uint32_t dirty_mask = state->dirty_mask;
1877
1878 while (dirty_mask) {
1879 struct pipe_constant_buffer *cb;
1880 struct r600_resource *rbuffer;
1881 uint64_t va;
1882 unsigned buffer_index = ffs(dirty_mask) - 1;
1883 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1884
1885 cb = &state->cb[buffer_index];
1886 rbuffer = (struct r600_resource*)cb->buffer;
1887 assert(rbuffer);
1888
1889 va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
1890 va += cb->buffer_offset;
1891
1892 if (!gs_ring_buffer) {
1893 r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
1894 ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
1895 r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
1896 pkt_flags);
1897 }
1898
1899 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1900 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1901 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1902
1903 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1904 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
1905 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
1906 radeon_emit(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1907 radeon_emit(cs, /* RESOURCEi_WORD2 */
1908 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1909 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
1910 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
1911 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
1912 radeon_emit(cs, /* RESOURCEi_WORD3 */
1913 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
1914 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1915 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1916 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1917 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1918 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1919 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1920 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
1921 radeon_emit(cs, /* RESOURCEi_WORD7 */
1922 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
1923
1924 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1925 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1926 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1927
1928 dirty_mask &= ~(1 << buffer_index);
1929 }
1930 state->dirty_mask = 0;
1931 }
1932
1933 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1934 {
1935 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
1936 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1937 R_028980_ALU_CONST_CACHE_VS_0,
1938 0 /* PKT3 flags */);
1939 }
1940
1941 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1942 {
1943 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1944 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1945 R_0289C0_ALU_CONST_CACHE_GS_0,
1946 0 /* PKT3 flags */);
1947 }
1948
1949 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1950 {
1951 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1952 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1953 R_028940_ALU_CONST_CACHE_PS_0,
1954 0 /* PKT3 flags */);
1955 }
1956
1957 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1958 {
1959 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 816,
1960 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
1961 R_028F40_ALU_CONST_CACHE_LS_0,
1962 RADEON_CP_PACKET3_COMPUTE_MODE);
1963 }
1964
1965 static void evergreen_emit_sampler_views(struct r600_context *rctx,
1966 struct r600_samplerview_state *state,
1967 unsigned resource_id_base)
1968 {
1969 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1970 uint32_t dirty_mask = state->dirty_mask;
1971
1972 while (dirty_mask) {
1973 struct r600_pipe_sampler_view *rview;
1974 unsigned resource_index = u_bit_scan(&dirty_mask);
1975 unsigned reloc;
1976
1977 rview = state->views[resource_index];
1978 assert(rview);
1979
1980 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1981 radeon_emit(cs, (resource_id_base + resource_index) * 8);
1982 radeon_emit_array(cs, rview->tex_resource_words, 8);
1983
1984 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1985 RADEON_USAGE_READ,
1986 rview->tex_resource->b.b.nr_samples > 1 ?
1987 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1988 RADEON_PRIO_SHADER_TEXTURE_RO);
1989 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1990 radeon_emit(cs, reloc);
1991
1992 if (!rview->skip_mip_address_reloc) {
1993 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1994 radeon_emit(cs, reloc);
1995 }
1996 }
1997 state->dirty_mask = 0;
1998 }
1999
2000 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2001 {
2002 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2003 }
2004
2005 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2006 {
2007 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2008 }
2009
2010 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2011 {
2012 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2013 }
2014
2015 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2016 struct r600_textures_info *texinfo,
2017 unsigned resource_id_base,
2018 unsigned border_index_reg)
2019 {
2020 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2021 uint32_t dirty_mask = texinfo->states.dirty_mask;
2022
2023 while (dirty_mask) {
2024 struct r600_pipe_sampler_state *rstate;
2025 unsigned i = u_bit_scan(&dirty_mask);
2026
2027 rstate = texinfo->states.states[i];
2028 assert(rstate);
2029
2030 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2031 radeon_emit(cs, (resource_id_base + i) * 3);
2032 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2033
2034 if (rstate->border_color_use) {
2035 r600_write_config_reg_seq(cs, border_index_reg, 5);
2036 radeon_emit(cs, i);
2037 radeon_emit_array(cs, rstate->border_color.ui, 4);
2038 }
2039 }
2040 texinfo->states.dirty_mask = 0;
2041 }
2042
2043 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2044 {
2045 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2046 }
2047
2048 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2049 {
2050 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2051 }
2052
2053 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2054 {
2055 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2056 }
2057
2058 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2059 {
2060 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2061 uint8_t mask = s->sample_mask;
2062
2063 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2064 mask | (mask << 8) | (mask << 16) | (mask << 24));
2065 }
2066
2067 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2068 {
2069 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2070 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2071 uint16_t mask = s->sample_mask;
2072
2073 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2074 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2075 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2076 }
2077
2078 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2079 {
2080 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2081 struct r600_cso_state *state = (struct r600_cso_state*)a;
2082 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2083
2084 r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2085 (r600_resource_va(rctx->b.b.screen, &shader->buffer->b.b) + shader->offset) >> 8);
2086 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2087 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
2088 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
2089 }
2090
2091 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2092 {
2093 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2094 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2095
2096 uint32_t v = 0, v2 = 0, primid = 0;
2097
2098 if (state->geom_enable) {
2099 uint32_t cut_val;
2100
2101 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
2102 cut_val = V_028A40_GS_CUT_128;
2103 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
2104 cut_val = V_028A40_GS_CUT_256;
2105 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
2106 cut_val = V_028A40_GS_CUT_512;
2107 else
2108 cut_val = V_028A40_GS_CUT_1024;
2109 v = S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2110 S_028B54_GS_EN(1) |
2111 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2112
2113 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2114 S_028A40_CUT_MODE(cut_val);
2115
2116 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2117 primid = 1;
2118 }
2119
2120 r600_write_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2121 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2122 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2123 }
2124
2125 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2126 {
2127 struct pipe_screen *screen = rctx->b.b.screen;
2128 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2129 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2130 struct r600_resource *rbuffer;
2131
2132 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2133 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2134 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2135
2136 if (state->enable) {
2137 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2138 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2139 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
2140 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2141 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
2142 RADEON_USAGE_READWRITE,
2143 RADEON_PRIO_SHADER_RESOURCE_RW));
2144 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2145 state->esgs_ring.buffer_size >> 8);
2146
2147 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2148 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2149 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
2150 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2151 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
2152 RADEON_USAGE_READWRITE,
2153 RADEON_PRIO_SHADER_RESOURCE_RW));
2154 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2155 state->gsvs_ring.buffer_size >> 8);
2156 } else {
2157 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2158 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2159 }
2160
2161 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2162 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2163 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2164 }
2165
2166 void cayman_init_common_regs(struct r600_command_buffer *cb,
2167 enum chip_class ctx_chip_class,
2168 enum radeon_family ctx_family,
2169 int ctx_drm_minor)
2170 {
2171 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2172 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2173 /* always set the temp clauses */
2174 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2175
2176 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2177 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2178 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2179
2180 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2181
2182 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2183 r600_store_value(cb, 0);
2184 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2185
2186 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2187 }
2188
2189 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2190 {
2191 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2192 int tmp;
2193
2194 r600_init_command_buffer(cb, 256);
2195
2196 /* This must be first. */
2197 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2198 r600_store_value(cb, 0x80000000);
2199 r600_store_value(cb, 0x80000000);
2200
2201 /* We're setting config registers here. */
2202 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2203 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2204
2205 cayman_init_common_regs(cb, rctx->b.chip_class,
2206 rctx->b.family, rctx->screen->b.info.drm_minor);
2207
2208 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2209 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2210
2211 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2212 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2213 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2214 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2215 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2216 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2217 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2218
2219 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2220 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2221 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2222 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2223 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2224
2225 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2226 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2227 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2228 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2229 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2230 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2231 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2232 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2233 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2234 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2235 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2236 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2237 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2238 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2239
2240 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2241
2242 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2243 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2244 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2245
2246 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2247
2248 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2249
2250 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2251 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2252 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2253
2254 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2255 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2256 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2257
2258 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2259
2260 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2261 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2262 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2263
2264 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2265
2266 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2267
2268 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2269
2270 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2271 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2272 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2273 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2274
2275 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2276 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2277
2278 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2279 for (tmp = 0; tmp < 16; tmp++) {
2280 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2281 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2282 }
2283
2284 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2285 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2286
2287 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2288 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2289 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2290 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2291 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2292
2293 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2294 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2295 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2296
2297 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2298 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2299 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2300
2301 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2302 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2303 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2304
2305 /* to avoid GPU doing any preloading of constant from random address */
2306 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2307 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2308 r600_store_value(cb, 0);
2309 r600_store_value(cb, 0);
2310 r600_store_value(cb, 0);
2311 r600_store_value(cb, 0);
2312 r600_store_value(cb, 0);
2313 r600_store_value(cb, 0);
2314 r600_store_value(cb, 0);
2315 r600_store_value(cb, 0);
2316 r600_store_value(cb, 0);
2317 r600_store_value(cb, 0);
2318 r600_store_value(cb, 0);
2319 r600_store_value(cb, 0);
2320 r600_store_value(cb, 0);
2321 r600_store_value(cb, 0);
2322 r600_store_value(cb, 0);
2323
2324 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2325 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2326 r600_store_value(cb, 0);
2327 r600_store_value(cb, 0);
2328 r600_store_value(cb, 0);
2329 r600_store_value(cb, 0);
2330 r600_store_value(cb, 0);
2331 r600_store_value(cb, 0);
2332 r600_store_value(cb, 0);
2333 r600_store_value(cb, 0);
2334 r600_store_value(cb, 0);
2335 r600_store_value(cb, 0);
2336 r600_store_value(cb, 0);
2337 r600_store_value(cb, 0);
2338 r600_store_value(cb, 0);
2339 r600_store_value(cb, 0);
2340 r600_store_value(cb, 0);
2341
2342 if (rctx->screen->b.has_streamout) {
2343 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2344 }
2345
2346 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2347 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2348 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2349 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2350 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2351 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2352 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
2353
2354 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2355 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2356 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2357 }
2358
2359 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2360 enum chip_class ctx_chip_class,
2361 enum radeon_family ctx_family,
2362 int ctx_drm_minor)
2363 {
2364 int ps_prio;
2365 int vs_prio;
2366 int gs_prio;
2367 int es_prio;
2368
2369 int hs_prio;
2370 int cs_prio;
2371 int ls_prio;
2372
2373 int num_ps_gprs;
2374 int num_vs_gprs;
2375 int num_gs_gprs;
2376 int num_es_gprs;
2377 int num_hs_gprs;
2378 int num_ls_gprs;
2379 int num_temp_gprs;
2380
2381 unsigned tmp;
2382
2383 ps_prio = 0;
2384 vs_prio = 1;
2385 gs_prio = 2;
2386 es_prio = 3;
2387 hs_prio = 0;
2388 ls_prio = 0;
2389 cs_prio = 0;
2390
2391 num_ps_gprs = 93;
2392 num_vs_gprs = 46;
2393 num_temp_gprs = 4;
2394 num_gs_gprs = 31;
2395 num_es_gprs = 31;
2396 num_hs_gprs = 23;
2397 num_ls_gprs = 23;
2398
2399 tmp = 0;
2400 switch (ctx_family) {
2401 case CHIP_CEDAR:
2402 case CHIP_PALM:
2403 case CHIP_SUMO:
2404 case CHIP_SUMO2:
2405 case CHIP_CAICOS:
2406 break;
2407 default:
2408 tmp |= S_008C00_VC_ENABLE(1);
2409 break;
2410 }
2411 tmp |= S_008C00_EXPORT_SRC_C(1);
2412 tmp |= S_008C00_CS_PRIO(cs_prio);
2413 tmp |= S_008C00_LS_PRIO(ls_prio);
2414 tmp |= S_008C00_HS_PRIO(hs_prio);
2415 tmp |= S_008C00_PS_PRIO(ps_prio);
2416 tmp |= S_008C00_VS_PRIO(vs_prio);
2417 tmp |= S_008C00_GS_PRIO(gs_prio);
2418 tmp |= S_008C00_ES_PRIO(es_prio);
2419
2420 /* enable dynamic GPR resource management */
2421 if (ctx_drm_minor >= 7) {
2422 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2423 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2424 /* always set temp clauses */
2425 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2426 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2427 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2428 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2429 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2430 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2431 S_028838_PS_GPRS(0x1e) |
2432 S_028838_VS_GPRS(0x1e) |
2433 S_028838_GS_GPRS(0x1e) |
2434 S_028838_ES_GPRS(0x1e) |
2435 S_028838_HS_GPRS(0x1e) |
2436 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2437 } else {
2438 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2439 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2440
2441 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2442 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2443 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2444 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2445
2446 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2447 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2448 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2449
2450 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2451 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2452 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2453 }
2454
2455 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2456
2457 /* The cs checker requires this register to be set. */
2458 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2459
2460 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2463
2464 return;
2465 }
2466
2467 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2468 {
2469 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2470 int num_ps_threads;
2471 int num_vs_threads;
2472 int num_gs_threads;
2473 int num_es_threads;
2474 int num_hs_threads;
2475 int num_ls_threads;
2476
2477 int num_ps_stack_entries;
2478 int num_vs_stack_entries;
2479 int num_gs_stack_entries;
2480 int num_es_stack_entries;
2481 int num_hs_stack_entries;
2482 int num_ls_stack_entries;
2483 enum radeon_family family;
2484 unsigned tmp;
2485
2486 if (rctx->b.chip_class == CAYMAN) {
2487 cayman_init_atom_start_cs(rctx);
2488 return;
2489 }
2490
2491 r600_init_command_buffer(cb, 256);
2492
2493 /* This must be first. */
2494 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2495 r600_store_value(cb, 0x80000000);
2496 r600_store_value(cb, 0x80000000);
2497
2498 /* We're setting config registers here. */
2499 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2500 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2501
2502 evergreen_init_common_regs(cb, rctx->b.chip_class,
2503 rctx->b.family, rctx->screen->b.info.drm_minor);
2504
2505 family = rctx->b.family;
2506 switch (family) {
2507 case CHIP_CEDAR:
2508 default:
2509 num_ps_threads = 96;
2510 num_vs_threads = 16;
2511 num_gs_threads = 16;
2512 num_es_threads = 16;
2513 num_hs_threads = 16;
2514 num_ls_threads = 16;
2515 num_ps_stack_entries = 42;
2516 num_vs_stack_entries = 42;
2517 num_gs_stack_entries = 42;
2518 num_es_stack_entries = 42;
2519 num_hs_stack_entries = 42;
2520 num_ls_stack_entries = 42;
2521 break;
2522 case CHIP_REDWOOD:
2523 num_ps_threads = 128;
2524 num_vs_threads = 20;
2525 num_gs_threads = 20;
2526 num_es_threads = 20;
2527 num_hs_threads = 20;
2528 num_ls_threads = 20;
2529 num_ps_stack_entries = 42;
2530 num_vs_stack_entries = 42;
2531 num_gs_stack_entries = 42;
2532 num_es_stack_entries = 42;
2533 num_hs_stack_entries = 42;
2534 num_ls_stack_entries = 42;
2535 break;
2536 case CHIP_JUNIPER:
2537 num_ps_threads = 128;
2538 num_vs_threads = 20;
2539 num_gs_threads = 20;
2540 num_es_threads = 20;
2541 num_hs_threads = 20;
2542 num_ls_threads = 20;
2543 num_ps_stack_entries = 85;
2544 num_vs_stack_entries = 85;
2545 num_gs_stack_entries = 85;
2546 num_es_stack_entries = 85;
2547 num_hs_stack_entries = 85;
2548 num_ls_stack_entries = 85;
2549 break;
2550 case CHIP_CYPRESS:
2551 case CHIP_HEMLOCK:
2552 num_ps_threads = 128;
2553 num_vs_threads = 20;
2554 num_gs_threads = 20;
2555 num_es_threads = 20;
2556 num_hs_threads = 20;
2557 num_ls_threads = 20;
2558 num_ps_stack_entries = 85;
2559 num_vs_stack_entries = 85;
2560 num_gs_stack_entries = 85;
2561 num_es_stack_entries = 85;
2562 num_hs_stack_entries = 85;
2563 num_ls_stack_entries = 85;
2564 break;
2565 case CHIP_PALM:
2566 num_ps_threads = 96;
2567 num_vs_threads = 16;
2568 num_gs_threads = 16;
2569 num_es_threads = 16;
2570 num_hs_threads = 16;
2571 num_ls_threads = 16;
2572 num_ps_stack_entries = 42;
2573 num_vs_stack_entries = 42;
2574 num_gs_stack_entries = 42;
2575 num_es_stack_entries = 42;
2576 num_hs_stack_entries = 42;
2577 num_ls_stack_entries = 42;
2578 break;
2579 case CHIP_SUMO:
2580 num_ps_threads = 96;
2581 num_vs_threads = 25;
2582 num_gs_threads = 25;
2583 num_es_threads = 25;
2584 num_hs_threads = 25;
2585 num_ls_threads = 25;
2586 num_ps_stack_entries = 42;
2587 num_vs_stack_entries = 42;
2588 num_gs_stack_entries = 42;
2589 num_es_stack_entries = 42;
2590 num_hs_stack_entries = 42;
2591 num_ls_stack_entries = 42;
2592 break;
2593 case CHIP_SUMO2:
2594 num_ps_threads = 96;
2595 num_vs_threads = 25;
2596 num_gs_threads = 25;
2597 num_es_threads = 25;
2598 num_hs_threads = 25;
2599 num_ls_threads = 25;
2600 num_ps_stack_entries = 85;
2601 num_vs_stack_entries = 85;
2602 num_gs_stack_entries = 85;
2603 num_es_stack_entries = 85;
2604 num_hs_stack_entries = 85;
2605 num_ls_stack_entries = 85;
2606 break;
2607 case CHIP_BARTS:
2608 num_ps_threads = 128;
2609 num_vs_threads = 20;
2610 num_gs_threads = 20;
2611 num_es_threads = 20;
2612 num_hs_threads = 20;
2613 num_ls_threads = 20;
2614 num_ps_stack_entries = 85;
2615 num_vs_stack_entries = 85;
2616 num_gs_stack_entries = 85;
2617 num_es_stack_entries = 85;
2618 num_hs_stack_entries = 85;
2619 num_ls_stack_entries = 85;
2620 break;
2621 case CHIP_TURKS:
2622 num_ps_threads = 128;
2623 num_vs_threads = 20;
2624 num_gs_threads = 20;
2625 num_es_threads = 20;
2626 num_hs_threads = 20;
2627 num_ls_threads = 20;
2628 num_ps_stack_entries = 42;
2629 num_vs_stack_entries = 42;
2630 num_gs_stack_entries = 42;
2631 num_es_stack_entries = 42;
2632 num_hs_stack_entries = 42;
2633 num_ls_stack_entries = 42;
2634 break;
2635 case CHIP_CAICOS:
2636 num_ps_threads = 128;
2637 num_vs_threads = 10;
2638 num_gs_threads = 10;
2639 num_es_threads = 10;
2640 num_hs_threads = 10;
2641 num_ls_threads = 10;
2642 num_ps_stack_entries = 42;
2643 num_vs_stack_entries = 42;
2644 num_gs_stack_entries = 42;
2645 num_es_stack_entries = 42;
2646 num_hs_stack_entries = 42;
2647 num_ls_stack_entries = 42;
2648 break;
2649 }
2650
2651 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2652 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2653 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2654 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2655
2656 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2657 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2658
2659 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2660 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2661 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2662
2663 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2664 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2665 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2666
2667 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2668 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2669 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2670
2671 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2672 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2673 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2674
2675 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2676 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2677
2678 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2679 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2680
2681 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2682 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2683 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2684 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2685 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2686 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2687 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2688
2689 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2690 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2691 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2692 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2693 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2694
2695 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2696 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2697 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2698 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2699 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2700 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2701 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2702 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2703 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2704 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2705 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2706 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2707 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2708 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2709
2710 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2711 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2712 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2713
2714 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2715
2716 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2717
2718 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2719 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2720 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2721
2722 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2723
2724 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2725
2726 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2727 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2728 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2729
2730 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2731 for (tmp = 0; tmp < 16; tmp++) {
2732 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2733 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2734 }
2735
2736 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2737 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2738
2739 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2740 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2741 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2742 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2743
2744 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2745 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2746 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2747 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2748 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2749
2750 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2751 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2752 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2753
2754 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2755 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2756 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2757
2758 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2759 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2760 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2761
2762 /* to avoid GPU doing any preloading of constant from random address */
2763 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2764 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2765 r600_store_value(cb, 0);
2766 r600_store_value(cb, 0);
2767 r600_store_value(cb, 0);
2768 r600_store_value(cb, 0);
2769 r600_store_value(cb, 0);
2770 r600_store_value(cb, 0);
2771 r600_store_value(cb, 0);
2772 r600_store_value(cb, 0);
2773 r600_store_value(cb, 0);
2774 r600_store_value(cb, 0);
2775 r600_store_value(cb, 0);
2776 r600_store_value(cb, 0);
2777 r600_store_value(cb, 0);
2778 r600_store_value(cb, 0);
2779 r600_store_value(cb, 0);
2780
2781 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2782 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2783 r600_store_value(cb, 0);
2784 r600_store_value(cb, 0);
2785 r600_store_value(cb, 0);
2786 r600_store_value(cb, 0);
2787 r600_store_value(cb, 0);
2788 r600_store_value(cb, 0);
2789 r600_store_value(cb, 0);
2790 r600_store_value(cb, 0);
2791 r600_store_value(cb, 0);
2792 r600_store_value(cb, 0);
2793 r600_store_value(cb, 0);
2794 r600_store_value(cb, 0);
2795 r600_store_value(cb, 0);
2796 r600_store_value(cb, 0);
2797 r600_store_value(cb, 0);
2798
2799 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2800
2801 if (rctx->screen->b.has_streamout) {
2802 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2803 }
2804
2805 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2806 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2807 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2808 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2809 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2810 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2811 r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
2812 r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
2813
2814 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2815 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2816 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2817 }
2818
2819 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2820 {
2821 struct r600_context *rctx = (struct r600_context *)ctx;
2822 struct r600_command_buffer *cb = &shader->command_buffer;
2823 struct r600_shader *rshader = &shader->shader;
2824 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
2825 int pos_index = -1, face_index = -1;
2826 int ninterp = 0;
2827 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2828 unsigned spi_baryc_cntl, sid, tmp, num = 0;
2829 unsigned z_export = 0, stencil_export = 0;
2830 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2831 uint32_t spi_ps_input_cntl[32];
2832
2833 if (!cb->buf) {
2834 r600_init_command_buffer(cb, 64);
2835 } else {
2836 cb->num_dw = 0;
2837 }
2838
2839 for (i = 0; i < rshader->ninput; i++) {
2840 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2841 POSITION goes via GPRs from the SC so isn't counted */
2842 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2843 pos_index = i;
2844 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) {
2845 if (face_index == -1)
2846 face_index = i;
2847 }
2848 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2849 if (face_index == -1)
2850 face_index = i; /* lives in same register, same enable bit */
2851 }
2852 else {
2853 ninterp++;
2854 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2855 have_linear = TRUE;
2856 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2857 have_perspective = TRUE;
2858 if (rshader->input[i].centroid)
2859 have_centroid = TRUE;
2860 }
2861
2862 sid = rshader->input[i].spi_sid;
2863
2864 if (sid) {
2865 tmp = S_028644_SEMANTIC(sid);
2866
2867 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2868 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2869 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2870 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2871 tmp |= S_028644_FLAT_SHADE(1);
2872 }
2873
2874 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2875 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
2876 tmp |= S_028644_PT_SPRITE_TEX(1);
2877 }
2878
2879 spi_ps_input_cntl[num++] = tmp;
2880 }
2881 }
2882
2883 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
2884 r600_store_array(cb, num, spi_ps_input_cntl);
2885
2886 for (i = 0; i < rshader->noutput; i++) {
2887 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2888 z_export = 1;
2889 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2890 stencil_export = 1;
2891 }
2892 if (rshader->uses_kill)
2893 db_shader_control |= S_02880C_KILL_ENABLE(1);
2894
2895 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2896 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2897
2898 exports_ps = 0;
2899 for (i = 0; i < rshader->noutput; i++) {
2900 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2901 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2902 exports_ps |= 1;
2903 }
2904
2905 num_cout = rshader->nr_ps_color_exports;
2906
2907 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2908 if (!exports_ps) {
2909 /* always at least export 1 component per pixel */
2910 exports_ps = 2;
2911 }
2912 shader->nr_ps_color_outputs = num_cout;
2913 if (ninterp == 0) {
2914 ninterp = 1;
2915 have_perspective = TRUE;
2916 }
2917
2918 if (!have_perspective && !have_linear)
2919 have_perspective = TRUE;
2920
2921 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2922 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2923 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2924 spi_input_z = 0;
2925 if (pos_index != -1) {
2926 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2927 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2928 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2929 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2930 }
2931
2932 spi_ps_in_control_1 = 0;
2933 if (face_index != -1) {
2934 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2935 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2936 }
2937
2938 spi_baryc_cntl = 0;
2939 if (have_perspective)
2940 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2941 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2942 if (have_linear)
2943 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2944 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2945
2946 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2947 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2948 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2949
2950 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
2951 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2952 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
2953
2954 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
2955 r600_store_value(cb, r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2956 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
2957 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2958 S_028844_PRIME_CACHE_ON_DRAW(1) |
2959 S_028844_STACK_SIZE(rshader->bc.nstack));
2960 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2961
2962 shader->db_shader_control = db_shader_control;
2963 shader->ps_depth_export = z_export | stencil_export;
2964
2965 shader->sprite_coord_enable = sprite_coord_enable;
2966 if (rctx->rasterizer)
2967 shader->flatshade = rctx->rasterizer->flatshade;
2968 }
2969
2970 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2971 {
2972 struct r600_command_buffer *cb = &shader->command_buffer;
2973 struct r600_shader *rshader = &shader->shader;
2974
2975 r600_init_command_buffer(cb, 32);
2976
2977 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2978 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2979 S_028890_STACK_SIZE(rshader->bc.nstack));
2980 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
2981 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2982 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2983 }
2984
2985 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2986 {
2987 struct r600_context *rctx = (struct r600_context *)ctx;
2988 struct r600_command_buffer *cb = &shader->command_buffer;
2989 struct r600_shader *rshader = &shader->shader;
2990 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2991 unsigned gsvs_itemsize =
2992 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
2993
2994 r600_init_command_buffer(cb, 64);
2995
2996 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
2997
2998 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2999
3000 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3001 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
3002 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3003 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
3004
3005 if (rctx->screen->b.info.drm_minor >= 35) {
3006 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3007 S_028B90_CNT(0) |
3008 S_028B90_ENABLE(0));
3009 }
3010 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3011 r600_store_value(cb, cp_shader->ring_item_size >> 2);
3012 r600_store_value(cb, 0);
3013 r600_store_value(cb, 0);
3014 r600_store_value(cb, 0);
3015
3016 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3017 (rshader->ring_item_size) >> 2);
3018
3019 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3020 gsvs_itemsize);
3021
3022 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3023 r600_store_value(cb, gsvs_itemsize);
3024 r600_store_value(cb, gsvs_itemsize);
3025 r600_store_value(cb, gsvs_itemsize);
3026
3027 /* FIXME calculate these values somehow ??? */
3028 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3029 r600_store_value(cb, 0x80); /* GS_PER_ES */
3030 r600_store_value(cb, 0x100); /* ES_PER_GS */
3031 r600_store_value(cb, 0x2); /* GS_PER_VS */
3032
3033 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3034 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3035 S_028878_STACK_SIZE(rshader->bc.nstack));
3036 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3037 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3038 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3039 }
3040
3041
3042 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3043 {
3044 struct r600_command_buffer *cb = &shader->command_buffer;
3045 struct r600_shader *rshader = &shader->shader;
3046 unsigned spi_vs_out_id[10] = {};
3047 unsigned i, tmp, nparams = 0;
3048
3049 for (i = 0; i < rshader->noutput; i++) {
3050 if (rshader->output[i].spi_sid) {
3051 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3052 spi_vs_out_id[nparams / 4] |= tmp;
3053 nparams++;
3054 }
3055 }
3056
3057 r600_init_command_buffer(cb, 32);
3058
3059 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3060 for (i = 0; i < 10; i++) {
3061 r600_store_value(cb, spi_vs_out_id[i]);
3062 }
3063
3064 /* Certain attributes (position, psize, etc.) don't count as params.
3065 * VS is required to export at least one param and r600_shader_from_tgsi()
3066 * takes care of adding a dummy export.
3067 */
3068 if (nparams < 1)
3069 nparams = 1;
3070
3071 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3072 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3073 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3074 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3075 S_028860_STACK_SIZE(rshader->bc.nstack));
3076 if (rshader->vs_position_window_space) {
3077 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3078 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3079 } else {
3080 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3081 S_028818_VTX_W0_FMT(1) |
3082 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3083 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3084 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3085
3086 }
3087 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3088 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3089 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3090
3091 shader->pa_cl_vs_out_cntl =
3092 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3093 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3094 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3095 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3096 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3097 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3098 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3099 }
3100
3101 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3102 {
3103 struct pipe_blend_state blend;
3104
3105 memset(&blend, 0, sizeof(blend));
3106 blend.independent_blend_enable = true;
3107 blend.rt[0].colormask = 0xf;
3108 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3109 }
3110
3111 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3112 {
3113 struct pipe_blend_state blend;
3114 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3115 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3116
3117 memset(&blend, 0, sizeof(blend));
3118 blend.independent_blend_enable = true;
3119 blend.rt[0].colormask = 0xf;
3120 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3121 }
3122
3123 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3124 {
3125 struct pipe_blend_state blend;
3126 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3127
3128 memset(&blend, 0, sizeof(blend));
3129 blend.independent_blend_enable = true;
3130 blend.rt[0].colormask = 0xf;
3131 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3132 }
3133
3134 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3135 {
3136 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3137
3138 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3139 }
3140
3141 void evergreen_update_db_shader_control(struct r600_context * rctx)
3142 {
3143 bool dual_export;
3144 unsigned db_shader_control;
3145
3146 if (!rctx->ps_shader) {
3147 return;
3148 }
3149
3150 dual_export = rctx->framebuffer.export_16bpc &&
3151 !rctx->ps_shader->current->ps_depth_export;
3152
3153 db_shader_control = rctx->ps_shader->current->db_shader_control |
3154 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3155 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3156 V_02880C_EXPORT_DB_FULL) |
3157 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3158
3159 /* When alpha test is enabled we can't trust the hw to make the proper
3160 * decision on the order in which ztest should be run related to fragment
3161 * shader execution.
3162 *
3163 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3164 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3165 * execution and thus after alpha test so if discarded by the alpha test
3166 * the z value is not written.
3167 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3168 * get a hang unless you flush the DB in between. For now just use
3169 * LATE_Z.
3170 */
3171 if (rctx->alphatest_state.sx_alpha_test_control) {
3172 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3173 } else {
3174 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3175 }
3176
3177 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3178 rctx->db_misc_state.db_shader_control = db_shader_control;
3179 rctx->db_misc_state.atom.dirty = true;
3180 }
3181 }
3182
3183 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3184 struct pipe_resource *dst,
3185 unsigned dst_level,
3186 unsigned dst_x,
3187 unsigned dst_y,
3188 unsigned dst_z,
3189 struct pipe_resource *src,
3190 unsigned src_level,
3191 unsigned src_x,
3192 unsigned src_y,
3193 unsigned src_z,
3194 unsigned copy_height,
3195 unsigned pitch,
3196 unsigned bpp)
3197 {
3198 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
3199 struct r600_texture *rsrc = (struct r600_texture*)src;
3200 struct r600_texture *rdst = (struct r600_texture*)dst;
3201 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3202 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3203 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3204 uint64_t base, addr;
3205
3206 dst_mode = rdst->surface.level[dst_level].mode;
3207 src_mode = rsrc->surface.level[src_level].mode;
3208 /* downcast linear aligned to linear to simplify test */
3209 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3210 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3211 assert(dst_mode != src_mode);
3212
3213 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3214 if (util_format_has_depth(util_format_description(src->format)))
3215 non_disp_tiling = 1;
3216
3217 y = 0;
3218 sub_cmd = EG_DMA_COPY_TILED;
3219 lbpp = util_logbase2(bpp);
3220 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3221 nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
3222
3223 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3224 /* T2L */
3225 array_mode = evergreen_array_mode(src_mode);
3226 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
3227 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3228 /* linear height must be the same as the slice tile max height, it's ok even
3229 * if the linear destination/source have smaller heigh as the size of the
3230 * dma packet will be using the copy_height which is always smaller or equal
3231 * to the linear height
3232 */
3233 height = rsrc->surface.level[src_level].npix_y;
3234 detile = 1;
3235 x = src_x;
3236 y = src_y;
3237 z = src_z;
3238 base = rsrc->surface.level[src_level].offset;
3239 addr = rdst->surface.level[dst_level].offset;
3240 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3241 addr += dst_y * pitch + dst_x * bpp;
3242 bank_h = eg_bank_wh(rsrc->surface.bankh);
3243 bank_w = eg_bank_wh(rsrc->surface.bankw);
3244 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
3245 tile_split = eg_tile_split(rsrc->surface.tile_split);
3246 base += r600_resource_va(&rctx->screen->b.b, src);
3247 addr += r600_resource_va(&rctx->screen->b.b, dst);
3248 } else {
3249 /* L2T */
3250 array_mode = evergreen_array_mode(dst_mode);
3251 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
3252 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3253 /* linear height must be the same as the slice tile max height, it's ok even
3254 * if the linear destination/source have smaller heigh as the size of the
3255 * dma packet will be using the copy_height which is always smaller or equal
3256 * to the linear height
3257 */
3258 height = rdst->surface.level[dst_level].npix_y;
3259 detile = 0;
3260 x = dst_x;
3261 y = dst_y;
3262 z = dst_z;
3263 base = rdst->surface.level[dst_level].offset;
3264 addr = rsrc->surface.level[src_level].offset;
3265 addr += rsrc->surface.level[src_level].slice_size * src_z;
3266 addr += src_y * pitch + src_x * bpp;
3267 bank_h = eg_bank_wh(rdst->surface.bankh);
3268 bank_w = eg_bank_wh(rdst->surface.bankw);
3269 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
3270 tile_split = eg_tile_split(rdst->surface.tile_split);
3271 base += r600_resource_va(&rctx->screen->b.b, dst);
3272 addr += r600_resource_va(&rctx->screen->b.b, src);
3273 }
3274
3275 size = (copy_height * pitch) / 4;
3276 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3277 r600_need_dma_space(&rctx->b, ncopy * 9);
3278
3279 for (i = 0; i < ncopy; i++) {
3280 cheight = copy_height;
3281 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3282 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3283 }
3284 size = (cheight * pitch) / 4;
3285 /* emit reloc before writting cs so that cs is always in consistent state */
3286 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource,
3287 RADEON_USAGE_READ, RADEON_PRIO_MIN);
3288 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource,
3289 RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
3290 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
3291 cs->buf[cs->cdw++] = base >> 8;
3292 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3293 (lbpp << 24) | (bank_h << 21) |
3294 (bank_w << 18) | (mt_aspect << 16);
3295 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
3296 cs->buf[cs->cdw++] = (slice_tile_max << 0);
3297 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
3298 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
3299 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3300 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3301 copy_height -= cheight;
3302 addr += cheight * pitch;
3303 y += cheight;
3304 }
3305 }
3306
3307 static void evergreen_dma_copy(struct pipe_context *ctx,
3308 struct pipe_resource *dst,
3309 unsigned dst_level,
3310 unsigned dstx, unsigned dsty, unsigned dstz,
3311 struct pipe_resource *src,
3312 unsigned src_level,
3313 const struct pipe_box *src_box)
3314 {
3315 struct r600_context *rctx = (struct r600_context *)ctx;
3316 struct r600_texture *rsrc = (struct r600_texture*)src;
3317 struct r600_texture *rdst = (struct r600_texture*)dst;
3318 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3319 unsigned src_w, dst_w;
3320 unsigned src_x, src_y;
3321 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3322
3323 if (rctx->b.rings.dma.cs == NULL) {
3324 goto fallback;
3325 }
3326
3327 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3328 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3329 return;
3330 }
3331
3332 if (src->format != dst->format || src_box->depth > 1 ||
3333 rdst->dirty_level_mask != 0) {
3334 goto fallback;
3335 }
3336
3337 if (rsrc->dirty_level_mask) {
3338 ctx->flush_resource(ctx, src);
3339 }
3340
3341 src_x = util_format_get_nblocksx(src->format, src_box->x);
3342 dst_x = util_format_get_nblocksx(src->format, dst_x);
3343 src_y = util_format_get_nblocksy(src->format, src_box->y);
3344 dst_y = util_format_get_nblocksy(src->format, dst_y);
3345
3346 bpp = rdst->surface.bpe;
3347 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3348 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3349 src_w = rsrc->surface.level[src_level].npix_x;
3350 dst_w = rdst->surface.level[dst_level].npix_x;
3351 copy_height = src_box->height / rsrc->surface.blk_h;
3352
3353 dst_mode = rdst->surface.level[dst_level].mode;
3354 src_mode = rsrc->surface.level[src_level].mode;
3355 /* downcast linear aligned to linear to simplify test */
3356 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3357 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3358
3359 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3360 /* FIXME evergreen can do partial blit */
3361 goto fallback;
3362 }
3363 /* the x test here are currently useless (because we don't support partial blit)
3364 * but keep them around so we don't forget about those
3365 */
3366 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
3367 goto fallback;
3368 }
3369
3370 /* 128 bpp surfaces require non_disp_tiling for both
3371 * tiled and linear buffers on cayman. However, async
3372 * DMA only supports it on the tiled side. As such
3373 * the tile order is backwards after a L2T/T2L packet.
3374 */
3375 if ((rctx->b.chip_class == CAYMAN) &&
3376 (src_mode != dst_mode) &&
3377 (util_format_get_blocksize(src->format) >= 16)) {
3378 goto fallback;
3379 }
3380
3381 if (src_mode == dst_mode) {
3382 uint64_t dst_offset, src_offset;
3383 /* simple dma blit would do NOTE code here assume :
3384 * src_box.x/y == 0
3385 * dst_x/y == 0
3386 * dst_pitch == src_pitch
3387 */
3388 src_offset= rsrc->surface.level[src_level].offset;
3389 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3390 src_offset += src_y * src_pitch + src_x * bpp;
3391 dst_offset = rdst->surface.level[dst_level].offset;
3392 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3393 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3394 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3395 src_box->height * src_pitch);
3396 } else {
3397 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3398 src, src_level, src_x, src_y, src_box->z,
3399 copy_height, dst_pitch, bpp);
3400 }
3401 return;
3402
3403 fallback:
3404 ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3405 src, src_level, src_box);
3406 }
3407
3408 void evergreen_init_state_functions(struct r600_context *rctx)
3409 {
3410 unsigned id = 4;
3411 int i;
3412 /* !!!
3413 * To avoid GPU lockup registers must be emited in a specific order
3414 * (no kidding ...). The order below is important and have been
3415 * partialy infered from analyzing fglrx command stream.
3416 *
3417 * Don't reorder atom without carefully checking the effect (GPU lockup
3418 * or piglit regression).
3419 * !!!
3420 */
3421
3422 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
3423 /* shader const */
3424 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
3425 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
3426 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
3427 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
3428 /* shader program */
3429 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
3430 /* sampler */
3431 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
3432 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
3433 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
3434 /* resources */
3435 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
3436 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
3437 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
3438 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
3439 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
3440
3441 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3442
3443 if (rctx->b.chip_class == EVERGREEN) {
3444 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
3445 } else {
3446 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
3447 }
3448 rctx->sample_mask.sample_mask = ~0;
3449
3450 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3451 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3452 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3453 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
3454 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3455 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
3456 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
3457 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
3458 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3459 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
3460 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3461 for (i = 0; i < 16; i++) {
3462 r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
3463 r600_init_atom(rctx, &rctx->scissor[i].atom, id++, evergreen_emit_scissor_state, 4);
3464 rctx->viewport[i].idx = i;
3465 rctx->scissor[i].idx = i;
3466 }
3467 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3468 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
3469 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3470 rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
3471 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3472 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3473 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3474 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3475 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 6);
3476 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
3477
3478 rctx->b.b.create_blend_state = evergreen_create_blend_state;
3479 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
3480 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
3481 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
3482 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
3483 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
3484 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
3485 rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
3486
3487 if (rctx->b.chip_class == EVERGREEN)
3488 rctx->b.b.get_sample_position = evergreen_get_sample_position;
3489 else
3490 rctx->b.b.get_sample_position = cayman_get_sample_position;
3491 rctx->b.dma_copy = evergreen_dma_copy;
3492
3493 evergreen_init_compute_state_functions(rctx);
3494 }