projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: consolidate code for setting sampler views and fix bugs in the process
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return V_030000_SQ_TEX_DIM_2D;
169 case PIPE_TEXTURE_2D_ARRAY:
170 return V_030000_SQ_TEX_DIM_2D_ARRAY;
171 case PIPE_TEXTURE_3D:
172 return V_030000_SQ_TEX_DIM_3D;
173 case PIPE_TEXTURE_CUBE:
174 return V_030000_SQ_TEX_DIM_CUBEMAP;
175 }
176 }
177
178 static uint32_t r600_translate_dbformat(enum pipe_format format)
179 {
180 switch (format) {
181 case PIPE_FORMAT_Z16_UNORM:
182 return V_028040_Z_16;
183 case PIPE_FORMAT_Z24X8_UNORM:
184 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185 return V_028040_Z_24;
186 case PIPE_FORMAT_Z32_FLOAT:
187 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188 return V_028040_Z_32_FLOAT;
189 default:
190 return ~0U;
191 }
192 }
193
194 static uint32_t r600_translate_colorswap(enum pipe_format format)
195 {
196 switch (format) {
197 /* 8-bit buffers. */
198 case PIPE_FORMAT_L4A4_UNORM:
199 case PIPE_FORMAT_A4R4_UNORM:
200 return V_028C70_SWAP_ALT;
201
202 case PIPE_FORMAT_A8_UNORM:
203 case PIPE_FORMAT_A8_SNORM:
204 case PIPE_FORMAT_A8_UINT:
205 case PIPE_FORMAT_A8_SINT:
206 case PIPE_FORMAT_A16_UNORM:
207 case PIPE_FORMAT_A16_SNORM:
208 case PIPE_FORMAT_A16_UINT:
209 case PIPE_FORMAT_A16_SINT:
210 case PIPE_FORMAT_A16_FLOAT:
211 case PIPE_FORMAT_A32_UINT:
212 case PIPE_FORMAT_A32_SINT:
213 case PIPE_FORMAT_A32_FLOAT:
214 case PIPE_FORMAT_R4A4_UNORM:
215 return V_028C70_SWAP_ALT_REV;
216 case PIPE_FORMAT_I8_UNORM:
217 case PIPE_FORMAT_I8_SNORM:
218 case PIPE_FORMAT_I8_UINT:
219 case PIPE_FORMAT_I8_SINT:
220 case PIPE_FORMAT_I16_UNORM:
221 case PIPE_FORMAT_I16_SNORM:
222 case PIPE_FORMAT_I16_UINT:
223 case PIPE_FORMAT_I16_SINT:
224 case PIPE_FORMAT_I16_FLOAT:
225 case PIPE_FORMAT_I32_UINT:
226 case PIPE_FORMAT_I32_SINT:
227 case PIPE_FORMAT_I32_FLOAT:
228 case PIPE_FORMAT_L8_UNORM:
229 case PIPE_FORMAT_L8_SNORM:
230 case PIPE_FORMAT_L8_UINT:
231 case PIPE_FORMAT_L8_SINT:
232 case PIPE_FORMAT_L8_SRGB:
233 case PIPE_FORMAT_L16_UNORM:
234 case PIPE_FORMAT_L16_SNORM:
235 case PIPE_FORMAT_L16_UINT:
236 case PIPE_FORMAT_L16_SINT:
237 case PIPE_FORMAT_L16_FLOAT:
238 case PIPE_FORMAT_L32_UINT:
239 case PIPE_FORMAT_L32_SINT:
240 case PIPE_FORMAT_L32_FLOAT:
241 case PIPE_FORMAT_R8_UNORM:
242 case PIPE_FORMAT_R8_SNORM:
243 case PIPE_FORMAT_R8_UINT:
244 case PIPE_FORMAT_R8_SINT:
245 return V_028C70_SWAP_STD;
246
247 /* 16-bit buffers. */
248 case PIPE_FORMAT_B5G6R5_UNORM:
249 return V_028C70_SWAP_STD_REV;
250
251 case PIPE_FORMAT_B5G5R5A1_UNORM:
252 case PIPE_FORMAT_B5G5R5X1_UNORM:
253 return V_028C70_SWAP_ALT;
254
255 case PIPE_FORMAT_B4G4R4A4_UNORM:
256 case PIPE_FORMAT_B4G4R4X4_UNORM:
257 return V_028C70_SWAP_ALT;
258
259 case PIPE_FORMAT_Z16_UNORM:
260 return V_028C70_SWAP_STD;
261
262 case PIPE_FORMAT_L8A8_UNORM:
263 case PIPE_FORMAT_L8A8_SNORM:
264 case PIPE_FORMAT_L8A8_UINT:
265 case PIPE_FORMAT_L8A8_SINT:
266 case PIPE_FORMAT_L8A8_SRGB:
267 case PIPE_FORMAT_L16A16_UNORM:
268 case PIPE_FORMAT_L16A16_SNORM:
269 case PIPE_FORMAT_L16A16_UINT:
270 case PIPE_FORMAT_L16A16_SINT:
271 case PIPE_FORMAT_L16A16_FLOAT:
272 case PIPE_FORMAT_L32A32_UINT:
273 case PIPE_FORMAT_L32A32_SINT:
274 case PIPE_FORMAT_L32A32_FLOAT:
275 return V_028C70_SWAP_ALT;
276 case PIPE_FORMAT_R8G8_UNORM:
277 case PIPE_FORMAT_R8G8_SNORM:
278 case PIPE_FORMAT_R8G8_UINT:
279 case PIPE_FORMAT_R8G8_SINT:
280 return V_028C70_SWAP_STD;
281
282 case PIPE_FORMAT_R16_UNORM:
283 case PIPE_FORMAT_R16_SNORM:
284 case PIPE_FORMAT_R16_UINT:
285 case PIPE_FORMAT_R16_SINT:
286 case PIPE_FORMAT_R16_FLOAT:
287 return V_028C70_SWAP_STD;
288
289 /* 32-bit buffers. */
290 case PIPE_FORMAT_A8B8G8R8_SRGB:
291 return V_028C70_SWAP_STD_REV;
292 case PIPE_FORMAT_B8G8R8A8_SRGB:
293 return V_028C70_SWAP_ALT;
294
295 case PIPE_FORMAT_B8G8R8A8_UNORM:
296 case PIPE_FORMAT_B8G8R8X8_UNORM:
297 return V_028C70_SWAP_ALT;
298
299 case PIPE_FORMAT_A8R8G8B8_UNORM:
300 case PIPE_FORMAT_X8R8G8B8_UNORM:
301 return V_028C70_SWAP_ALT_REV;
302 case PIPE_FORMAT_R8G8B8A8_SNORM:
303 case PIPE_FORMAT_R8G8B8A8_UNORM:
304 case PIPE_FORMAT_R8G8B8A8_SINT:
305 case PIPE_FORMAT_R8G8B8A8_UINT:
306 case PIPE_FORMAT_R8G8B8X8_UNORM:
307 return V_028C70_SWAP_STD;
308
309 case PIPE_FORMAT_A8B8G8R8_UNORM:
310 case PIPE_FORMAT_X8B8G8R8_UNORM:
311 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312 return V_028C70_SWAP_STD_REV;
313
314 case PIPE_FORMAT_Z24X8_UNORM:
315 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316 return V_028C70_SWAP_STD;
317
318 case PIPE_FORMAT_X8Z24_UNORM:
319 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320 return V_028C70_SWAP_STD;
321
322 case PIPE_FORMAT_R10G10B10A2_UNORM:
323 case PIPE_FORMAT_R10G10B10X2_SNORM:
324 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325 return V_028C70_SWAP_STD;
326
327 case PIPE_FORMAT_B10G10R10A2_UNORM:
328 case PIPE_FORMAT_B10G10R10A2_UINT:
329 return V_028C70_SWAP_ALT;
330
331 case PIPE_FORMAT_R11G11B10_FLOAT:
332 case PIPE_FORMAT_R32_FLOAT:
333 case PIPE_FORMAT_R32_UINT:
334 case PIPE_FORMAT_R32_SINT:
335 case PIPE_FORMAT_Z32_FLOAT:
336 case PIPE_FORMAT_R16G16_FLOAT:
337 case PIPE_FORMAT_R16G16_UNORM:
338 case PIPE_FORMAT_R16G16_SNORM:
339 case PIPE_FORMAT_R16G16_UINT:
340 case PIPE_FORMAT_R16G16_SINT:
341 case PIPE_FORMAT_R16G16B16_FLOAT:
342 case PIPE_FORMAT_R32G32B32_FLOAT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16_FLOAT:
521 case PIPE_FORMAT_R16G16B16A16_FLOAT:
522 return V_028C70_COLOR_16_16_16_16_FLOAT;
523
524 case PIPE_FORMAT_R32G32_FLOAT:
525 case PIPE_FORMAT_L32A32_FLOAT:
526 return V_028C70_COLOR_32_32_FLOAT;
527
528 case PIPE_FORMAT_R32G32_SINT:
529 case PIPE_FORMAT_R32G32_UINT:
530 case PIPE_FORMAT_L32A32_UINT:
531 case PIPE_FORMAT_L32A32_SINT:
532 return V_028C70_COLOR_32_32;
533
534 /* 96-bit buffers. */
535 case PIPE_FORMAT_R32G32B32_FLOAT:
536 return V_028C70_COLOR_32_32_32_FLOAT;
537
538 /* 128-bit buffers. */
539 case PIPE_FORMAT_R32G32B32A32_SNORM:
540 case PIPE_FORMAT_R32G32B32A32_UNORM:
541 case PIPE_FORMAT_R32G32B32A32_SINT:
542 case PIPE_FORMAT_R32G32B32A32_UINT:
543 return V_028C70_COLOR_32_32_32_32;
544 case PIPE_FORMAT_R32G32B32A32_FLOAT:
545 return V_028C70_COLOR_32_32_32_32_FLOAT;
546
547 /* YUV buffers. */
548 case PIPE_FORMAT_UYVY:
549 case PIPE_FORMAT_YUYV:
550 default:
551 return ~0U; /* Unsupported. */
552 }
553 }
554
555 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
556 {
557 if (R600_BIG_ENDIAN) {
558 switch(colorformat) {
559
560 /* 8-bit buffers. */
561 case V_028C70_COLOR_8:
562 return ENDIAN_NONE;
563
564 /* 16-bit buffers. */
565 case V_028C70_COLOR_5_6_5:
566 case V_028C70_COLOR_1_5_5_5:
567 case V_028C70_COLOR_4_4_4_4:
568 case V_028C70_COLOR_16:
569 case V_028C70_COLOR_8_8:
570 return ENDIAN_8IN16;
571
572 /* 32-bit buffers. */
573 case V_028C70_COLOR_8_8_8_8:
574 case V_028C70_COLOR_2_10_10_10:
575 case V_028C70_COLOR_8_24:
576 case V_028C70_COLOR_24_8:
577 case V_028C70_COLOR_32_FLOAT:
578 case V_028C70_COLOR_16_16_FLOAT:
579 case V_028C70_COLOR_16_16:
580 return ENDIAN_8IN32;
581
582 /* 64-bit buffers. */
583 case V_028C70_COLOR_16_16_16_16:
584 case V_028C70_COLOR_16_16_16_16_FLOAT:
585 return ENDIAN_8IN16;
586
587 case V_028C70_COLOR_32_32_FLOAT:
588 case V_028C70_COLOR_32_32:
589 case V_028C70_COLOR_X24_8_32_FLOAT:
590 return ENDIAN_8IN32;
591
592 /* 96-bit buffers. */
593 case V_028C70_COLOR_32_32_32_FLOAT:
594 /* 128-bit buffers. */
595 case V_028C70_COLOR_32_32_32_32_FLOAT:
596 case V_028C70_COLOR_32_32_32_32:
597 return ENDIAN_8IN32;
598 default:
599 return ENDIAN_NONE; /* Unsupported. */
600 }
601 } else {
602 return ENDIAN_NONE;
603 }
604 }
605
606 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
607 {
608 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
609 }
610
611 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
612 {
613 return r600_translate_colorformat(format) != ~0U &&
614 r600_translate_colorswap(format) != ~0U;
615 }
616
617 static bool r600_is_zs_format_supported(enum pipe_format format)
618 {
619 return r600_translate_dbformat(format) != ~0U;
620 }
621
622 boolean evergreen_is_format_supported(struct pipe_screen *screen,
623 enum pipe_format format,
624 enum pipe_texture_target target,
625 unsigned sample_count,
626 unsigned usage)
627 {
628 unsigned retval = 0;
629
630 if (target >= PIPE_MAX_TEXTURE_TYPES) {
631 R600_ERR("r600: unsupported texture type %d\n", target);
632 return FALSE;
633 }
634
635 if (!util_format_is_supported(format, usage))
636 return FALSE;
637
638 /* Multisample */
639 if (sample_count > 1)
640 return FALSE;
641
642 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
643 r600_is_sampler_format_supported(screen, format)) {
644 retval |= PIPE_BIND_SAMPLER_VIEW;
645 }
646
647 if ((usage & (PIPE_BIND_RENDER_TARGET |
648 PIPE_BIND_DISPLAY_TARGET |
649 PIPE_BIND_SCANOUT |
650 PIPE_BIND_SHARED)) &&
651 r600_is_colorbuffer_format_supported(format)) {
652 retval |= usage &
653 (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED);
657 }
658
659 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
660 r600_is_zs_format_supported(format)) {
661 retval |= PIPE_BIND_DEPTH_STENCIL;
662 }
663
664 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
665 r600_is_vertex_format_supported(format)) {
666 retval |= PIPE_BIND_VERTEX_BUFFER;
667 }
668
669 if (usage & PIPE_BIND_TRANSFER_READ)
670 retval |= PIPE_BIND_TRANSFER_READ;
671 if (usage & PIPE_BIND_TRANSFER_WRITE)
672 retval |= PIPE_BIND_TRANSFER_WRITE;
673
674 return retval == usage;
675 }
676
677 static void *evergreen_create_blend_state(struct pipe_context *ctx,
678 const struct pipe_blend_state *state)
679 {
680 struct r600_context *rctx = (struct r600_context *)ctx;
681 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
682 struct r600_pipe_state *rstate;
683 uint32_t color_control = 0, target_mask;
684 /* XXX there is more then 8 framebuffer */
685 unsigned blend_cntl[8];
686
687 if (blend == NULL) {
688 return NULL;
689 }
690
691 rstate = &blend->rstate;
692
693 rstate->id = R600_PIPE_STATE_BLEND;
694
695 target_mask = 0;
696 if (state->logicop_enable) {
697 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
698 } else {
699 color_control |= (0xcc << 16);
700 }
701 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
702 if (state->independent_blend_enable) {
703 for (int i = 0; i < 8; i++) {
704 target_mask |= (state->rt[i].colormask << (4 * i));
705 }
706 } else {
707 for (int i = 0; i < 8; i++) {
708 target_mask |= (state->rt[0].colormask << (4 * i));
709 }
710 }
711 blend->cb_target_mask = target_mask;
712
713 if (target_mask)
714 color_control |= S_028808_MODE(V_028808_CB_NORMAL);
715 else
716 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
717
718 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
719 color_control);
720 /* only have dual source on MRT0 */
721 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
722 for (int i = 0; i < 8; i++) {
723 /* state->rt entries > 0 only written if independent blending */
724 const int j = state->independent_blend_enable ? i : 0;
725
726 unsigned eqRGB = state->rt[j].rgb_func;
727 unsigned srcRGB = state->rt[j].rgb_src_factor;
728 unsigned dstRGB = state->rt[j].rgb_dst_factor;
729 unsigned eqA = state->rt[j].alpha_func;
730 unsigned srcA = state->rt[j].alpha_src_factor;
731 unsigned dstA = state->rt[j].alpha_dst_factor;
732
733 blend_cntl[i] = 0;
734 if (!state->rt[j].blend_enable)
735 continue;
736
737 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
738 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
739 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
740 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
741
742 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
743 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
744 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
745 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
746 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
747 }
748 }
749 for (int i = 0; i < 8; i++) {
750 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
751 }
752
753 return rstate;
754 }
755
756 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
757 const struct pipe_depth_stencil_alpha_state *state)
758 {
759 struct r600_context *rctx = (struct r600_context *)ctx;
760 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
761 unsigned db_depth_control, alpha_test_control, alpha_ref;
762 struct r600_pipe_state *rstate;
763
764 if (dsa == NULL) {
765 return NULL;
766 }
767
768 dsa->valuemask[0] = state->stencil[0].valuemask;
769 dsa->valuemask[1] = state->stencil[1].valuemask;
770 dsa->writemask[0] = state->stencil[0].writemask;
771 dsa->writemask[1] = state->stencil[1].writemask;
772
773 rstate = &dsa->rstate;
774
775 rstate->id = R600_PIPE_STATE_DSA;
776 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
777 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
778 S_028800_ZFUNC(state->depth.func);
779
780 /* stencil */
781 if (state->stencil[0].enabled) {
782 db_depth_control |= S_028800_STENCIL_ENABLE(1);
783 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
784 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
785 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
786 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
787
788 if (state->stencil[1].enabled) {
789 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
790 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
791 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
792 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
793 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
794 }
795 }
796
797 /* alpha */
798 alpha_test_control = 0;
799 alpha_ref = 0;
800 if (state->alpha.enabled) {
801 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
802 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
803 alpha_ref = fui(state->alpha.ref_value);
804 }
805 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
806 dsa->alpha_ref = alpha_ref;
807
808 /* misc */
809 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
810 return rstate;
811 }
812
813 static void *evergreen_create_rs_state(struct pipe_context *ctx,
814 const struct pipe_rasterizer_state *state)
815 {
816 struct r600_context *rctx = (struct r600_context *)ctx;
817 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
818 struct r600_pipe_state *rstate;
819 unsigned tmp;
820 unsigned prov_vtx = 1, polygon_dual_mode;
821 float psize_min, psize_max;
822
823 if (rs == NULL) {
824 return NULL;
825 }
826
827 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
828 state->fill_back != PIPE_POLYGON_MODE_FILL);
829
830 if (state->flatshade_first)
831 prov_vtx = 0;
832
833 rstate = &rs->rstate;
834 rs->flatshade = state->flatshade;
835 rs->sprite_coord_enable = state->sprite_coord_enable;
836 rs->two_side = state->light_twoside;
837 rs->clip_plane_enable = state->clip_plane_enable;
838 rs->pa_sc_line_stipple = state->line_stipple_enable ?
839 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
840 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
841 rs->pa_cl_clip_cntl =
842 S_028810_PS_UCP_MODE(3) |
843 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
844 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
845 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
846
847 /* offset */
848 rs->offset_units = state->offset_units;
849 rs->offset_scale = state->offset_scale * 12.0f;
850
851 rstate->id = R600_PIPE_STATE_RASTERIZER;
852 tmp = S_0286D4_FLAT_SHADE_ENA(1);
853 if (state->sprite_coord_enable) {
854 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
855 S_0286D4_PNT_SPRITE_OVRD_X(2) |
856 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
857 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
858 S_0286D4_PNT_SPRITE_OVRD_W(1);
859 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
860 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
861 }
862 }
863 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
864
865 /* point size 12.4 fixed point */
866 tmp = (unsigned)(state->point_size * 8.0);
867 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
868
869 if (state->point_size_per_vertex) {
870 psize_min = util_get_min_point_size(state);
871 psize_max = 8192;
872 } else {
873 /* Force the point size to be as if the vertex output was disabled. */
874 psize_min = state->point_size;
875 psize_max = state->point_size;
876 }
877 /* Divide by two, because 0.5 = 1 pixel. */
878 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
879 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
880 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
881
882 tmp = (unsigned)state->line_width * 8;
883 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
884 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
885 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
886 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
887
888 if (rctx->chip_class == CAYMAN) {
889 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
890 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
891 } else {
892 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
893 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
894 }
895 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
896 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
897 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
898 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
899 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
900 S_028814_FACE(!state->front_ccw) |
901 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
902 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
903 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
904 S_028814_POLY_MODE(polygon_dual_mode) |
905 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
906 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
907 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
908 return rstate;
909 }
910
911 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
912 const struct pipe_sampler_state *state)
913 {
914 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
915 union util_color uc;
916 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
917
918 if (rstate == NULL) {
919 return NULL;
920 }
921
922 rstate->id = R600_PIPE_STATE_SAMPLER;
923 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
924 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
925 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
926 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
927 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
928 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
929 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
930 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
931 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
932 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
933 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
934 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
935 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
936 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
937 NULL, 0);
938 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
939 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
940 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
941 S_03C008_TYPE(1),
942 NULL, 0);
943
944 if (uc.ui) {
945 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
946 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
947 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
948 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
949 }
950 return rstate;
951 }
952
953 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
954 struct pipe_resource *texture,
955 const struct pipe_sampler_view *state)
956 {
957 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
958 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
959 struct r600_pipe_resource_state *rstate;
960 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
961 unsigned format, endian;
962 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
963 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
964 unsigned height, depth, width;
965 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
966
967 if (view == NULL)
968 return NULL;
969 rstate = &view->state;
970
971 /* initialize base object */
972 view->base = *state;
973 view->base.texture = NULL;
974 pipe_reference(NULL, &texture->reference);
975 view->base.texture = texture;
976 view->base.reference.count = 1;
977 view->base.context = ctx;
978
979 swizzle[0] = state->swizzle_r;
980 swizzle[1] = state->swizzle_g;
981 swizzle[2] = state->swizzle_b;
982 swizzle[3] = state->swizzle_a;
983
984 format = r600_translate_texformat(ctx->screen, state->format,
985 swizzle,
986 &word4, &yuv_format);
987 assert(format != ~0);
988 if (format == ~0) {
989 FREE(view);
990 return NULL;
991 }
992
993 if (tmp->is_depth && !tmp->is_flushing_texture) {
994 r600_init_flushed_depth_texture(ctx, texture, NULL);
995 tmp = tmp->flushed_depth_texture;
996 if (!tmp) {
997 FREE(view);
998 return NULL;
999 }
1000 }
1001
1002 endian = r600_colorformat_endian_swap(format);
1003
1004 if (!rscreen->use_surface_alloc) {
1005 height = texture->height0;
1006 depth = texture->depth0;
1007 width = texture->width0;
1008 pitch = align(tmp->pitch_in_blocks[0] *
1009 util_format_get_blockwidth(state->format), 8);
1010 array_mode = tmp->array_mode[0];
1011 tile_type = tmp->tile_type;
1012 tile_split = 0;
1013 macro_aspect = 0;
1014 bankw = 0;
1015 bankh = 0;
1016 } else {
1017 width = tmp->surface.level[0].npix_x;
1018 height = tmp->surface.level[0].npix_y;
1019 depth = tmp->surface.level[0].npix_z;
1020 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1021 tile_type = tmp->tile_type;
1022
1023 switch (tmp->surface.level[0].mode) {
1024 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1025 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1026 break;
1027 case RADEON_SURF_MODE_2D:
1028 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1029 break;
1030 case RADEON_SURF_MODE_1D:
1031 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1032 break;
1033 case RADEON_SURF_MODE_LINEAR:
1034 default:
1035 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1036 break;
1037 }
1038 tile_split = tmp->surface.tile_split;
1039 macro_aspect = tmp->surface.mtilea;
1040 bankw = tmp->surface.bankw;
1041 bankh = tmp->surface.bankh;
1042 tile_split = eg_tile_split(tile_split);
1043 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1044 bankw = eg_bank_wh(bankw);
1045 bankh = eg_bank_wh(bankh);
1046 }
1047 /* 128 bit formats require tile type = 1 */
1048 if (rscreen->chip_class == CAYMAN) {
1049 if (util_format_get_blocksize(state->format) >= 16)
1050 tile_type = 1;
1051 }
1052 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1053
1054 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1055 height = 1;
1056 depth = texture->array_size;
1057 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1058 depth = texture->array_size;
1059 }
1060
1061 rstate->bo[0] = &tmp->resource;
1062 rstate->bo[1] = &tmp->resource;
1063 rstate->bo_usage[0] = RADEON_USAGE_READ;
1064 rstate->bo_usage[1] = RADEON_USAGE_READ;
1065
1066 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1067 S_030000_PITCH((pitch / 8) - 1) |
1068 S_030000_TEX_WIDTH(width - 1));
1069 if (rscreen->chip_class == CAYMAN)
1070 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1071 else
1072 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1073 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1074 S_030004_TEX_DEPTH(depth - 1) |
1075 S_030004_ARRAY_MODE(array_mode));
1076 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1077 if (state->u.tex.last_level) {
1078 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1079 } else {
1080 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1081 }
1082 rstate->val[4] = (word4 |
1083 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1084 S_030010_ENDIAN_SWAP(endian) |
1085 S_030010_BASE_LEVEL(state->u.tex.first_level));
1086 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1087 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1088 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1089 /* aniso max 16 samples */
1090 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1091 (S_030018_TILE_SPLIT(tile_split));
1092 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1093 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1094 S_03001C_BANK_WIDTH(bankw) |
1095 S_03001C_BANK_HEIGHT(bankh) |
1096 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1097 S_03001C_NUM_BANKS(nbanks);
1098
1099 return &view->base;
1100 }
1101
1102 static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1103 struct pipe_sampler_view **views)
1104 {
1105 struct r600_context *rctx = (struct r600_context *)ctx;
1106 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1107 r600_context_pipe_state_set_vs_resource);
1108 }
1109
1110 static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1111 struct pipe_sampler_view **views)
1112 {
1113 struct r600_context *rctx = (struct r600_context *)ctx;
1114 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1115 r600_context_pipe_state_set_ps_resource);
1116 }
1117
1118 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1119 {
1120 struct r600_context *rctx = (struct r600_context *)ctx;
1121 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1122
1123 if (count)
1124 r600_inval_texture_cache(rctx);
1125
1126 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1127 rctx->ps_samplers.n_samplers = count;
1128
1129 for (int i = 0; i < count; i++) {
1130 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1131 }
1132 }
1133
1134 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1135 {
1136 struct r600_context *rctx = (struct r600_context *)ctx;
1137 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1138
1139 if (count)
1140 r600_inval_texture_cache(rctx);
1141
1142 for (int i = 0; i < count; i++) {
1143 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1144 }
1145 }
1146
1147 static void evergreen_set_clip_state(struct pipe_context *ctx,
1148 const struct pipe_clip_state *state)
1149 {
1150 struct r600_context *rctx = (struct r600_context *)ctx;
1151 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1152 struct pipe_constant_buffer cb;
1153
1154 if (rstate == NULL)
1155 return;
1156
1157 rctx->clip = *state;
1158 rstate->id = R600_PIPE_STATE_CLIP;
1159 for (int i = 0; i < 6; i++) {
1160 r600_pipe_state_add_reg(rstate,
1161 R_0285BC_PA_CL_UCP0_X + i * 16,
1162 fui(state->ucp[i][0]));
1163 r600_pipe_state_add_reg(rstate,
1164 R_0285C0_PA_CL_UCP0_Y + i * 16,
1165 fui(state->ucp[i][1]) );
1166 r600_pipe_state_add_reg(rstate,
1167 R_0285C4_PA_CL_UCP0_Z + i * 16,
1168 fui(state->ucp[i][2]));
1169 r600_pipe_state_add_reg(rstate,
1170 R_0285C8_PA_CL_UCP0_W + i * 16,
1171 fui(state->ucp[i][3]));
1172 }
1173
1174 free(rctx->states[R600_PIPE_STATE_CLIP]);
1175 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1176 r600_context_pipe_state_set(rctx, rstate);
1177
1178 cb.buffer = NULL;
1179 cb.user_buffer = state->ucp;
1180 cb.buffer_offset = 0;
1181 cb.buffer_size = 4*4*8;
1182 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1183 pipe_resource_reference(&cb.buffer, NULL);
1184 }
1185
1186 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1187 const struct pipe_poly_stipple *state)
1188 {
1189 }
1190
1191 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1192 {
1193 }
1194
1195 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1196 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1197 uint32_t *tl, uint32_t *br)
1198 {
1199 /* EG hw workaround */
1200 if (br_x == 0)
1201 tl_x = 1;
1202 if (br_y == 0)
1203 tl_y = 1;
1204
1205 /* cayman hw workaround */
1206 if (rctx->chip_class == CAYMAN) {
1207 if (br_x == 1 && br_y == 1)
1208 br_x = 2;
1209 }
1210
1211 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1212 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1213 }
1214
1215 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1216 const struct pipe_scissor_state *state)
1217 {
1218 struct r600_context *rctx = (struct r600_context *)ctx;
1219 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1220 uint32_t tl, br;
1221
1222 if (rstate == NULL)
1223 return;
1224
1225 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1226
1227 rstate->id = R600_PIPE_STATE_SCISSOR;
1228 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1229 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1230
1231 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1232 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1233 r600_context_pipe_state_set(rctx, rstate);
1234 }
1235
1236 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1237 const struct pipe_viewport_state *state)
1238 {
1239 struct r600_context *rctx = (struct r600_context *)ctx;
1240 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1241
1242 if (rstate == NULL)
1243 return;
1244
1245 rctx->viewport = *state;
1246 rstate->id = R600_PIPE_STATE_VIEWPORT;
1247 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1248 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1249 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1250 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1251 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1252 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1253
1254 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1255 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1256 r600_context_pipe_state_set(rctx, rstate);
1257 }
1258
1259 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1260 const struct pipe_framebuffer_state *state, int cb)
1261 {
1262 struct r600_screen *rscreen = rctx->screen;
1263 struct r600_resource_texture *rtex;
1264 struct pipe_resource * pipe_tex;
1265 struct r600_surface *surf;
1266 unsigned level = state->cbufs[cb]->u.tex.level;
1267 unsigned pitch, slice;
1268 unsigned color_info, color_attrib, color_dim = 0;
1269 unsigned format, swap, ntype, endian;
1270 uint64_t offset;
1271 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1272 const struct util_format_description *desc;
1273 int i;
1274 unsigned blend_clamp = 0, blend_bypass = 0;
1275
1276 surf = (struct r600_surface *)state->cbufs[cb];
1277 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1278 pipe_tex = state->cbufs[cb]->texture;
1279
1280 if (rtex->is_depth && !rtex->is_flushing_texture) {
1281 r600_init_flushed_depth_texture(&rctx->context,
1282 state->cbufs[cb]->texture, NULL);
1283 rtex = rtex->flushed_depth_texture;
1284 assert(rtex);
1285 }
1286
1287 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1288 if (!rscreen->use_surface_alloc) {
1289 offset = r600_texture_get_offset(rtex,
1290 level, state->cbufs[cb]->u.tex.first_layer);
1291 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1292 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1293 if (slice) {
1294 slice = slice - 1;
1295 }
1296 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1297 tile_split = 0;
1298 macro_aspect = 0;
1299 bankw = 0;
1300 bankh = 0;
1301 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1302 tile_type = rtex->tile_type;
1303 } else {
1304 /* workaround for linear buffers */
1305 tile_type = 1;
1306 }
1307 } else {
1308 offset = rtex->surface.level[level].offset;
1309 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1310 offset += rtex->surface.level[level].slice_size *
1311 state->cbufs[cb]->u.tex.first_layer;
1312 }
1313 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1314 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1315 if (slice) {
1316 slice = slice - 1;
1317 }
1318 color_info = 0;
1319 switch (rtex->surface.level[level].mode) {
1320 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1321 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1322 tile_type = 1;
1323 break;
1324 case RADEON_SURF_MODE_1D:
1325 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1326 tile_type = rtex->tile_type;
1327 break;
1328 case RADEON_SURF_MODE_2D:
1329 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1330 tile_type = rtex->tile_type;
1331 break;
1332 case RADEON_SURF_MODE_LINEAR:
1333 default:
1334 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1335 tile_type = 1;
1336 break;
1337 }
1338 tile_split = rtex->surface.tile_split;
1339 macro_aspect = rtex->surface.mtilea;
1340 bankw = rtex->surface.bankw;
1341 bankh = rtex->surface.bankh;
1342 tile_split = eg_tile_split(tile_split);
1343 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1344 bankw = eg_bank_wh(bankw);
1345 bankh = eg_bank_wh(bankh);
1346 }
1347 /* 128 bit formats require tile type = 1 */
1348 if (rscreen->chip_class == CAYMAN) {
1349 if (util_format_get_blocksize(surf->base.format) >= 16)
1350 tile_type = 1;
1351 }
1352 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1353 desc = util_format_description(surf->base.format);
1354 for (i = 0; i < 4; i++) {
1355 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1356 break;
1357 }
1358 }
1359
1360 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1361 S_028C74_NUM_BANKS(nbanks) |
1362 S_028C74_BANK_WIDTH(bankw) |
1363 S_028C74_BANK_HEIGHT(bankh) |
1364 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1365 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1366
1367 ntype = V_028C70_NUMBER_UNORM;
1368 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1369 ntype = V_028C70_NUMBER_SRGB;
1370 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1371 if (desc->channel[i].normalized)
1372 ntype = V_028C70_NUMBER_SNORM;
1373 else if (desc->channel[i].pure_integer)
1374 ntype = V_028C70_NUMBER_SINT;
1375 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1376 if (desc->channel[i].normalized)
1377 ntype = V_028C70_NUMBER_UNORM;
1378 else if (desc->channel[i].pure_integer)
1379 ntype = V_028C70_NUMBER_UINT;
1380 }
1381
1382 format = r600_translate_colorformat(surf->base.format);
1383 assert(format != ~0);
1384
1385 swap = r600_translate_colorswap(surf->base.format);
1386 assert(swap != ~0);
1387
1388 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1389 endian = ENDIAN_NONE;
1390 } else {
1391 endian = r600_colorformat_endian_swap(format);
1392 }
1393
1394 /* blend clamp should be set for all NORM/SRGB types */
1395 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1396 ntype == V_028C70_NUMBER_SRGB)
1397 blend_clamp = 1;
1398
1399 /* set blend bypass according to docs if SINT/UINT or
1400 8/24 COLOR variants */
1401 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1402 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1403 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1404 blend_clamp = 0;
1405 blend_bypass = 1;
1406 }
1407
1408 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
1409 rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1410 else
1411 rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1412
1413 color_info |= S_028C70_FORMAT(format) |
1414 S_028C70_COMP_SWAP(swap) |
1415 S_028C70_BLEND_CLAMP(blend_clamp) |
1416 S_028C70_BLEND_BYPASS(blend_bypass) |
1417 S_028C70_NUMBER_TYPE(ntype) |
1418 S_028C70_ENDIAN(endian);
1419
1420 if (rtex->is_rat) {
1421 color_info |= S_028C70_RAT(1);
1422 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1423 | S_028C78_HEIGHT_MAX(pipe_tex->height0);
1424 }
1425
1426 /* EXPORT_NORM is an optimzation that can be enabled for better
1427 * performance in certain cases.
1428 * EXPORT_NORM can be enabled if:
1429 * - 11-bit or smaller UNORM/SNORM/SRGB
1430 * - 16-bit or smaller FLOAT
1431 */
1432 /* XXX: This should probably be the same for all CBs if we want
1433 * useful alpha tests. */
1434 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1435 ((desc->channel[i].size < 12 &&
1436 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1437 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1438 (desc->channel[i].size < 17 &&
1439 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1440 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1441 } else {
1442 rctx->export_16bpc = false;
1443 }
1444 rctx->alpha_ref_dirty = true;
1445
1446 /* for possible dual-src MRT */
1447 if (cb == 0 && rctx->framebuffer.nr_cbufs == 1 && !rtex->is_rat) {
1448 r600_pipe_state_add_reg_bo(rstate,
1449 R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1450 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1451 }
1452
1453 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1454 offset >>= 8;
1455
1456 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1457 r600_pipe_state_add_reg_bo(rstate,
1458 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1459 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1460 r600_pipe_state_add_reg(rstate,
1461 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1462 color_dim);
1463 r600_pipe_state_add_reg_bo(rstate,
1464 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1465 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1466 r600_pipe_state_add_reg(rstate,
1467 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1468 S_028C64_PITCH_TILE_MAX(pitch));
1469 r600_pipe_state_add_reg(rstate,
1470 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1471 S_028C68_SLICE_TILE_MAX(slice));
1472 if (!rscreen->use_surface_alloc) {
1473 r600_pipe_state_add_reg(rstate,
1474 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1475 0x00000000);
1476 } else {
1477 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1478 r600_pipe_state_add_reg(rstate,
1479 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1480 0x00000000);
1481 } else {
1482 r600_pipe_state_add_reg(rstate,
1483 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1484 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1485 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1486 }
1487 }
1488 r600_pipe_state_add_reg_bo(rstate,
1489 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1490 color_attrib,
1491 &rtex->resource, RADEON_USAGE_READWRITE);
1492 }
1493
1494 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1495 const struct pipe_framebuffer_state *state)
1496 {
1497 struct r600_screen *rscreen = rctx->screen;
1498 struct r600_resource_texture *rtex;
1499 struct r600_surface *surf;
1500 uint64_t offset;
1501 unsigned level, first_layer, pitch, slice, format, array_mode;
1502 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1503
1504 if (state->zsbuf == NULL)
1505 return;
1506
1507 surf = (struct r600_surface *)state->zsbuf;
1508 level = surf->base.u.tex.level;
1509 rtex = (struct r600_resource_texture*)surf->base.texture;
1510 first_layer = surf->base.u.tex.first_layer;
1511 format = r600_translate_dbformat(surf->base.format);
1512 assert(format != ~0);
1513
1514 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1515 /* XXX remove this once tiling is properly supported */
1516 if (!rscreen->use_surface_alloc) {
1517 /* XXX remove this once tiling is properly supported */
1518 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1519 V_028C70_ARRAY_1D_TILED_THIN1;
1520
1521 offset += r600_texture_get_offset(rtex, level, first_layer);
1522 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1523 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1524 if (slice) {
1525 slice = slice - 1;
1526 }
1527 tile_split = 0;
1528 macro_aspect = 0;
1529 bankw = 0;
1530 bankh = 0;
1531 } else {
1532 offset += rtex->surface.level[level].offset;
1533 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1534 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1535 if (slice) {
1536 slice = slice - 1;
1537 }
1538 switch (rtex->surface.level[level].mode) {
1539 case RADEON_SURF_MODE_2D:
1540 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1541 break;
1542 case RADEON_SURF_MODE_1D:
1543 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1544 case RADEON_SURF_MODE_LINEAR:
1545 default:
1546 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1547 break;
1548 }
1549 tile_split = rtex->surface.tile_split;
1550 macro_aspect = rtex->surface.mtilea;
1551 bankw = rtex->surface.bankw;
1552 bankh = rtex->surface.bankh;
1553 tile_split = eg_tile_split(tile_split);
1554 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1555 bankw = eg_bank_wh(bankw);
1556 bankh = eg_bank_wh(bankh);
1557 }
1558 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1559 offset >>= 8;
1560
1561 z_info = S_028040_ARRAY_MODE(array_mode) |
1562 S_028040_FORMAT(format) |
1563 S_028040_TILE_SPLIT(tile_split)|
1564 S_028040_NUM_BANKS(nbanks) |
1565 S_028040_BANK_WIDTH(bankw) |
1566 S_028040_BANK_HEIGHT(bankh) |
1567 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1568
1569 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE,
1570 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1571 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE,
1572 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1573 if (!rscreen->use_surface_alloc) {
1574 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1575 0x00000000);
1576 } else {
1577 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1578 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1579 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1580 }
1581
1582 if (rtex->stencil) {
1583 uint64_t stencil_offset =
1584 r600_texture_get_offset(rtex->stencil, level, first_layer);
1585 unsigned stile_split;
1586
1587 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1588 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1589 stencil_offset >>= 8;
1590
1591 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1592 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1593 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1594 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1595 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1596 1 | S_028044_TILE_SPLIT(stile_split),
1597 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1598 } else {
1599 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1600 uint64_t stencil_offset = rtex->surface.stencil_offset;
1601 unsigned stile_split = rtex->surface.stencil_tile_split;
1602
1603 stile_split = eg_tile_split(stile_split);
1604 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1605 stencil_offset += rtex->surface.level[level].offset / 4;
1606 stencil_offset >>= 8;
1607
1608 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1609 stencil_offset, &rtex->resource,
1610 RADEON_USAGE_READWRITE);
1611 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1612 stencil_offset, &rtex->resource,
1613 RADEON_USAGE_READWRITE);
1614 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1615 1 | S_028044_TILE_SPLIT(stile_split),
1616 &rtex->resource,
1617 RADEON_USAGE_READWRITE);
1618 } else {
1619 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1620 offset, &rtex->resource,
1621 RADEON_USAGE_READWRITE);
1622 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1623 offset, &rtex->resource,
1624 RADEON_USAGE_READWRITE);
1625 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1626 1, NULL, RADEON_USAGE_READWRITE);
1627 }
1628 }
1629
1630 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, z_info,
1631 &rtex->resource, RADEON_USAGE_READWRITE);
1632 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1633 S_028058_PITCH_TILE_MAX(pitch));
1634 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1635 S_02805C_SLICE_TILE_MAX(slice));
1636 }
1637
1638 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1639 const struct pipe_framebuffer_state *state)
1640 {
1641 struct r600_context *rctx = (struct r600_context *)ctx;
1642 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1643 uint32_t tl, br;
1644 int i;
1645
1646 if (rstate == NULL)
1647 return;
1648
1649 r600_flush_framebuffer(rctx, false);
1650
1651 /* unreference old buffer and reference new one */
1652 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1653
1654 util_copy_framebuffer_state(&rctx->framebuffer, state);
1655
1656 /* build states */
1657 rctx->export_16bpc = true;
1658 rctx->nr_cbufs = state->nr_cbufs;
1659 for (i = 0; i < state->nr_cbufs; i++) {
1660 evergreen_cb(rctx, rstate, state, i);
1661 }
1662
1663 for (; i < 8 ; i++) {
1664 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1665 }
1666
1667 if (state->zsbuf) {
1668 evergreen_db(rctx, rstate, state);
1669 }
1670
1671 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1672
1673 r600_pipe_state_add_reg(rstate,
1674 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1675 r600_pipe_state_add_reg(rstate,
1676 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1677
1678 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1679 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1680 r600_context_pipe_state_set(rctx, rstate);
1681
1682 if (state->zsbuf) {
1683 evergreen_polygon_offset_update(rctx);
1684 }
1685
1686 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1687 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1688 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1689 }
1690 }
1691
1692 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1693 {
1694 struct radeon_winsys_cs *cs = rctx->cs;
1695 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1696 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1697 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1698
1699 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1700 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1701 r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1702 }
1703
1704 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1705 {
1706 struct radeon_winsys_cs *cs = rctx->cs;
1707 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1708 unsigned db_render_control = 0;
1709 unsigned db_count_control = 0;
1710 unsigned db_render_override =
1711 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1712 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1713 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1714
1715 if (a->occlusion_query_enabled) {
1716 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1717 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1718 }
1719 if (a->flush_depthstencil_through_cb) {
1720 db_render_control |= S_028000_DEPTH_COPY_ENABLE(1) |
1721 S_028000_STENCIL_COPY_ENABLE(1) |
1722 S_028000_COPY_CENTROID(1);
1723 }
1724
1725 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1726 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1727 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1728 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1729 }
1730
1731 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1732 struct r600_vertexbuf_state *state,
1733 unsigned resource_offset,
1734 unsigned pkt_flags)
1735 {
1736 struct radeon_winsys_cs *cs = rctx->cs;
1737 uint32_t dirty_mask = state->dirty_mask;
1738
1739 while (dirty_mask) {
1740 struct pipe_vertex_buffer *vb;
1741 struct r600_resource *rbuffer;
1742 uint64_t va;
1743 unsigned buffer_index = u_bit_scan(&dirty_mask);
1744
1745 vb = &state->vb[buffer_index];
1746 rbuffer = (struct r600_resource*)vb->buffer;
1747 assert(rbuffer);
1748
1749 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1750 va += vb->buffer_offset;
1751
1752 /* fetch resources start at index 992 */
1753 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1754 r600_write_value(cs, (resource_offset + buffer_index) * 8);
1755 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1756 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1757 r600_write_value(cs, /* RESOURCEi_WORD2 */
1758 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1759 S_030008_STRIDE(vb->stride) |
1760 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1761 r600_write_value(cs, /* RESOURCEi_WORD3 */
1762 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1763 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1764 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1765 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1766 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1767 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1768 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1769 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1770
1771 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1772 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1773 }
1774 state->dirty_mask = 0;
1775 }
1776
1777 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1778 {
1779 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1780 }
1781
1782 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1783 {
1784 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1785 RADEON_CP_PACKET3_COMPUTE_MODE);
1786 }
1787
1788 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1789 struct r600_constbuf_state *state,
1790 unsigned buffer_id_base,
1791 unsigned reg_alu_constbuf_size,
1792 unsigned reg_alu_const_cache)
1793 {
1794 struct radeon_winsys_cs *cs = rctx->cs;
1795 uint32_t dirty_mask = state->dirty_mask;
1796
1797 while (dirty_mask) {
1798 struct pipe_constant_buffer *cb;
1799 struct r600_resource *rbuffer;
1800 uint64_t va;
1801 unsigned buffer_index = ffs(dirty_mask) - 1;
1802
1803 cb = &state->cb[buffer_index];
1804 rbuffer = (struct r600_resource*)cb->buffer;
1805 assert(rbuffer);
1806
1807 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1808 va += cb->buffer_offset;
1809
1810 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1811 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1812 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1813
1814 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1815 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1816
1817 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1818 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1819 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1820 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1821 r600_write_value(cs, /* RESOURCEi_WORD2 */
1822 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1823 S_030008_STRIDE(16) |
1824 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1825 r600_write_value(cs, /* RESOURCEi_WORD3 */
1826 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1827 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1828 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1829 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1830 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1831 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1832 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1833 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1834
1835 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1836 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1837
1838 dirty_mask &= ~(1 << buffer_index);
1839 }
1840 state->dirty_mask = 0;
1841 }
1842
1843 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1844 {
1845 evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1846 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1847 R_028980_ALU_CONST_CACHE_VS_0);
1848 }
1849
1850 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1851 {
1852 evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1853 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1854 R_028940_ALU_CONST_CACHE_PS_0);
1855 }
1856
1857 void evergreen_init_state_functions(struct r600_context *rctx)
1858 {
1859 r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
1860 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1861 r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
1862 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1863 r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
1864 r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
1865 r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
1866 r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
1867
1868 rctx->context.create_blend_state = evergreen_create_blend_state;
1869 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1870 rctx->context.create_fs_state = r600_create_shader_state_ps;
1871 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1872 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1873 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1874 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1875 rctx->context.create_vs_state = r600_create_shader_state_vs;
1876 rctx->context.bind_blend_state = r600_bind_blend_state;
1877 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1878 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1879 rctx->context.bind_fs_state = r600_bind_ps_shader;
1880 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1881 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1882 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1883 rctx->context.bind_vs_state = r600_bind_vs_shader;
1884 rctx->context.delete_blend_state = r600_delete_state;
1885 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1886 rctx->context.delete_fs_state = r600_delete_ps_shader;
1887 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1888 rctx->context.delete_sampler_state = r600_delete_state;
1889 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1890 rctx->context.delete_vs_state = r600_delete_vs_shader;
1891 rctx->context.set_blend_color = r600_set_blend_color;
1892 rctx->context.set_clip_state = evergreen_set_clip_state;
1893 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1894 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
1895 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1896 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1897 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1898 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1899 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1900 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1901 rctx->context.set_index_buffer = r600_set_index_buffer;
1902 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
1903 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1904 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1905 rctx->context.texture_barrier = r600_texture_barrier;
1906 rctx->context.create_stream_output_target = r600_create_so_target;
1907 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1908 rctx->context.set_stream_output_targets = r600_set_so_targets;
1909 evergreen_init_compute_state_functions(rctx);
1910 }
1911
1912 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1913 {
1914 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1915
1916 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1917
1918 /* This must be first. */
1919 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1920 r600_store_value(cb, 0x80000000);
1921 r600_store_value(cb, 0x80000000);
1922
1923 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1924 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1925 /* always set the temp clauses */
1926 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1927
1928 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1929 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1930 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1931
1932 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1933
1934 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1935
1936 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1937 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1938 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1939 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1940 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1941 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1942 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1943 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1944 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1945 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1946 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1947 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1948 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1949 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1950
1951 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1952 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1953 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1954
1955 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1956 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1957 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1958
1959 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1960
1961 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1962
1963 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1964 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1965 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1966
1967 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1968 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1969 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1970
1971 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1972
1973 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1974 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1975 r600_store_value(cb, 0);
1976 r600_store_value(cb, 0);
1977 r600_store_value(cb, 0);
1978 r600_store_value(cb, 0);
1979 r600_store_value(cb, 0);
1980 r600_store_value(cb, 0);
1981 r600_store_value(cb, 0);
1982 r600_store_value(cb, 0);
1983 r600_store_value(cb, 0);
1984 r600_store_value(cb, 0);
1985 r600_store_value(cb, 0);
1986 r600_store_value(cb, 0);
1987 r600_store_value(cb, 0);
1988 r600_store_value(cb, 0);
1989 r600_store_value(cb, 0);
1990 r600_store_value(cb, 0);
1991 r600_store_value(cb, 0);
1992 r600_store_value(cb, 0);
1993 r600_store_value(cb, 0);
1994 r600_store_value(cb, 0);
1995 r600_store_value(cb, 0);
1996 r600_store_value(cb, 0);
1997 r600_store_value(cb, 0);
1998 r600_store_value(cb, 0);
1999 r600_store_value(cb, 0);
2000 r600_store_value(cb, 0);
2001 r600_store_value(cb, 0);
2002 r600_store_value(cb, 0);
2003 r600_store_value(cb, 0);
2004 r600_store_value(cb, 0);
2005 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2006 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2007 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2008
2009 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2010
2011 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2012 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
2013 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
2014
2015 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2016 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2017 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2018
2019 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2020
2021 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2022 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2023 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2024 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2025
2026 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2027 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2028
2029 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2030 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2031 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2032
2033 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2034 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2035 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2036 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2037
2038 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2039 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2040 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2041
2042 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2043 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2044 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2045 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2046 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2047
2048 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2049 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2050 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2051
2052 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2053 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2054 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2055
2056 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2057 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2058 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2059
2060 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2061 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2062
2063 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2064 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2065 }
2066
2067 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2068 {
2069 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2070 int ps_prio;
2071 int vs_prio;
2072 int gs_prio;
2073 int es_prio;
2074 int hs_prio, cs_prio, ls_prio;
2075 int num_ps_gprs;
2076 int num_vs_gprs;
2077 int num_gs_gprs;
2078 int num_es_gprs;
2079 int num_hs_gprs;
2080 int num_ls_gprs;
2081 int num_temp_gprs;
2082 int num_ps_threads;
2083 int num_vs_threads;
2084 int num_gs_threads;
2085 int num_es_threads;
2086 int num_hs_threads;
2087 int num_ls_threads;
2088 int num_ps_stack_entries;
2089 int num_vs_stack_entries;
2090 int num_gs_stack_entries;
2091 int num_es_stack_entries;
2092 int num_hs_stack_entries;
2093 int num_ls_stack_entries;
2094 enum radeon_family family;
2095 unsigned tmp;
2096
2097 if (rctx->chip_class == CAYMAN) {
2098 cayman_init_atom_start_cs(rctx);
2099 return;
2100 }
2101
2102 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2103
2104 /* This must be first. */
2105 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2106 r600_store_value(cb, 0x80000000);
2107 r600_store_value(cb, 0x80000000);
2108
2109 family = rctx->family;
2110 ps_prio = 0;
2111 vs_prio = 1;
2112 gs_prio = 2;
2113 es_prio = 3;
2114 hs_prio = 0;
2115 ls_prio = 0;
2116 cs_prio = 0;
2117
2118 switch (family) {
2119 case CHIP_CEDAR:
2120 default:
2121 num_ps_gprs = 93;
2122 num_vs_gprs = 46;
2123 num_temp_gprs = 4;
2124 num_gs_gprs = 31;
2125 num_es_gprs = 31;
2126 num_hs_gprs = 23;
2127 num_ls_gprs = 23;
2128 num_ps_threads = 96;
2129 num_vs_threads = 16;
2130 num_gs_threads = 16;
2131 num_es_threads = 16;
2132 num_hs_threads = 16;
2133 num_ls_threads = 16;
2134 num_ps_stack_entries = 42;
2135 num_vs_stack_entries = 42;
2136 num_gs_stack_entries = 42;
2137 num_es_stack_entries = 42;
2138 num_hs_stack_entries = 42;
2139 num_ls_stack_entries = 42;
2140 break;
2141 case CHIP_REDWOOD:
2142 num_ps_gprs = 93;
2143 num_vs_gprs = 46;
2144 num_temp_gprs = 4;
2145 num_gs_gprs = 31;
2146 num_es_gprs = 31;
2147 num_hs_gprs = 23;
2148 num_ls_gprs = 23;
2149 num_ps_threads = 128;
2150 num_vs_threads = 20;
2151 num_gs_threads = 20;
2152 num_es_threads = 20;
2153 num_hs_threads = 20;
2154 num_ls_threads = 20;
2155 num_ps_stack_entries = 42;
2156 num_vs_stack_entries = 42;
2157 num_gs_stack_entries = 42;
2158 num_es_stack_entries = 42;
2159 num_hs_stack_entries = 42;
2160 num_ls_stack_entries = 42;
2161 break;
2162 case CHIP_JUNIPER:
2163 num_ps_gprs = 93;
2164 num_vs_gprs = 46;
2165 num_temp_gprs = 4;
2166 num_gs_gprs = 31;
2167 num_es_gprs = 31;
2168 num_hs_gprs = 23;
2169 num_ls_gprs = 23;
2170 num_ps_threads = 128;
2171 num_vs_threads = 20;
2172 num_gs_threads = 20;
2173 num_es_threads = 20;
2174 num_hs_threads = 20;
2175 num_ls_threads = 20;
2176 num_ps_stack_entries = 85;
2177 num_vs_stack_entries = 85;
2178 num_gs_stack_entries = 85;
2179 num_es_stack_entries = 85;
2180 num_hs_stack_entries = 85;
2181 num_ls_stack_entries = 85;
2182 break;
2183 case CHIP_CYPRESS:
2184 case CHIP_HEMLOCK:
2185 num_ps_gprs = 93;
2186 num_vs_gprs = 46;
2187 num_temp_gprs = 4;
2188 num_gs_gprs = 31;
2189 num_es_gprs = 31;
2190 num_hs_gprs = 23;
2191 num_ls_gprs = 23;
2192 num_ps_threads = 128;
2193 num_vs_threads = 20;
2194 num_gs_threads = 20;
2195 num_es_threads = 20;
2196 num_hs_threads = 20;
2197 num_ls_threads = 20;
2198 num_ps_stack_entries = 85;
2199 num_vs_stack_entries = 85;
2200 num_gs_stack_entries = 85;
2201 num_es_stack_entries = 85;
2202 num_hs_stack_entries = 85;
2203 num_ls_stack_entries = 85;
2204 break;
2205 case CHIP_PALM:
2206 num_ps_gprs = 93;
2207 num_vs_gprs = 46;
2208 num_temp_gprs = 4;
2209 num_gs_gprs = 31;
2210 num_es_gprs = 31;
2211 num_hs_gprs = 23;
2212 num_ls_gprs = 23;
2213 num_ps_threads = 96;
2214 num_vs_threads = 16;
2215 num_gs_threads = 16;
2216 num_es_threads = 16;
2217 num_hs_threads = 16;
2218 num_ls_threads = 16;
2219 num_ps_stack_entries = 42;
2220 num_vs_stack_entries = 42;
2221 num_gs_stack_entries = 42;
2222 num_es_stack_entries = 42;
2223 num_hs_stack_entries = 42;
2224 num_ls_stack_entries = 42;
2225 break;
2226 case CHIP_SUMO:
2227 num_ps_gprs = 93;
2228 num_vs_gprs = 46;
2229 num_temp_gprs = 4;
2230 num_gs_gprs = 31;
2231 num_es_gprs = 31;
2232 num_hs_gprs = 23;
2233 num_ls_gprs = 23;
2234 num_ps_threads = 96;
2235 num_vs_threads = 25;
2236 num_gs_threads = 25;
2237 num_es_threads = 25;
2238 num_hs_threads = 25;
2239 num_ls_threads = 25;
2240 num_ps_stack_entries = 42;
2241 num_vs_stack_entries = 42;
2242 num_gs_stack_entries = 42;
2243 num_es_stack_entries = 42;
2244 num_hs_stack_entries = 42;
2245 num_ls_stack_entries = 42;
2246 break;
2247 case CHIP_SUMO2:
2248 num_ps_gprs = 93;
2249 num_vs_gprs = 46;
2250 num_temp_gprs = 4;
2251 num_gs_gprs = 31;
2252 num_es_gprs = 31;
2253 num_hs_gprs = 23;
2254 num_ls_gprs = 23;
2255 num_ps_threads = 96;
2256 num_vs_threads = 25;
2257 num_gs_threads = 25;
2258 num_es_threads = 25;
2259 num_hs_threads = 25;
2260 num_ls_threads = 25;
2261 num_ps_stack_entries = 85;
2262 num_vs_stack_entries = 85;
2263 num_gs_stack_entries = 85;
2264 num_es_stack_entries = 85;
2265 num_hs_stack_entries = 85;
2266 num_ls_stack_entries = 85;
2267 break;
2268 case CHIP_BARTS:
2269 num_ps_gprs = 93;
2270 num_vs_gprs = 46;
2271 num_temp_gprs = 4;
2272 num_gs_gprs = 31;
2273 num_es_gprs = 31;
2274 num_hs_gprs = 23;
2275 num_ls_gprs = 23;
2276 num_ps_threads = 128;
2277 num_vs_threads = 20;
2278 num_gs_threads = 20;
2279 num_es_threads = 20;
2280 num_hs_threads = 20;
2281 num_ls_threads = 20;
2282 num_ps_stack_entries = 85;
2283 num_vs_stack_entries = 85;
2284 num_gs_stack_entries = 85;
2285 num_es_stack_entries = 85;
2286 num_hs_stack_entries = 85;
2287 num_ls_stack_entries = 85;
2288 break;
2289 case CHIP_TURKS:
2290 num_ps_gprs = 93;
2291 num_vs_gprs = 46;
2292 num_temp_gprs = 4;
2293 num_gs_gprs = 31;
2294 num_es_gprs = 31;
2295 num_hs_gprs = 23;
2296 num_ls_gprs = 23;
2297 num_ps_threads = 128;
2298 num_vs_threads = 20;
2299 num_gs_threads = 20;
2300 num_es_threads = 20;
2301 num_hs_threads = 20;
2302 num_ls_threads = 20;
2303 num_ps_stack_entries = 42;
2304 num_vs_stack_entries = 42;
2305 num_gs_stack_entries = 42;
2306 num_es_stack_entries = 42;
2307 num_hs_stack_entries = 42;
2308 num_ls_stack_entries = 42;
2309 break;
2310 case CHIP_CAICOS:
2311 num_ps_gprs = 93;
2312 num_vs_gprs = 46;
2313 num_temp_gprs = 4;
2314 num_gs_gprs = 31;
2315 num_es_gprs = 31;
2316 num_hs_gprs = 23;
2317 num_ls_gprs = 23;
2318 num_ps_threads = 128;
2319 num_vs_threads = 10;
2320 num_gs_threads = 10;
2321 num_es_threads = 10;
2322 num_hs_threads = 10;
2323 num_ls_threads = 10;
2324 num_ps_stack_entries = 42;
2325 num_vs_stack_entries = 42;
2326 num_gs_stack_entries = 42;
2327 num_es_stack_entries = 42;
2328 num_hs_stack_entries = 42;
2329 num_ls_stack_entries = 42;
2330 break;
2331 }
2332
2333 tmp = 0;
2334 switch (family) {
2335 case CHIP_CEDAR:
2336 case CHIP_PALM:
2337 case CHIP_SUMO:
2338 case CHIP_SUMO2:
2339 case CHIP_CAICOS:
2340 break;
2341 default:
2342 tmp |= S_008C00_VC_ENABLE(1);
2343 break;
2344 }
2345 tmp |= S_008C00_EXPORT_SRC_C(1);
2346 tmp |= S_008C00_CS_PRIO(cs_prio);
2347 tmp |= S_008C00_LS_PRIO(ls_prio);
2348 tmp |= S_008C00_HS_PRIO(hs_prio);
2349 tmp |= S_008C00_PS_PRIO(ps_prio);
2350 tmp |= S_008C00_VS_PRIO(vs_prio);
2351 tmp |= S_008C00_GS_PRIO(gs_prio);
2352 tmp |= S_008C00_ES_PRIO(es_prio);
2353
2354 /* enable dynamic GPR resource management */
2355 if (rctx->screen->info.drm_minor >= 7) {
2356 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2357 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2358 /* always set temp clauses */
2359 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2360 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2361 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2362 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2363 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2364 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2365 S_028838_PS_GPRS(0x1e) |
2366 S_028838_VS_GPRS(0x1e) |
2367 S_028838_GS_GPRS(0x1e) |
2368 S_028838_ES_GPRS(0x1e) |
2369 S_028838_HS_GPRS(0x1e) |
2370 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2371 } else {
2372 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2373 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2374
2375 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2376 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2377 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2378 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2379
2380 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2381 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2382 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2383
2384 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2385 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2386 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2387 }
2388
2389 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2390 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2391 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2392 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2393 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2394 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2395
2396 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2397 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2398 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2399
2400 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2401 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2402 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2403
2404 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2405 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2406 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2407
2408 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2409 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2410 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2411
2412 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2413 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2414
2415 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2416 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2417
2418 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2419
2420 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2421 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2422 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2423 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2424 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2425 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2426 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2427
2428 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2429 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2430 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2431 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2432 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2433
2434 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2435 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2436 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2437 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2438 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2439 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2440 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2441 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2442 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2443 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2444 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2445 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2446 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2447 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2448
2449 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2450 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2451 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2452
2453 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2454 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2455 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2456
2457 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2458
2459 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2460 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0);
2464 r600_store_value(cb, 0);
2465 r600_store_value(cb, 0);
2466 r600_store_value(cb, 0);
2467 r600_store_value(cb, 0);
2468 r600_store_value(cb, 0);
2469 r600_store_value(cb, 0);
2470 r600_store_value(cb, 0);
2471 r600_store_value(cb, 0);
2472 r600_store_value(cb, 0);
2473 r600_store_value(cb, 0);
2474 r600_store_value(cb, 0);
2475 r600_store_value(cb, 0);
2476 r600_store_value(cb, 0);
2477 r600_store_value(cb, 0);
2478 r600_store_value(cb, 0);
2479 r600_store_value(cb, 0);
2480 r600_store_value(cb, 0);
2481 r600_store_value(cb, 0);
2482 r600_store_value(cb, 0);
2483 r600_store_value(cb, 0);
2484 r600_store_value(cb, 0);
2485 r600_store_value(cb, 0);
2486 r600_store_value(cb, 0);
2487 r600_store_value(cb, 0);
2488 r600_store_value(cb, 0);
2489 r600_store_value(cb, 0);
2490 r600_store_value(cb, 0);
2491 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2492 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2493 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2494
2495 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2496
2497 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2498 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2499 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2500
2501 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2502 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2503 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2504
2505 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2506 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2507 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2508
2509 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2510 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2511 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2512
2513 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2514 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2515 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2516 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2517
2518 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2519
2520 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2521 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2522 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2523
2524 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2525 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2526 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2527 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2528 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2529 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2530
2531 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2532
2533 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2534 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2535 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2536
2537 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2538 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2539 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2540
2541 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2542 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2543 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2544
2545 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2546 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2547
2548 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2549 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2550 }
2551
2552 void evergreen_polygon_offset_update(struct r600_context *rctx)
2553 {
2554 struct r600_pipe_state state;
2555
2556 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2557 state.nregs = 0;
2558 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2559 float offset_units = rctx->rasterizer->offset_units;
2560 unsigned offset_db_fmt_cntl = 0, depth;
2561
2562 switch (rctx->framebuffer.zsbuf->format) {
2563 case PIPE_FORMAT_Z24X8_UNORM:
2564 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2565 depth = -24;
2566 offset_units *= 2.0f;
2567 break;
2568 case PIPE_FORMAT_Z32_FLOAT:
2569 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2570 depth = -23;
2571 offset_units *= 1.0f;
2572 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2573 break;
2574 case PIPE_FORMAT_Z16_UNORM:
2575 depth = -16;
2576 offset_units *= 4.0f;
2577 break;
2578 default:
2579 return;
2580 }
2581 /* XXX some of those reg can be computed with cso */
2582 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2583 r600_pipe_state_add_reg(&state,
2584 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2585 fui(rctx->rasterizer->offset_scale));
2586 r600_pipe_state_add_reg(&state,
2587 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2588 fui(offset_units));
2589 r600_pipe_state_add_reg(&state,
2590 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2591 fui(rctx->rasterizer->offset_scale));
2592 r600_pipe_state_add_reg(&state,
2593 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2594 fui(offset_units));
2595 r600_pipe_state_add_reg(&state,
2596 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2597 offset_db_fmt_cntl);
2598 r600_context_pipe_state_set(rctx, &state);
2599 }
2600 }
2601
2602 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2603 {
2604 struct r600_context *rctx = (struct r600_context *)ctx;
2605 struct r600_pipe_state *rstate = &shader->rstate;
2606 struct r600_shader *rshader = &shader->shader;
2607 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2608 int pos_index = -1, face_index = -1;
2609 int ninterp = 0;
2610 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2611 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2612 unsigned z_export = 0, stencil_export = 0;
2613
2614 rstate->nregs = 0;
2615
2616 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2617 for (i = 0; i < rshader->ninput; i++) {
2618 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2619 POSITION goes via GPRs from the SC so isn't counted */
2620 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2621 pos_index = i;
2622 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2623 face_index = i;
2624 else {
2625 ninterp++;
2626 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2627 have_linear = TRUE;
2628 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2629 have_perspective = TRUE;
2630 if (rshader->input[i].centroid)
2631 have_centroid = TRUE;
2632 }
2633
2634 sid = rshader->input[i].spi_sid;
2635
2636 if (sid) {
2637
2638 tmp = S_028644_SEMANTIC(sid);
2639
2640 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2641 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2642 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2643 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2644 tmp |= S_028644_FLAT_SHADE(1);
2645 }
2646
2647 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2648 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2649 tmp |= S_028644_PT_SPRITE_TEX(1);
2650 }
2651
2652 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2653 tmp);
2654
2655 idx++;
2656 }
2657 }
2658
2659 for (i = 0; i < rshader->noutput; i++) {
2660 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2661 z_export = 1;
2662 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2663 stencil_export = 1;
2664 }
2665 if (rshader->uses_kill)
2666 db_shader_control |= S_02880C_KILL_ENABLE(1);
2667
2668 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2669 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2670
2671 exports_ps = 0;
2672 for (i = 0; i < rshader->noutput; i++) {
2673 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2674 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2675 exports_ps |= 1;
2676 }
2677
2678 num_cout = rshader->nr_ps_color_exports;
2679
2680 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2681 if (!exports_ps) {
2682 /* always at least export 1 component per pixel */
2683 exports_ps = 2;
2684 }
2685 shader->nr_ps_color_outputs = num_cout;
2686 if (ninterp == 0) {
2687 ninterp = 1;
2688 have_perspective = TRUE;
2689 }
2690
2691 if (!have_perspective && !have_linear)
2692 have_perspective = TRUE;
2693
2694 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2695 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2696 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2697 spi_input_z = 0;
2698 if (pos_index != -1) {
2699 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2700 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2701 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2702 spi_input_z |= 1;
2703 }
2704
2705 spi_ps_in_control_1 = 0;
2706 if (face_index != -1) {
2707 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2708 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2709 }
2710
2711 spi_baryc_cntl = 0;
2712 if (have_perspective)
2713 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2714 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2715 if (have_linear)
2716 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2717 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2718
2719 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2720 spi_ps_in_control_0);
2721 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2722 spi_ps_in_control_1);
2723 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2724 0);
2725 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2726 r600_pipe_state_add_reg(rstate,
2727 R_0286E0_SPI_BARYC_CNTL,
2728 spi_baryc_cntl);
2729
2730 r600_pipe_state_add_reg_bo(rstate,
2731 R_028840_SQ_PGM_START_PS,
2732 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2733 shader->bo, RADEON_USAGE_READ);
2734 r600_pipe_state_add_reg(rstate,
2735 R_028844_SQ_PGM_RESOURCES_PS,
2736 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2737 S_028844_PRIME_CACHE_ON_DRAW(1) |
2738 S_028844_STACK_SIZE(rshader->bc.nstack));
2739 r600_pipe_state_add_reg(rstate,
2740 R_02884C_SQ_PGM_EXPORTS_PS,
2741 exports_ps);
2742
2743 shader->db_shader_control = db_shader_control;
2744 shader->ps_depth_export = z_export | stencil_export;
2745
2746 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2747 if (rctx->rasterizer)
2748 shader->flatshade = rctx->rasterizer->flatshade;
2749 }
2750
2751 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2752 {
2753 struct r600_context *rctx = (struct r600_context *)ctx;
2754 struct r600_pipe_state *rstate = &shader->rstate;
2755 struct r600_shader *rshader = &shader->shader;
2756 unsigned spi_vs_out_id[10] = {};
2757 unsigned i, tmp, nparams = 0;
2758
2759 /* clear previous register */
2760 rstate->nregs = 0;
2761
2762 for (i = 0; i < rshader->noutput; i++) {
2763 if (rshader->output[i].spi_sid) {
2764 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2765 spi_vs_out_id[nparams / 4] |= tmp;
2766 nparams++;
2767 }
2768 }
2769
2770 for (i = 0; i < 10; i++) {
2771 r600_pipe_state_add_reg(rstate,
2772 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2773 spi_vs_out_id[i]);
2774 }
2775
2776 /* Certain attributes (position, psize, etc.) don't count as params.
2777 * VS is required to export at least one param and r600_shader_from_tgsi()
2778 * takes care of adding a dummy export.
2779 */
2780 if (nparams < 1)
2781 nparams = 1;
2782
2783 r600_pipe_state_add_reg(rstate,
2784 R_0286C4_SPI_VS_OUT_CONFIG,
2785 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2786 r600_pipe_state_add_reg(rstate,
2787 R_028860_SQ_PGM_RESOURCES_VS,
2788 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2789 S_028860_STACK_SIZE(rshader->bc.nstack));
2790 r600_pipe_state_add_reg_bo(rstate,
2791 R_02885C_SQ_PGM_START_VS,
2792 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2793 shader->bo, RADEON_USAGE_READ);
2794
2795 shader->pa_cl_vs_out_cntl =
2796 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2797 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2798 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2799 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2800 }
2801
2802 void evergreen_fetch_shader(struct pipe_context *ctx,
2803 struct r600_vertex_element *ve)
2804 {
2805 struct r600_context *rctx = (struct r600_context *)ctx;
2806 struct r600_pipe_state *rstate = &ve->rstate;
2807 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2808 rstate->nregs = 0;
2809 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2810 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2811 ve->fetch_shader, RADEON_USAGE_READ);
2812 }
2813
2814 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2815 {
2816 struct pipe_depth_stencil_alpha_state dsa = {{0}};
2817
2818 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2819 }
2820
2821 void evergreen_update_dual_export_state(struct r600_context * rctx)
2822 {
2823 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2824 !rctx->ps_shader->current->ps_depth_export;
2825
2826 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2827 V_02880C_EXPORT_DB_FULL;
2828
2829 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2830 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2831 S_02880C_DB_SOURCE_FORMAT(db_source_format);
2832
2833 if (db_shader_control != rctx->db_shader_control) {
2834 struct r600_pipe_state rstate;
2835
2836 rctx->db_shader_control = db_shader_control;
2837
2838 rstate.nregs = 0;
2839 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2840 r600_context_pipe_state_set(rctx, &rstate);
2841 }
2842 }