2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
51 static void evergreen_set_blend_color(struct pipe_context
*ctx
,
52 const struct pipe_blend_color
*state
)
54 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
55 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
60 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
61 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
);
62 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
);
63 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
);
64 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
);
66 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
67 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
68 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
71 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
72 const struct pipe_blend_state
*state
)
74 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
75 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
76 struct r600_pipe_state
*rstate
;
77 u32 color_control
, target_mask
;
78 /* FIXME there is more then 8 framebuffer */
79 unsigned blend_cntl
[8];
80 enum radeon_family family
;
86 family
= r600_get_family(rctx
->radeon
);
87 rstate
= &blend
->rstate
;
89 rstate
->id
= R600_PIPE_STATE_BLEND
;
92 color_control
= S_028808_MODE(1);
93 if (state
->logicop_enable
) {
94 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
96 color_control
|= (0xcc << 16);
98 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
99 if (state
->independent_blend_enable
) {
100 for (int i
= 0; i
< 8; i
++) {
101 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
104 for (int i
= 0; i
< 8; i
++) {
105 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
108 blend
->cb_target_mask
= target_mask
;
110 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
111 color_control
, 0xFFFFFFFD, NULL
);
113 if (family
!= CHIP_CAYMAN
)
114 r600_pipe_state_add_reg(rstate
, R_028C3C_PA_SC_AA_MASK
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
116 r600_pipe_state_add_reg(rstate
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
117 r600_pipe_state_add_reg(rstate
, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
120 for (int i
= 0; i
< 8; i
++) {
121 /* state->rt entries > 0 only written if independent blending */
122 const int j
= state
->independent_blend_enable
? i
: 0;
124 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
125 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
126 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
127 unsigned eqA
= state
->rt
[j
].alpha_func
;
128 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
129 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
132 if (!state
->rt
[j
].blend_enable
)
135 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
136 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
137 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
138 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
140 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
141 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
142 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
143 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
144 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
147 for (int i
= 0; i
< 8; i
++) {
148 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
], 0xFFFFFFFF, NULL
);
154 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
155 const struct pipe_depth_stencil_alpha_state
*state
)
157 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
158 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
159 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
160 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
161 struct r600_pipe_state
*rstate
;
167 rstate
= &dsa
->rstate
;
169 rstate
->id
= R600_PIPE_STATE_DSA
;
170 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
171 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
172 stencil_ref_mask
= 0;
173 stencil_ref_mask_bf
= 0;
174 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
175 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
176 S_028800_ZFUNC(state
->depth
.func
);
179 if (state
->stencil
[0].enabled
) {
180 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
181 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
182 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
183 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
184 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
187 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
188 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
189 if (state
->stencil
[1].enabled
) {
190 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
191 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
192 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
193 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
194 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
195 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
196 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
201 alpha_test_control
= 0;
203 if (state
->alpha
.enabled
) {
204 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
205 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
206 alpha_ref
= fui(state
->alpha
.ref_value
);
208 dsa
->alpha_ref
= alpha_ref
;
211 db_render_control
= 0;
212 db_render_override
= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
213 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
214 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
215 /* TODO db_render_override depends on query */
216 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
);
217 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
);
218 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
);
219 r600_pipe_state_add_reg(rstate
,
220 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
221 0xFFFFFFFF & C_028430_STENCILREF
, NULL
);
222 r600_pipe_state_add_reg(rstate
,
223 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
224 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
);
225 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
226 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
);
227 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
228 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
229 * evergreen_pipe_shader_ps().*/
230 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBC, NULL
);
231 r600_pipe_state_add_reg(rstate
, R_028000_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
);
232 r600_pipe_state_add_reg(rstate
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
);
233 r600_pipe_state_add_reg(rstate
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0, 0xFFFFFFFF, NULL
);
234 r600_pipe_state_add_reg(rstate
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0, 0xFFFFFFFF, NULL
);
235 r600_pipe_state_add_reg(rstate
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0, 0xFFFFFFFF, NULL
);
236 r600_pipe_state_add_reg(rstate
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
);
241 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
242 const struct pipe_rasterizer_state
*state
)
244 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
245 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
246 struct r600_pipe_state
*rstate
;
248 unsigned prov_vtx
= 1, polygon_dual_mode
;
250 enum radeon_family family
;
252 family
= r600_get_family(rctx
->radeon
);
258 rstate
= &rs
->rstate
;
259 rs
->flatshade
= state
->flatshade
;
260 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
262 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
265 rs
->offset_units
= state
->offset_units
;
266 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
268 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
269 if (state
->flatshade_first
)
271 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
272 if (state
->sprite_coord_enable
) {
273 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
274 S_0286D4_PNT_SPRITE_OVRD_X(2) |
275 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
276 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
277 S_0286D4_PNT_SPRITE_OVRD_W(1);
278 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
279 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
282 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
);
284 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
285 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
286 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
287 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
288 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
289 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
290 S_028814_FACE(!state
->front_ccw
) |
291 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
292 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
293 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
294 S_028814_POLY_MODE(polygon_dual_mode
) |
295 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
296 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
);
297 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
298 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
299 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
);
300 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
301 /* point size 12.4 fixed point */
302 tmp
= (unsigned)(state
->point_size
* 8.0);
303 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
304 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
);
306 tmp
= (unsigned)state
->line_width
* 8;
307 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
309 if (family
== CHIP_CAYMAN
) {
310 r600_pipe_state_add_reg(rstate
, CM_R_028BDC_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
311 r600_pipe_state_add_reg(rstate
, CM_R_028BE4_PA_SU_VTX_CNTL
,
312 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
314 r600_pipe_state_add_reg(rstate
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
315 r600_pipe_state_add_reg(rstate
, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
316 r600_pipe_state_add_reg(rstate
, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
317 r600_pipe_state_add_reg(rstate
, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
321 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
323 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
324 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
325 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
326 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
328 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
329 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
332 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 0x0, 0xFFFFFFFF, NULL
);
333 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
);
337 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
338 const struct pipe_sampler_state
*state
)
340 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
342 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
344 if (rstate
== NULL
) {
348 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
349 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
350 r600_pipe_state_add_reg_noblock(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
351 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
352 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
353 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
354 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
355 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
356 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
357 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
358 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
359 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
);
360 r600_pipe_state_add_reg_noblock(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
361 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
362 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)),
364 r600_pipe_state_add_reg_noblock(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
,
365 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
366 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
371 r600_pipe_state_add_reg_noblock(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
);
372 r600_pipe_state_add_reg_noblock(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
);
373 r600_pipe_state_add_reg_noblock(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
);
374 r600_pipe_state_add_reg_noblock(rstate
, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
);
379 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
380 struct pipe_resource
*texture
,
381 const struct pipe_sampler_view
*state
)
383 struct r600_pipe_sampler_view
*resource
= CALLOC_STRUCT(r600_pipe_sampler_view
);
384 struct r600_pipe_resource_state
*rstate
;
385 const struct util_format_description
*desc
;
386 struct r600_resource_texture
*tmp
;
387 struct r600_resource
*rbuffer
;
388 unsigned format
, endian
;
389 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
390 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
391 struct r600_bo
*bo
[2];
393 if (resource
== NULL
)
395 rstate
= &resource
->state
;
397 /* initialize base object */
398 resource
->base
= *state
;
399 resource
->base
.texture
= NULL
;
400 pipe_reference(NULL
, &texture
->reference
);
401 resource
->base
.texture
= texture
;
402 resource
->base
.reference
.count
= 1;
403 resource
->base
.context
= ctx
;
405 swizzle
[0] = state
->swizzle_r
;
406 swizzle
[1] = state
->swizzle_g
;
407 swizzle
[2] = state
->swizzle_b
;
408 swizzle
[3] = state
->swizzle_a
;
409 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
411 &word4
, &yuv_format
);
415 desc
= util_format_description(state
->format
);
417 R600_ERR("unknow format %d\n", state
->format
);
419 tmp
= (struct r600_resource_texture
*)texture
;
420 if (tmp
->depth
&& !tmp
->is_flushing_texture
) {
421 r600_texture_depth_flush(ctx
, texture
, TRUE
);
422 tmp
= tmp
->flushed_depth_texture
;
425 endian
= r600_colorformat_endian_swap(format
);
427 if (tmp
->force_int_type
) {
428 word4
&= C_030010_NUM_FORMAT_ALL
;
429 word4
|= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT
);
432 rbuffer
= &tmp
->resource
;
436 pitch
= align(tmp
->pitch_in_blocks
[0] * util_format_get_blockwidth(state
->format
), 8);
437 array_mode
= tmp
->array_mode
[0];
438 tile_type
= tmp
->tile_type
;
440 rstate
->bo
[0] = bo
[0];
441 rstate
->bo
[1] = bo
[1];
442 rstate
->val
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
)) |
443 S_030000_PITCH((pitch
/ 8) - 1) |
444 S_030000_NON_DISP_TILING_ORDER(tile_type
) |
445 S_030000_TEX_WIDTH(texture
->width0
- 1));
446 rstate
->val
[1] = (S_030004_TEX_HEIGHT(texture
->height0
- 1) |
447 S_030004_TEX_DEPTH(texture
->depth0
- 1) |
448 S_030004_ARRAY_MODE(array_mode
));
449 rstate
->val
[2] = (tmp
->offset
[0] + r600_bo_offset(bo
[0])) >> 8;
450 rstate
->val
[3] = (tmp
->offset
[1] + r600_bo_offset(bo
[1])) >> 8;
451 rstate
->val
[4] = (word4
|
452 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
453 S_030010_ENDIAN_SWAP(endian
) |
454 S_030010_BASE_LEVEL(state
->u
.tex
.first_level
));
455 rstate
->val
[5] = (S_030014_LAST_LEVEL(state
->u
.tex
.last_level
) |
456 S_030014_BASE_ARRAY(0) |
457 S_030014_LAST_ARRAY(0));
458 rstate
->val
[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
459 rstate
->val
[7] = (S_03001C_DATA_FORMAT(format
) |
460 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
));
462 return &resource
->base
;
465 static void evergreen_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
466 struct pipe_sampler_view
**views
)
468 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
469 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
471 for (int i
= 0; i
< count
; i
++) {
473 evergreen_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
,
474 i
+ R600_MAX_CONST_BUFFERS
);
479 static void evergreen_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
480 struct pipe_sampler_view
**views
)
482 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
483 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
486 for (i
= 0; i
< count
; i
++) {
487 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
489 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
,
490 i
+ R600_MAX_CONST_BUFFERS
);
492 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
493 i
+ R600_MAX_CONST_BUFFERS
);
495 pipe_sampler_view_reference(
496 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
500 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
501 if (rctx
->ps_samplers
.views
[i
]) {
502 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
503 i
+ R600_MAX_CONST_BUFFERS
);
504 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
507 rctx
->ps_samplers
.n_views
= count
;
510 static void evergreen_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
512 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
513 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
516 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
517 rctx
->ps_samplers
.n_samplers
= count
;
519 for (int i
= 0; i
< count
; i
++) {
520 evergreen_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
524 static void evergreen_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
526 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
527 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
529 for (int i
= 0; i
< count
; i
++) {
530 evergreen_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
534 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
535 const struct pipe_clip_state
*state
)
537 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
538 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
544 rstate
->id
= R600_PIPE_STATE_CLIP
;
545 for (int i
= 0; i
< state
->nr
; i
++) {
546 r600_pipe_state_add_reg(rstate
,
547 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
548 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
);
549 r600_pipe_state_add_reg(rstate
,
550 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
551 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
);
552 r600_pipe_state_add_reg(rstate
,
553 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
554 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
);
555 r600_pipe_state_add_reg(rstate
,
556 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
557 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
);
559 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
560 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
561 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
562 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
);
564 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
565 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
566 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
569 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
570 const struct pipe_poly_stipple
*state
)
574 static void evergreen_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
578 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
579 const struct pipe_scissor_state
*state
)
581 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
582 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
588 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
589 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
590 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
591 r600_pipe_state_add_reg(rstate
,
592 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
594 r600_pipe_state_add_reg(rstate
,
595 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
597 r600_pipe_state_add_reg(rstate
,
598 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
600 r600_pipe_state_add_reg(rstate
,
601 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
603 r600_pipe_state_add_reg(rstate
,
604 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
606 r600_pipe_state_add_reg(rstate
,
607 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
609 r600_pipe_state_add_reg(rstate
,
610 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
612 r600_pipe_state_add_reg(rstate
,
613 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
616 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
617 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
618 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
621 static void evergreen_set_stencil_ref(struct pipe_context
*ctx
,
622 const struct pipe_stencil_ref
*state
)
624 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
625 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
631 rctx
->stencil_ref
= *state
;
632 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
633 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
634 r600_pipe_state_add_reg(rstate
,
635 R_028430_DB_STENCILREFMASK
, tmp
,
636 ~C_028430_STENCILREF
, NULL
);
637 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
638 r600_pipe_state_add_reg(rstate
,
639 R_028434_DB_STENCILREFMASK_BF
, tmp
,
640 ~C_028434_STENCILREF_BF
, NULL
);
642 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
643 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
644 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
647 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
648 const struct pipe_viewport_state
*state
)
650 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
651 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
656 rctx
->viewport
= *state
;
657 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
658 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
);
659 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
);
660 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
);
661 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
);
662 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
);
663 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
);
664 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
);
665 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
);
666 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
);
668 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
669 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
670 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
673 static void evergreen_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
674 const struct pipe_framebuffer_state
*state
, int cb
)
676 struct r600_resource_texture
*rtex
;
677 struct r600_resource
*rbuffer
;
678 struct r600_surface
*surf
;
679 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
680 unsigned pitch
, slice
;
682 unsigned format
, swap
, ntype
, endian
;
685 const struct util_format_description
*desc
;
686 struct r600_bo
*bo
[3];
689 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
690 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
692 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
693 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
694 rtex
= rtex
->flushed_depth_texture
;
697 rbuffer
= &rtex
->resource
;
702 /* XXX quite sure for dx10+ hw don't need any offset hacks */
703 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
,
704 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
705 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
706 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
707 desc
= util_format_description(surf
->base
.format
);
708 for (i
= 0; i
< 4; i
++) {
709 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
713 ntype
= V_028C70_NUMBER_UNORM
;
714 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
715 ntype
= V_028C70_NUMBER_SRGB
;
716 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
)
717 ntype
= V_028C70_NUMBER_SNORM
;
719 format
= r600_translate_colorformat(surf
->base
.format
);
720 swap
= r600_translate_colorswap(surf
->base
.format
);
721 if (rbuffer
->b
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
722 endian
= ENDIAN_NONE
;
724 endian
= r600_colorformat_endian_swap(format
);
727 /* disable when gallium grows int textures */
728 if ((format
== FMT_32_32_32_32
|| format
== FMT_16_16_16_16
) && rtex
->force_int_type
)
729 ntype
= V_028C70_NUMBER_UINT
;
731 color_info
= S_028C70_FORMAT(format
) |
732 S_028C70_COMP_SWAP(swap
) |
733 S_028C70_ARRAY_MODE(rtex
->array_mode
[level
]) |
734 S_028C70_BLEND_CLAMP(1) |
735 S_028C70_NUMBER_TYPE(ntype
) |
736 S_028C70_ENDIAN(endian
);
739 /* EXPORT_NORM is an optimzation that can be enabled for better
740 * performance in certain cases.
741 * EXPORT_NORM can be enabled if:
742 * - 11-bit or smaller UNORM/SNORM/SRGB
743 * - 16-bit or smaller FLOAT
745 /* FIXME: This should probably be the same for all CBs if we want
746 * useful alpha tests. */
747 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
748 ((desc
->channel
[i
].size
< 12 &&
749 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
750 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
751 (desc
->channel
[i
].size
< 17 &&
752 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
753 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
754 rctx
->export_16bpc
= true;
756 rctx
->export_16bpc
= false;
758 rctx
->alpha_ref_dirty
= true;
760 if (rtex
->array_mode
[level
] > V_028C70_ARRAY_LINEAR_ALIGNED
) {
761 tile_type
= rtex
->tile_type
;
762 } else /* workaround for linear buffers */
765 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
766 r600_pipe_state_add_reg(rstate
,
767 R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C,
768 (offset
+ r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
769 r600_pipe_state_add_reg(rstate
,
770 R_028C78_CB_COLOR0_DIM
+ cb
* 0x3C,
771 0x0, 0xFFFFFFFF, NULL
);
772 r600_pipe_state_add_reg(rstate
,
773 R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C,
774 color_info
, 0xFFFFFFFF, bo
[0]);
775 r600_pipe_state_add_reg(rstate
,
776 R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C,
777 S_028C64_PITCH_TILE_MAX(pitch
),
779 r600_pipe_state_add_reg(rstate
,
780 R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C,
781 S_028C68_SLICE_TILE_MAX(slice
),
783 r600_pipe_state_add_reg(rstate
,
784 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
785 0x00000000, 0xFFFFFFFF, NULL
);
786 r600_pipe_state_add_reg(rstate
,
787 R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
788 S_028C74_NON_DISP_TILING_ORDER(tile_type
),
792 static void evergreen_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
793 const struct pipe_framebuffer_state
*state
)
795 struct r600_resource_texture
*rtex
;
796 struct r600_resource
*rbuffer
;
797 struct r600_surface
*surf
;
799 unsigned pitch
, slice
, format
, stencil_format
;
802 if (state
->zsbuf
== NULL
)
805 level
= state
->zsbuf
->u
.tex
.level
;
807 surf
= (struct r600_surface
*)state
->zsbuf
;
808 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
810 rbuffer
= &rtex
->resource
;
812 /* XXX quite sure for dx10+ hw don't need any offset hacks */
813 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->zsbuf
->texture
,
814 level
, state
->zsbuf
->u
.tex
.first_layer
);
815 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
816 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
817 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
818 stencil_format
= r600_translate_stencilformat(state
->zsbuf
->texture
->format
);
820 r600_pipe_state_add_reg(rstate
, R_028048_DB_Z_READ_BASE
,
821 (offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
822 r600_pipe_state_add_reg(rstate
, R_028050_DB_Z_WRITE_BASE
,
823 (offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
825 if (stencil_format
) {
826 uint32_t stencil_offset
;
828 stencil_offset
= ((surf
->aligned_height
* rtex
->pitch_in_bytes
[level
]) + 255) & ~255;
829 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
830 (offset
+ stencil_offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
831 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
832 (offset
+ stencil_offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
835 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
);
836 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
837 S_028044_FORMAT(stencil_format
), 0xFFFFFFFF, rbuffer
->bo
);
839 r600_pipe_state_add_reg(rstate
, R_028040_DB_Z_INFO
,
840 S_028040_ARRAY_MODE(rtex
->array_mode
[level
]) | S_028040_FORMAT(format
),
841 0xFFFFFFFF, rbuffer
->bo
);
842 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
,
843 S_028058_PITCH_TILE_MAX(pitch
),
845 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
,
846 S_02805C_SLICE_TILE_MAX(slice
),
850 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
851 const struct pipe_framebuffer_state
*state
)
853 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
854 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
855 u32 shader_mask
, tl
, br
, target_mask
;
856 enum radeon_family family
;
857 int tl_x
, tl_y
, br_x
, br_y
;
862 family
= r600_get_family(rctx
->radeon
);
864 evergreen_context_flush_dest_caches(&rctx
->ctx
);
865 rctx
->ctx
.num_dest_buffers
= state
->nr_cbufs
;
867 /* unreference old buffer and reference new one */
868 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
870 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
873 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
874 evergreen_cb(rctx
, rstate
, state
, i
);
877 evergreen_db(rctx
, rstate
, state
);
878 rctx
->ctx
.num_dest_buffers
++;
881 target_mask
= 0x00000000;
882 target_mask
= 0xFFFFFFFF;
884 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
885 target_mask
^= 0xf << (i
* 4);
886 shader_mask
|= 0xf << (i
* 4);
891 br_y
= state
->height
;
892 /* EG hw workaround */
897 /* cayman hw workaround */
898 if (family
== CHIP_CAYMAN
) {
899 if (br_x
== 1 && br_y
== 1)
902 tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
903 br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
905 r600_pipe_state_add_reg(rstate
,
906 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
908 r600_pipe_state_add_reg(rstate
,
909 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
911 r600_pipe_state_add_reg(rstate
,
912 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
914 r600_pipe_state_add_reg(rstate
,
915 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
917 r600_pipe_state_add_reg(rstate
,
918 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
920 r600_pipe_state_add_reg(rstate
,
921 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
923 r600_pipe_state_add_reg(rstate
,
924 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
926 r600_pipe_state_add_reg(rstate
,
927 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
929 r600_pipe_state_add_reg(rstate
,
930 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
932 r600_pipe_state_add_reg(rstate
,
933 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
936 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
937 0x00000000, target_mask
, NULL
);
938 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
939 shader_mask
, 0xFFFFFFFF, NULL
);
942 if (family
== CHIP_CAYMAN
) {
943 r600_pipe_state_add_reg(rstate
, CM_R_028BE0_PA_SC_AA_CONFIG
,
944 0x00000000, 0xFFFFFFFF, NULL
);
946 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
947 0x00000000, 0xFFFFFFFF, NULL
);
948 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
949 0x00000000, 0xFFFFFFFF, NULL
);
952 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
953 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
954 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
957 evergreen_polygon_offset_update(rctx
);
961 static void evergreen_texture_barrier(struct pipe_context
*ctx
)
963 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
965 r600_context_flush_all(&rctx
->ctx
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
966 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
967 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
968 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
969 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
970 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
971 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
974 void evergreen_init_state_functions(struct r600_pipe_context
*rctx
)
976 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
977 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
978 rctx
->context
.create_fs_state
= r600_create_shader_state
;
979 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
980 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
981 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
982 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
983 rctx
->context
.create_vs_state
= r600_create_shader_state
;
984 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
985 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
986 rctx
->context
.bind_fragment_sampler_states
= evergreen_bind_ps_sampler
;
987 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
988 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
989 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
990 rctx
->context
.bind_vertex_sampler_states
= evergreen_bind_vs_sampler
;
991 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
992 rctx
->context
.delete_blend_state
= r600_delete_state
;
993 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
994 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
995 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
996 rctx
->context
.delete_sampler_state
= r600_delete_state
;
997 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
998 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
999 rctx
->context
.set_blend_color
= evergreen_set_blend_color
;
1000 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
1001 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1002 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_view
;
1003 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
1004 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
1005 rctx
->context
.set_sample_mask
= evergreen_set_sample_mask
;
1006 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
1007 rctx
->context
.set_stencil_ref
= evergreen_set_stencil_ref
;
1008 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1009 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1010 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_view
;
1011 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
1012 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1013 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
1014 rctx
->context
.texture_barrier
= evergreen_texture_barrier
;
1017 static void cayman_init_config(struct r600_pipe_context
*rctx
)
1019 struct r600_pipe_state
*rstate
= &rctx
->config
;
1023 tmp
|= S_008C00_EXPORT_SRC_C(1);
1024 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1026 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, (4 << 28), 0xFFFFFFFF, NULL
);
1027 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8), 0xFFFFFFFF, NULL
);
1029 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
);
1030 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
);
1032 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1033 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1034 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1035 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1036 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
);
1037 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
);
1038 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1039 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1040 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1041 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1042 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1043 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1044 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
);
1045 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1046 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1047 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
);
1048 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
);
1049 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
);
1051 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
);
1052 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
);
1053 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
);
1054 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
);
1055 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
);
1056 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
);
1057 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
);
1058 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
);
1059 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
);
1060 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
);
1061 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
);
1062 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
);
1063 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
);
1064 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
);
1065 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
);
1066 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
);
1067 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
);
1068 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
);
1069 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
);
1070 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
);
1071 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
);
1072 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
);
1073 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
);
1074 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
);
1075 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
);
1076 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
);
1077 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
);
1078 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
);
1079 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
);
1080 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
);
1081 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
);
1082 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
);
1084 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1086 r600_pipe_state_add_reg(rstate
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210, 0xffffffff, 0);
1087 r600_pipe_state_add_reg(rstate
, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98, 0xffffffff, 0);
1089 r600_pipe_state_add_reg(rstate
, CM_R_0288E8_SQ_LDS_ALLOC
, 0, 0xffffffff, NULL
);
1090 r600_pipe_state_add_reg(rstate
, R_0288EC_SQ_LDS_ALLOC_PS
, 0, 0xffffffff, NULL
);
1092 r600_pipe_state_add_reg(rstate
, CM_R_028804_DB_EQAA
, 0x110000, 0xffffffff, NULL
);
1093 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1096 void evergreen_init_config(struct r600_pipe_context
*rctx
)
1098 struct r600_pipe_state
*rstate
= &rctx
->config
;
1103 int hs_prio
, cs_prio
, ls_prio
;
1117 int num_ps_stack_entries
;
1118 int num_vs_stack_entries
;
1119 int num_gs_stack_entries
;
1120 int num_es_stack_entries
;
1121 int num_hs_stack_entries
;
1122 int num_ls_stack_entries
;
1123 enum radeon_family family
;
1126 family
= r600_get_family(rctx
->radeon
);
1128 if (family
== CHIP_CAYMAN
) {
1129 cayman_init_config(rctx
);
1151 num_ps_threads
= 96;
1152 num_vs_threads
= 16;
1153 num_gs_threads
= 16;
1154 num_es_threads
= 16;
1155 num_hs_threads
= 16;
1156 num_ls_threads
= 16;
1157 num_ps_stack_entries
= 42;
1158 num_vs_stack_entries
= 42;
1159 num_gs_stack_entries
= 42;
1160 num_es_stack_entries
= 42;
1161 num_hs_stack_entries
= 42;
1162 num_ls_stack_entries
= 42;
1172 num_ps_threads
= 128;
1173 num_vs_threads
= 20;
1174 num_gs_threads
= 20;
1175 num_es_threads
= 20;
1176 num_hs_threads
= 20;
1177 num_ls_threads
= 20;
1178 num_ps_stack_entries
= 42;
1179 num_vs_stack_entries
= 42;
1180 num_gs_stack_entries
= 42;
1181 num_es_stack_entries
= 42;
1182 num_hs_stack_entries
= 42;
1183 num_ls_stack_entries
= 42;
1193 num_ps_threads
= 128;
1194 num_vs_threads
= 20;
1195 num_gs_threads
= 20;
1196 num_es_threads
= 20;
1197 num_hs_threads
= 20;
1198 num_ls_threads
= 20;
1199 num_ps_stack_entries
= 85;
1200 num_vs_stack_entries
= 85;
1201 num_gs_stack_entries
= 85;
1202 num_es_stack_entries
= 85;
1203 num_hs_stack_entries
= 85;
1204 num_ls_stack_entries
= 85;
1215 num_ps_threads
= 128;
1216 num_vs_threads
= 20;
1217 num_gs_threads
= 20;
1218 num_es_threads
= 20;
1219 num_hs_threads
= 20;
1220 num_ls_threads
= 20;
1221 num_ps_stack_entries
= 85;
1222 num_vs_stack_entries
= 85;
1223 num_gs_stack_entries
= 85;
1224 num_es_stack_entries
= 85;
1225 num_hs_stack_entries
= 85;
1226 num_ls_stack_entries
= 85;
1236 num_ps_threads
= 96;
1237 num_vs_threads
= 16;
1238 num_gs_threads
= 16;
1239 num_es_threads
= 16;
1240 num_hs_threads
= 16;
1241 num_ls_threads
= 16;
1242 num_ps_stack_entries
= 42;
1243 num_vs_stack_entries
= 42;
1244 num_gs_stack_entries
= 42;
1245 num_es_stack_entries
= 42;
1246 num_hs_stack_entries
= 42;
1247 num_ls_stack_entries
= 42;
1257 num_ps_threads
= 96;
1258 num_vs_threads
= 25;
1259 num_gs_threads
= 25;
1260 num_es_threads
= 25;
1261 num_hs_threads
= 25;
1262 num_ls_threads
= 25;
1263 num_ps_stack_entries
= 42;
1264 num_vs_stack_entries
= 42;
1265 num_gs_stack_entries
= 42;
1266 num_es_stack_entries
= 42;
1267 num_hs_stack_entries
= 42;
1268 num_ls_stack_entries
= 42;
1278 num_ps_threads
= 96;
1279 num_vs_threads
= 25;
1280 num_gs_threads
= 25;
1281 num_es_threads
= 25;
1282 num_hs_threads
= 25;
1283 num_ls_threads
= 25;
1284 num_ps_stack_entries
= 85;
1285 num_vs_stack_entries
= 85;
1286 num_gs_stack_entries
= 85;
1287 num_es_stack_entries
= 85;
1288 num_hs_stack_entries
= 85;
1289 num_ls_stack_entries
= 85;
1299 num_ps_threads
= 128;
1300 num_vs_threads
= 20;
1301 num_gs_threads
= 20;
1302 num_es_threads
= 20;
1303 num_hs_threads
= 20;
1304 num_ls_threads
= 20;
1305 num_ps_stack_entries
= 85;
1306 num_vs_stack_entries
= 85;
1307 num_gs_stack_entries
= 85;
1308 num_es_stack_entries
= 85;
1309 num_hs_stack_entries
= 85;
1310 num_ls_stack_entries
= 85;
1320 num_ps_threads
= 128;
1321 num_vs_threads
= 20;
1322 num_gs_threads
= 20;
1323 num_es_threads
= 20;
1324 num_hs_threads
= 20;
1325 num_ls_threads
= 20;
1326 num_ps_stack_entries
= 42;
1327 num_vs_stack_entries
= 42;
1328 num_gs_stack_entries
= 42;
1329 num_es_stack_entries
= 42;
1330 num_hs_stack_entries
= 42;
1331 num_ls_stack_entries
= 42;
1341 num_ps_threads
= 128;
1342 num_vs_threads
= 10;
1343 num_gs_threads
= 10;
1344 num_es_threads
= 10;
1345 num_hs_threads
= 10;
1346 num_ls_threads
= 10;
1347 num_ps_stack_entries
= 42;
1348 num_vs_stack_entries
= 42;
1349 num_gs_stack_entries
= 42;
1350 num_es_stack_entries
= 42;
1351 num_hs_stack_entries
= 42;
1352 num_ls_stack_entries
= 42;
1365 tmp
|= S_008C00_VC_ENABLE(1);
1368 tmp
|= S_008C00_EXPORT_SRC_C(1);
1369 tmp
|= S_008C00_CS_PRIO(cs_prio
);
1370 tmp
|= S_008C00_LS_PRIO(ls_prio
);
1371 tmp
|= S_008C00_HS_PRIO(hs_prio
);
1372 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1373 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1374 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1375 tmp
|= S_008C00_ES_PRIO(es_prio
);
1376 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1378 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, (4 << 28), 0xFFFFFFFF, NULL
);
1379 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8), 0xFFFFFFFF, NULL
);
1382 tmp
|= S_008C18_NUM_PS_THREADS(num_ps_threads
);
1383 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
1384 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
1385 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
1386 r600_pipe_state_add_reg(rstate
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1389 tmp
|= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
1390 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
1391 r600_pipe_state_add_reg(rstate
, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1394 tmp
|= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
1395 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
1396 r600_pipe_state_add_reg(rstate
, R_008C20_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1399 tmp
|= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
1400 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
1401 r600_pipe_state_add_reg(rstate
, R_008C24_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1404 tmp
|= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
1405 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
1406 r600_pipe_state_add_reg(rstate
, R_008C28_SQ_STACK_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
);
1408 r600_pipe_state_add_reg(rstate
, R_009100_SPI_CONFIG_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1409 r600_pipe_state_add_reg(rstate
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL
);
1412 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, 0x0, 0xFFFFFFFF, NULL
);
1414 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x0, 0xFFFFFFFF, NULL
);
1416 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
);
1417 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
);
1419 r600_pipe_state_add_reg(rstate
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1420 r600_pipe_state_add_reg(rstate
, R_028904_SQ_GSVS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1421 r600_pipe_state_add_reg(rstate
, R_028908_SQ_ESTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1422 r600_pipe_state_add_reg(rstate
, R_02890C_SQ_GSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1423 r600_pipe_state_add_reg(rstate
, R_028910_SQ_VSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1424 r600_pipe_state_add_reg(rstate
, R_028914_SQ_PSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1426 r600_pipe_state_add_reg(rstate
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1427 r600_pipe_state_add_reg(rstate
, R_028920_SQ_GS_VERT_ITEMSIZE_1
, 0x0, 0xFFFFFFFF, NULL
);
1428 r600_pipe_state_add_reg(rstate
, R_028924_SQ_GS_VERT_ITEMSIZE_2
, 0x0, 0xFFFFFFFF, NULL
);
1429 r600_pipe_state_add_reg(rstate
, R_028928_SQ_GS_VERT_ITEMSIZE_3
, 0x0, 0xFFFFFFFF, NULL
);
1431 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1432 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1433 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1434 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1435 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
);
1436 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
);
1437 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1438 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1439 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1440 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1441 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1442 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1443 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
);
1444 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1445 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1446 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
);
1447 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
);
1448 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
);
1450 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
);
1451 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
);
1452 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
);
1453 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
);
1454 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
);
1455 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
);
1456 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
);
1457 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
);
1458 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
);
1459 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
);
1460 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
);
1461 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
);
1462 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
);
1463 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
);
1464 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
);
1465 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
);
1466 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
);
1467 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
);
1468 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
);
1469 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
);
1470 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
);
1471 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
);
1472 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
);
1473 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
);
1474 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
);
1475 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
);
1476 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
);
1477 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
);
1478 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
);
1479 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
);
1480 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
);
1481 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
);
1483 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1485 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1488 void evergreen_polygon_offset_update(struct r600_pipe_context
*rctx
)
1490 struct r600_pipe_state state
;
1492 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
1494 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
1495 float offset_units
= rctx
->rasterizer
->offset_units
;
1496 unsigned offset_db_fmt_cntl
= 0, depth
;
1498 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
1499 case PIPE_FORMAT_Z24X8_UNORM
:
1500 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
1502 offset_units
*= 2.0f
;
1504 case PIPE_FORMAT_Z32_FLOAT
:
1506 offset_units
*= 1.0f
;
1507 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1509 case PIPE_FORMAT_Z16_UNORM
:
1511 offset_units
*= 4.0f
;
1516 /* FIXME some of those reg can be computed with cso */
1517 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
1518 r600_pipe_state_add_reg(&state
,
1519 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1520 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
1521 r600_pipe_state_add_reg(&state
,
1522 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1523 fui(offset_units
), 0xFFFFFFFF, NULL
);
1524 r600_pipe_state_add_reg(&state
,
1525 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1526 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
1527 r600_pipe_state_add_reg(&state
,
1528 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1529 fui(offset_units
), 0xFFFFFFFF, NULL
);
1530 r600_pipe_state_add_reg(&state
,
1531 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1532 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
);
1533 r600_context_pipe_state_set(&rctx
->ctx
, &state
);
1537 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1539 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1540 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1541 struct r600_shader
*rshader
= &shader
->shader
;
1542 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
1543 int pos_index
= -1, face_index
= -1;
1545 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
1546 unsigned spi_baryc_cntl
;
1550 db_shader_control
= 0;
1551 for (i
= 0; i
< rshader
->ninput
; i
++) {
1552 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1553 POSITION goes via GPRs from the SC so isn't counted */
1554 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
1556 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
1559 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
||
1560 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
1562 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
1564 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
1565 have_perspective
= TRUE
;
1566 if (rshader
->input
[i
].centroid
)
1567 have_centroid
= TRUE
;
1570 for (i
= 0; i
< rshader
->noutput
; i
++) {
1571 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
1572 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
1573 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1574 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(1);
1576 if (rshader
->uses_kill
)
1577 db_shader_control
|= S_02880C_KILL_ENABLE(1);
1581 for (i
= 0; i
< rshader
->noutput
; i
++) {
1582 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
1583 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1585 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1589 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
1591 /* always at least export 1 component per pixel */
1597 have_perspective
= TRUE
;
1600 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
1601 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
1602 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
1604 if (pos_index
!= -1) {
1605 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
1606 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
1607 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
1611 spi_ps_in_control_1
= 0;
1612 if (face_index
!= -1) {
1613 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
1614 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
1618 if (have_perspective
)
1619 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
1620 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
1622 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
1623 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
1625 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
1626 spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
1627 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
1628 spi_ps_in_control_1
, 0xFFFFFFFF, NULL
);
1629 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
1630 0, 0xFFFFFFFF, NULL
);
1631 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
1632 r600_pipe_state_add_reg(rstate
,
1633 R_0286E0_SPI_BARYC_CNTL
,
1637 r600_pipe_state_add_reg(rstate
,
1638 R_028840_SQ_PGM_START_PS
,
1639 (r600_bo_offset(shader
->bo
)) >> 8, 0xFFFFFFFF, shader
->bo
);
1640 r600_pipe_state_add_reg(rstate
,
1641 R_028844_SQ_PGM_RESOURCES_PS
,
1642 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
1643 S_028844_PRIME_CACHE_ON_DRAW(1) |
1644 S_028844_STACK_SIZE(rshader
->bc
.nstack
),
1646 r600_pipe_state_add_reg(rstate
,
1647 R_028848_SQ_PGM_RESOURCES_2_PS
,
1648 0x0, 0xFFFFFFFF, NULL
);
1649 r600_pipe_state_add_reg(rstate
,
1650 R_02884C_SQ_PGM_EXPORTS_PS
,
1651 exports_ps
, 0xFFFFFFFF, NULL
);
1652 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1653 /* only set some bits here, the other bits are set in the dsa state */
1654 r600_pipe_state_add_reg(rstate
,
1655 R_02880C_DB_SHADER_CONTROL
,
1657 S_02880C_Z_EXPORT_ENABLE(1) |
1658 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1659 S_02880C_KILL_ENABLE(1),
1661 r600_pipe_state_add_reg(rstate
,
1662 R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF,
1666 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1668 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1669 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1670 struct r600_shader
*rshader
= &shader
->shader
;
1671 unsigned spi_vs_out_id
[10];
1674 /* clear previous register */
1677 /* so far never got proper semantic id from tgsi */
1678 for (i
= 0; i
< 10; i
++) {
1679 spi_vs_out_id
[i
] = 0;
1681 for (i
= 0; i
< 32; i
++) {
1682 tmp
= i
<< ((i
& 3) * 8);
1683 spi_vs_out_id
[i
/ 4] |= tmp
;
1685 for (i
= 0; i
< 10; i
++) {
1686 r600_pipe_state_add_reg(rstate
,
1687 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
1688 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
1691 r600_pipe_state_add_reg(rstate
,
1692 R_0286C4_SPI_VS_OUT_CONFIG
,
1693 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
1695 r600_pipe_state_add_reg(rstate
,
1696 R_028860_SQ_PGM_RESOURCES_VS
,
1697 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
1698 S_028860_STACK_SIZE(rshader
->bc
.nstack
),
1700 r600_pipe_state_add_reg(rstate
,
1701 R_028864_SQ_PGM_RESOURCES_2_VS
,
1702 0x0, 0xFFFFFFFF, NULL
);
1703 r600_pipe_state_add_reg(rstate
,
1704 R_02885C_SQ_PGM_START_VS
,
1705 (r600_bo_offset(shader
->bo
)) >> 8, 0xFFFFFFFF, shader
->bo
);
1707 r600_pipe_state_add_reg(rstate
,
1708 R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
1712 void evergreen_fetch_shader(struct pipe_context
*ctx
,
1713 struct r600_vertex_element
*ve
)
1715 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1716 struct r600_pipe_state
*rstate
= &ve
->rstate
;
1717 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
1719 r600_pipe_state_add_reg(rstate
, R_0288A8_SQ_PGM_RESOURCES_FS
,
1720 0x00000000, 0xFFFFFFFF, NULL
);
1721 r600_pipe_state_add_reg(rstate
, R_0288A4_SQ_PGM_START_FS
,
1722 (r600_bo_offset(ve
->fetch_shader
)) >> 8,
1723 0xFFFFFFFF, ve
->fetch_shader
);
1726 void *evergreen_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
1728 struct pipe_depth_stencil_alpha_state dsa
;
1729 struct r600_pipe_state
*rstate
;
1731 memset(&dsa
, 0, sizeof(dsa
));
1733 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
1734 r600_pipe_state_add_reg(rstate
,
1735 R_02880C_DB_SHADER_CONTROL
,
1737 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
);
1738 r600_pipe_state_add_reg(rstate
,
1739 R_028000_DB_RENDER_CONTROL
,
1740 S_028000_DEPTH_COPY_ENABLE(1) |
1741 S_028000_STENCIL_COPY_ENABLE(1) |
1742 S_028000_COPY_CENTROID(1),
1743 S_028000_DEPTH_COPY_ENABLE(1) |
1744 S_028000_STENCIL_COPY_ENABLE(1) |
1745 S_028000_COPY_CENTROID(1), NULL
);
1749 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
1750 struct r600_pipe_resource_state
*rstate
)
1752 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
1755 rstate
->bo
[0] = NULL
;
1757 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
1758 rstate
->val
[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1759 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1760 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1761 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
);
1765 rstate
->val
[7] = 0xc0000000;
1769 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
1770 struct r600_resource
*rbuffer
,
1771 unsigned offset
, unsigned stride
)
1773 rstate
->bo
[0] = rbuffer
->bo
;
1774 rstate
->val
[0] = offset
;
1775 rstate
->val
[1] = rbuffer
->bo_size
- offset
- 1;
1776 rstate
->val
[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1777 S_030008_STRIDE(stride
);