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r600g: move DB_SHADER_CONTROL into db_misc_state
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169 V_030000_SQ_TEX_DIM_2D;
170 case PIPE_TEXTURE_2D_ARRAY:
171 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172 V_030000_SQ_TEX_DIM_2D_ARRAY;
173 case PIPE_TEXTURE_3D:
174 return V_030000_SQ_TEX_DIM_3D;
175 case PIPE_TEXTURE_CUBE:
176 return V_030000_SQ_TEX_DIM_CUBEMAP;
177 }
178 }
179
180 static uint32_t r600_translate_dbformat(enum pipe_format format)
181 {
182 switch (format) {
183 case PIPE_FORMAT_Z16_UNORM:
184 return V_028040_Z_16;
185 case PIPE_FORMAT_Z24X8_UNORM:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187 return V_028040_Z_24;
188 case PIPE_FORMAT_Z32_FLOAT:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190 return V_028040_Z_32_FLOAT;
191 default:
192 return ~0U;
193 }
194 }
195
196 static uint32_t r600_translate_colorswap(enum pipe_format format)
197 {
198 switch (format) {
199 /* 8-bit buffers. */
200 case PIPE_FORMAT_L4A4_UNORM:
201 case PIPE_FORMAT_A4R4_UNORM:
202 return V_028C70_SWAP_ALT;
203
204 case PIPE_FORMAT_A8_UNORM:
205 case PIPE_FORMAT_A8_SNORM:
206 case PIPE_FORMAT_A8_UINT:
207 case PIPE_FORMAT_A8_SINT:
208 case PIPE_FORMAT_A16_UNORM:
209 case PIPE_FORMAT_A16_SNORM:
210 case PIPE_FORMAT_A16_UINT:
211 case PIPE_FORMAT_A16_SINT:
212 case PIPE_FORMAT_A16_FLOAT:
213 case PIPE_FORMAT_A32_UINT:
214 case PIPE_FORMAT_A32_SINT:
215 case PIPE_FORMAT_A32_FLOAT:
216 case PIPE_FORMAT_R4A4_UNORM:
217 return V_028C70_SWAP_ALT_REV;
218 case PIPE_FORMAT_I8_UNORM:
219 case PIPE_FORMAT_I8_SNORM:
220 case PIPE_FORMAT_I8_UINT:
221 case PIPE_FORMAT_I8_SINT:
222 case PIPE_FORMAT_I16_UNORM:
223 case PIPE_FORMAT_I16_SNORM:
224 case PIPE_FORMAT_I16_UINT:
225 case PIPE_FORMAT_I16_SINT:
226 case PIPE_FORMAT_I16_FLOAT:
227 case PIPE_FORMAT_I32_UINT:
228 case PIPE_FORMAT_I32_SINT:
229 case PIPE_FORMAT_I32_FLOAT:
230 case PIPE_FORMAT_L8_UNORM:
231 case PIPE_FORMAT_L8_SNORM:
232 case PIPE_FORMAT_L8_UINT:
233 case PIPE_FORMAT_L8_SINT:
234 case PIPE_FORMAT_L8_SRGB:
235 case PIPE_FORMAT_L16_UNORM:
236 case PIPE_FORMAT_L16_SNORM:
237 case PIPE_FORMAT_L16_UINT:
238 case PIPE_FORMAT_L16_SINT:
239 case PIPE_FORMAT_L16_FLOAT:
240 case PIPE_FORMAT_L32_UINT:
241 case PIPE_FORMAT_L32_SINT:
242 case PIPE_FORMAT_L32_FLOAT:
243 case PIPE_FORMAT_R8_UNORM:
244 case PIPE_FORMAT_R8_SNORM:
245 case PIPE_FORMAT_R8_UINT:
246 case PIPE_FORMAT_R8_SINT:
247 return V_028C70_SWAP_STD;
248
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM:
251 return V_028C70_SWAP_STD_REV;
252
253 case PIPE_FORMAT_B5G5R5A1_UNORM:
254 case PIPE_FORMAT_B5G5R5X1_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_B4G4R4A4_UNORM:
258 case PIPE_FORMAT_B4G4R4X4_UNORM:
259 return V_028C70_SWAP_ALT;
260
261 case PIPE_FORMAT_Z16_UNORM:
262 return V_028C70_SWAP_STD;
263
264 case PIPE_FORMAT_L8A8_UNORM:
265 case PIPE_FORMAT_L8A8_SNORM:
266 case PIPE_FORMAT_L8A8_UINT:
267 case PIPE_FORMAT_L8A8_SINT:
268 case PIPE_FORMAT_L8A8_SRGB:
269 case PIPE_FORMAT_L16A16_UNORM:
270 case PIPE_FORMAT_L16A16_SNORM:
271 case PIPE_FORMAT_L16A16_UINT:
272 case PIPE_FORMAT_L16A16_SINT:
273 case PIPE_FORMAT_L16A16_FLOAT:
274 case PIPE_FORMAT_L32A32_UINT:
275 case PIPE_FORMAT_L32A32_SINT:
276 case PIPE_FORMAT_L32A32_FLOAT:
277 return V_028C70_SWAP_ALT;
278 case PIPE_FORMAT_R8G8_UNORM:
279 case PIPE_FORMAT_R8G8_SNORM:
280 case PIPE_FORMAT_R8G8_UINT:
281 case PIPE_FORMAT_R8G8_SINT:
282 return V_028C70_SWAP_STD;
283
284 case PIPE_FORMAT_R16_UNORM:
285 case PIPE_FORMAT_R16_SNORM:
286 case PIPE_FORMAT_R16_UINT:
287 case PIPE_FORMAT_R16_SINT:
288 case PIPE_FORMAT_R16_FLOAT:
289 return V_028C70_SWAP_STD;
290
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB:
293 return V_028C70_SWAP_STD_REV;
294 case PIPE_FORMAT_B8G8R8A8_SRGB:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_B8G8R8A8_UNORM:
298 case PIPE_FORMAT_B8G8R8X8_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_A8R8G8B8_UNORM:
302 case PIPE_FORMAT_X8R8G8B8_UNORM:
303 return V_028C70_SWAP_ALT_REV;
304 case PIPE_FORMAT_R8G8B8A8_SNORM:
305 case PIPE_FORMAT_R8G8B8A8_UNORM:
306 case PIPE_FORMAT_R8G8B8A8_SINT:
307 case PIPE_FORMAT_R8G8B8A8_UINT:
308 case PIPE_FORMAT_R8G8B8X8_UNORM:
309 return V_028C70_SWAP_STD;
310
311 case PIPE_FORMAT_A8B8G8R8_UNORM:
312 case PIPE_FORMAT_X8B8G8R8_UNORM:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV;
315
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_X8Z24_UNORM:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R10G10B10A2_UNORM:
325 case PIPE_FORMAT_R10G10B10X2_SNORM:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327 return V_028C70_SWAP_STD;
328
329 case PIPE_FORMAT_B10G10R10A2_UNORM:
330 case PIPE_FORMAT_B10G10R10A2_UINT:
331 return V_028C70_SWAP_ALT;
332
333 case PIPE_FORMAT_R11G11B10_FLOAT:
334 case PIPE_FORMAT_R32_FLOAT:
335 case PIPE_FORMAT_R32_UINT:
336 case PIPE_FORMAT_R32_SINT:
337 case PIPE_FORMAT_Z32_FLOAT:
338 case PIPE_FORMAT_R16G16_FLOAT:
339 case PIPE_FORMAT_R16G16_UNORM:
340 case PIPE_FORMAT_R16G16_SNORM:
341 case PIPE_FORMAT_R16G16_UINT:
342 case PIPE_FORMAT_R16G16_SINT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16A16_FLOAT:
521 return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523 case PIPE_FORMAT_R32G32_FLOAT:
524 case PIPE_FORMAT_L32A32_FLOAT:
525 return V_028C70_COLOR_32_32_FLOAT;
526
527 case PIPE_FORMAT_R32G32_SINT:
528 case PIPE_FORMAT_R32G32_UINT:
529 case PIPE_FORMAT_L32A32_UINT:
530 case PIPE_FORMAT_L32A32_SINT:
531 return V_028C70_COLOR_32_32;
532
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM:
535 case PIPE_FORMAT_R32G32B32A32_UNORM:
536 case PIPE_FORMAT_R32G32B32A32_SINT:
537 case PIPE_FORMAT_R32G32B32A32_UINT:
538 return V_028C70_COLOR_32_32_32_32;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT:
540 return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542 /* YUV buffers. */
543 case PIPE_FORMAT_UYVY:
544 case PIPE_FORMAT_YUYV:
545 default:
546 return ~0U; /* Unsupported. */
547 }
548 }
549
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551 {
552 if (R600_BIG_ENDIAN) {
553 switch(colorformat) {
554
555 /* 8-bit buffers. */
556 case V_028C70_COLOR_8:
557 return ENDIAN_NONE;
558
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5:
561 case V_028C70_COLOR_1_5_5_5:
562 case V_028C70_COLOR_4_4_4_4:
563 case V_028C70_COLOR_16:
564 case V_028C70_COLOR_8_8:
565 return ENDIAN_8IN16;
566
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8:
569 case V_028C70_COLOR_2_10_10_10:
570 case V_028C70_COLOR_8_24:
571 case V_028C70_COLOR_24_8:
572 case V_028C70_COLOR_32_FLOAT:
573 case V_028C70_COLOR_16_16_FLOAT:
574 case V_028C70_COLOR_16_16:
575 return ENDIAN_8IN32;
576
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16:
579 case V_028C70_COLOR_16_16_16_16_FLOAT:
580 return ENDIAN_8IN16;
581
582 case V_028C70_COLOR_32_32_FLOAT:
583 case V_028C70_COLOR_32_32:
584 case V_028C70_COLOR_X24_8_32_FLOAT:
585 return ENDIAN_8IN32;
586
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT:
591 case V_028C70_COLOR_32_32_32_32:
592 return ENDIAN_8IN32;
593 default:
594 return ENDIAN_NONE; /* Unsupported. */
595 }
596 } else {
597 return ENDIAN_NONE;
598 }
599 }
600
601 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602 {
603 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604 }
605
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607 {
608 return r600_translate_colorformat(format) != ~0U &&
609 r600_translate_colorswap(format) != ~0U;
610 }
611
612 static bool r600_is_zs_format_supported(enum pipe_format format)
613 {
614 return r600_translate_dbformat(format) != ~0U;
615 }
616
617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 if (sample_count > 1) {
635 if (rscreen->info.drm_minor < 19)
636 return FALSE;
637
638 switch (sample_count) {
639 case 2:
640 case 4:
641 case 8:
642 break;
643 default:
644 return FALSE;
645 }
646 }
647
648 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
649 r600_is_sampler_format_supported(screen, format)) {
650 retval |= PIPE_BIND_SAMPLER_VIEW;
651 }
652
653 if ((usage & (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED)) &&
657 r600_is_colorbuffer_format_supported(format)) {
658 retval |= usage &
659 (PIPE_BIND_RENDER_TARGET |
660 PIPE_BIND_DISPLAY_TARGET |
661 PIPE_BIND_SCANOUT |
662 PIPE_BIND_SHARED);
663 }
664
665 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
666 r600_is_zs_format_supported(format)) {
667 retval |= PIPE_BIND_DEPTH_STENCIL;
668 }
669
670 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
671 r600_is_vertex_format_supported(format)) {
672 retval |= PIPE_BIND_VERTEX_BUFFER;
673 }
674
675 if (usage & PIPE_BIND_TRANSFER_READ)
676 retval |= PIPE_BIND_TRANSFER_READ;
677 if (usage & PIPE_BIND_TRANSFER_WRITE)
678 retval |= PIPE_BIND_TRANSFER_WRITE;
679
680 return retval == usage;
681 }
682
683 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
684 const struct pipe_blend_state *state, int mode)
685 {
686 uint32_t color_control = 0, target_mask = 0;
687 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
688
689 if (!blend) {
690 return NULL;
691 }
692
693 r600_init_command_buffer(&blend->buffer, 20);
694 r600_init_command_buffer(&blend->buffer_no_blend, 20);
695
696 if (state->logicop_enable) {
697 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
698 } else {
699 color_control |= (0xcc << 16);
700 }
701 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
702 if (state->independent_blend_enable) {
703 for (int i = 0; i < 8; i++) {
704 target_mask |= (state->rt[i].colormask << (4 * i));
705 }
706 } else {
707 for (int i = 0; i < 8; i++) {
708 target_mask |= (state->rt[0].colormask << (4 * i));
709 }
710 }
711
712 /* only have dual source on MRT0 */
713 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
714 blend->cb_target_mask = target_mask;
715 blend->alpha_to_one = state->alpha_to_one;
716
717 if (target_mask)
718 color_control |= S_028808_MODE(mode);
719 else
720 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
721
722
723 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
724 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
725 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
726 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
727 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
728 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
729 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
730 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
731
732 /* Copy over the dwords set so far into buffer_no_blend.
733 * Only the CB_BLENDi_CONTROL registers must be set after this. */
734 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
735 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
736
737 for (int i = 0; i < 8; i++) {
738 /* state->rt entries > 0 only written if independent blending */
739 const int j = state->independent_blend_enable ? i : 0;
740
741 unsigned eqRGB = state->rt[j].rgb_func;
742 unsigned srcRGB = state->rt[j].rgb_src_factor;
743 unsigned dstRGB = state->rt[j].rgb_dst_factor;
744 unsigned eqA = state->rt[j].alpha_func;
745 unsigned srcA = state->rt[j].alpha_src_factor;
746 unsigned dstA = state->rt[j].alpha_dst_factor;
747 uint32_t bc = 0;
748
749 r600_store_value(&blend->buffer_no_blend, 0);
750
751 if (!state->rt[j].blend_enable) {
752 r600_store_value(&blend->buffer, 0);
753 continue;
754 }
755
756 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
757 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
758 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
759 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
760
761 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
762 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
763 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
764 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
765 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
766 }
767 r600_store_value(&blend->buffer, bc);
768 }
769 return blend;
770 }
771
772 static void *evergreen_create_blend_state(struct pipe_context *ctx,
773 const struct pipe_blend_state *state)
774 {
775
776 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
777 }
778
779 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
780 const struct pipe_depth_stencil_alpha_state *state)
781 {
782 unsigned db_depth_control, alpha_test_control, alpha_ref;
783 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
784
785 if (dsa == NULL) {
786 return NULL;
787 }
788
789 r600_init_command_buffer(&dsa->buffer, 3);
790
791 dsa->valuemask[0] = state->stencil[0].valuemask;
792 dsa->valuemask[1] = state->stencil[1].valuemask;
793 dsa->writemask[0] = state->stencil[0].writemask;
794 dsa->writemask[1] = state->stencil[1].writemask;
795
796 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
797 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
798 S_028800_ZFUNC(state->depth.func);
799
800 /* stencil */
801 if (state->stencil[0].enabled) {
802 db_depth_control |= S_028800_STENCIL_ENABLE(1);
803 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
804 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
805 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
806 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
807
808 if (state->stencil[1].enabled) {
809 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
810 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
811 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
812 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
813 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
814 }
815 }
816
817 /* alpha */
818 alpha_test_control = 0;
819 alpha_ref = 0;
820 if (state->alpha.enabled) {
821 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
822 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
823 alpha_ref = fui(state->alpha.ref_value);
824 }
825 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
826 dsa->alpha_ref = alpha_ref;
827
828 /* misc */
829 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
830 return dsa;
831 }
832
833 static void *evergreen_create_rs_state(struct pipe_context *ctx,
834 const struct pipe_rasterizer_state *state)
835 {
836 struct r600_context *rctx = (struct r600_context *)ctx;
837 unsigned tmp, spi_interp;
838 float psize_min, psize_max;
839 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
840
841 if (rs == NULL) {
842 return NULL;
843 }
844
845 r600_init_command_buffer(&rs->buffer, 30);
846
847 rs->flatshade = state->flatshade;
848 rs->sprite_coord_enable = state->sprite_coord_enable;
849 rs->two_side = state->light_twoside;
850 rs->clip_plane_enable = state->clip_plane_enable;
851 rs->pa_sc_line_stipple = state->line_stipple_enable ?
852 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
853 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
854 rs->pa_cl_clip_cntl =
855 S_028810_PS_UCP_MODE(3) |
856 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
857 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
858 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
859 rs->multisample_enable = state->multisample;
860
861 /* offset */
862 rs->offset_units = state->offset_units;
863 rs->offset_scale = state->offset_scale * 12.0f;
864 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
865
866 if (state->point_size_per_vertex) {
867 psize_min = util_get_min_point_size(state);
868 psize_max = 8192;
869 } else {
870 /* Force the point size to be as if the vertex output was disabled. */
871 psize_min = state->point_size;
872 psize_max = state->point_size;
873 }
874
875 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
876 if (state->sprite_coord_enable) {
877 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
878 S_0286D4_PNT_SPRITE_OVRD_X(2) |
879 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
880 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
881 S_0286D4_PNT_SPRITE_OVRD_W(1);
882 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
883 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
884 }
885 }
886
887 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
888 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
889 tmp = r600_pack_float_12p4(state->point_size/2);
890 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
891 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
892 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
893 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
894 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
895 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
896 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
897
898 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
899 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
900 S_028A48_MSAA_ENABLE(state->multisample) |
901 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
902 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
903
904 if (rctx->chip_class == CAYMAN) {
905 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
906 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
907 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
908 } else {
909 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
910 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
911 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
912 }
913
914 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
915 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
916 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
917 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
918 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
919 S_028814_FACE(!state->front_ccw) |
920 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
921 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
922 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
923 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
924 state->fill_back != PIPE_POLYGON_MODE_FILL) |
925 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
926 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
927 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
928 return rs;
929 }
930
931 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
932 const struct pipe_sampler_state *state)
933 {
934 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
935 union util_color uc;
936 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
937
938 if (ss == NULL) {
939 return NULL;
940 }
941
942 /* directly into sampler avoid r6xx code to emit useless reg */
943 ss->seamless_cube_map = false;
944 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
945 ss->border_color_use = false;
946 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
947 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
948 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
949 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
950 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
951 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
952 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
953 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
954 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
955 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
956 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
957 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
958 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
959 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
960 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
961 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
962 S_03C008_TYPE(1);
963 if (uc.ui) {
964 ss->border_color_use = true;
965 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
966 ss->border_color[0] = fui(state->border_color.f[0]);
967 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
968 ss->border_color[1] = fui(state->border_color.f[1]);
969 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
970 ss->border_color[2] = fui(state->border_color.f[2]);
971 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
972 ss->border_color[3] = fui(state->border_color.f[3]);
973 }
974 return ss;
975 }
976
977 struct pipe_sampler_view *
978 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
979 struct pipe_resource *texture,
980 const struct pipe_sampler_view *state,
981 unsigned width0, unsigned height0)
982 {
983 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
984 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
985 struct r600_texture *tmp = (struct r600_texture*)texture;
986 unsigned format, endian;
987 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
988 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
989 unsigned height, depth, width;
990 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
991
992 if (view == NULL)
993 return NULL;
994
995 /* initialize base object */
996 view->base = *state;
997 view->base.texture = NULL;
998 pipe_reference(NULL, &texture->reference);
999 view->base.texture = texture;
1000 view->base.reference.count = 1;
1001 view->base.context = ctx;
1002
1003 swizzle[0] = state->swizzle_r;
1004 swizzle[1] = state->swizzle_g;
1005 swizzle[2] = state->swizzle_b;
1006 swizzle[3] = state->swizzle_a;
1007
1008 format = r600_translate_texformat(ctx->screen, state->format,
1009 swizzle,
1010 &word4, &yuv_format);
1011 assert(format != ~0);
1012 if (format == ~0) {
1013 FREE(view);
1014 return NULL;
1015 }
1016
1017 if (tmp->is_depth && !tmp->is_flushing_texture) {
1018 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1019 FREE(view);
1020 return NULL;
1021 }
1022 tmp = tmp->flushed_depth_texture;
1023 }
1024
1025 endian = r600_colorformat_endian_swap(format);
1026
1027 width = width0;
1028 height = height0;
1029 depth = tmp->surface.level[0].npix_z;
1030 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1031 tile_type = tmp->tile_type;
1032
1033 switch (tmp->surface.level[0].mode) {
1034 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1035 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1036 break;
1037 case RADEON_SURF_MODE_2D:
1038 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1039 break;
1040 case RADEON_SURF_MODE_1D:
1041 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1042 break;
1043 case RADEON_SURF_MODE_LINEAR:
1044 default:
1045 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1046 break;
1047 }
1048 tile_split = tmp->surface.tile_split;
1049 macro_aspect = tmp->surface.mtilea;
1050 bankw = tmp->surface.bankw;
1051 bankh = tmp->surface.bankh;
1052 tile_split = eg_tile_split(tile_split);
1053 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1054 bankw = eg_bank_wh(bankw);
1055 bankh = eg_bank_wh(bankh);
1056
1057 /* 128 bit formats require tile type = 1 */
1058 if (rscreen->chip_class == CAYMAN) {
1059 if (util_format_get_blocksize(state->format) >= 16)
1060 tile_type = 1;
1061 }
1062 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1063
1064 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1065 height = 1;
1066 depth = texture->array_size;
1067 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1068 depth = texture->array_size;
1069 }
1070
1071 view->tex_resource = &tmp->resource;
1072 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1073 S_030000_PITCH((pitch / 8) - 1) |
1074 S_030000_TEX_WIDTH(width - 1));
1075 if (rscreen->chip_class == CAYMAN)
1076 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1077 else
1078 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1079 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1080 S_030004_TEX_DEPTH(depth - 1) |
1081 S_030004_ARRAY_MODE(array_mode));
1082 view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1083 if (state->u.tex.last_level && texture->nr_samples <= 1) {
1084 view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1085 } else {
1086 view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1087 }
1088 view->tex_resource_words[4] = (word4 |
1089 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1090 S_030010_ENDIAN_SWAP(endian));
1091 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1092 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1093 if (texture->nr_samples > 1) {
1094 unsigned log_samples = util_logbase2(texture->nr_samples);
1095 if (rscreen->chip_class == CAYMAN) {
1096 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1097 }
1098 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1099 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1100 } else {
1101 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1102 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1103 }
1104 /* aniso max 16 samples */
1105 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1106 (S_030018_TILE_SPLIT(tile_split));
1107 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1108 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1109 S_03001C_BANK_WIDTH(bankw) |
1110 S_03001C_BANK_HEIGHT(bankh) |
1111 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1112 S_03001C_NUM_BANKS(nbanks);
1113 return &view->base;
1114 }
1115
1116 static struct pipe_sampler_view *
1117 evergreen_create_sampler_view(struct pipe_context *ctx,
1118 struct pipe_resource *tex,
1119 const struct pipe_sampler_view *state)
1120 {
1121 return evergreen_create_sampler_view_custom(ctx, tex, state,
1122 tex->width0, tex->height0);
1123 }
1124
1125 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1126 {
1127 struct radeon_winsys_cs *cs = rctx->cs;
1128 struct pipe_clip_state *state = &rctx->clip_state.state;
1129
1130 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1131 r600_write_array(cs, 6*4, (unsigned*)state);
1132 }
1133
1134 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1135 const struct pipe_poly_stipple *state)
1136 {
1137 }
1138
1139 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1140 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1141 uint32_t *tl, uint32_t *br)
1142 {
1143 /* EG hw workaround */
1144 if (br_x == 0)
1145 tl_x = 1;
1146 if (br_y == 0)
1147 tl_y = 1;
1148
1149 /* cayman hw workaround */
1150 if (rctx->chip_class == CAYMAN) {
1151 if (br_x == 1 && br_y == 1)
1152 br_x = 2;
1153 }
1154
1155 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1156 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1157 }
1158
1159 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1160 const struct pipe_scissor_state *state)
1161 {
1162 struct r600_context *rctx = (struct r600_context *)ctx;
1163
1164 rctx->scissor.scissor = *state;
1165 rctx->scissor.atom.dirty = true;
1166 }
1167
1168 static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1169 {
1170 struct radeon_winsys_cs *cs = rctx->cs;
1171 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1172 uint32_t tl, br;
1173
1174 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1175
1176 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1177 r600_write_value(cs, tl);
1178 r600_write_value(cs, br);
1179 }
1180
1181 /**
1182 * This function intializes the CB* register values for RATs. It is meant
1183 * to be used for 1D aligned buffers that do not have an associated
1184 * radeon_surface.
1185 */
1186 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1187 struct r600_surface *surf)
1188 {
1189 struct pipe_resource *pipe_buffer = surf->base.texture;
1190 unsigned format = r600_translate_colorformat(surf->base.format);
1191 unsigned endian = r600_colorformat_endian_swap(format);
1192 unsigned swap = r600_translate_colorswap(surf->base.format);
1193 unsigned block_size =
1194 align(util_format_get_blocksize(pipe_buffer->format), 4);
1195 unsigned pitch_alignment =
1196 MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
1197 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
1198
1199 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1200 * know why this is necessary.
1201 */
1202 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
1203 endian = ENDIAN_NONE;
1204 }
1205
1206 surf->cb_color_base =
1207 r600_resource_va(rctx->context.screen, pipe_buffer) >> 8;
1208
1209 surf->cb_color_pitch = (pitch / 8) - 1;
1210
1211 surf->cb_color_slice = 0;
1212
1213 surf->cb_color_view = 0;
1214
1215 surf->cb_color_info =
1216 S_028C70_ENDIAN(endian)
1217 | S_028C70_FORMAT(format)
1218 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1219 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1220 | S_028C70_COMP_SWAP(swap)
1221 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1222 * are using NUMBER_UINT */
1223 | S_028C70_RAT(1)
1224 ;
1225
1226 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1227
1228 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1229 * elements. */
1230 surf->cb_color_dim = pipe_buffer->width0;
1231
1232 surf->cb_color_cmask = surf->cb_color_base;
1233 surf->cb_color_cmask_slice = 0;
1234 surf->cb_color_fmask = surf->cb_color_base;
1235 surf->cb_color_fmask_slice = 0;
1236 }
1237
1238 void evergreen_init_color_surface(struct r600_context *rctx,
1239 struct r600_surface *surf)
1240 {
1241 struct r600_screen *rscreen = rctx->screen;
1242 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1243 struct pipe_resource *pipe_tex = surf->base.texture;
1244 unsigned level = surf->base.u.tex.level;
1245 unsigned pitch, slice;
1246 unsigned color_info, color_attrib, color_dim = 0;
1247 unsigned format, swap, ntype, endian;
1248 uint64_t offset, base_offset;
1249 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1250 const struct util_format_description *desc;
1251 int i;
1252 bool blend_clamp = 0, blend_bypass = 0;
1253
1254 if (rtex->is_depth && !rtex->is_flushing_texture) {
1255 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1256 rtex = rtex->flushed_depth_texture;
1257 assert(rtex);
1258 }
1259
1260 offset = rtex->surface.level[level].offset;
1261 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1262 offset += rtex->surface.level[level].slice_size *
1263 surf->base.u.tex.first_layer;
1264 }
1265 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1266 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1267 if (slice) {
1268 slice = slice - 1;
1269 }
1270 color_info = 0;
1271 switch (rtex->surface.level[level].mode) {
1272 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1273 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1274 tile_type = 1;
1275 break;
1276 case RADEON_SURF_MODE_1D:
1277 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1278 tile_type = rtex->tile_type;
1279 break;
1280 case RADEON_SURF_MODE_2D:
1281 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1282 tile_type = rtex->tile_type;
1283 break;
1284 case RADEON_SURF_MODE_LINEAR:
1285 default:
1286 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1287 tile_type = 1;
1288 break;
1289 }
1290 tile_split = rtex->surface.tile_split;
1291 macro_aspect = rtex->surface.mtilea;
1292 bankw = rtex->surface.bankw;
1293 bankh = rtex->surface.bankh;
1294 fmask_bankh = rtex->fmask_bank_height;
1295 tile_split = eg_tile_split(tile_split);
1296 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1297 bankw = eg_bank_wh(bankw);
1298 bankh = eg_bank_wh(bankh);
1299 fmask_bankh = eg_bank_wh(fmask_bankh);
1300
1301 /* 128 bit formats require tile type = 1 */
1302 if (rscreen->chip_class == CAYMAN) {
1303 if (util_format_get_blocksize(surf->base.format) >= 16)
1304 tile_type = 1;
1305 }
1306 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1307 desc = util_format_description(surf->base.format);
1308 for (i = 0; i < 4; i++) {
1309 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1310 break;
1311 }
1312 }
1313
1314 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1315 S_028C74_NUM_BANKS(nbanks) |
1316 S_028C74_BANK_WIDTH(bankw) |
1317 S_028C74_BANK_HEIGHT(bankh) |
1318 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1319 S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1320 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1321
1322 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1323 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1324 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1325 S_028C74_NUM_FRAGMENTS(log_samples);
1326 }
1327
1328 ntype = V_028C70_NUMBER_UNORM;
1329 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1330 ntype = V_028C70_NUMBER_SRGB;
1331 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1332 if (desc->channel[i].normalized)
1333 ntype = V_028C70_NUMBER_SNORM;
1334 else if (desc->channel[i].pure_integer)
1335 ntype = V_028C70_NUMBER_SINT;
1336 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1337 if (desc->channel[i].normalized)
1338 ntype = V_028C70_NUMBER_UNORM;
1339 else if (desc->channel[i].pure_integer)
1340 ntype = V_028C70_NUMBER_UINT;
1341 }
1342
1343 format = r600_translate_colorformat(surf->base.format);
1344 assert(format != ~0);
1345
1346 swap = r600_translate_colorswap(surf->base.format);
1347 assert(swap != ~0);
1348
1349 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1350 endian = ENDIAN_NONE;
1351 } else {
1352 endian = r600_colorformat_endian_swap(format);
1353 }
1354
1355 /* blend clamp should be set for all NORM/SRGB types */
1356 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1357 ntype == V_028C70_NUMBER_SRGB)
1358 blend_clamp = 1;
1359
1360 /* set blend bypass according to docs if SINT/UINT or
1361 8/24 COLOR variants */
1362 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1363 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1364 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1365 blend_clamp = 0;
1366 blend_bypass = 1;
1367 }
1368
1369 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1370
1371 color_info |= S_028C70_FORMAT(format) |
1372 S_028C70_COMP_SWAP(swap) |
1373 S_028C70_BLEND_CLAMP(blend_clamp) |
1374 S_028C70_BLEND_BYPASS(blend_bypass) |
1375 S_028C70_NUMBER_TYPE(ntype) |
1376 S_028C70_ENDIAN(endian);
1377
1378 if (rtex->is_rat) {
1379 color_info |= S_028C70_RAT(1);
1380 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
1381 | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
1382 }
1383
1384 /* EXPORT_NORM is an optimzation that can be enabled for better
1385 * performance in certain cases.
1386 * EXPORT_NORM can be enabled if:
1387 * - 11-bit or smaller UNORM/SNORM/SRGB
1388 * - 16-bit or smaller FLOAT
1389 */
1390 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1391 ((desc->channel[i].size < 12 &&
1392 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1393 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1394 (desc->channel[i].size < 17 &&
1395 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1396 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1397 surf->export_16bpc = true;
1398 }
1399
1400 if (rtex->fmask_size && rtex->cmask_size) {
1401 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1402 }
1403
1404 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1405
1406 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1407 surf->cb_color_base = (base_offset + offset) >> 8;
1408 surf->cb_color_dim = color_dim;
1409 surf->cb_color_info = color_info;
1410 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1411 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1412 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1413 surf->cb_color_view = 0;
1414 } else {
1415 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1416 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1417 }
1418 surf->cb_color_attrib = color_attrib;
1419 if (rtex->fmask_size && rtex->cmask_size) {
1420 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1421 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1422 } else {
1423 surf->cb_color_fmask = surf->cb_color_base;
1424 surf->cb_color_cmask = surf->cb_color_base;
1425 }
1426 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1427 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1428
1429 surf->color_initialized = true;
1430 }
1431
1432 static void evergreen_init_depth_surface(struct r600_context *rctx,
1433 struct r600_surface *surf)
1434 {
1435 struct r600_screen *rscreen = rctx->screen;
1436 struct pipe_screen *screen = &rscreen->screen;
1437 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1438 uint64_t offset;
1439 unsigned level, pitch, slice, format, array_mode;
1440 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1441
1442 level = surf->base.u.tex.level;
1443 format = r600_translate_dbformat(surf->base.format);
1444 assert(format != ~0);
1445
1446 offset = r600_resource_va(screen, surf->base.texture);
1447 offset += rtex->surface.level[level].offset;
1448 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1449 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1450 if (slice) {
1451 slice = slice - 1;
1452 }
1453 switch (rtex->surface.level[level].mode) {
1454 case RADEON_SURF_MODE_2D:
1455 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1456 break;
1457 case RADEON_SURF_MODE_1D:
1458 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1459 case RADEON_SURF_MODE_LINEAR:
1460 default:
1461 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1462 break;
1463 }
1464 tile_split = rtex->surface.tile_split;
1465 macro_aspect = rtex->surface.mtilea;
1466 bankw = rtex->surface.bankw;
1467 bankh = rtex->surface.bankh;
1468 tile_split = eg_tile_split(tile_split);
1469 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1470 bankw = eg_bank_wh(bankw);
1471 bankh = eg_bank_wh(bankh);
1472 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1473 offset >>= 8;
1474
1475 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1476 S_028040_FORMAT(format) |
1477 S_028040_TILE_SPLIT(tile_split)|
1478 S_028040_NUM_BANKS(nbanks) |
1479 S_028040_BANK_WIDTH(bankw) |
1480 S_028040_BANK_HEIGHT(bankh) |
1481 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1482 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1483 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1484 }
1485 surf->db_depth_base = offset;
1486 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1487 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1488 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1489 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1490
1491 switch (surf->base.format) {
1492 case PIPE_FORMAT_Z24X8_UNORM:
1493 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1494 surf->pa_su_poly_offset_db_fmt_cntl =
1495 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1496 break;
1497 case PIPE_FORMAT_Z32_FLOAT:
1498 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1499 surf->pa_su_poly_offset_db_fmt_cntl =
1500 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1501 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1502 break;
1503 case PIPE_FORMAT_Z16_UNORM:
1504 surf->pa_su_poly_offset_db_fmt_cntl =
1505 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1506 break;
1507 default:;
1508 }
1509
1510 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1511 uint64_t stencil_offset = rtex->surface.stencil_offset;
1512 unsigned i, stile_split = rtex->surface.stencil_tile_split;
1513
1514 stile_split = eg_tile_split(stile_split);
1515 stencil_offset += r600_resource_va(screen, surf->base.texture);
1516 stencil_offset += rtex->surface.level[level].offset / 4;
1517 stencil_offset >>= 8;
1518
1519 /* We're guessing the stencil offset from the depth offset.
1520 * Make sure each mipmap level has a unique offset. */
1521 for (i = 1; i <= level; i++) {
1522 /* If two levels have the same address, add 256
1523 * to the offset of the smaller level. */
1524 if ((rtex->surface.level[i-1].offset / 4) >> 8 ==
1525 (rtex->surface.level[i].offset / 4) >> 8) {
1526 stencil_offset++;
1527 }
1528 }
1529
1530 surf->db_stencil_base = stencil_offset;
1531 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1532 S_028044_TILE_SPLIT(stile_split);
1533 } else {
1534 surf->db_stencil_base = offset;
1535 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1536 * Older kernels are out of luck. */
1537 surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
1538 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1539 S_028044_FORMAT(V_028044_STENCIL_8);
1540 }
1541
1542 surf->depth_initialized = true;
1543 }
1544
1545 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1546 const struct pipe_framebuffer_state *state)
1547 {
1548 struct r600_context *rctx = (struct r600_context *)ctx;
1549 struct r600_surface *surf;
1550 struct r600_texture *rtex;
1551 uint32_t i, log_samples;
1552
1553 if (rctx->framebuffer.state.nr_cbufs) {
1554 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1555
1556 if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1557 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1558 }
1559 }
1560 if (rctx->framebuffer.state.zsbuf) {
1561 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1562 }
1563
1564 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1565
1566 /* Colorbuffers. */
1567 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1568 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1569 util_format_is_pure_integer(state->cbufs[0]->format);
1570 rctx->framebuffer.compressed_cb_mask = 0;
1571
1572 if (state->nr_cbufs)
1573 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1574 else if (state->zsbuf)
1575 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1576 else
1577 rctx->framebuffer.nr_samples = 0;
1578
1579 for (i = 0; i < state->nr_cbufs; i++) {
1580 surf = (struct r600_surface*)state->cbufs[i];
1581 rtex = (struct r600_texture*)surf->base.texture;
1582
1583 if (!surf->color_initialized) {
1584 evergreen_init_color_surface(rctx, surf);
1585 }
1586
1587 if (!surf->export_16bpc) {
1588 rctx->framebuffer.export_16bpc = false;
1589 }
1590
1591 /* Cayman can fetch from a compressed MSAA colorbuffer,
1592 * so it's pointless to track them. */
1593 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1594 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1595 }
1596 }
1597
1598 /* Update alpha-test state dependencies.
1599 * Alpha-test is done on the first colorbuffer only. */
1600 if (state->nr_cbufs) {
1601 surf = (struct r600_surface*)state->cbufs[0];
1602 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1603 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1604 rctx->alphatest_state.atom.dirty = true;
1605 }
1606 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1607 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1608 rctx->alphatest_state.atom.dirty = true;
1609 }
1610 }
1611
1612 /* ZS buffer. */
1613 if (state->zsbuf) {
1614 surf = (struct r600_surface*)state->zsbuf;
1615
1616 if (!surf->depth_initialized) {
1617 evergreen_init_depth_surface(rctx, surf);
1618 }
1619
1620 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1621 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1622 rctx->poly_offset_state.atom.dirty = true;
1623 }
1624 }
1625
1626 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1627 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1628 rctx->cb_misc_state.atom.dirty = true;
1629 }
1630
1631 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1632 rctx->alphatest_state.bypass = false;
1633 rctx->alphatest_state.atom.dirty = true;
1634 }
1635
1636 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1637 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1638 rctx->db_misc_state.log_samples = log_samples;
1639 rctx->db_misc_state.atom.dirty = true;
1640 }
1641
1642 evergreen_update_db_shader_control(rctx);
1643
1644 /* Calculate the CS size. */
1645 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1646
1647 /* MSAA. */
1648 if (rctx->chip_class == EVERGREEN) {
1649 switch (rctx->framebuffer.nr_samples) {
1650 case 2:
1651 case 4:
1652 rctx->framebuffer.atom.num_dw += 6;
1653 break;
1654 case 8:
1655 rctx->framebuffer.atom.num_dw += 10;
1656 break;
1657 }
1658 rctx->framebuffer.atom.num_dw += 4;
1659 } else {
1660 switch (rctx->framebuffer.nr_samples) {
1661 case 2:
1662 case 4:
1663 rctx->framebuffer.atom.num_dw += 12;
1664 break;
1665 case 8:
1666 rctx->framebuffer.atom.num_dw += 16;
1667 break;
1668 case 16:
1669 rctx->framebuffer.atom.num_dw += 18;
1670 break;
1671 }
1672 rctx->framebuffer.atom.num_dw += 7;
1673 }
1674
1675 /* Colorbuffers. */
1676 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
1677 if (rctx->keep_tiling_flags)
1678 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1679 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1680
1681 /* ZS buffer. */
1682 if (state->zsbuf) {
1683 rctx->framebuffer.atom.num_dw += 24;
1684 if (rctx->keep_tiling_flags)
1685 rctx->framebuffer.atom.num_dw += 2;
1686 } else if (rctx->screen->info.drm_minor >= 18) {
1687 rctx->framebuffer.atom.num_dw += 4;
1688 }
1689
1690 rctx->framebuffer.atom.dirty = true;
1691 }
1692
1693 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1694 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1695 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1696 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1697 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1698
1699 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1700 {
1701 /* 2xMSAA
1702 * There are two locations (-4, 4), (4, -4). */
1703 static uint32_t sample_locs_2x[] = {
1704 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1705 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1706 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1707 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1708 };
1709 static unsigned max_dist_2x = 4;
1710 /* 4xMSAA
1711 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1712 static uint32_t sample_locs_4x[] = {
1713 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1714 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1715 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1716 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1717 };
1718 static unsigned max_dist_4x = 6;
1719 /* 8xMSAA */
1720 static uint32_t sample_locs_8x[] = {
1721 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1722 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1723 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1724 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1725 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1726 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1727 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1728 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1729 };
1730 static unsigned max_dist_8x = 8;
1731
1732 struct radeon_winsys_cs *cs = rctx->cs;
1733 unsigned max_dist = 0;
1734
1735 switch (nr_samples) {
1736 default:
1737 nr_samples = 0;
1738 break;
1739 case 2:
1740 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1741 r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
1742 max_dist = max_dist_2x;
1743 break;
1744 case 4:
1745 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1746 r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
1747 max_dist = max_dist_4x;
1748 break;
1749 case 8:
1750 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1751 r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
1752 max_dist = max_dist_8x;
1753 break;
1754 }
1755
1756 if (nr_samples > 1) {
1757 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1758 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1759 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1760 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1761 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1762 } else {
1763 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1764 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1765 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1766 }
1767 }
1768
1769 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1770 {
1771 /* 2xMSAA
1772 * There are two locations (-4, 4), (4, -4). */
1773 static uint32_t sample_locs_2x[] = {
1774 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1775 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1776 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1777 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1778 };
1779 static unsigned max_dist_2x = 4;
1780 /* 4xMSAA
1781 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1782 static uint32_t sample_locs_4x[] = {
1783 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1784 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1785 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1786 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1787 };
1788 static unsigned max_dist_4x = 6;
1789 /* 8xMSAA */
1790 static uint32_t sample_locs_8x[] = {
1791 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1792 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1793 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1794 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1795 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1796 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1797 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1798 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1799 };
1800 static unsigned max_dist_8x = 8;
1801 /* 16xMSAA */
1802 static uint32_t sample_locs_16x[] = {
1803 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1804 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1805 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1806 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1807 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1808 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1809 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1810 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1811 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1812 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1813 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1814 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1815 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1816 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1817 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1818 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1819 };
1820 static unsigned max_dist_16x = 8;
1821
1822 struct radeon_winsys_cs *cs = rctx->cs;
1823 unsigned max_dist = 0;
1824
1825 switch (nr_samples) {
1826 default:
1827 nr_samples = 0;
1828 break;
1829 case 2:
1830 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1831 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1832 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1833 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1834 max_dist = max_dist_2x;
1835 break;
1836 case 4:
1837 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1838 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1839 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1840 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1841 max_dist = max_dist_4x;
1842 break;
1843 case 8:
1844 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1845 r600_write_value(cs, sample_locs_8x[0]);
1846 r600_write_value(cs, sample_locs_8x[4]);
1847 r600_write_value(cs, 0);
1848 r600_write_value(cs, 0);
1849 r600_write_value(cs, sample_locs_8x[1]);
1850 r600_write_value(cs, sample_locs_8x[5]);
1851 r600_write_value(cs, 0);
1852 r600_write_value(cs, 0);
1853 r600_write_value(cs, sample_locs_8x[2]);
1854 r600_write_value(cs, sample_locs_8x[6]);
1855 r600_write_value(cs, 0);
1856 r600_write_value(cs, 0);
1857 r600_write_value(cs, sample_locs_8x[3]);
1858 r600_write_value(cs, sample_locs_8x[7]);
1859 max_dist = max_dist_8x;
1860 break;
1861 case 16:
1862 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1863 r600_write_value(cs, sample_locs_16x[0]);
1864 r600_write_value(cs, sample_locs_16x[4]);
1865 r600_write_value(cs, sample_locs_16x[8]);
1866 r600_write_value(cs, sample_locs_16x[12]);
1867 r600_write_value(cs, sample_locs_16x[1]);
1868 r600_write_value(cs, sample_locs_16x[5]);
1869 r600_write_value(cs, sample_locs_16x[9]);
1870 r600_write_value(cs, sample_locs_16x[13]);
1871 r600_write_value(cs, sample_locs_16x[2]);
1872 r600_write_value(cs, sample_locs_16x[6]);
1873 r600_write_value(cs, sample_locs_16x[10]);
1874 r600_write_value(cs, sample_locs_16x[14]);
1875 r600_write_value(cs, sample_locs_16x[3]);
1876 r600_write_value(cs, sample_locs_16x[7]);
1877 r600_write_value(cs, sample_locs_16x[11]);
1878 r600_write_value(cs, sample_locs_16x[15]);
1879 max_dist = max_dist_16x;
1880 break;
1881 }
1882
1883 if (nr_samples > 1) {
1884 unsigned log_samples = util_logbase2(nr_samples);
1885
1886 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1887 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1888 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1889 r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1890 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1891 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1892
1893 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1894 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1895 S_028804_PS_ITER_SAMPLES(log_samples) |
1896 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1897 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1898 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1899 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1900 } else {
1901 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1902 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1903 r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1904
1905 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1906 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1907 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1908 }
1909 }
1910
1911 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1912 {
1913 struct radeon_winsys_cs *cs = rctx->cs;
1914 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1915 unsigned nr_cbufs = state->nr_cbufs;
1916 unsigned i, tl, br;
1917
1918 /* XXX support more colorbuffers once we need them */
1919 assert(nr_cbufs <= 8);
1920 if (nr_cbufs > 8)
1921 nr_cbufs = 8;
1922
1923 /* Colorbuffers. */
1924 for (i = 0; i < nr_cbufs; i++) {
1925 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
1926 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)cb->base.texture,
1927 RADEON_USAGE_READWRITE);
1928
1929 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
1930 r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1931 r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1932 r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1933 r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1934 r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1935 r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1936 r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1937 r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
1938 r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1939 r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1940 r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1941
1942 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1943 r600_write_value(cs, reloc);
1944
1945 if (!rctx->keep_tiling_flags) {
1946 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1947 r600_write_value(cs, reloc);
1948 }
1949
1950 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1951 r600_write_value(cs, reloc);
1952
1953 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1954 r600_write_value(cs, reloc);
1955
1956 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1957 r600_write_value(cs, reloc);
1958 }
1959 /* set CB_COLOR1_INFO for possible dual-src blending */
1960 if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
1961 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1962 ((struct r600_surface*)state->cbufs[0])->cb_color_info);
1963
1964 if (!rctx->keep_tiling_flags) {
1965 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->cbufs[0]->texture,
1966 RADEON_USAGE_READWRITE);
1967
1968 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1969 r600_write_value(cs, reloc);
1970 }
1971 i++;
1972 }
1973 if (rctx->keep_tiling_flags) {
1974 for (; i < 8 ; i++) {
1975 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1976 }
1977 for (; i < 12; i++) {
1978 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1979 }
1980 }
1981
1982 /* ZS buffer. */
1983 if (state->zsbuf) {
1984 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1985 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->zsbuf->texture,
1986 RADEON_USAGE_READWRITE);
1987
1988 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1989 zb->pa_su_poly_offset_db_fmt_cntl);
1990 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1991
1992 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1993 r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
1994 r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1995 r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1996 r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1997 r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1998 r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1999 r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2000 r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2001
2002 if (!rctx->keep_tiling_flags) {
2003 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
2004 r600_write_value(cs, reloc);
2005 }
2006
2007 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2008 r600_write_value(cs, reloc);
2009
2010 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2011 r600_write_value(cs, reloc);
2012
2013 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2014 r600_write_value(cs, reloc);
2015
2016 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2017 r600_write_value(cs, reloc);
2018 } else if (rctx->screen->info.drm_minor >= 18) {
2019 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2020 * Older kernels are out of luck. */
2021 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2022 r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2023 r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2024 }
2025
2026 /* Framebuffer dimensions. */
2027 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
2028
2029 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
2030 r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2031 r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2032
2033 if (rctx->chip_class == EVERGREEN) {
2034 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2035 } else {
2036 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2037 }
2038 }
2039
2040 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
2041 {
2042 struct radeon_winsys_cs *cs = rctx->cs;
2043 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
2044 float offset_units = state->offset_units;
2045 float offset_scale = state->offset_scale;
2046
2047 switch (state->zs_format) {
2048 case PIPE_FORMAT_Z24X8_UNORM:
2049 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2050 offset_units *= 2.0f;
2051 break;
2052 case PIPE_FORMAT_Z16_UNORM:
2053 offset_units *= 4.0f;
2054 break;
2055 default:;
2056 }
2057
2058 r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2059 r600_write_value(cs, fui(offset_scale));
2060 r600_write_value(cs, fui(offset_units));
2061 r600_write_value(cs, fui(offset_scale));
2062 r600_write_value(cs, fui(offset_units));
2063 }
2064
2065 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2066 {
2067 struct radeon_winsys_cs *cs = rctx->cs;
2068 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2069 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2070 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2071
2072 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2073 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
2074 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2075 * will assure that the alpha-test will work even if there is
2076 * no colorbuffer bound. */
2077 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
2078 }
2079
2080 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2081 {
2082 struct radeon_winsys_cs *cs = rctx->cs;
2083 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2084 unsigned db_render_control = 0;
2085 unsigned db_count_control = 0;
2086 unsigned db_render_override =
2087 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
2088 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2089 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2090
2091 if (a->occlusion_query_enabled) {
2092 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2093 if (rctx->chip_class == CAYMAN) {
2094 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2095 }
2096 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2097 }
2098
2099 if (a->flush_depthstencil_through_cb) {
2100 assert(a->copy_depth || a->copy_stencil);
2101
2102 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2103 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2104 S_028000_COPY_CENTROID(1) |
2105 S_028000_COPY_SAMPLE(a->copy_sample);
2106 }
2107
2108 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2109 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2110 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2111 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2112 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2113 }
2114
2115 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2116 struct r600_vertexbuf_state *state,
2117 unsigned resource_offset,
2118 unsigned pkt_flags)
2119 {
2120 struct radeon_winsys_cs *cs = rctx->cs;
2121 uint32_t dirty_mask = state->dirty_mask;
2122
2123 while (dirty_mask) {
2124 struct pipe_vertex_buffer *vb;
2125 struct r600_resource *rbuffer;
2126 uint64_t va;
2127 unsigned buffer_index = u_bit_scan(&dirty_mask);
2128
2129 vb = &state->vb[buffer_index];
2130 rbuffer = (struct r600_resource*)vb->buffer;
2131 assert(rbuffer);
2132
2133 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2134 va += vb->buffer_offset;
2135
2136 /* fetch resources start at index 992 */
2137 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2138 r600_write_value(cs, (resource_offset + buffer_index) * 8);
2139 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2140 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2141 r600_write_value(cs, /* RESOURCEi_WORD2 */
2142 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2143 S_030008_STRIDE(vb->stride) |
2144 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2145 r600_write_value(cs, /* RESOURCEi_WORD3 */
2146 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2147 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2148 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2149 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2150 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2151 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2152 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2153 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2154
2155 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2156 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2157 }
2158 state->dirty_mask = 0;
2159 }
2160
2161 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2162 {
2163 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2164 }
2165
2166 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2167 {
2168 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2169 RADEON_CP_PACKET3_COMPUTE_MODE);
2170 }
2171
2172 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2173 struct r600_constbuf_state *state,
2174 unsigned buffer_id_base,
2175 unsigned reg_alu_constbuf_size,
2176 unsigned reg_alu_const_cache)
2177 {
2178 struct radeon_winsys_cs *cs = rctx->cs;
2179 uint32_t dirty_mask = state->dirty_mask;
2180
2181 while (dirty_mask) {
2182 struct pipe_constant_buffer *cb;
2183 struct r600_resource *rbuffer;
2184 uint64_t va;
2185 unsigned buffer_index = ffs(dirty_mask) - 1;
2186
2187 cb = &state->cb[buffer_index];
2188 rbuffer = (struct r600_resource*)cb->buffer;
2189 assert(rbuffer);
2190
2191 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2192 va += cb->buffer_offset;
2193
2194 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2195 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2196 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2197
2198 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2199 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2200
2201 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2202 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2203 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2204 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2205 r600_write_value(cs, /* RESOURCEi_WORD2 */
2206 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2207 S_030008_STRIDE(16) |
2208 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2209 r600_write_value(cs, /* RESOURCEi_WORD3 */
2210 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2211 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2212 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2213 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2214 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2215 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2216 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2217 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2218
2219 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2220 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2221
2222 dirty_mask &= ~(1 << buffer_index);
2223 }
2224 state->dirty_mask = 0;
2225 }
2226
2227 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2228 {
2229 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2230 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2231 R_028980_ALU_CONST_CACHE_VS_0);
2232 }
2233
2234 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2235 {
2236 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2237 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2238 R_0289C0_ALU_CONST_CACHE_GS_0);
2239 }
2240
2241 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2242 {
2243 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2244 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2245 R_028940_ALU_CONST_CACHE_PS_0);
2246 }
2247
2248 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2249 struct r600_samplerview_state *state,
2250 unsigned resource_id_base)
2251 {
2252 struct radeon_winsys_cs *cs = rctx->cs;
2253 uint32_t dirty_mask = state->dirty_mask;
2254
2255 while (dirty_mask) {
2256 struct r600_pipe_sampler_view *rview;
2257 unsigned resource_index = u_bit_scan(&dirty_mask);
2258 unsigned reloc;
2259
2260 rview = state->views[resource_index];
2261 assert(rview);
2262
2263 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2264 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2265 r600_write_array(cs, 8, rview->tex_resource_words);
2266
2267 /* XXX The kernel needs two relocations. This is stupid. */
2268 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2269 RADEON_USAGE_READ);
2270 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2271 r600_write_value(cs, reloc);
2272 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2273 r600_write_value(cs, reloc);
2274 }
2275 state->dirty_mask = 0;
2276 }
2277
2278 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2279 {
2280 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2281 }
2282
2283 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2284 {
2285 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2286 }
2287
2288 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2289 {
2290 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2291 }
2292
2293 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2294 struct r600_textures_info *texinfo,
2295 unsigned resource_id_base,
2296 unsigned border_index_reg)
2297 {
2298 struct radeon_winsys_cs *cs = rctx->cs;
2299 uint32_t dirty_mask = texinfo->states.dirty_mask;
2300
2301 while (dirty_mask) {
2302 struct r600_pipe_sampler_state *rstate;
2303 unsigned i = u_bit_scan(&dirty_mask);
2304
2305 rstate = texinfo->states.states[i];
2306 assert(rstate);
2307
2308 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2309 r600_write_value(cs, (resource_id_base + i) * 3);
2310 r600_write_array(cs, 3, rstate->tex_sampler_words);
2311
2312 if (rstate->border_color_use) {
2313 r600_write_config_reg_seq(cs, border_index_reg, 5);
2314 r600_write_value(cs, i);
2315 r600_write_array(cs, 4, rstate->border_color);
2316 }
2317 }
2318 texinfo->states.dirty_mask = 0;
2319 }
2320
2321 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2322 {
2323 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2324 }
2325
2326 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2327 {
2328 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2329 }
2330
2331 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2332 {
2333 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2334 }
2335
2336 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2337 {
2338 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2339 uint8_t mask = s->sample_mask;
2340
2341 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2342 mask | (mask << 8) | (mask << 16) | (mask << 24));
2343 }
2344
2345 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2346 {
2347 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2348 struct radeon_winsys_cs *cs = rctx->cs;
2349 uint16_t mask = s->sample_mask;
2350
2351 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2352 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2353 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2354 }
2355
2356 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2357 {
2358 struct radeon_winsys_cs *cs = rctx->cs;
2359 struct r600_cso_state *state = (struct r600_cso_state*)a;
2360 struct r600_resource *shader = (struct r600_resource*)state->cso;
2361
2362 r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2363 r600_resource_va(rctx->context.screen, &shader->b.b) >> 8);
2364 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2365 r600_write_value(cs, r600_context_bo_reloc(rctx, shader, RADEON_USAGE_READ));
2366 }
2367
2368 void evergreen_init_state_functions(struct r600_context *rctx)
2369 {
2370 unsigned id = 4;
2371
2372 /* !!!
2373 * To avoid GPU lockup registers must be emited in a specific order
2374 * (no kidding ...). The order below is important and have been
2375 * partialy infered from analyzing fglrx command stream.
2376 *
2377 * Don't reorder atom without carefully checking the effect (GPU lockup
2378 * or piglit regression).
2379 * !!!
2380 */
2381
2382 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
2383 /* shader const */
2384 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2385 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
2386 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2387 /* shader program */
2388 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2389 /* sampler */
2390 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
2391 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
2392 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
2393 /* resources */
2394 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2395 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2396 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2397 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
2398 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2399
2400 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2401 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2402
2403 if (rctx->chip_class == EVERGREEN) {
2404 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2405 } else {
2406 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2407 }
2408 rctx->sample_mask.sample_mask = ~0;
2409
2410 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2411 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2412 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2413 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
2414 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2415 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
2416 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
2417 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2418 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
2419 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2420 r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
2421 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2422 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2423 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
2424
2425 rctx->context.create_blend_state = evergreen_create_blend_state;
2426 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2427 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2428 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2429 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2430 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2431 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2432 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2433 evergreen_init_compute_state_functions(rctx);
2434 }
2435
2436 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2437 {
2438 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2439
2440 r600_init_command_buffer(cb, 256);
2441
2442 /* This must be first. */
2443 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2444 r600_store_value(cb, 0x80000000);
2445 r600_store_value(cb, 0x80000000);
2446
2447 /* We're setting config registers here. */
2448 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2449 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2450
2451 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2452 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2453 /* always set the temp clauses */
2454 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2455
2456 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2457 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2458 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2459
2460 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2461
2462 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2463
2464 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2465 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2466 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2467 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2468 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2469 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2470 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2471 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2472 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2473 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2474 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2475 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2476 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2477 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2478
2479 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2480 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2481 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2482
2483 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2484 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2485 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2486
2487 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2488
2489 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2490
2491 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2492 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2493 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2494
2495 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2496 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2497 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2498
2499 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2500 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2501 r600_store_value(cb, 0);
2502 r600_store_value(cb, 0);
2503 r600_store_value(cb, 0);
2504 r600_store_value(cb, 0);
2505 r600_store_value(cb, 0);
2506 r600_store_value(cb, 0);
2507 r600_store_value(cb, 0);
2508 r600_store_value(cb, 0);
2509 r600_store_value(cb, 0);
2510 r600_store_value(cb, 0);
2511 r600_store_value(cb, 0);
2512 r600_store_value(cb, 0);
2513 r600_store_value(cb, 0);
2514 r600_store_value(cb, 0);
2515 r600_store_value(cb, 0);
2516 r600_store_value(cb, 0);
2517 r600_store_value(cb, 0);
2518 r600_store_value(cb, 0);
2519 r600_store_value(cb, 0);
2520 r600_store_value(cb, 0);
2521 r600_store_value(cb, 0);
2522 r600_store_value(cb, 0);
2523 r600_store_value(cb, 0);
2524 r600_store_value(cb, 0);
2525 r600_store_value(cb, 0);
2526 r600_store_value(cb, 0);
2527 r600_store_value(cb, 0);
2528 r600_store_value(cb, 0);
2529 r600_store_value(cb, 0);
2530 r600_store_value(cb, 0);
2531 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2532 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2533 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2534
2535 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2536
2537 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2538 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2539 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2540
2541 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2542
2543 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2544 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2545 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2546 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2547
2548 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2549 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2550
2551 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2552 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2553 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2554
2555 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2556 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2557 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2558
2559 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2560 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2561 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2562 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2563 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2564
2565 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2566 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2567 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2568
2569 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2570 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2571 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2572
2573 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2574 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2575 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2576
2577 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2578 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2579 if (rctx->screen->has_streamout) {
2580 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2581 }
2582
2583 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2584 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2585 }
2586
2587 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2588 enum chip_class ctx_chip_class,
2589 enum radeon_family ctx_family,
2590 int ctx_drm_minor)
2591 {
2592 int ps_prio;
2593 int vs_prio;
2594 int gs_prio;
2595 int es_prio;
2596
2597 int hs_prio;
2598 int cs_prio;
2599 int ls_prio;
2600
2601 int num_ps_gprs;
2602 int num_vs_gprs;
2603 int num_gs_gprs;
2604 int num_es_gprs;
2605 int num_hs_gprs;
2606 int num_ls_gprs;
2607 int num_temp_gprs;
2608
2609 unsigned tmp;
2610
2611 ps_prio = 0;
2612 vs_prio = 1;
2613 gs_prio = 2;
2614 es_prio = 3;
2615 hs_prio = 0;
2616 ls_prio = 0;
2617 cs_prio = 0;
2618
2619 switch (ctx_family) {
2620 case CHIP_CEDAR:
2621 default:
2622 num_ps_gprs = 93;
2623 num_vs_gprs = 46;
2624 num_temp_gprs = 4;
2625 num_gs_gprs = 31;
2626 num_es_gprs = 31;
2627 num_hs_gprs = 23;
2628 num_ls_gprs = 23;
2629 break;
2630 case CHIP_REDWOOD:
2631 num_ps_gprs = 93;
2632 num_vs_gprs = 46;
2633 num_temp_gprs = 4;
2634 num_gs_gprs = 31;
2635 num_es_gprs = 31;
2636 num_hs_gprs = 23;
2637 num_ls_gprs = 23;
2638 break;
2639 case CHIP_JUNIPER:
2640 num_ps_gprs = 93;
2641 num_vs_gprs = 46;
2642 num_temp_gprs = 4;
2643 num_gs_gprs = 31;
2644 num_es_gprs = 31;
2645 num_hs_gprs = 23;
2646 num_ls_gprs = 23;
2647 break;
2648 case CHIP_CYPRESS:
2649 case CHIP_HEMLOCK:
2650 num_ps_gprs = 93;
2651 num_vs_gprs = 46;
2652 num_temp_gprs = 4;
2653 num_gs_gprs = 31;
2654 num_es_gprs = 31;
2655 num_hs_gprs = 23;
2656 num_ls_gprs = 23;
2657 break;
2658 case CHIP_PALM:
2659 num_ps_gprs = 93;
2660 num_vs_gprs = 46;
2661 num_temp_gprs = 4;
2662 num_gs_gprs = 31;
2663 num_es_gprs = 31;
2664 num_hs_gprs = 23;
2665 num_ls_gprs = 23;
2666 break;
2667 case CHIP_SUMO:
2668 num_ps_gprs = 93;
2669 num_vs_gprs = 46;
2670 num_temp_gprs = 4;
2671 num_gs_gprs = 31;
2672 num_es_gprs = 31;
2673 num_hs_gprs = 23;
2674 num_ls_gprs = 23;
2675 break;
2676 case CHIP_SUMO2:
2677 num_ps_gprs = 93;
2678 num_vs_gprs = 46;
2679 num_temp_gprs = 4;
2680 num_gs_gprs = 31;
2681 num_es_gprs = 31;
2682 num_hs_gprs = 23;
2683 num_ls_gprs = 23;
2684 break;
2685 case CHIP_BARTS:
2686 num_ps_gprs = 93;
2687 num_vs_gprs = 46;
2688 num_temp_gprs = 4;
2689 num_gs_gprs = 31;
2690 num_es_gprs = 31;
2691 num_hs_gprs = 23;
2692 num_ls_gprs = 23;
2693 break;
2694 case CHIP_TURKS:
2695 num_ps_gprs = 93;
2696 num_vs_gprs = 46;
2697 num_temp_gprs = 4;
2698 num_gs_gprs = 31;
2699 num_es_gprs = 31;
2700 num_hs_gprs = 23;
2701 num_ls_gprs = 23;
2702 break;
2703 case CHIP_CAICOS:
2704 num_ps_gprs = 93;
2705 num_vs_gprs = 46;
2706 num_temp_gprs = 4;
2707 num_gs_gprs = 31;
2708 num_es_gprs = 31;
2709 num_hs_gprs = 23;
2710 num_ls_gprs = 23;
2711 break;
2712 }
2713
2714 tmp = 0;
2715 switch (ctx_family) {
2716 case CHIP_CEDAR:
2717 case CHIP_PALM:
2718 case CHIP_SUMO:
2719 case CHIP_SUMO2:
2720 case CHIP_CAICOS:
2721 break;
2722 default:
2723 tmp |= S_008C00_VC_ENABLE(1);
2724 break;
2725 }
2726 tmp |= S_008C00_EXPORT_SRC_C(1);
2727 tmp |= S_008C00_CS_PRIO(cs_prio);
2728 tmp |= S_008C00_LS_PRIO(ls_prio);
2729 tmp |= S_008C00_HS_PRIO(hs_prio);
2730 tmp |= S_008C00_PS_PRIO(ps_prio);
2731 tmp |= S_008C00_VS_PRIO(vs_prio);
2732 tmp |= S_008C00_GS_PRIO(gs_prio);
2733 tmp |= S_008C00_ES_PRIO(es_prio);
2734
2735 /* enable dynamic GPR resource management */
2736 if (ctx_drm_minor >= 7) {
2737 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2738 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2739 /* always set temp clauses */
2740 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2741 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2742 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2743 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2744 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2745 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2746 S_028838_PS_GPRS(0x1e) |
2747 S_028838_VS_GPRS(0x1e) |
2748 S_028838_GS_GPRS(0x1e) |
2749 S_028838_ES_GPRS(0x1e) |
2750 S_028838_HS_GPRS(0x1e) |
2751 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2752 } else {
2753 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2754 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2755
2756 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2757 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2758 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2759 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2760
2761 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2762 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2763 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2764
2765 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2766 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2767 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2768 }
2769
2770 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2771 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2772
2773 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2774
2775 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2776 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2777 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2778
2779 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2780
2781 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2782 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2783 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2784
2785 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2786 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2787 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2788 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2789
2790 /* The cs checker requires this register to be set. */
2791 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2792
2793 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2794 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2795
2796 /* to avoid GPU doing any preloading of constant from random address */
2797 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2798 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2799 r600_store_value(cb, 0);
2800 r600_store_value(cb, 0);
2801 r600_store_value(cb, 0);
2802 r600_store_value(cb, 0);
2803 r600_store_value(cb, 0);
2804 r600_store_value(cb, 0);
2805 r600_store_value(cb, 0);
2806 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2807 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2808 r600_store_value(cb, 0);
2809 r600_store_value(cb, 0);
2810 r600_store_value(cb, 0);
2811 r600_store_value(cb, 0);
2812 r600_store_value(cb, 0);
2813 r600_store_value(cb, 0);
2814 r600_store_value(cb, 0);
2815
2816 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2817
2818 return;
2819 }
2820
2821 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2822 {
2823 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2824 int num_ps_threads;
2825 int num_vs_threads;
2826 int num_gs_threads;
2827 int num_es_threads;
2828 int num_hs_threads;
2829 int num_ls_threads;
2830
2831 int num_ps_stack_entries;
2832 int num_vs_stack_entries;
2833 int num_gs_stack_entries;
2834 int num_es_stack_entries;
2835 int num_hs_stack_entries;
2836 int num_ls_stack_entries;
2837 enum radeon_family family;
2838 unsigned tmp;
2839
2840 if (rctx->chip_class == CAYMAN) {
2841 cayman_init_atom_start_cs(rctx);
2842 return;
2843 }
2844
2845 r600_init_command_buffer(cb, 256);
2846
2847 /* This must be first. */
2848 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2849 r600_store_value(cb, 0x80000000);
2850 r600_store_value(cb, 0x80000000);
2851
2852 /* We're setting config registers here. */
2853 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2854 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2855
2856 evergreen_init_common_regs(cb, rctx->chip_class
2857 , rctx->family, rctx->screen->info.drm_minor);
2858
2859 family = rctx->family;
2860 switch (family) {
2861 case CHIP_CEDAR:
2862 default:
2863 num_ps_threads = 96;
2864 num_vs_threads = 16;
2865 num_gs_threads = 16;
2866 num_es_threads = 16;
2867 num_hs_threads = 16;
2868 num_ls_threads = 16;
2869 num_ps_stack_entries = 42;
2870 num_vs_stack_entries = 42;
2871 num_gs_stack_entries = 42;
2872 num_es_stack_entries = 42;
2873 num_hs_stack_entries = 42;
2874 num_ls_stack_entries = 42;
2875 break;
2876 case CHIP_REDWOOD:
2877 num_ps_threads = 128;
2878 num_vs_threads = 20;
2879 num_gs_threads = 20;
2880 num_es_threads = 20;
2881 num_hs_threads = 20;
2882 num_ls_threads = 20;
2883 num_ps_stack_entries = 42;
2884 num_vs_stack_entries = 42;
2885 num_gs_stack_entries = 42;
2886 num_es_stack_entries = 42;
2887 num_hs_stack_entries = 42;
2888 num_ls_stack_entries = 42;
2889 break;
2890 case CHIP_JUNIPER:
2891 num_ps_threads = 128;
2892 num_vs_threads = 20;
2893 num_gs_threads = 20;
2894 num_es_threads = 20;
2895 num_hs_threads = 20;
2896 num_ls_threads = 20;
2897 num_ps_stack_entries = 85;
2898 num_vs_stack_entries = 85;
2899 num_gs_stack_entries = 85;
2900 num_es_stack_entries = 85;
2901 num_hs_stack_entries = 85;
2902 num_ls_stack_entries = 85;
2903 break;
2904 case CHIP_CYPRESS:
2905 case CHIP_HEMLOCK:
2906 num_ps_threads = 128;
2907 num_vs_threads = 20;
2908 num_gs_threads = 20;
2909 num_es_threads = 20;
2910 num_hs_threads = 20;
2911 num_ls_threads = 20;
2912 num_ps_stack_entries = 85;
2913 num_vs_stack_entries = 85;
2914 num_gs_stack_entries = 85;
2915 num_es_stack_entries = 85;
2916 num_hs_stack_entries = 85;
2917 num_ls_stack_entries = 85;
2918 break;
2919 case CHIP_PALM:
2920 num_ps_threads = 96;
2921 num_vs_threads = 16;
2922 num_gs_threads = 16;
2923 num_es_threads = 16;
2924 num_hs_threads = 16;
2925 num_ls_threads = 16;
2926 num_ps_stack_entries = 42;
2927 num_vs_stack_entries = 42;
2928 num_gs_stack_entries = 42;
2929 num_es_stack_entries = 42;
2930 num_hs_stack_entries = 42;
2931 num_ls_stack_entries = 42;
2932 break;
2933 case CHIP_SUMO:
2934 num_ps_threads = 96;
2935 num_vs_threads = 25;
2936 num_gs_threads = 25;
2937 num_es_threads = 25;
2938 num_hs_threads = 25;
2939 num_ls_threads = 25;
2940 num_ps_stack_entries = 42;
2941 num_vs_stack_entries = 42;
2942 num_gs_stack_entries = 42;
2943 num_es_stack_entries = 42;
2944 num_hs_stack_entries = 42;
2945 num_ls_stack_entries = 42;
2946 break;
2947 case CHIP_SUMO2:
2948 num_ps_threads = 96;
2949 num_vs_threads = 25;
2950 num_gs_threads = 25;
2951 num_es_threads = 25;
2952 num_hs_threads = 25;
2953 num_ls_threads = 25;
2954 num_ps_stack_entries = 85;
2955 num_vs_stack_entries = 85;
2956 num_gs_stack_entries = 85;
2957 num_es_stack_entries = 85;
2958 num_hs_stack_entries = 85;
2959 num_ls_stack_entries = 85;
2960 break;
2961 case CHIP_BARTS:
2962 num_ps_threads = 128;
2963 num_vs_threads = 20;
2964 num_gs_threads = 20;
2965 num_es_threads = 20;
2966 num_hs_threads = 20;
2967 num_ls_threads = 20;
2968 num_ps_stack_entries = 85;
2969 num_vs_stack_entries = 85;
2970 num_gs_stack_entries = 85;
2971 num_es_stack_entries = 85;
2972 num_hs_stack_entries = 85;
2973 num_ls_stack_entries = 85;
2974 break;
2975 case CHIP_TURKS:
2976 num_ps_threads = 128;
2977 num_vs_threads = 20;
2978 num_gs_threads = 20;
2979 num_es_threads = 20;
2980 num_hs_threads = 20;
2981 num_ls_threads = 20;
2982 num_ps_stack_entries = 42;
2983 num_vs_stack_entries = 42;
2984 num_gs_stack_entries = 42;
2985 num_es_stack_entries = 42;
2986 num_hs_stack_entries = 42;
2987 num_ls_stack_entries = 42;
2988 break;
2989 case CHIP_CAICOS:
2990 num_ps_threads = 128;
2991 num_vs_threads = 10;
2992 num_gs_threads = 10;
2993 num_es_threads = 10;
2994 num_hs_threads = 10;
2995 num_ls_threads = 10;
2996 num_ps_stack_entries = 42;
2997 num_vs_stack_entries = 42;
2998 num_gs_stack_entries = 42;
2999 num_es_stack_entries = 42;
3000 num_hs_stack_entries = 42;
3001 num_ls_stack_entries = 42;
3002 break;
3003 }
3004
3005 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3006 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3007 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3008 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3009
3010 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3011 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3012
3013 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3014 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3015 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3016
3017 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3018 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3019 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3020
3021 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3022 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3023 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3024
3025 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3026 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3027 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3028
3029 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3030 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3031
3032 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3033 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3034 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3035 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3036 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3037 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3038 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3039
3040 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3041 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3042 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3043 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3044 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3045
3046 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3047 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3048 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3049 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3050 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3051 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3052 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3053 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3054 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3055 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3056 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3057 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3058 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3059 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3060
3061 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
3062 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
3063 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3064
3065 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3066
3067 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
3068 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
3069 r600_store_value(cb, 0);
3070 r600_store_value(cb, 0);
3071 r600_store_value(cb, 0);
3072 r600_store_value(cb, 0);
3073 r600_store_value(cb, 0);
3074 r600_store_value(cb, 0);
3075 r600_store_value(cb, 0);
3076 r600_store_value(cb, 0);
3077 r600_store_value(cb, 0);
3078 r600_store_value(cb, 0);
3079 r600_store_value(cb, 0);
3080 r600_store_value(cb, 0);
3081 r600_store_value(cb, 0);
3082 r600_store_value(cb, 0);
3083 r600_store_value(cb, 0);
3084 r600_store_value(cb, 0);
3085 r600_store_value(cb, 0);
3086 r600_store_value(cb, 0);
3087 r600_store_value(cb, 0);
3088 r600_store_value(cb, 0);
3089 r600_store_value(cb, 0);
3090 r600_store_value(cb, 0);
3091 r600_store_value(cb, 0);
3092 r600_store_value(cb, 0);
3093 r600_store_value(cb, 0);
3094 r600_store_value(cb, 0);
3095 r600_store_value(cb, 0);
3096 r600_store_value(cb, 0);
3097 r600_store_value(cb, 0);
3098 r600_store_value(cb, 0);
3099 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
3100 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3101 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3102
3103 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3104
3105 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
3106 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
3107 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
3108
3109 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3110 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3111
3112 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3113 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3114 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3115
3116 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3117 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3118 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3119 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3120
3121 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
3122 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3123 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3124 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3125 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3126
3127 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3128 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3129 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3130
3131 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3132 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3133 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3134
3135 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3136
3137 if (rctx->screen->has_streamout) {
3138 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3139 }
3140
3141 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3142 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3143 }
3144
3145 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3146 {
3147 struct r600_context *rctx = (struct r600_context *)ctx;
3148 struct r600_pipe_state *rstate = &shader->rstate;
3149 struct r600_shader *rshader = &shader->shader;
3150 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
3151 int pos_index = -1, face_index = -1;
3152 int ninterp = 0;
3153 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3154 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
3155 unsigned z_export = 0, stencil_export = 0;
3156 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3157
3158 rstate->nregs = 0;
3159
3160 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3161 for (i = 0; i < rshader->ninput; i++) {
3162 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3163 POSITION goes via GPRs from the SC so isn't counted */
3164 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3165 pos_index = i;
3166 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3167 face_index = i;
3168 else {
3169 ninterp++;
3170 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3171 have_linear = TRUE;
3172 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3173 have_perspective = TRUE;
3174 if (rshader->input[i].centroid)
3175 have_centroid = TRUE;
3176 }
3177
3178 sid = rshader->input[i].spi_sid;
3179
3180 if (sid) {
3181
3182 tmp = S_028644_SEMANTIC(sid);
3183
3184 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3185 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3186 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3187 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3188 tmp |= S_028644_FLAT_SHADE(1);
3189 }
3190
3191 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3192 (sprite_coord_enable & (1 << rshader->input[i].sid))) {
3193 tmp |= S_028644_PT_SPRITE_TEX(1);
3194 }
3195
3196 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3197 tmp);
3198
3199 idx++;
3200 }
3201 }
3202
3203 for (i = 0; i < rshader->noutput; i++) {
3204 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3205 z_export = 1;
3206 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3207 stencil_export = 1;
3208 }
3209 if (rshader->uses_kill)
3210 db_shader_control |= S_02880C_KILL_ENABLE(1);
3211
3212 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3213 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3214
3215 exports_ps = 0;
3216 for (i = 0; i < rshader->noutput; i++) {
3217 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3218 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3219 exports_ps |= 1;
3220 }
3221
3222 num_cout = rshader->nr_ps_color_exports;
3223
3224 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3225 if (!exports_ps) {
3226 /* always at least export 1 component per pixel */
3227 exports_ps = 2;
3228 }
3229 shader->nr_ps_color_outputs = num_cout;
3230 if (ninterp == 0) {
3231 ninterp = 1;
3232 have_perspective = TRUE;
3233 }
3234
3235 if (!have_perspective && !have_linear)
3236 have_perspective = TRUE;
3237
3238 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3239 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3240 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3241 spi_input_z = 0;
3242 if (pos_index != -1) {
3243 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3244 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3245 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3246 spi_input_z |= 1;
3247 }
3248
3249 spi_ps_in_control_1 = 0;
3250 if (face_index != -1) {
3251 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3252 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3253 }
3254
3255 spi_baryc_cntl = 0;
3256 if (have_perspective)
3257 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3258 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3259 if (have_linear)
3260 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3261 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3262
3263 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3264 spi_ps_in_control_0);
3265 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3266 spi_ps_in_control_1);
3267 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3268 0);
3269 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3270 r600_pipe_state_add_reg(rstate,
3271 R_0286E0_SPI_BARYC_CNTL,
3272 spi_baryc_cntl);
3273
3274 r600_pipe_state_add_reg_bo(rstate,
3275 R_028840_SQ_PGM_START_PS,
3276 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3277 shader->bo, RADEON_USAGE_READ);
3278 r600_pipe_state_add_reg(rstate,
3279 R_028844_SQ_PGM_RESOURCES_PS,
3280 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3281 S_028844_PRIME_CACHE_ON_DRAW(1) |
3282 S_028844_STACK_SIZE(rshader->bc.nstack));
3283 r600_pipe_state_add_reg(rstate,
3284 R_02884C_SQ_PGM_EXPORTS_PS,
3285 exports_ps);
3286
3287 shader->db_shader_control = db_shader_control;
3288 shader->ps_depth_export = z_export | stencil_export;
3289
3290 shader->sprite_coord_enable = sprite_coord_enable;
3291 if (rctx->rasterizer)
3292 shader->flatshade = rctx->rasterizer->flatshade;
3293 }
3294
3295 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3296 {
3297 struct r600_context *rctx = (struct r600_context *)ctx;
3298 struct r600_pipe_state *rstate = &shader->rstate;
3299 struct r600_shader *rshader = &shader->shader;
3300 unsigned spi_vs_out_id[10] = {};
3301 unsigned i, tmp, nparams = 0;
3302
3303 /* clear previous register */
3304 rstate->nregs = 0;
3305
3306 for (i = 0; i < rshader->noutput; i++) {
3307 if (rshader->output[i].spi_sid) {
3308 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3309 spi_vs_out_id[nparams / 4] |= tmp;
3310 nparams++;
3311 }
3312 }
3313
3314 for (i = 0; i < 10; i++) {
3315 r600_pipe_state_add_reg(rstate,
3316 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3317 spi_vs_out_id[i]);
3318 }
3319
3320 /* Certain attributes (position, psize, etc.) don't count as params.
3321 * VS is required to export at least one param and r600_shader_from_tgsi()
3322 * takes care of adding a dummy export.
3323 */
3324 if (nparams < 1)
3325 nparams = 1;
3326
3327 r600_pipe_state_add_reg(rstate,
3328 R_0286C4_SPI_VS_OUT_CONFIG,
3329 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3330 r600_pipe_state_add_reg(rstate,
3331 R_028860_SQ_PGM_RESOURCES_VS,
3332 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3333 S_028860_STACK_SIZE(rshader->bc.nstack));
3334 r600_pipe_state_add_reg_bo(rstate,
3335 R_02885C_SQ_PGM_START_VS,
3336 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3337 shader->bo, RADEON_USAGE_READ);
3338
3339 shader->pa_cl_vs_out_cntl =
3340 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3341 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3342 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3343 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3344 }
3345
3346 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3347 {
3348 struct pipe_blend_state blend;
3349
3350 memset(&blend, 0, sizeof(blend));
3351 blend.independent_blend_enable = true;
3352 blend.rt[0].colormask = 0xf;
3353 return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3354 }
3355
3356 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3357 {
3358 struct pipe_blend_state blend;
3359
3360 memset(&blend, 0, sizeof(blend));
3361 blend.independent_blend_enable = true;
3362 blend.rt[0].colormask = 0xf;
3363 return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3364 }
3365
3366 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3367 {
3368 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3369
3370 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3371 }
3372
3373 void evergreen_update_db_shader_control(struct r600_context * rctx)
3374 {
3375 bool dual_export = rctx->framebuffer.export_16bpc &&
3376 !rctx->ps_shader->current->ps_depth_export;
3377
3378 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3379 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3380 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3381 V_02880C_EXPORT_DB_FULL) |
3382 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3383
3384 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3385 rctx->db_misc_state.db_shader_control = db_shader_control;
3386 rctx->db_misc_state.atom.dirty = true;
3387 }
3388 }