projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: make some scissor regs invariant on evergreen
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <errno.h>
26 #include "pipe/p_defines.h"
27 #include "pipe/p_state.h"
28 #include "pipe/p_context.h"
29 #include "tgsi/tgsi_scan.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_util.h"
32 #include "util/u_blitter.h"
33 #include "util/u_double_list.h"
34 #include "util/u_transfer.h"
35 #include "util/u_surface.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "pipebuffer/pb_buffer.h"
41 #include "r600.h"
42 #include "evergreend.h"
43 #include "r600_resource.h"
44 #include "r600_shader.h"
45 #include "r600_pipe.h"
46 #include "r600_formats.h"
47
48 static uint32_t eg_num_banks(uint32_t nbanks)
49 {
50 switch (nbanks) {
51 case 2:
52 return 0;
53 case 4:
54 return 1;
55 case 8:
56 default:
57 return 2;
58 case 16:
59 return 3;
60 }
61 }
62
63
64 static unsigned eg_tile_split(unsigned tile_split)
65 {
66 switch (tile_split) {
67 case 64: tile_split = 0; break;
68 case 128: tile_split = 1; break;
69 case 256: tile_split = 2; break;
70 case 512: tile_split = 3; break;
71 default:
72 case 1024: tile_split = 4; break;
73 case 2048: tile_split = 5; break;
74 case 4096: tile_split = 6; break;
75 }
76 return tile_split;
77 }
78
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
80 {
81 switch (macro_tile_aspect) {
82 default:
83 case 1: macro_tile_aspect = 0; break;
84 case 2: macro_tile_aspect = 1; break;
85 case 4: macro_tile_aspect = 2; break;
86 case 8: macro_tile_aspect = 3; break;
87 }
88 return macro_tile_aspect;
89 }
90
91 static unsigned eg_bank_wh(unsigned bankwh)
92 {
93 switch (bankwh) {
94 default:
95 case 1: bankwh = 0; break;
96 case 2: bankwh = 1; break;
97 case 4: bankwh = 2; break;
98 case 8: bankwh = 3; break;
99 }
100 return bankwh;
101 }
102
103 static uint32_t r600_translate_blend_function(int blend_func)
104 {
105 switch (blend_func) {
106 case PIPE_BLEND_ADD:
107 return V_028780_COMB_DST_PLUS_SRC;
108 case PIPE_BLEND_SUBTRACT:
109 return V_028780_COMB_SRC_MINUS_DST;
110 case PIPE_BLEND_REVERSE_SUBTRACT:
111 return V_028780_COMB_DST_MINUS_SRC;
112 case PIPE_BLEND_MIN:
113 return V_028780_COMB_MIN_DST_SRC;
114 case PIPE_BLEND_MAX:
115 return V_028780_COMB_MAX_DST_SRC;
116 default:
117 R600_ERR("Unknown blend function %d\n", blend_func);
118 assert(0);
119 break;
120 }
121 return 0;
122 }
123
124 static uint32_t r600_translate_blend_factor(int blend_fact)
125 {
126 switch (blend_fact) {
127 case PIPE_BLENDFACTOR_ONE:
128 return V_028780_BLEND_ONE;
129 case PIPE_BLENDFACTOR_SRC_COLOR:
130 return V_028780_BLEND_SRC_COLOR;
131 case PIPE_BLENDFACTOR_SRC_ALPHA:
132 return V_028780_BLEND_SRC_ALPHA;
133 case PIPE_BLENDFACTOR_DST_ALPHA:
134 return V_028780_BLEND_DST_ALPHA;
135 case PIPE_BLENDFACTOR_DST_COLOR:
136 return V_028780_BLEND_DST_COLOR;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE;
139 case PIPE_BLENDFACTOR_CONST_COLOR:
140 return V_028780_BLEND_CONST_COLOR;
141 case PIPE_BLENDFACTOR_CONST_ALPHA:
142 return V_028780_BLEND_CONST_ALPHA;
143 case PIPE_BLENDFACTOR_ZERO:
144 return V_028780_BLEND_ZERO;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
157 case PIPE_BLENDFACTOR_SRC1_COLOR:
158 return V_028780_BLEND_SRC1_COLOR;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA:
160 return V_028780_BLEND_SRC1_ALPHA;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
162 return V_028780_BLEND_INV_SRC1_COLOR;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
164 return V_028780_BLEND_INV_SRC1_ALPHA;
165 default:
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
167 assert(0);
168 break;
169 }
170 return 0;
171 }
172
173 static unsigned r600_tex_dim(unsigned dim)
174 {
175 switch (dim) {
176 default:
177 case PIPE_TEXTURE_1D:
178 return V_030000_SQ_TEX_DIM_1D;
179 case PIPE_TEXTURE_1D_ARRAY:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY;
181 case PIPE_TEXTURE_2D:
182 case PIPE_TEXTURE_RECT:
183 return V_030000_SQ_TEX_DIM_2D;
184 case PIPE_TEXTURE_2D_ARRAY:
185 return V_030000_SQ_TEX_DIM_2D_ARRAY;
186 case PIPE_TEXTURE_3D:
187 return V_030000_SQ_TEX_DIM_3D;
188 case PIPE_TEXTURE_CUBE:
189 return V_030000_SQ_TEX_DIM_CUBEMAP;
190 }
191 }
192
193 static uint32_t r600_translate_dbformat(enum pipe_format format)
194 {
195 switch (format) {
196 case PIPE_FORMAT_Z16_UNORM:
197 return V_028040_Z_16;
198 case PIPE_FORMAT_Z24X8_UNORM:
199 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
200 return V_028040_Z_24;
201 case PIPE_FORMAT_Z32_FLOAT:
202 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
203 return V_028040_Z_32_FLOAT;
204 default:
205 return ~0U;
206 }
207 }
208
209 static uint32_t r600_translate_colorswap(enum pipe_format format)
210 {
211 switch (format) {
212 /* 8-bit buffers. */
213 case PIPE_FORMAT_L4A4_UNORM:
214 case PIPE_FORMAT_A4R4_UNORM:
215 return V_028C70_SWAP_ALT;
216
217 case PIPE_FORMAT_A8_UNORM:
218 case PIPE_FORMAT_A8_UINT:
219 case PIPE_FORMAT_A8_SINT:
220 case PIPE_FORMAT_R4A4_UNORM:
221 return V_028C70_SWAP_ALT_REV;
222 case PIPE_FORMAT_I8_UNORM:
223 case PIPE_FORMAT_L8_UNORM:
224 case PIPE_FORMAT_I8_UINT:
225 case PIPE_FORMAT_I8_SINT:
226 case PIPE_FORMAT_L8_UINT:
227 case PIPE_FORMAT_L8_SINT:
228 case PIPE_FORMAT_L8_SRGB:
229 case PIPE_FORMAT_R8_UNORM:
230 case PIPE_FORMAT_R8_SNORM:
231 case PIPE_FORMAT_R8_UINT:
232 case PIPE_FORMAT_R8_SINT:
233 return V_028C70_SWAP_STD;
234
235 /* 16-bit buffers. */
236 case PIPE_FORMAT_B5G6R5_UNORM:
237 return V_028C70_SWAP_STD_REV;
238
239 case PIPE_FORMAT_B5G5R5A1_UNORM:
240 case PIPE_FORMAT_B5G5R5X1_UNORM:
241 return V_028C70_SWAP_ALT;
242
243 case PIPE_FORMAT_B4G4R4A4_UNORM:
244 case PIPE_FORMAT_B4G4R4X4_UNORM:
245 return V_028C70_SWAP_ALT;
246
247 case PIPE_FORMAT_Z16_UNORM:
248 return V_028C70_SWAP_STD;
249
250 case PIPE_FORMAT_L8A8_UNORM:
251 case PIPE_FORMAT_L8A8_UINT:
252 case PIPE_FORMAT_L8A8_SINT:
253 case PIPE_FORMAT_L8A8_SRGB:
254 return V_028C70_SWAP_ALT;
255 case PIPE_FORMAT_R8G8_UNORM:
256 case PIPE_FORMAT_R8G8_UINT:
257 case PIPE_FORMAT_R8G8_SINT:
258 return V_028C70_SWAP_STD;
259
260 case PIPE_FORMAT_R16_UNORM:
261 case PIPE_FORMAT_R16_UINT:
262 case PIPE_FORMAT_R16_SINT:
263 case PIPE_FORMAT_R16_FLOAT:
264 return V_028C70_SWAP_STD;
265
266 /* 32-bit buffers. */
267 case PIPE_FORMAT_A8B8G8R8_SRGB:
268 return V_028C70_SWAP_STD_REV;
269 case PIPE_FORMAT_B8G8R8A8_SRGB:
270 return V_028C70_SWAP_ALT;
271
272 case PIPE_FORMAT_B8G8R8A8_UNORM:
273 case PIPE_FORMAT_B8G8R8X8_UNORM:
274 return V_028C70_SWAP_ALT;
275
276 case PIPE_FORMAT_A8R8G8B8_UNORM:
277 case PIPE_FORMAT_X8R8G8B8_UNORM:
278 return V_028C70_SWAP_ALT_REV;
279 case PIPE_FORMAT_R8G8B8A8_SNORM:
280 case PIPE_FORMAT_R8G8B8A8_UNORM:
281 case PIPE_FORMAT_R8G8B8A8_SSCALED:
282 case PIPE_FORMAT_R8G8B8A8_USCALED:
283 case PIPE_FORMAT_R8G8B8A8_SINT:
284 case PIPE_FORMAT_R8G8B8A8_UINT:
285 case PIPE_FORMAT_R8G8B8X8_UNORM:
286 return V_028C70_SWAP_STD;
287
288 case PIPE_FORMAT_A8B8G8R8_UNORM:
289 case PIPE_FORMAT_X8B8G8R8_UNORM:
290 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
291 return V_028C70_SWAP_STD_REV;
292
293 case PIPE_FORMAT_Z24X8_UNORM:
294 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
295 return V_028C70_SWAP_STD;
296
297 case PIPE_FORMAT_X8Z24_UNORM:
298 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
299 return V_028C70_SWAP_STD;
300
301 case PIPE_FORMAT_R10G10B10A2_UNORM:
302 case PIPE_FORMAT_R10G10B10X2_SNORM:
303 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
304 return V_028C70_SWAP_STD;
305
306 case PIPE_FORMAT_B10G10R10A2_UNORM:
307 case PIPE_FORMAT_B10G10R10A2_UINT:
308 return V_028C70_SWAP_ALT;
309
310 case PIPE_FORMAT_R11G11B10_FLOAT:
311 case PIPE_FORMAT_R32_FLOAT:
312 case PIPE_FORMAT_R32_UINT:
313 case PIPE_FORMAT_R32_SINT:
314 case PIPE_FORMAT_Z32_FLOAT:
315 case PIPE_FORMAT_R16G16_FLOAT:
316 case PIPE_FORMAT_R16G16_UNORM:
317 case PIPE_FORMAT_R16G16_UINT:
318 case PIPE_FORMAT_R16G16_SINT:
319 return V_028C70_SWAP_STD;
320
321 /* 64-bit buffers. */
322 case PIPE_FORMAT_R32G32_FLOAT:
323 case PIPE_FORMAT_R32G32_UINT:
324 case PIPE_FORMAT_R32G32_SINT:
325 case PIPE_FORMAT_R16G16B16A16_UNORM:
326 case PIPE_FORMAT_R16G16B16A16_SNORM:
327 case PIPE_FORMAT_R16G16B16A16_USCALED:
328 case PIPE_FORMAT_R16G16B16A16_SSCALED:
329 case PIPE_FORMAT_R16G16B16A16_UINT:
330 case PIPE_FORMAT_R16G16B16A16_SINT:
331 case PIPE_FORMAT_R16G16B16A16_FLOAT:
332 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
333
334 /* 128-bit buffers. */
335 case PIPE_FORMAT_R32G32B32A32_FLOAT:
336 case PIPE_FORMAT_R32G32B32A32_SNORM:
337 case PIPE_FORMAT_R32G32B32A32_UNORM:
338 case PIPE_FORMAT_R32G32B32A32_SSCALED:
339 case PIPE_FORMAT_R32G32B32A32_USCALED:
340 case PIPE_FORMAT_R32G32B32A32_SINT:
341 case PIPE_FORMAT_R32G32B32A32_UINT:
342 return V_028C70_SWAP_STD;
343 default:
344 R600_ERR("unsupported colorswap format %d\n", format);
345 return ~0U;
346 }
347 return ~0U;
348 }
349
350 static uint32_t r600_translate_colorformat(enum pipe_format format)
351 {
352 switch (format) {
353 /* 8-bit buffers. */
354 case PIPE_FORMAT_A8_UNORM:
355 case PIPE_FORMAT_A8_UINT:
356 case PIPE_FORMAT_A8_SINT:
357 case PIPE_FORMAT_I8_UNORM:
358 case PIPE_FORMAT_I8_UINT:
359 case PIPE_FORMAT_I8_SINT:
360 case PIPE_FORMAT_L8_UNORM:
361 case PIPE_FORMAT_L8_UINT:
362 case PIPE_FORMAT_L8_SINT:
363 case PIPE_FORMAT_L8_SRGB:
364 case PIPE_FORMAT_R8_UNORM:
365 case PIPE_FORMAT_R8_SNORM:
366 case PIPE_FORMAT_R8_UINT:
367 case PIPE_FORMAT_R8_SINT:
368 return V_028C70_COLOR_8;
369
370 /* 16-bit buffers. */
371 case PIPE_FORMAT_B5G6R5_UNORM:
372 return V_028C70_COLOR_5_6_5;
373
374 case PIPE_FORMAT_B5G5R5A1_UNORM:
375 case PIPE_FORMAT_B5G5R5X1_UNORM:
376 return V_028C70_COLOR_1_5_5_5;
377
378 case PIPE_FORMAT_B4G4R4A4_UNORM:
379 case PIPE_FORMAT_B4G4R4X4_UNORM:
380 return V_028C70_COLOR_4_4_4_4;
381
382 case PIPE_FORMAT_Z16_UNORM:
383 return V_028C70_COLOR_16;
384
385 case PIPE_FORMAT_L8A8_UNORM:
386 case PIPE_FORMAT_L8A8_UINT:
387 case PIPE_FORMAT_L8A8_SINT:
388 case PIPE_FORMAT_L8A8_SRGB:
389 case PIPE_FORMAT_R8G8_UNORM:
390 case PIPE_FORMAT_R8G8_UINT:
391 case PIPE_FORMAT_R8G8_SINT:
392 return V_028C70_COLOR_8_8;
393
394 case PIPE_FORMAT_R16_UNORM:
395 case PIPE_FORMAT_R16_UINT:
396 case PIPE_FORMAT_R16_SINT:
397 return V_028C70_COLOR_16;
398
399 case PIPE_FORMAT_R16_FLOAT:
400 return V_028C70_COLOR_16_FLOAT;
401
402 /* 32-bit buffers. */
403 case PIPE_FORMAT_A8B8G8R8_SRGB:
404 case PIPE_FORMAT_A8B8G8R8_UNORM:
405 case PIPE_FORMAT_A8R8G8B8_UNORM:
406 case PIPE_FORMAT_B8G8R8A8_SRGB:
407 case PIPE_FORMAT_B8G8R8A8_UNORM:
408 case PIPE_FORMAT_B8G8R8X8_UNORM:
409 case PIPE_FORMAT_R8G8B8A8_SNORM:
410 case PIPE_FORMAT_R8G8B8A8_UNORM:
411 case PIPE_FORMAT_R8G8B8X8_UNORM:
412 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
413 case PIPE_FORMAT_X8B8G8R8_UNORM:
414 case PIPE_FORMAT_X8R8G8B8_UNORM:
415 case PIPE_FORMAT_R8G8B8_UNORM:
416 case PIPE_FORMAT_R8G8B8A8_SSCALED:
417 case PIPE_FORMAT_R8G8B8A8_USCALED:
418 case PIPE_FORMAT_R8G8B8A8_SINT:
419 case PIPE_FORMAT_R8G8B8A8_UINT:
420 return V_028C70_COLOR_8_8_8_8;
421
422 case PIPE_FORMAT_R10G10B10A2_UNORM:
423 case PIPE_FORMAT_R10G10B10X2_SNORM:
424 case PIPE_FORMAT_B10G10R10A2_UNORM:
425 case PIPE_FORMAT_B10G10R10A2_UINT:
426 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
427 return V_028C70_COLOR_2_10_10_10;
428
429 case PIPE_FORMAT_Z24X8_UNORM:
430 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
431 return V_028C70_COLOR_8_24;
432
433 case PIPE_FORMAT_X8Z24_UNORM:
434 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
435 return V_028C70_COLOR_24_8;
436
437 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
438 return V_028C70_COLOR_X24_8_32_FLOAT;
439
440 case PIPE_FORMAT_R32_UINT:
441 case PIPE_FORMAT_R32_SINT:
442 return V_028C70_COLOR_32;
443
444 case PIPE_FORMAT_R32_FLOAT:
445 case PIPE_FORMAT_Z32_FLOAT:
446 return V_028C70_COLOR_32_FLOAT;
447
448 case PIPE_FORMAT_R16G16_FLOAT:
449 return V_028C70_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_SSCALED:
452 case PIPE_FORMAT_R16G16_UNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 return V_028C70_COLOR_16_16;
456
457 case PIPE_FORMAT_R11G11B10_FLOAT:
458 return V_028C70_COLOR_10_11_11_FLOAT;
459
460 /* 64-bit buffers. */
461 case PIPE_FORMAT_R16G16B16_USCALED:
462 case PIPE_FORMAT_R16G16B16_SSCALED:
463 case PIPE_FORMAT_R16G16B16A16_UINT:
464 case PIPE_FORMAT_R16G16B16A16_SINT:
465 case PIPE_FORMAT_R16G16B16A16_USCALED:
466 case PIPE_FORMAT_R16G16B16A16_SSCALED:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_028C70_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16_FLOAT:
472 case PIPE_FORMAT_R16G16B16A16_FLOAT:
473 return V_028C70_COLOR_16_16_16_16_FLOAT;
474
475 case PIPE_FORMAT_R32G32_FLOAT:
476 return V_028C70_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_USCALED:
479 case PIPE_FORMAT_R32G32_SSCALED:
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 return V_028C70_COLOR_32_32;
483
484 /* 96-bit buffers. */
485 case PIPE_FORMAT_R32G32B32_FLOAT:
486 return V_028C70_COLOR_32_32_32_FLOAT;
487
488 /* 128-bit buffers. */
489 case PIPE_FORMAT_R32G32B32A32_SNORM:
490 case PIPE_FORMAT_R32G32B32A32_UNORM:
491 case PIPE_FORMAT_R32G32B32A32_SSCALED:
492 case PIPE_FORMAT_R32G32B32A32_USCALED:
493 case PIPE_FORMAT_R32G32B32A32_SINT:
494 case PIPE_FORMAT_R32G32B32A32_UINT:
495 return V_028C70_COLOR_32_32_32_32;
496 case PIPE_FORMAT_R32G32B32A32_FLOAT:
497 return V_028C70_COLOR_32_32_32_32_FLOAT;
498
499 /* YUV buffers. */
500 case PIPE_FORMAT_UYVY:
501 case PIPE_FORMAT_YUYV:
502 default:
503 return ~0U; /* Unsupported. */
504 }
505 }
506
507 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
508 {
509 if (R600_BIG_ENDIAN) {
510 switch(colorformat) {
511
512 /* 8-bit buffers. */
513 case V_028C70_COLOR_8:
514 return ENDIAN_NONE;
515
516 /* 16-bit buffers. */
517 case V_028C70_COLOR_5_6_5:
518 case V_028C70_COLOR_1_5_5_5:
519 case V_028C70_COLOR_4_4_4_4:
520 case V_028C70_COLOR_16:
521 case V_028C70_COLOR_8_8:
522 return ENDIAN_8IN16;
523
524 /* 32-bit buffers. */
525 case V_028C70_COLOR_8_8_8_8:
526 case V_028C70_COLOR_2_10_10_10:
527 case V_028C70_COLOR_8_24:
528 case V_028C70_COLOR_24_8:
529 case V_028C70_COLOR_32_FLOAT:
530 case V_028C70_COLOR_16_16_FLOAT:
531 case V_028C70_COLOR_16_16:
532 return ENDIAN_8IN32;
533
534 /* 64-bit buffers. */
535 case V_028C70_COLOR_16_16_16_16:
536 case V_028C70_COLOR_16_16_16_16_FLOAT:
537 return ENDIAN_8IN16;
538
539 case V_028C70_COLOR_32_32_FLOAT:
540 case V_028C70_COLOR_32_32:
541 case V_028C70_COLOR_X24_8_32_FLOAT:
542 return ENDIAN_8IN32;
543
544 /* 96-bit buffers. */
545 case V_028C70_COLOR_32_32_32_FLOAT:
546 /* 128-bit buffers. */
547 case V_028C70_COLOR_32_32_32_32_FLOAT:
548 case V_028C70_COLOR_32_32_32_32:
549 return ENDIAN_8IN32;
550 default:
551 return ENDIAN_NONE; /* Unsupported. */
552 }
553 } else {
554 return ENDIAN_NONE;
555 }
556 }
557
558 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
559 {
560 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
561 }
562
563 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
564 {
565 return r600_translate_colorformat(format) != ~0U &&
566 r600_translate_colorswap(format) != ~0U;
567 }
568
569 static bool r600_is_zs_format_supported(enum pipe_format format)
570 {
571 return r600_translate_dbformat(format) != ~0U;
572 }
573
574 boolean evergreen_is_format_supported(struct pipe_screen *screen,
575 enum pipe_format format,
576 enum pipe_texture_target target,
577 unsigned sample_count,
578 unsigned usage)
579 {
580 unsigned retval = 0;
581
582 if (target >= PIPE_MAX_TEXTURE_TYPES) {
583 R600_ERR("r600: unsupported texture type %d\n", target);
584 return FALSE;
585 }
586
587 if (!util_format_is_supported(format, usage))
588 return FALSE;
589
590 /* Multisample */
591 if (sample_count > 1)
592 return FALSE;
593
594 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
595 r600_is_sampler_format_supported(screen, format)) {
596 retval |= PIPE_BIND_SAMPLER_VIEW;
597 }
598
599 if ((usage & (PIPE_BIND_RENDER_TARGET |
600 PIPE_BIND_DISPLAY_TARGET |
601 PIPE_BIND_SCANOUT |
602 PIPE_BIND_SHARED)) &&
603 r600_is_colorbuffer_format_supported(format)) {
604 retval |= usage &
605 (PIPE_BIND_RENDER_TARGET |
606 PIPE_BIND_DISPLAY_TARGET |
607 PIPE_BIND_SCANOUT |
608 PIPE_BIND_SHARED);
609 }
610
611 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
612 r600_is_zs_format_supported(format)) {
613 retval |= PIPE_BIND_DEPTH_STENCIL;
614 }
615
616 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
617 r600_is_vertex_format_supported(format)) {
618 retval |= PIPE_BIND_VERTEX_BUFFER;
619 }
620
621 if (usage & PIPE_BIND_TRANSFER_READ)
622 retval |= PIPE_BIND_TRANSFER_READ;
623 if (usage & PIPE_BIND_TRANSFER_WRITE)
624 retval |= PIPE_BIND_TRANSFER_WRITE;
625
626 return retval == usage;
627 }
628
629 static void *evergreen_create_blend_state(struct pipe_context *ctx,
630 const struct pipe_blend_state *state)
631 {
632 struct r600_context *rctx = (struct r600_context *)ctx;
633 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
634 struct r600_pipe_state *rstate;
635 uint32_t color_control, target_mask;
636 /* XXX there is more then 8 framebuffer */
637 unsigned blend_cntl[8];
638
639 if (blend == NULL) {
640 return NULL;
641 }
642
643 rstate = &blend->rstate;
644
645 rstate->id = R600_PIPE_STATE_BLEND;
646
647 target_mask = 0;
648 color_control = S_028808_MODE(1);
649 if (state->logicop_enable) {
650 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
651 } else {
652 color_control |= (0xcc << 16);
653 }
654 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
655 if (state->independent_blend_enable) {
656 for (int i = 0; i < 8; i++) {
657 target_mask |= (state->rt[i].colormask << (4 * i));
658 }
659 } else {
660 for (int i = 0; i < 8; i++) {
661 target_mask |= (state->rt[0].colormask << (4 * i));
662 }
663 }
664 blend->cb_target_mask = target_mask;
665
666 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
667 color_control, NULL, 0);
668
669 for (int i = 0; i < 8; i++) {
670 /* state->rt entries > 0 only written if independent blending */
671 const int j = state->independent_blend_enable ? i : 0;
672
673 unsigned eqRGB = state->rt[j].rgb_func;
674 unsigned srcRGB = state->rt[j].rgb_src_factor;
675 unsigned dstRGB = state->rt[j].rgb_dst_factor;
676 unsigned eqA = state->rt[j].alpha_func;
677 unsigned srcA = state->rt[j].alpha_src_factor;
678 unsigned dstA = state->rt[j].alpha_dst_factor;
679
680 blend_cntl[i] = 0;
681 if (!state->rt[j].blend_enable)
682 continue;
683
684 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
685 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
686 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
687 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
688
689 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
690 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
691 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
692 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
693 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
694 }
695 }
696 for (int i = 0; i < 8; i++) {
697 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
698 }
699
700 return rstate;
701 }
702
703 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
704 const struct pipe_depth_stencil_alpha_state *state)
705 {
706 struct r600_context *rctx = (struct r600_context *)ctx;
707 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
708 unsigned db_depth_control, alpha_test_control, alpha_ref;
709 unsigned db_render_control;
710 struct r600_pipe_state *rstate;
711
712 if (dsa == NULL) {
713 return NULL;
714 }
715
716 dsa->valuemask[0] = state->stencil[0].valuemask;
717 dsa->valuemask[1] = state->stencil[1].valuemask;
718 dsa->writemask[0] = state->stencil[0].writemask;
719 dsa->writemask[1] = state->stencil[1].writemask;
720
721 rstate = &dsa->rstate;
722
723 rstate->id = R600_PIPE_STATE_DSA;
724 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
725 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
726 S_028800_ZFUNC(state->depth.func);
727
728 /* stencil */
729 if (state->stencil[0].enabled) {
730 db_depth_control |= S_028800_STENCIL_ENABLE(1);
731 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
732 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
733 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
734 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
735
736 if (state->stencil[1].enabled) {
737 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
738 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
739 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
740 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
741 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
742 }
743 }
744
745 /* alpha */
746 alpha_test_control = 0;
747 alpha_ref = 0;
748 if (state->alpha.enabled) {
749 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
750 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
751 alpha_ref = fui(state->alpha.ref_value);
752 }
753 dsa->alpha_ref = alpha_ref;
754
755 /* misc */
756 db_render_control = 0;
757 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
758 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
759 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
760 return rstate;
761 }
762
763 static void *evergreen_create_rs_state(struct pipe_context *ctx,
764 const struct pipe_rasterizer_state *state)
765 {
766 struct r600_context *rctx = (struct r600_context *)ctx;
767 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
768 struct r600_pipe_state *rstate;
769 unsigned tmp;
770 unsigned prov_vtx = 1, polygon_dual_mode;
771 float psize_min, psize_max;
772
773 if (rs == NULL) {
774 return NULL;
775 }
776
777 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
778 state->fill_back != PIPE_POLYGON_MODE_FILL);
779
780 if (state->flatshade_first)
781 prov_vtx = 0;
782
783 rstate = &rs->rstate;
784 rs->flatshade = state->flatshade;
785 rs->sprite_coord_enable = state->sprite_coord_enable;
786 rs->two_side = state->light_twoside;
787 rs->clip_plane_enable = state->clip_plane_enable;
788 rs->pa_sc_line_stipple = state->line_stipple_enable ?
789 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
790 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
791 rs->pa_cl_clip_cntl =
792 S_028810_PS_UCP_MODE(3) |
793 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
794 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
795 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
796
797 /* offset */
798 rs->offset_units = state->offset_units;
799 rs->offset_scale = state->offset_scale * 12.0f;
800
801 rstate->id = R600_PIPE_STATE_RASTERIZER;
802 tmp = S_0286D4_FLAT_SHADE_ENA(1);
803 if (state->sprite_coord_enable) {
804 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
805 S_0286D4_PNT_SPRITE_OVRD_X(2) |
806 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
807 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
808 S_0286D4_PNT_SPRITE_OVRD_W(1);
809 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
810 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
811 }
812 }
813 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
814
815 /* point size 12.4 fixed point */
816 tmp = (unsigned)(state->point_size * 8.0);
817 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
818
819 if (state->point_size_per_vertex) {
820 psize_min = util_get_min_point_size(state);
821 psize_max = 8192;
822 } else {
823 /* Force the point size to be as if the vertex output was disabled. */
824 psize_min = state->point_size;
825 psize_max = state->point_size;
826 }
827 /* Divide by two, because 0.5 = 1 pixel. */
828 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
829 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
830 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
831 NULL, 0);
832
833 tmp = (unsigned)state->line_width * 8;
834 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
835 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
836 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
837 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
838 NULL, 0);
839
840 if (rctx->chip_class == CAYMAN) {
841 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
842 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
843 NULL, 0);
844 } else {
845 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
846 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
847 NULL, 0);
848 }
849 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
850 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
851 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
852 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
853 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
854 S_028814_FACE(!state->front_ccw) |
855 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
856 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
857 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
858 S_028814_POLY_MODE(polygon_dual_mode) |
859 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
860 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
861 NULL, 0);
862 return rstate;
863 }
864
865 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
866 const struct pipe_sampler_state *state)
867 {
868 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
869 union util_color uc;
870 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
871
872 if (rstate == NULL) {
873 return NULL;
874 }
875
876 rstate->id = R600_PIPE_STATE_SAMPLER;
877 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
878 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
879 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
880 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
881 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
882 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
883 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
884 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
885 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
886 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
887 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
888 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
889 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
890 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
891 NULL, 0);
892 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
893 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
894 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
895 S_03C008_TYPE(1),
896 NULL, 0);
897
898 if (uc.ui) {
899 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
900 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
901 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
902 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
903 }
904 return rstate;
905 }
906
907 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
908 struct pipe_resource *texture,
909 const struct pipe_sampler_view *state)
910 {
911 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
912 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
913 struct r600_pipe_resource_state *rstate;
914 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
915 unsigned format, endian;
916 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
917 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
918 unsigned height, depth, width;
919 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
920
921 if (view == NULL)
922 return NULL;
923 rstate = &view->state;
924
925 /* initialize base object */
926 view->base = *state;
927 view->base.texture = NULL;
928 pipe_reference(NULL, &texture->reference);
929 view->base.texture = texture;
930 view->base.reference.count = 1;
931 view->base.context = ctx;
932
933 swizzle[0] = state->swizzle_r;
934 swizzle[1] = state->swizzle_g;
935 swizzle[2] = state->swizzle_b;
936 swizzle[3] = state->swizzle_a;
937
938 format = r600_translate_texformat(ctx->screen, state->format,
939 swizzle,
940 &word4, &yuv_format);
941 if (format == ~0) {
942 format = 0;
943 }
944
945 if (tmp->is_depth && !tmp->is_flushing_texture) {
946 r600_texture_depth_flush(ctx, texture, TRUE);
947 tmp = tmp->flushed_depth_texture;
948 }
949
950 endian = r600_colorformat_endian_swap(format);
951
952 if (!rscreen->use_surface_alloc) {
953 height = texture->height0;
954 depth = texture->depth0;
955 width = texture->width0;
956 pitch = align(tmp->pitch_in_blocks[0] *
957 util_format_get_blockwidth(state->format), 8);
958 array_mode = tmp->array_mode[0];
959 tile_type = tmp->tile_type;
960 tile_split = 0;
961 macro_aspect = 0;
962 bankw = 0;
963 bankh = 0;
964 } else {
965 width = tmp->surface.level[0].npix_x;
966 height = tmp->surface.level[0].npix_y;
967 depth = tmp->surface.level[0].npix_z;
968 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
969 tile_type = tmp->tile_type;
970
971 switch (tmp->surface.level[0].mode) {
972 case RADEON_SURF_MODE_LINEAR_ALIGNED:
973 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
974 break;
975 case RADEON_SURF_MODE_2D:
976 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
977 break;
978 case RADEON_SURF_MODE_1D:
979 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
980 break;
981 case RADEON_SURF_MODE_LINEAR:
982 default:
983 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
984 break;
985 }
986 tile_split = tmp->surface.tile_split;
987 macro_aspect = tmp->surface.mtilea;
988 bankw = tmp->surface.bankw;
989 bankh = tmp->surface.bankh;
990 tile_split = eg_tile_split(tile_split);
991 macro_aspect = eg_macro_tile_aspect(macro_aspect);
992 bankw = eg_bank_wh(bankw);
993 bankh = eg_bank_wh(bankh);
994 }
995 /* 128 bit formats require tile type = 1 */
996 if (rscreen->chip_class == CAYMAN) {
997 if (util_format_get_blocksize(state->format) >= 16)
998 tile_type = 1;
999 }
1000 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1001
1002 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1003 height = 1;
1004 depth = texture->array_size;
1005 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1006 depth = texture->array_size;
1007 }
1008
1009 rstate->bo[0] = &tmp->resource;
1010 rstate->bo[1] = &tmp->resource;
1011 rstate->bo_usage[0] = RADEON_USAGE_READ;
1012 rstate->bo_usage[1] = RADEON_USAGE_READ;
1013
1014 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1015 S_030000_PITCH((pitch / 8) - 1) |
1016 S_030000_TEX_WIDTH(width - 1));
1017 if (rscreen->chip_class == CAYMAN)
1018 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1019 else
1020 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1021 rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1022 S_030004_TEX_DEPTH(depth - 1) |
1023 S_030004_ARRAY_MODE(array_mode));
1024 rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1025 if (state->u.tex.last_level) {
1026 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1027 } else {
1028 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1029 }
1030 rstate->val[4] = (word4 |
1031 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1032 S_030010_ENDIAN_SWAP(endian) |
1033 S_030010_BASE_LEVEL(state->u.tex.first_level));
1034 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1035 S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1036 S_030014_LAST_ARRAY(state->u.tex.last_layer));
1037 /* aniso max 16 samples */
1038 rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1039 (S_030018_TILE_SPLIT(tile_split));
1040 rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1041 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1042 S_03001C_BANK_WIDTH(bankw) |
1043 S_03001C_BANK_HEIGHT(bankh) |
1044 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1045 S_03001C_NUM_BANKS(nbanks);
1046
1047 return &view->base;
1048 }
1049
1050 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1051 struct pipe_sampler_view **views)
1052 {
1053 struct r600_context *rctx = (struct r600_context *)ctx;
1054 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1055
1056 for (int i = 0; i < count; i++) {
1057 if (resource[i]) {
1058 r600_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1059 i + R600_MAX_CONST_BUFFERS);
1060 }
1061 }
1062 }
1063
1064 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1065 struct pipe_sampler_view **views)
1066 {
1067 struct r600_context *rctx = (struct r600_context *)ctx;
1068 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1069 int i;
1070 int has_depth = 0;
1071
1072 for (i = 0; i < count; i++) {
1073 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1074 if (resource[i]) {
1075 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1076 has_depth = 1;
1077 r600_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1078 i + R600_MAX_CONST_BUFFERS);
1079 } else
1080 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1081 i + R600_MAX_CONST_BUFFERS);
1082
1083 pipe_sampler_view_reference(
1084 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1085 views[i]);
1086 } else {
1087 if (resource[i]) {
1088 if (((struct r600_resource_texture *)resource[i]->base.texture)->is_depth)
1089 has_depth = 1;
1090 }
1091 }
1092 }
1093 for (i = count; i < NUM_TEX_UNITS; i++) {
1094 if (rctx->ps_samplers.views[i]) {
1095 r600_context_pipe_state_set_ps_resource(rctx, NULL,
1096 i + R600_MAX_CONST_BUFFERS);
1097 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1098 }
1099 }
1100 rctx->have_depth_texture = has_depth;
1101 rctx->ps_samplers.n_views = count;
1102 }
1103
1104 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1105 {
1106 struct r600_context *rctx = (struct r600_context *)ctx;
1107 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1108
1109 if (count)
1110 r600_inval_texture_cache(rctx);
1111
1112 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1113 rctx->ps_samplers.n_samplers = count;
1114
1115 for (int i = 0; i < count; i++) {
1116 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1117 }
1118 }
1119
1120 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1121 {
1122 struct r600_context *rctx = (struct r600_context *)ctx;
1123 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1124
1125 if (count)
1126 r600_inval_texture_cache(rctx);
1127
1128 for (int i = 0; i < count; i++) {
1129 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1130 }
1131 }
1132
1133 static void evergreen_set_clip_state(struct pipe_context *ctx,
1134 const struct pipe_clip_state *state)
1135 {
1136 struct r600_context *rctx = (struct r600_context *)ctx;
1137 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1138 struct pipe_resource *cbuf;
1139
1140 if (rstate == NULL)
1141 return;
1142
1143 rctx->clip = *state;
1144 rstate->id = R600_PIPE_STATE_CLIP;
1145 for (int i = 0; i < 6; i++) {
1146 r600_pipe_state_add_reg(rstate,
1147 R_0285BC_PA_CL_UCP0_X + i * 16,
1148 fui(state->ucp[i][0]), NULL, 0);
1149 r600_pipe_state_add_reg(rstate,
1150 R_0285C0_PA_CL_UCP0_Y + i * 16,
1151 fui(state->ucp[i][1]) , NULL, 0);
1152 r600_pipe_state_add_reg(rstate,
1153 R_0285C4_PA_CL_UCP0_Z + i * 16,
1154 fui(state->ucp[i][2]), NULL, 0);
1155 r600_pipe_state_add_reg(rstate,
1156 R_0285C8_PA_CL_UCP0_W + i * 16,
1157 fui(state->ucp[i][3]), NULL, 0);
1158 }
1159
1160 free(rctx->states[R600_PIPE_STATE_CLIP]);
1161 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1162 r600_context_pipe_state_set(rctx, rstate);
1163
1164 cbuf = pipe_user_buffer_create(ctx->screen,
1165 state->ucp,
1166 4*4*8, /* 8*4 floats */
1167 PIPE_BIND_CONSTANT_BUFFER);
1168 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1169 pipe_resource_reference(&cbuf, NULL);
1170 }
1171
1172 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1173 const struct pipe_poly_stipple *state)
1174 {
1175 }
1176
1177 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1178 {
1179 }
1180
1181 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1182 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1183 uint32_t *tl, uint32_t *br)
1184 {
1185 /* EG hw workaround */
1186 if (br_x == 0)
1187 tl_x = 1;
1188 if (br_y == 0)
1189 tl_y = 1;
1190
1191 /* cayman hw workaround */
1192 if (rctx->chip_class == CAYMAN) {
1193 if (br_x == 1 && br_y == 1)
1194 br_x = 2;
1195 }
1196
1197 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1198 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1199 }
1200
1201 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1202 const struct pipe_scissor_state *state)
1203 {
1204 struct r600_context *rctx = (struct r600_context *)ctx;
1205 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1206 uint32_t tl, br;
1207
1208 if (rstate == NULL)
1209 return;
1210
1211 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1212
1213 rstate->id = R600_PIPE_STATE_SCISSOR;
1214 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, NULL, 0);
1215 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, NULL, 0);
1216
1217 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1218 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1219 r600_context_pipe_state_set(rctx, rstate);
1220 }
1221
1222 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1223 const struct pipe_viewport_state *state)
1224 {
1225 struct r600_context *rctx = (struct r600_context *)ctx;
1226 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1227
1228 if (rstate == NULL)
1229 return;
1230
1231 rctx->viewport = *state;
1232 rstate->id = R600_PIPE_STATE_VIEWPORT;
1233 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1234 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1235 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1236 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1237 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1238 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1239
1240 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1241 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1242 r600_context_pipe_state_set(rctx, rstate);
1243 }
1244
1245 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1246 const struct pipe_framebuffer_state *state, int cb)
1247 {
1248 struct r600_screen *rscreen = rctx->screen;
1249 struct r600_resource_texture *rtex;
1250 struct r600_surface *surf;
1251 unsigned level = state->cbufs[cb]->u.tex.level;
1252 unsigned pitch, slice;
1253 unsigned color_info, color_attrib;
1254 unsigned format, swap, ntype, endian;
1255 uint64_t offset;
1256 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1257 const struct util_format_description *desc;
1258 int i;
1259 unsigned blend_clamp = 0, blend_bypass = 0;
1260
1261 surf = (struct r600_surface *)state->cbufs[cb];
1262 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1263
1264 if (rtex->is_depth)
1265 rctx->have_depth_fb = TRUE;
1266
1267 if (rtex->is_depth && !rtex->is_flushing_texture) {
1268 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1269 rtex = rtex->flushed_depth_texture;
1270 }
1271
1272 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1273 if (!rscreen->use_surface_alloc) {
1274 offset = r600_texture_get_offset(rtex,
1275 level, state->cbufs[cb]->u.tex.first_layer);
1276 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1277 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1278 if (slice) {
1279 slice = slice - 1;
1280 }
1281 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1282 tile_split = 0;
1283 macro_aspect = 0;
1284 bankw = 0;
1285 bankh = 0;
1286 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1287 tile_type = rtex->tile_type;
1288 } else {
1289 /* workaround for linear buffers */
1290 tile_type = 1;
1291 }
1292 } else {
1293 offset = rtex->surface.level[level].offset;
1294 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1295 offset += rtex->surface.level[level].slice_size *
1296 state->cbufs[cb]->u.tex.first_layer;
1297 }
1298 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1299 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1300 if (slice) {
1301 slice = slice - 1;
1302 }
1303 color_info = 0;
1304 switch (rtex->surface.level[level].mode) {
1305 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1306 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1307 tile_type = 1;
1308 break;
1309 case RADEON_SURF_MODE_1D:
1310 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1311 tile_type = rtex->tile_type;
1312 break;
1313 case RADEON_SURF_MODE_2D:
1314 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1315 tile_type = rtex->tile_type;
1316 break;
1317 case RADEON_SURF_MODE_LINEAR:
1318 default:
1319 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1320 tile_type = 1;
1321 break;
1322 }
1323 tile_split = rtex->surface.tile_split;
1324 macro_aspect = rtex->surface.mtilea;
1325 bankw = rtex->surface.bankw;
1326 bankh = rtex->surface.bankh;
1327 tile_split = eg_tile_split(tile_split);
1328 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1329 bankw = eg_bank_wh(bankw);
1330 bankh = eg_bank_wh(bankh);
1331 }
1332 /* 128 bit formats require tile type = 1 */
1333 if (rscreen->chip_class == CAYMAN) {
1334 if (util_format_get_blocksize(surf->base.format) >= 16)
1335 tile_type = 1;
1336 }
1337 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1338 desc = util_format_description(surf->base.format);
1339 for (i = 0; i < 4; i++) {
1340 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1341 break;
1342 }
1343 }
1344
1345 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1346 S_028C74_NUM_BANKS(nbanks) |
1347 S_028C74_BANK_WIDTH(bankw) |
1348 S_028C74_BANK_HEIGHT(bankh) |
1349 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1350 S_028C74_NON_DISP_TILING_ORDER(tile_type);
1351
1352 ntype = V_028C70_NUMBER_UNORM;
1353 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1354 ntype = V_028C70_NUMBER_SRGB;
1355 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1356 if (desc->channel[i].normalized)
1357 ntype = V_028C70_NUMBER_SNORM;
1358 else if (desc->channel[i].pure_integer)
1359 ntype = V_028C70_NUMBER_SINT;
1360 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1361 if (desc->channel[i].normalized)
1362 ntype = V_028C70_NUMBER_UNORM;
1363 else if (desc->channel[i].pure_integer)
1364 ntype = V_028C70_NUMBER_UINT;
1365 }
1366
1367 format = r600_translate_colorformat(surf->base.format);
1368 swap = r600_translate_colorswap(surf->base.format);
1369 if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1370 endian = ENDIAN_NONE;
1371 } else {
1372 endian = r600_colorformat_endian_swap(format);
1373 }
1374
1375 /* blend clamp should be set for all NORM/SRGB types */
1376 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1377 ntype == V_028C70_NUMBER_SRGB)
1378 blend_clamp = 1;
1379
1380 /* set blend bypass according to docs if SINT/UINT or
1381 8/24 COLOR variants */
1382 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1383 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1384 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1385 blend_clamp = 0;
1386 blend_bypass = 1;
1387 }
1388
1389 color_info |= S_028C70_FORMAT(format) |
1390 S_028C70_COMP_SWAP(swap) |
1391 S_028C70_BLEND_CLAMP(blend_clamp) |
1392 S_028C70_BLEND_BYPASS(blend_bypass) |
1393 S_028C70_NUMBER_TYPE(ntype) |
1394 S_028C70_ENDIAN(endian);
1395
1396 /* EXPORT_NORM is an optimzation that can be enabled for better
1397 * performance in certain cases.
1398 * EXPORT_NORM can be enabled if:
1399 * - 11-bit or smaller UNORM/SNORM/SRGB
1400 * - 16-bit or smaller FLOAT
1401 */
1402 /* XXX: This should probably be the same for all CBs if we want
1403 * useful alpha tests. */
1404 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1405 ((desc->channel[i].size < 12 &&
1406 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1407 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1408 (desc->channel[i].size < 17 &&
1409 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1410 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1411 rctx->export_16bpc = true;
1412 } else {
1413 rctx->export_16bpc = false;
1414 }
1415 rctx->alpha_ref_dirty = true;
1416
1417
1418 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1419 offset >>= 8;
1420
1421 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1422 r600_pipe_state_add_reg(rstate,
1423 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1424 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1425 r600_pipe_state_add_reg(rstate,
1426 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1427 0x0, NULL, 0);
1428 r600_pipe_state_add_reg(rstate,
1429 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1430 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1431 r600_pipe_state_add_reg(rstate,
1432 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1433 S_028C64_PITCH_TILE_MAX(pitch),
1434 NULL, 0);
1435 r600_pipe_state_add_reg(rstate,
1436 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1437 S_028C68_SLICE_TILE_MAX(slice),
1438 NULL, 0);
1439 if (!rscreen->use_surface_alloc) {
1440 r600_pipe_state_add_reg(rstate,
1441 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1442 0x00000000, NULL, 0);
1443 } else {
1444 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1445 r600_pipe_state_add_reg(rstate,
1446 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1447 0x00000000, NULL, 0);
1448 } else {
1449 r600_pipe_state_add_reg(rstate,
1450 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1451 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1452 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1453 NULL, 0);
1454 }
1455 }
1456 r600_pipe_state_add_reg(rstate,
1457 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1458 color_attrib,
1459 &rtex->resource, RADEON_USAGE_READWRITE);
1460 }
1461
1462 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1463 const struct pipe_framebuffer_state *state)
1464 {
1465 struct r600_screen *rscreen = rctx->screen;
1466 struct r600_resource_texture *rtex;
1467 struct r600_surface *surf;
1468 uint64_t offset;
1469 unsigned level, first_layer, pitch, slice, format, array_mode;
1470 unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1471
1472 if (state->zsbuf == NULL)
1473 return;
1474
1475 surf = (struct r600_surface *)state->zsbuf;
1476 level = surf->base.u.tex.level;
1477 rtex = (struct r600_resource_texture*)surf->base.texture;
1478 first_layer = surf->base.u.tex.first_layer;
1479 format = r600_translate_dbformat(rtex->real_format);
1480
1481 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1482 /* XXX remove this once tiling is properly supported */
1483 if (!rscreen->use_surface_alloc) {
1484 /* XXX remove this once tiling is properly supported */
1485 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1486 V_028C70_ARRAY_1D_TILED_THIN1;
1487
1488 offset += r600_texture_get_offset(rtex, level, first_layer);
1489 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1490 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1491 if (slice) {
1492 slice = slice - 1;
1493 }
1494 tile_split = 0;
1495 macro_aspect = 0;
1496 bankw = 0;
1497 bankh = 0;
1498 } else {
1499 offset += rtex->surface.level[level].offset;
1500 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1501 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1502 if (slice) {
1503 slice = slice - 1;
1504 }
1505 switch (rtex->surface.level[level].mode) {
1506 case RADEON_SURF_MODE_2D:
1507 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1508 break;
1509 case RADEON_SURF_MODE_1D:
1510 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1511 case RADEON_SURF_MODE_LINEAR:
1512 default:
1513 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1514 break;
1515 }
1516 tile_split = rtex->surface.tile_split;
1517 macro_aspect = rtex->surface.mtilea;
1518 bankw = rtex->surface.bankw;
1519 bankh = rtex->surface.bankh;
1520 tile_split = eg_tile_split(tile_split);
1521 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1522 bankw = eg_bank_wh(bankw);
1523 bankh = eg_bank_wh(bankh);
1524 }
1525 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1526 offset >>= 8;
1527
1528 z_info = S_028040_ARRAY_MODE(array_mode) |
1529 S_028040_FORMAT(format) |
1530 S_028040_TILE_SPLIT(tile_split)|
1531 S_028040_NUM_BANKS(nbanks) |
1532 S_028040_BANK_WIDTH(bankw) |
1533 S_028040_BANK_HEIGHT(bankh) |
1534 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1535
1536 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1537 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1538 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1539 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1540 if (!rscreen->use_surface_alloc) {
1541 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1542 0x00000000, NULL, 0);
1543 } else {
1544 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1545 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1546 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1547 NULL, 0);
1548 }
1549
1550 if (rtex->stencil) {
1551 uint64_t stencil_offset =
1552 r600_texture_get_offset(rtex->stencil, level, first_layer);
1553 unsigned stile_split;
1554
1555 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1556 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1557 stencil_offset >>= 8;
1558
1559 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1560 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1561 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1562 stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1563 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1564 1 | S_028044_TILE_SPLIT(stile_split),
1565 &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1566 } else {
1567 if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1568 uint64_t stencil_offset = rtex->surface.stencil_offset;
1569 unsigned stile_split = rtex->surface.stencil_tile_split;
1570
1571 stile_split = eg_tile_split(stile_split);
1572 stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1573 stencil_offset += rtex->surface.level[level].offset / 4;
1574 stencil_offset >>= 8;
1575
1576 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1577 stencil_offset, &rtex->resource,
1578 RADEON_USAGE_READWRITE);
1579 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1580 stencil_offset, &rtex->resource,
1581 RADEON_USAGE_READWRITE);
1582 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1583 1 | S_028044_TILE_SPLIT(stile_split),
1584 &rtex->resource,
1585 RADEON_USAGE_READWRITE);
1586 } else {
1587 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1588 offset, &rtex->resource,
1589 RADEON_USAGE_READWRITE);
1590 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1591 offset, &rtex->resource,
1592 RADEON_USAGE_READWRITE);
1593 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1594 0, NULL, RADEON_USAGE_READWRITE);
1595 }
1596 }
1597
1598 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1599 &rtex->resource, RADEON_USAGE_READWRITE);
1600 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1601 S_028058_PITCH_TILE_MAX(pitch),
1602 NULL, 0);
1603 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1604 S_02805C_SLICE_TILE_MAX(slice),
1605 NULL, 0);
1606 }
1607
1608 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1609 const struct pipe_framebuffer_state *state)
1610 {
1611 struct r600_context *rctx = (struct r600_context *)ctx;
1612 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1613 uint32_t shader_mask, tl, br;
1614
1615 if (rstate == NULL)
1616 return;
1617
1618 r600_flush_framebuffer(rctx, false);
1619
1620 /* unreference old buffer and reference new one */
1621 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1622
1623 util_copy_framebuffer_state(&rctx->framebuffer, state);
1624
1625 /* build states */
1626 rctx->have_depth_fb = 0;
1627 rctx->nr_cbufs = state->nr_cbufs;
1628 for (int i = 0; i < state->nr_cbufs; i++) {
1629 evergreen_cb(rctx, rstate, state, i);
1630 }
1631 if (state->zsbuf) {
1632 evergreen_db(rctx, rstate, state);
1633 }
1634
1635 shader_mask = 0;
1636 for (int i = 0; i < state->nr_cbufs; i++) {
1637 shader_mask |= 0xf << (i * 4);
1638 }
1639
1640 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1641
1642 r600_pipe_state_add_reg(rstate,
1643 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1644 NULL, 0);
1645 r600_pipe_state_add_reg(rstate,
1646 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1647 NULL, 0);
1648 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1649 shader_mask, NULL, 0);
1650
1651 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1652 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1653 r600_context_pipe_state_set(rctx, rstate);
1654
1655 if (state->zsbuf) {
1656 evergreen_polygon_offset_update(rctx);
1657 }
1658 }
1659
1660 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1661 {
1662 struct radeon_winsys_cs *cs = rctx->cs;
1663 struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom;
1664 unsigned db_count_control = 0;
1665 unsigned db_render_override =
1666 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1667 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1668 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1669
1670 if (a->occlusion_query_enabled) {
1671 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1672 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1673 }
1674
1675 r600_write_context_reg(cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1676 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1677 }
1678
1679 void evergreen_init_state_functions(struct r600_context *rctx)
1680 {
1681 r600_init_atom(&rctx->atom_db_misc_state.atom, evergreen_emit_db_misc_state, 6, 0);
1682
1683 rctx->context.create_blend_state = evergreen_create_blend_state;
1684 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1685 rctx->context.create_fs_state = r600_create_shader_state;
1686 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1687 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1688 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1689 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1690 rctx->context.create_vs_state = r600_create_shader_state;
1691 rctx->context.bind_blend_state = r600_bind_blend_state;
1692 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1693 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1694 rctx->context.bind_fs_state = r600_bind_ps_shader;
1695 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1696 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1697 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1698 rctx->context.bind_vs_state = r600_bind_vs_shader;
1699 rctx->context.delete_blend_state = r600_delete_state;
1700 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1701 rctx->context.delete_fs_state = r600_delete_ps_shader;
1702 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1703 rctx->context.delete_sampler_state = r600_delete_state;
1704 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1705 rctx->context.delete_vs_state = r600_delete_vs_shader;
1706 rctx->context.set_blend_color = r600_set_blend_color;
1707 rctx->context.set_clip_state = evergreen_set_clip_state;
1708 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1709 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1710 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1711 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1712 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1713 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1714 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1715 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1716 rctx->context.set_index_buffer = r600_set_index_buffer;
1717 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1718 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1719 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1720 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1721 rctx->context.texture_barrier = r600_texture_barrier;
1722 rctx->context.create_stream_output_target = r600_create_so_target;
1723 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1724 rctx->context.set_stream_output_targets = r600_set_so_targets;
1725 }
1726
1727 static void cayman_init_atom_start_cs(struct r600_context *rctx)
1728 {
1729 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1730
1731 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1732
1733 /* This must be first. */
1734 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1735 r600_store_value(cb, 0x80000000);
1736 r600_store_value(cb, 0x80000000);
1737
1738 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1739 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1740 /* always set the temp clauses */
1741 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1742
1743 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1744 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1745 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1746
1747 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1748
1749 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1750
1751 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1752 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1753 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1754 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1755 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1756 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1757 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1758 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1759 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1760 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1761 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1762 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1763 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1764 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1765
1766 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1767 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1768 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1769
1770 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1771 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1772 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1773
1774 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1775
1776 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1777
1778 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1779 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1780 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1781
1782 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1783 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1784 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1785
1786 r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1787
1788 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1789 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1790 r600_store_value(cb, 0);
1791 r600_store_value(cb, 0);
1792 r600_store_value(cb, 0);
1793 r600_store_value(cb, 0);
1794 r600_store_value(cb, 0);
1795 r600_store_value(cb, 0);
1796 r600_store_value(cb, 0);
1797 r600_store_value(cb, 0);
1798 r600_store_value(cb, 0);
1799 r600_store_value(cb, 0);
1800 r600_store_value(cb, 0);
1801 r600_store_value(cb, 0);
1802 r600_store_value(cb, 0);
1803 r600_store_value(cb, 0);
1804 r600_store_value(cb, 0);
1805 r600_store_value(cb, 0);
1806 r600_store_value(cb, 0);
1807 r600_store_value(cb, 0);
1808 r600_store_value(cb, 0);
1809 r600_store_value(cb, 0);
1810 r600_store_value(cb, 0);
1811 r600_store_value(cb, 0);
1812 r600_store_value(cb, 0);
1813 r600_store_value(cb, 0);
1814 r600_store_value(cb, 0);
1815 r600_store_value(cb, 0);
1816 r600_store_value(cb, 0);
1817 r600_store_value(cb, 0);
1818 r600_store_value(cb, 0);
1819 r600_store_value(cb, 0);
1820 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1821 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1822 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1823
1824 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1825
1826 r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1827 r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1828 r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1829
1830 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1831 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1832 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1833
1834 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1835
1836 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
1837 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1838 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1839 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1840
1841 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
1842 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
1843
1844 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
1845 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
1846 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
1847
1848 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1849 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
1850 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
1851 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
1852
1853 r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1854 r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1855 r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1856
1857 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
1858 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
1859 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
1860 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
1861 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
1862
1863 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
1864 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
1865 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
1866
1867 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
1868 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
1869 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
1870
1871 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1872 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
1873 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
1874
1875 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
1876 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
1877 }
1878
1879 void evergreen_init_atom_start_cs(struct r600_context *rctx)
1880 {
1881 struct r600_command_buffer *cb = &rctx->atom_start_cs;
1882 int ps_prio;
1883 int vs_prio;
1884 int gs_prio;
1885 int es_prio;
1886 int hs_prio, cs_prio, ls_prio;
1887 int num_ps_gprs;
1888 int num_vs_gprs;
1889 int num_gs_gprs;
1890 int num_es_gprs;
1891 int num_hs_gprs;
1892 int num_ls_gprs;
1893 int num_temp_gprs;
1894 int num_ps_threads;
1895 int num_vs_threads;
1896 int num_gs_threads;
1897 int num_es_threads;
1898 int num_hs_threads;
1899 int num_ls_threads;
1900 int num_ps_stack_entries;
1901 int num_vs_stack_entries;
1902 int num_gs_stack_entries;
1903 int num_es_stack_entries;
1904 int num_hs_stack_entries;
1905 int num_ls_stack_entries;
1906 enum radeon_family family;
1907 unsigned tmp;
1908
1909 if (rctx->chip_class == CAYMAN) {
1910 cayman_init_atom_start_cs(rctx);
1911 return;
1912 }
1913
1914 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1915
1916 /* This must be first. */
1917 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1918 r600_store_value(cb, 0x80000000);
1919 r600_store_value(cb, 0x80000000);
1920
1921 family = rctx->family;
1922 ps_prio = 0;
1923 vs_prio = 1;
1924 gs_prio = 2;
1925 es_prio = 3;
1926 hs_prio = 0;
1927 ls_prio = 0;
1928 cs_prio = 0;
1929
1930 switch (family) {
1931 case CHIP_CEDAR:
1932 default:
1933 num_ps_gprs = 93;
1934 num_vs_gprs = 46;
1935 num_temp_gprs = 4;
1936 num_gs_gprs = 31;
1937 num_es_gprs = 31;
1938 num_hs_gprs = 23;
1939 num_ls_gprs = 23;
1940 num_ps_threads = 96;
1941 num_vs_threads = 16;
1942 num_gs_threads = 16;
1943 num_es_threads = 16;
1944 num_hs_threads = 16;
1945 num_ls_threads = 16;
1946 num_ps_stack_entries = 42;
1947 num_vs_stack_entries = 42;
1948 num_gs_stack_entries = 42;
1949 num_es_stack_entries = 42;
1950 num_hs_stack_entries = 42;
1951 num_ls_stack_entries = 42;
1952 break;
1953 case CHIP_REDWOOD:
1954 num_ps_gprs = 93;
1955 num_vs_gprs = 46;
1956 num_temp_gprs = 4;
1957 num_gs_gprs = 31;
1958 num_es_gprs = 31;
1959 num_hs_gprs = 23;
1960 num_ls_gprs = 23;
1961 num_ps_threads = 128;
1962 num_vs_threads = 20;
1963 num_gs_threads = 20;
1964 num_es_threads = 20;
1965 num_hs_threads = 20;
1966 num_ls_threads = 20;
1967 num_ps_stack_entries = 42;
1968 num_vs_stack_entries = 42;
1969 num_gs_stack_entries = 42;
1970 num_es_stack_entries = 42;
1971 num_hs_stack_entries = 42;
1972 num_ls_stack_entries = 42;
1973 break;
1974 case CHIP_JUNIPER:
1975 num_ps_gprs = 93;
1976 num_vs_gprs = 46;
1977 num_temp_gprs = 4;
1978 num_gs_gprs = 31;
1979 num_es_gprs = 31;
1980 num_hs_gprs = 23;
1981 num_ls_gprs = 23;
1982 num_ps_threads = 128;
1983 num_vs_threads = 20;
1984 num_gs_threads = 20;
1985 num_es_threads = 20;
1986 num_hs_threads = 20;
1987 num_ls_threads = 20;
1988 num_ps_stack_entries = 85;
1989 num_vs_stack_entries = 85;
1990 num_gs_stack_entries = 85;
1991 num_es_stack_entries = 85;
1992 num_hs_stack_entries = 85;
1993 num_ls_stack_entries = 85;
1994 break;
1995 case CHIP_CYPRESS:
1996 case CHIP_HEMLOCK:
1997 num_ps_gprs = 93;
1998 num_vs_gprs = 46;
1999 num_temp_gprs = 4;
2000 num_gs_gprs = 31;
2001 num_es_gprs = 31;
2002 num_hs_gprs = 23;
2003 num_ls_gprs = 23;
2004 num_ps_threads = 128;
2005 num_vs_threads = 20;
2006 num_gs_threads = 20;
2007 num_es_threads = 20;
2008 num_hs_threads = 20;
2009 num_ls_threads = 20;
2010 num_ps_stack_entries = 85;
2011 num_vs_stack_entries = 85;
2012 num_gs_stack_entries = 85;
2013 num_es_stack_entries = 85;
2014 num_hs_stack_entries = 85;
2015 num_ls_stack_entries = 85;
2016 break;
2017 case CHIP_PALM:
2018 num_ps_gprs = 93;
2019 num_vs_gprs = 46;
2020 num_temp_gprs = 4;
2021 num_gs_gprs = 31;
2022 num_es_gprs = 31;
2023 num_hs_gprs = 23;
2024 num_ls_gprs = 23;
2025 num_ps_threads = 96;
2026 num_vs_threads = 16;
2027 num_gs_threads = 16;
2028 num_es_threads = 16;
2029 num_hs_threads = 16;
2030 num_ls_threads = 16;
2031 num_ps_stack_entries = 42;
2032 num_vs_stack_entries = 42;
2033 num_gs_stack_entries = 42;
2034 num_es_stack_entries = 42;
2035 num_hs_stack_entries = 42;
2036 num_ls_stack_entries = 42;
2037 break;
2038 case CHIP_SUMO:
2039 num_ps_gprs = 93;
2040 num_vs_gprs = 46;
2041 num_temp_gprs = 4;
2042 num_gs_gprs = 31;
2043 num_es_gprs = 31;
2044 num_hs_gprs = 23;
2045 num_ls_gprs = 23;
2046 num_ps_threads = 96;
2047 num_vs_threads = 25;
2048 num_gs_threads = 25;
2049 num_es_threads = 25;
2050 num_hs_threads = 25;
2051 num_ls_threads = 25;
2052 num_ps_stack_entries = 42;
2053 num_vs_stack_entries = 42;
2054 num_gs_stack_entries = 42;
2055 num_es_stack_entries = 42;
2056 num_hs_stack_entries = 42;
2057 num_ls_stack_entries = 42;
2058 break;
2059 case CHIP_SUMO2:
2060 num_ps_gprs = 93;
2061 num_vs_gprs = 46;
2062 num_temp_gprs = 4;
2063 num_gs_gprs = 31;
2064 num_es_gprs = 31;
2065 num_hs_gprs = 23;
2066 num_ls_gprs = 23;
2067 num_ps_threads = 96;
2068 num_vs_threads = 25;
2069 num_gs_threads = 25;
2070 num_es_threads = 25;
2071 num_hs_threads = 25;
2072 num_ls_threads = 25;
2073 num_ps_stack_entries = 85;
2074 num_vs_stack_entries = 85;
2075 num_gs_stack_entries = 85;
2076 num_es_stack_entries = 85;
2077 num_hs_stack_entries = 85;
2078 num_ls_stack_entries = 85;
2079 break;
2080 case CHIP_BARTS:
2081 num_ps_gprs = 93;
2082 num_vs_gprs = 46;
2083 num_temp_gprs = 4;
2084 num_gs_gprs = 31;
2085 num_es_gprs = 31;
2086 num_hs_gprs = 23;
2087 num_ls_gprs = 23;
2088 num_ps_threads = 128;
2089 num_vs_threads = 20;
2090 num_gs_threads = 20;
2091 num_es_threads = 20;
2092 num_hs_threads = 20;
2093 num_ls_threads = 20;
2094 num_ps_stack_entries = 85;
2095 num_vs_stack_entries = 85;
2096 num_gs_stack_entries = 85;
2097 num_es_stack_entries = 85;
2098 num_hs_stack_entries = 85;
2099 num_ls_stack_entries = 85;
2100 break;
2101 case CHIP_TURKS:
2102 num_ps_gprs = 93;
2103 num_vs_gprs = 46;
2104 num_temp_gprs = 4;
2105 num_gs_gprs = 31;
2106 num_es_gprs = 31;
2107 num_hs_gprs = 23;
2108 num_ls_gprs = 23;
2109 num_ps_threads = 128;
2110 num_vs_threads = 20;
2111 num_gs_threads = 20;
2112 num_es_threads = 20;
2113 num_hs_threads = 20;
2114 num_ls_threads = 20;
2115 num_ps_stack_entries = 42;
2116 num_vs_stack_entries = 42;
2117 num_gs_stack_entries = 42;
2118 num_es_stack_entries = 42;
2119 num_hs_stack_entries = 42;
2120 num_ls_stack_entries = 42;
2121 break;
2122 case CHIP_CAICOS:
2123 num_ps_gprs = 93;
2124 num_vs_gprs = 46;
2125 num_temp_gprs = 4;
2126 num_gs_gprs = 31;
2127 num_es_gprs = 31;
2128 num_hs_gprs = 23;
2129 num_ls_gprs = 23;
2130 num_ps_threads = 128;
2131 num_vs_threads = 10;
2132 num_gs_threads = 10;
2133 num_es_threads = 10;
2134 num_hs_threads = 10;
2135 num_ls_threads = 10;
2136 num_ps_stack_entries = 42;
2137 num_vs_stack_entries = 42;
2138 num_gs_stack_entries = 42;
2139 num_es_stack_entries = 42;
2140 num_hs_stack_entries = 42;
2141 num_ls_stack_entries = 42;
2142 break;
2143 }
2144
2145 tmp = 0;
2146 switch (family) {
2147 case CHIP_CEDAR:
2148 case CHIP_PALM:
2149 case CHIP_SUMO:
2150 case CHIP_SUMO2:
2151 case CHIP_CAICOS:
2152 break;
2153 default:
2154 tmp |= S_008C00_VC_ENABLE(1);
2155 break;
2156 }
2157 tmp |= S_008C00_EXPORT_SRC_C(1);
2158 tmp |= S_008C00_CS_PRIO(cs_prio);
2159 tmp |= S_008C00_LS_PRIO(ls_prio);
2160 tmp |= S_008C00_HS_PRIO(hs_prio);
2161 tmp |= S_008C00_PS_PRIO(ps_prio);
2162 tmp |= S_008C00_VS_PRIO(vs_prio);
2163 tmp |= S_008C00_GS_PRIO(gs_prio);
2164 tmp |= S_008C00_ES_PRIO(es_prio);
2165
2166 /* enable dynamic GPR resource management */
2167 if (rctx->screen->info.drm_minor >= 7) {
2168 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2169 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2170 /* always set temp clauses */
2171 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2172 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2173 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2174 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2175 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2176 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2177 S_028838_PS_GPRS(0x1e) |
2178 S_028838_VS_GPRS(0x1e) |
2179 S_028838_GS_GPRS(0x1e) |
2180 S_028838_ES_GPRS(0x1e) |
2181 S_028838_HS_GPRS(0x1e) |
2182 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2183 } else {
2184 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2185 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2186
2187 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2188 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2189 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2190 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2191
2192 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2193 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2194 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2195
2196 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2197 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2198 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2199 }
2200
2201 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2202 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2203 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2204 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2205 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2206 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2207
2208 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2209 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2210 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2211
2212 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2213 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2214 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2215
2216 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2217 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2218 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2219
2220 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2221 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2222 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2223
2224 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2225 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2226
2227 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2228 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2229
2230 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2231
2232 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2233 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2234 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2235 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2236 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2237 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2238 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2239
2240 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2241 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2242 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2243 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2244 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2245
2246 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2247 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2248 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2249 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2250 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2251 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2252 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2253 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2254 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2255 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2256 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2257 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2258 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2259 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2260
2261 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2262 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2263 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2264
2265 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2266 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2267 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2268
2269 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2270
2271 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2272 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2273 r600_store_value(cb, 0);
2274 r600_store_value(cb, 0);
2275 r600_store_value(cb, 0);
2276 r600_store_value(cb, 0);
2277 r600_store_value(cb, 0);
2278 r600_store_value(cb, 0);
2279 r600_store_value(cb, 0);
2280 r600_store_value(cb, 0);
2281 r600_store_value(cb, 0);
2282 r600_store_value(cb, 0);
2283 r600_store_value(cb, 0);
2284 r600_store_value(cb, 0);
2285 r600_store_value(cb, 0);
2286 r600_store_value(cb, 0);
2287 r600_store_value(cb, 0);
2288 r600_store_value(cb, 0);
2289 r600_store_value(cb, 0);
2290 r600_store_value(cb, 0);
2291 r600_store_value(cb, 0);
2292 r600_store_value(cb, 0);
2293 r600_store_value(cb, 0);
2294 r600_store_value(cb, 0);
2295 r600_store_value(cb, 0);
2296 r600_store_value(cb, 0);
2297 r600_store_value(cb, 0);
2298 r600_store_value(cb, 0);
2299 r600_store_value(cb, 0);
2300 r600_store_value(cb, 0);
2301 r600_store_value(cb, 0);
2302 r600_store_value(cb, 0);
2303 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2304 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2305 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2306
2307 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2308
2309 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2310 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2311 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2312
2313 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2314 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2315 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2316
2317 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2318 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2319 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2320
2321 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2322 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2323 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2324
2325 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2326 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2327 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2328 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2329
2330 r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2331
2332 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2333 r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2334 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2335
2336 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2337 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2338 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2339 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2340 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2341 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2342
2343 r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2344
2345 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2346 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2347 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2348
2349 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2350 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2351 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2352
2353 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2354 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
2355 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2356
2357 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2358 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2359 }
2360
2361 void evergreen_polygon_offset_update(struct r600_context *rctx)
2362 {
2363 struct r600_pipe_state state;
2364
2365 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2366 state.nregs = 0;
2367 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2368 float offset_units = rctx->rasterizer->offset_units;
2369 unsigned offset_db_fmt_cntl = 0, depth;
2370
2371 switch (rctx->framebuffer.zsbuf->texture->format) {
2372 case PIPE_FORMAT_Z24X8_UNORM:
2373 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2374 depth = -24;
2375 offset_units *= 2.0f;
2376 break;
2377 case PIPE_FORMAT_Z32_FLOAT:
2378 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2379 depth = -23;
2380 offset_units *= 1.0f;
2381 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2382 break;
2383 case PIPE_FORMAT_Z16_UNORM:
2384 depth = -16;
2385 offset_units *= 4.0f;
2386 break;
2387 default:
2388 return;
2389 }
2390 /* XXX some of those reg can be computed with cso */
2391 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2392 r600_pipe_state_add_reg(&state,
2393 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2394 fui(rctx->rasterizer->offset_scale), NULL, 0);
2395 r600_pipe_state_add_reg(&state,
2396 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2397 fui(offset_units), NULL, 0);
2398 r600_pipe_state_add_reg(&state,
2399 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2400 fui(rctx->rasterizer->offset_scale), NULL, 0);
2401 r600_pipe_state_add_reg(&state,
2402 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2403 fui(offset_units), NULL, 0);
2404 r600_pipe_state_add_reg(&state,
2405 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2406 offset_db_fmt_cntl, NULL, 0);
2407 r600_context_pipe_state_set(rctx, &state);
2408 }
2409 }
2410
2411 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2412 {
2413 struct r600_context *rctx = (struct r600_context *)ctx;
2414 struct r600_pipe_state *rstate = &shader->rstate;
2415 struct r600_shader *rshader = &shader->shader;
2416 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2417 int pos_index = -1, face_index = -1;
2418 int ninterp = 0;
2419 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2420 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2421
2422 rstate->nregs = 0;
2423
2424 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2425 for (i = 0; i < rshader->ninput; i++) {
2426 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2427 POSITION goes via GPRs from the SC so isn't counted */
2428 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2429 pos_index = i;
2430 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2431 face_index = i;
2432 else {
2433 ninterp++;
2434 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2435 have_linear = TRUE;
2436 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2437 have_perspective = TRUE;
2438 if (rshader->input[i].centroid)
2439 have_centroid = TRUE;
2440 }
2441
2442 sid = rshader->input[i].spi_sid;
2443
2444 if (sid) {
2445
2446 tmp = S_028644_SEMANTIC(sid);
2447
2448 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2449 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2450 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2451 rctx->rasterizer && rctx->rasterizer->flatshade)) {
2452 tmp |= S_028644_FLAT_SHADE(1);
2453 }
2454
2455 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2456 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2457 tmp |= S_028644_PT_SPRITE_TEX(1);
2458 }
2459
2460 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2461 tmp, NULL, 0);
2462
2463 idx++;
2464 }
2465 }
2466
2467 for (i = 0; i < rshader->noutput; i++) {
2468 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2469 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2470 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2471 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2472 }
2473 if (rshader->uses_kill)
2474 db_shader_control |= S_02880C_KILL_ENABLE(1);
2475
2476 exports_ps = 0;
2477 num_cout = 0;
2478 for (i = 0; i < rshader->noutput; i++) {
2479 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2480 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2481 exports_ps |= 1;
2482 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2483 if (rshader->fs_write_all)
2484 num_cout = rshader->nr_cbufs;
2485 else
2486 num_cout++;
2487 }
2488 }
2489 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2490 if (!exports_ps) {
2491 /* always at least export 1 component per pixel */
2492 exports_ps = 2;
2493 }
2494
2495 if (ninterp == 0) {
2496 ninterp = 1;
2497 have_perspective = TRUE;
2498 }
2499
2500 if (!have_perspective && !have_linear)
2501 have_perspective = TRUE;
2502
2503 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2504 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2505 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2506 spi_input_z = 0;
2507 if (pos_index != -1) {
2508 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2509 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2510 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2511 spi_input_z |= 1;
2512 }
2513
2514 spi_ps_in_control_1 = 0;
2515 if (face_index != -1) {
2516 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2517 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2518 }
2519
2520 spi_baryc_cntl = 0;
2521 if (have_perspective)
2522 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2523 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2524 if (have_linear)
2525 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2526 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2527
2528 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2529 spi_ps_in_control_0, NULL, 0);
2530 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2531 spi_ps_in_control_1, NULL, 0);
2532 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2533 0, NULL, 0);
2534 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2535 r600_pipe_state_add_reg(rstate,
2536 R_0286E0_SPI_BARYC_CNTL,
2537 spi_baryc_cntl,
2538 NULL, 0);
2539
2540 r600_pipe_state_add_reg(rstate,
2541 R_028840_SQ_PGM_START_PS,
2542 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2543 shader->bo, RADEON_USAGE_READ);
2544 r600_pipe_state_add_reg(rstate,
2545 R_028844_SQ_PGM_RESOURCES_PS,
2546 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2547 S_028844_PRIME_CACHE_ON_DRAW(1) |
2548 S_028844_STACK_SIZE(rshader->bc.nstack),
2549 NULL, 0);
2550 r600_pipe_state_add_reg(rstate,
2551 R_02884C_SQ_PGM_EXPORTS_PS,
2552 exports_ps, NULL, 0);
2553 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2554 db_shader_control,
2555 NULL, 0);
2556
2557 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2558 if (rctx->rasterizer)
2559 shader->flatshade = rctx->rasterizer->flatshade;
2560 }
2561
2562 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2563 {
2564 struct r600_context *rctx = (struct r600_context *)ctx;
2565 struct r600_pipe_state *rstate = &shader->rstate;
2566 struct r600_shader *rshader = &shader->shader;
2567 unsigned spi_vs_out_id[10] = {};
2568 unsigned i, tmp, nparams = 0;
2569
2570 /* clear previous register */
2571 rstate->nregs = 0;
2572
2573 for (i = 0; i < rshader->noutput; i++) {
2574 if (rshader->output[i].spi_sid) {
2575 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2576 spi_vs_out_id[nparams / 4] |= tmp;
2577 nparams++;
2578 }
2579 }
2580
2581 for (i = 0; i < 10; i++) {
2582 r600_pipe_state_add_reg(rstate,
2583 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2584 spi_vs_out_id[i], NULL, 0);
2585 }
2586
2587 /* Certain attributes (position, psize, etc.) don't count as params.
2588 * VS is required to export at least one param and r600_shader_from_tgsi()
2589 * takes care of adding a dummy export.
2590 */
2591 if (nparams < 1)
2592 nparams = 1;
2593
2594 r600_pipe_state_add_reg(rstate,
2595 R_0286C4_SPI_VS_OUT_CONFIG,
2596 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2597 NULL, 0);
2598 r600_pipe_state_add_reg(rstate,
2599 R_028860_SQ_PGM_RESOURCES_VS,
2600 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2601 S_028860_STACK_SIZE(rshader->bc.nstack),
2602 NULL, 0);
2603 r600_pipe_state_add_reg(rstate,
2604 R_02885C_SQ_PGM_START_VS,
2605 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2606 shader->bo, RADEON_USAGE_READ);
2607
2608 shader->pa_cl_vs_out_cntl =
2609 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2610 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2611 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2612 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2613 }
2614
2615 void evergreen_fetch_shader(struct pipe_context *ctx,
2616 struct r600_vertex_element *ve)
2617 {
2618 struct r600_context *rctx = (struct r600_context *)ctx;
2619 struct r600_pipe_state *rstate = &ve->rstate;
2620 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2621 rstate->nregs = 0;
2622 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2623 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2624 ve->fetch_shader, RADEON_USAGE_READ);
2625 }
2626
2627 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2628 {
2629 struct pipe_depth_stencil_alpha_state dsa;
2630 struct r600_pipe_state *rstate;
2631
2632 memset(&dsa, 0, sizeof(dsa));
2633
2634 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2635 r600_pipe_state_add_reg(rstate,
2636 R_028000_DB_RENDER_CONTROL,
2637 S_028000_DEPTH_COPY_ENABLE(1) |
2638 S_028000_STENCIL_COPY_ENABLE(1) |
2639 S_028000_COPY_CENTROID(1),
2640 NULL, 0);
2641 /* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
2642 return rstate;
2643 }
2644
2645 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2646 struct r600_pipe_resource_state *rstate)
2647 {
2648 rstate->id = R600_PIPE_STATE_RESOURCE;
2649
2650 rstate->val[0] = 0;
2651 rstate->bo[0] = NULL;
2652 rstate->val[1] = 0;
2653 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2654 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2655 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2656 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2657 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2658 rstate->val[4] = 0;
2659 rstate->val[5] = 0;
2660 rstate->val[6] = 0;
2661 rstate->val[7] = 0xc0000000;
2662 }
2663
2664
2665 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2666 struct r600_pipe_resource_state *rstate,
2667 struct r600_resource *rbuffer,
2668 unsigned offset, unsigned stride,
2669 enum radeon_bo_usage usage)
2670 {
2671 uint64_t va;
2672
2673 va = r600_resource_va(ctx->screen, (void *)rbuffer);
2674 rstate->bo[0] = rbuffer;
2675 rstate->bo_usage[0] = usage;
2676 rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2677 rstate->val[1] = rbuffer->buf->size - offset - 1;
2678 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2679 S_030008_STRIDE(stride) |
2680 (((va + offset) >> 32UL) & 0xFF);
2681 }