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r600g: move resource setting to its own structures.
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
75 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
76 struct r600_pipe_state *rstate;
77 u32 color_control, target_mask;
78 /* FIXME there is more then 8 framebuffer */
79 unsigned blend_cntl[8];
80 enum radeon_family family;
81
82 if (blend == NULL) {
83 return NULL;
84 }
85
86 family = r600_get_family(rctx->radeon);
87 rstate = &blend->rstate;
88
89 rstate->id = R600_PIPE_STATE_BLEND;
90
91 target_mask = 0;
92 color_control = S_028808_MODE(1);
93 if (state->logicop_enable) {
94 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
95 } else {
96 color_control |= (0xcc << 16);
97 }
98 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
99 if (state->independent_blend_enable) {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[i].colormask << (4 * i));
102 }
103 } else {
104 for (int i = 0; i < 8; i++) {
105 target_mask |= (state->rt[0].colormask << (4 * i));
106 }
107 }
108 blend->cb_target_mask = target_mask;
109
110 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
111 color_control, 0xFFFFFFFD, NULL);
112
113 if (family != CHIP_CAYMAN)
114 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
115 else {
116 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
117 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
118 }
119
120 for (int i = 0; i < 8; i++) {
121 /* state->rt entries > 0 only written if independent blending */
122 const int j = state->independent_blend_enable ? i : 0;
123
124 unsigned eqRGB = state->rt[j].rgb_func;
125 unsigned srcRGB = state->rt[j].rgb_src_factor;
126 unsigned dstRGB = state->rt[j].rgb_dst_factor;
127 unsigned eqA = state->rt[j].alpha_func;
128 unsigned srcA = state->rt[j].alpha_src_factor;
129 unsigned dstA = state->rt[j].alpha_dst_factor;
130
131 blend_cntl[i] = 0;
132 if (!state->rt[j].blend_enable)
133 continue;
134
135 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
136 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
137 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
138 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
139
140 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
141 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
142 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
143 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
144 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
145 }
146 }
147 for (int i = 0; i < 8; i++) {
148 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
149 }
150
151 return rstate;
152 }
153
154 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
155 const struct pipe_depth_stencil_alpha_state *state)
156 {
157 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
158 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
159 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
160 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
161 struct r600_pipe_state *rstate;
162
163 if (dsa == NULL) {
164 return NULL;
165 }
166
167 rstate = &dsa->rstate;
168
169 rstate->id = R600_PIPE_STATE_DSA;
170 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
171 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
172 stencil_ref_mask = 0;
173 stencil_ref_mask_bf = 0;
174 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
175 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
176 S_028800_ZFUNC(state->depth.func);
177
178 /* stencil */
179 if (state->stencil[0].enabled) {
180 db_depth_control |= S_028800_STENCIL_ENABLE(1);
181 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
182 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
183 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
184 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
185
186
187 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
188 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
189 if (state->stencil[1].enabled) {
190 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
191 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
192 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
193 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
194 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
195 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
196 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
197 }
198 }
199
200 /* alpha */
201 alpha_test_control = 0;
202 alpha_ref = 0;
203 if (state->alpha.enabled) {
204 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
205 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
206 alpha_ref = fui(state->alpha.ref_value);
207 }
208 dsa->alpha_ref = alpha_ref;
209
210 /* misc */
211 db_render_control = 0;
212 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
213 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
214 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
215 /* TODO db_render_override depends on query */
216 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate,
220 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
221 0xFFFFFFFF & C_028430_STENCILREF, NULL);
222 r600_pipe_state_add_reg(rstate,
223 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
224 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
225 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
226 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
227 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
228 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
229 * evergreen_pipe_shader_ps().*/
230 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
231 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
232 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
233 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
234 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
235 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
236 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
237
238 return rstate;
239 }
240
241 static void *evergreen_create_rs_state(struct pipe_context *ctx,
242 const struct pipe_rasterizer_state *state)
243 {
244 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
245 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
246 struct r600_pipe_state *rstate;
247 unsigned tmp;
248 unsigned prov_vtx = 1, polygon_dual_mode;
249 unsigned clip_rule;
250 enum radeon_family family;
251
252 family = r600_get_family(rctx->radeon);
253
254 if (rs == NULL) {
255 return NULL;
256 }
257
258 rstate = &rs->rstate;
259 rs->flatshade = state->flatshade;
260 rs->sprite_coord_enable = state->sprite_coord_enable;
261
262 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
263
264 /* offset */
265 rs->offset_units = state->offset_units;
266 rs->offset_scale = state->offset_scale * 12.0f;
267
268 rstate->id = R600_PIPE_STATE_RASTERIZER;
269 if (state->flatshade_first)
270 prov_vtx = 0;
271 tmp = S_0286D4_FLAT_SHADE_ENA(1);
272 if (state->sprite_coord_enable) {
273 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
274 S_0286D4_PNT_SPRITE_OVRD_X(2) |
275 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
276 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
277 S_0286D4_PNT_SPRITE_OVRD_W(1);
278 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
279 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
280 }
281 }
282 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
283
284 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
285 state->fill_back != PIPE_POLYGON_MODE_FILL);
286 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
287 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
288 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
289 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
290 S_028814_FACE(!state->front_ccw) |
291 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
292 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
293 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
294 S_028814_POLY_MODE(polygon_dual_mode) |
295 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
296 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
297 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
298 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
299 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
301 /* point size 12.4 fixed point */
302 tmp = (unsigned)(state->point_size * 8.0);
303 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
304 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
305
306 tmp = (unsigned)state->line_width * 8;
307 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
308
309 if (family == CHIP_CAYMAN) {
310 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
311 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
312 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
313 0xFFFFFFFF, NULL);
314 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
315 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
316 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
317 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
318
319
320 } else {
321 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
322
323 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
324 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
325 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
326 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
327
328 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
329 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
330 0xFFFFFFFF, NULL);
331 }
332 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
333 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
334 return rstate;
335 }
336
337 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
338 const struct pipe_sampler_state *state)
339 {
340 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
341 union util_color uc;
342 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
343
344 if (rstate == NULL) {
345 return NULL;
346 }
347
348 rstate->id = R600_PIPE_STATE_SAMPLER;
349 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
350 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
351 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
352 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
353 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
354 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
355 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
356 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
357 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
358 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
359 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
360 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
361 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
362 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
363 0xFFFFFFFF, NULL);
364 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
365 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
366 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
367 S_03C008_TYPE(1),
368 0xFFFFFFFF, NULL);
369
370 if (uc.ui) {
371 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
372 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
373 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
374 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
375 }
376 return rstate;
377 }
378
379 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
380 struct pipe_resource *texture,
381 const struct pipe_sampler_view *state)
382 {
383 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
384 struct r600_pipe_resource_state *rstate;
385 const struct util_format_description *desc;
386 struct r600_resource_texture *tmp;
387 struct r600_resource *rbuffer;
388 unsigned format, endian;
389 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
390 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
391 struct r600_bo *bo[2];
392
393 if (resource == NULL)
394 return NULL;
395 rstate = &resource->state;
396
397 /* initialize base object */
398 resource->base = *state;
399 resource->base.texture = NULL;
400 pipe_reference(NULL, &texture->reference);
401 resource->base.texture = texture;
402 resource->base.reference.count = 1;
403 resource->base.context = ctx;
404
405 swizzle[0] = state->swizzle_r;
406 swizzle[1] = state->swizzle_g;
407 swizzle[2] = state->swizzle_b;
408 swizzle[3] = state->swizzle_a;
409 format = r600_translate_texformat(ctx->screen, state->format,
410 swizzle,
411 &word4, &yuv_format);
412 if (format == ~0) {
413 format = 0;
414 }
415 desc = util_format_description(state->format);
416 if (desc == NULL) {
417 R600_ERR("unknow format %d\n", state->format);
418 }
419 tmp = (struct r600_resource_texture *)texture;
420 if (tmp->depth && !tmp->is_flushing_texture) {
421 r600_texture_depth_flush(ctx, texture, TRUE);
422 tmp = tmp->flushed_depth_texture;
423 }
424
425 endian = r600_colorformat_endian_swap(format);
426
427 if (tmp->force_int_type) {
428 word4 &= C_030010_NUM_FORMAT_ALL;
429 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
430 }
431
432 rbuffer = &tmp->resource;
433 bo[0] = rbuffer->bo;
434 bo[1] = rbuffer->bo;
435
436 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
437 array_mode = tmp->array_mode[0];
438 tile_type = tmp->tile_type;
439
440 rstate->bo[0] = bo[0];
441 rstate->bo[1] = bo[1];
442 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
443 S_030000_PITCH((pitch / 8) - 1) |
444 S_030000_NON_DISP_TILING_ORDER(tile_type) |
445 S_030000_TEX_WIDTH(texture->width0 - 1));
446 rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
447 S_030004_TEX_DEPTH(texture->depth0 - 1) |
448 S_030004_ARRAY_MODE(array_mode));
449 rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
450 rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
451 rstate->val[4] = (word4 |
452 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
453 S_030010_ENDIAN_SWAP(endian) |
454 S_030010_BASE_LEVEL(state->u.tex.first_level));
455 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
456 S_030014_BASE_ARRAY(0) |
457 S_030014_LAST_ARRAY(0));
458 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
459 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
460 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
461
462 return &resource->base;
463 }
464
465 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
466 struct pipe_sampler_view **views)
467 {
468 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
469 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
470
471 for (int i = 0; i < count; i++) {
472 if (resource[i]) {
473 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
474 i + R600_MAX_CONST_BUFFERS);
475 }
476 }
477 }
478
479 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
480 struct pipe_sampler_view **views)
481 {
482 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
483 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
484 int i;
485
486 for (i = 0; i < count; i++) {
487 if (&rctx->ps_samplers.views[i]->base != views[i]) {
488 if (resource[i])
489 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
490 i + R600_MAX_CONST_BUFFERS);
491 else
492 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
493 i + R600_MAX_CONST_BUFFERS);
494
495 pipe_sampler_view_reference(
496 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
497 views[i]);
498 }
499 }
500 for (i = count; i < NUM_TEX_UNITS; i++) {
501 if (rctx->ps_samplers.views[i]) {
502 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
503 i + R600_MAX_CONST_BUFFERS);
504 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
505 }
506 }
507 rctx->ps_samplers.n_views = count;
508 }
509
510 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
511 {
512 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
513 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
514
515
516 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
517 rctx->ps_samplers.n_samplers = count;
518
519 for (int i = 0; i < count; i++) {
520 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
521 }
522 }
523
524 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
525 {
526 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
527 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
528
529 for (int i = 0; i < count; i++) {
530 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
531 }
532 }
533
534 static void evergreen_set_clip_state(struct pipe_context *ctx,
535 const struct pipe_clip_state *state)
536 {
537 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
538 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
539
540 if (rstate == NULL)
541 return;
542
543 rctx->clip = *state;
544 rstate->id = R600_PIPE_STATE_CLIP;
545 for (int i = 0; i < state->nr; i++) {
546 r600_pipe_state_add_reg(rstate,
547 R_0285BC_PA_CL_UCP0_X + i * 16,
548 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
549 r600_pipe_state_add_reg(rstate,
550 R_0285C0_PA_CL_UCP0_Y + i * 16,
551 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
552 r600_pipe_state_add_reg(rstate,
553 R_0285C4_PA_CL_UCP0_Z + i * 16,
554 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
555 r600_pipe_state_add_reg(rstate,
556 R_0285C8_PA_CL_UCP0_W + i * 16,
557 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
558 }
559 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
560 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
561 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
562 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
563
564 free(rctx->states[R600_PIPE_STATE_CLIP]);
565 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
566 r600_context_pipe_state_set(&rctx->ctx, rstate);
567 }
568
569 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
570 const struct pipe_poly_stipple *state)
571 {
572 }
573
574 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
575 {
576 }
577
578 static void evergreen_set_scissor_state(struct pipe_context *ctx,
579 const struct pipe_scissor_state *state)
580 {
581 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
582 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
583 u32 tl, br;
584
585 if (rstate == NULL)
586 return;
587
588 rstate->id = R600_PIPE_STATE_SCISSOR;
589 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
590 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
591 r600_pipe_state_add_reg(rstate,
592 R_028210_PA_SC_CLIPRECT_0_TL, tl,
593 0xFFFFFFFF, NULL);
594 r600_pipe_state_add_reg(rstate,
595 R_028214_PA_SC_CLIPRECT_0_BR, br,
596 0xFFFFFFFF, NULL);
597 r600_pipe_state_add_reg(rstate,
598 R_028218_PA_SC_CLIPRECT_1_TL, tl,
599 0xFFFFFFFF, NULL);
600 r600_pipe_state_add_reg(rstate,
601 R_02821C_PA_SC_CLIPRECT_1_BR, br,
602 0xFFFFFFFF, NULL);
603 r600_pipe_state_add_reg(rstate,
604 R_028220_PA_SC_CLIPRECT_2_TL, tl,
605 0xFFFFFFFF, NULL);
606 r600_pipe_state_add_reg(rstate,
607 R_028224_PA_SC_CLIPRECT_2_BR, br,
608 0xFFFFFFFF, NULL);
609 r600_pipe_state_add_reg(rstate,
610 R_028228_PA_SC_CLIPRECT_3_TL, tl,
611 0xFFFFFFFF, NULL);
612 r600_pipe_state_add_reg(rstate,
613 R_02822C_PA_SC_CLIPRECT_3_BR, br,
614 0xFFFFFFFF, NULL);
615
616 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
617 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
618 r600_context_pipe_state_set(&rctx->ctx, rstate);
619 }
620
621 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
622 const struct pipe_stencil_ref *state)
623 {
624 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
625 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
626 u32 tmp;
627
628 if (rstate == NULL)
629 return;
630
631 rctx->stencil_ref = *state;
632 rstate->id = R600_PIPE_STATE_STENCIL_REF;
633 tmp = S_028430_STENCILREF(state->ref_value[0]);
634 r600_pipe_state_add_reg(rstate,
635 R_028430_DB_STENCILREFMASK, tmp,
636 ~C_028430_STENCILREF, NULL);
637 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
638 r600_pipe_state_add_reg(rstate,
639 R_028434_DB_STENCILREFMASK_BF, tmp,
640 ~C_028434_STENCILREF_BF, NULL);
641
642 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
643 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
644 r600_context_pipe_state_set(&rctx->ctx, rstate);
645 }
646
647 static void evergreen_set_viewport_state(struct pipe_context *ctx,
648 const struct pipe_viewport_state *state)
649 {
650 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
651 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
652
653 if (rstate == NULL)
654 return;
655
656 rctx->viewport = *state;
657 rstate->id = R600_PIPE_STATE_VIEWPORT;
658 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
659 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
660 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
661 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
662 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
663 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
664 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
665 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
666 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
667
668 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
669 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
670 r600_context_pipe_state_set(&rctx->ctx, rstate);
671 }
672
673 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
674 const struct pipe_framebuffer_state *state, int cb)
675 {
676 struct r600_resource_texture *rtex;
677 struct r600_resource *rbuffer;
678 struct r600_surface *surf;
679 unsigned level = state->cbufs[cb]->u.tex.level;
680 unsigned pitch, slice;
681 unsigned color_info;
682 unsigned format, swap, ntype, endian;
683 unsigned offset;
684 unsigned tile_type;
685 const struct util_format_description *desc;
686 struct r600_bo *bo[3];
687 int i;
688
689 surf = (struct r600_surface *)state->cbufs[cb];
690 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
691
692 if (rtex->depth && !rtex->is_flushing_texture) {
693 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
694 rtex = rtex->flushed_depth_texture;
695 }
696
697 rbuffer = &rtex->resource;
698 bo[0] = rbuffer->bo;
699 bo[1] = rbuffer->bo;
700 bo[2] = rbuffer->bo;
701
702 /* XXX quite sure for dx10+ hw don't need any offset hacks */
703 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
704 level, state->cbufs[cb]->u.tex.first_layer);
705 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
706 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
707 desc = util_format_description(surf->base.format);
708 for (i = 0; i < 4; i++) {
709 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
710 break;
711 }
712 }
713 ntype = V_028C70_NUMBER_UNORM;
714 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
715 ntype = V_028C70_NUMBER_SRGB;
716 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
717 ntype = V_028C70_NUMBER_SNORM;
718
719 format = r600_translate_colorformat(surf->base.format);
720 swap = r600_translate_colorswap(surf->base.format);
721 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
722 endian = ENDIAN_NONE;
723 } else {
724 endian = r600_colorformat_endian_swap(format);
725 }
726
727 /* disable when gallium grows int textures */
728 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
729 ntype = V_028C70_NUMBER_UINT;
730
731 color_info = S_028C70_FORMAT(format) |
732 S_028C70_COMP_SWAP(swap) |
733 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
734 S_028C70_BLEND_CLAMP(1) |
735 S_028C70_NUMBER_TYPE(ntype) |
736 S_028C70_ENDIAN(endian);
737
738
739 /* EXPORT_NORM is an optimzation that can be enabled for better
740 * performance in certain cases.
741 * EXPORT_NORM can be enabled if:
742 * - 11-bit or smaller UNORM/SNORM/SRGB
743 * - 16-bit or smaller FLOAT
744 */
745 /* FIXME: This should probably be the same for all CBs if we want
746 * useful alpha tests. */
747 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
748 ((desc->channel[i].size < 12 &&
749 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
750 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
751 (desc->channel[i].size < 17 &&
752 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
753 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
754 rctx->export_16bpc = true;
755 } else {
756 rctx->export_16bpc = false;
757 }
758 rctx->alpha_ref_dirty = true;
759
760 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
761 tile_type = rtex->tile_type;
762 } else /* workaround for linear buffers */
763 tile_type = 1;
764
765 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
766 r600_pipe_state_add_reg(rstate,
767 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
768 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
769 r600_pipe_state_add_reg(rstate,
770 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
771 0x0, 0xFFFFFFFF, NULL);
772 r600_pipe_state_add_reg(rstate,
773 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
774 color_info, 0xFFFFFFFF, bo[0]);
775 r600_pipe_state_add_reg(rstate,
776 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
777 S_028C64_PITCH_TILE_MAX(pitch),
778 0xFFFFFFFF, NULL);
779 r600_pipe_state_add_reg(rstate,
780 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
781 S_028C68_SLICE_TILE_MAX(slice),
782 0xFFFFFFFF, NULL);
783 r600_pipe_state_add_reg(rstate,
784 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
785 0x00000000, 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate,
787 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
788 S_028C74_NON_DISP_TILING_ORDER(tile_type),
789 0xFFFFFFFF, bo[0]);
790 }
791
792 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
793 const struct pipe_framebuffer_state *state)
794 {
795 struct r600_resource_texture *rtex;
796 struct r600_resource *rbuffer;
797 struct r600_surface *surf;
798 unsigned level;
799 unsigned pitch, slice, format, stencil_format;
800 unsigned offset;
801
802 if (state->zsbuf == NULL)
803 return;
804
805 level = state->zsbuf->u.tex.level;
806
807 surf = (struct r600_surface *)state->zsbuf;
808 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
809
810 rbuffer = &rtex->resource;
811
812 /* XXX quite sure for dx10+ hw don't need any offset hacks */
813 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
814 level, state->zsbuf->u.tex.first_layer);
815 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
816 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
817 format = r600_translate_dbformat(state->zsbuf->texture->format);
818 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
819
820 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
821 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
822 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
823 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
824
825 if (stencil_format) {
826 uint32_t stencil_offset;
827
828 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
829 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
830 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
831 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
832 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
833 }
834
835 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
836 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
837 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
838
839 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
840 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
841 0xFFFFFFFF, rbuffer->bo);
842 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
843 S_028058_PITCH_TILE_MAX(pitch),
844 0xFFFFFFFF, NULL);
845 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
846 S_02805C_SLICE_TILE_MAX(slice),
847 0xFFFFFFFF, NULL);
848 }
849
850 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
851 const struct pipe_framebuffer_state *state)
852 {
853 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
854 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
855 u32 shader_mask, tl, br, target_mask;
856 enum radeon_family family;
857 int tl_x, tl_y, br_x, br_y;
858
859 if (rstate == NULL)
860 return;
861
862 family = r600_get_family(rctx->radeon);
863
864 evergreen_context_flush_dest_caches(&rctx->ctx);
865 rctx->ctx.num_dest_buffers = state->nr_cbufs;
866
867 /* unreference old buffer and reference new one */
868 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
869
870 util_copy_framebuffer_state(&rctx->framebuffer, state);
871
872 /* build states */
873 for (int i = 0; i < state->nr_cbufs; i++) {
874 evergreen_cb(rctx, rstate, state, i);
875 }
876 if (state->zsbuf) {
877 evergreen_db(rctx, rstate, state);
878 rctx->ctx.num_dest_buffers++;
879 }
880
881 target_mask = 0x00000000;
882 target_mask = 0xFFFFFFFF;
883 shader_mask = 0;
884 for (int i = 0; i < state->nr_cbufs; i++) {
885 target_mask ^= 0xf << (i * 4);
886 shader_mask |= 0xf << (i * 4);
887 }
888 tl_x = 0;
889 tl_y = 0;
890 br_x = state->width;
891 br_y = state->height;
892 /* EG hw workaround */
893 if (br_x == 0)
894 tl_x = 1;
895 if (br_y == 0)
896 tl_y = 1;
897 /* cayman hw workaround */
898 if (family == CHIP_CAYMAN) {
899 if (br_x == 1 && br_y == 1)
900 br_x = 2;
901 }
902 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
903 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
904
905 r600_pipe_state_add_reg(rstate,
906 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
907 0xFFFFFFFF, NULL);
908 r600_pipe_state_add_reg(rstate,
909 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
910 0xFFFFFFFF, NULL);
911 r600_pipe_state_add_reg(rstate,
912 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
913 0xFFFFFFFF, NULL);
914 r600_pipe_state_add_reg(rstate,
915 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
916 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate,
918 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
919 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate,
921 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
922 0xFFFFFFFF, NULL);
923 r600_pipe_state_add_reg(rstate,
924 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
925 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate,
927 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
928 0xFFFFFFFF, NULL);
929 r600_pipe_state_add_reg(rstate,
930 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
931 0xFFFFFFFF, NULL);
932 r600_pipe_state_add_reg(rstate,
933 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
934 0xFFFFFFFF, NULL);
935
936 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
937 0x00000000, target_mask, NULL);
938 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
939 shader_mask, 0xFFFFFFFF, NULL);
940
941
942 if (family == CHIP_CAYMAN) {
943 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
944 0x00000000, 0xFFFFFFFF, NULL);
945 } else {
946 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
947 0x00000000, 0xFFFFFFFF, NULL);
948 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
949 0x00000000, 0xFFFFFFFF, NULL);
950 }
951
952 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
953 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
954 r600_context_pipe_state_set(&rctx->ctx, rstate);
955
956 if (state->zsbuf) {
957 evergreen_polygon_offset_update(rctx);
958 }
959 }
960
961 static void evergreen_texture_barrier(struct pipe_context *ctx)
962 {
963 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
964
965 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
966 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
967 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
968 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
969 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
970 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
971 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
972 }
973
974 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
975 {
976 rctx->context.create_blend_state = evergreen_create_blend_state;
977 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
978 rctx->context.create_fs_state = r600_create_shader_state;
979 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
980 rctx->context.create_sampler_state = evergreen_create_sampler_state;
981 rctx->context.create_sampler_view = evergreen_create_sampler_view;
982 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
983 rctx->context.create_vs_state = r600_create_shader_state;
984 rctx->context.bind_blend_state = r600_bind_blend_state;
985 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
986 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
987 rctx->context.bind_fs_state = r600_bind_ps_shader;
988 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
989 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
990 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
991 rctx->context.bind_vs_state = r600_bind_vs_shader;
992 rctx->context.delete_blend_state = r600_delete_state;
993 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
994 rctx->context.delete_fs_state = r600_delete_ps_shader;
995 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
996 rctx->context.delete_sampler_state = r600_delete_state;
997 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
998 rctx->context.delete_vs_state = r600_delete_vs_shader;
999 rctx->context.set_blend_color = evergreen_set_blend_color;
1000 rctx->context.set_clip_state = evergreen_set_clip_state;
1001 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1002 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1003 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1004 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1005 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1006 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1007 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1008 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1009 rctx->context.set_index_buffer = r600_set_index_buffer;
1010 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1011 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1012 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1013 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1014 rctx->context.texture_barrier = evergreen_texture_barrier;
1015 }
1016
1017 static void cayman_init_config(struct r600_pipe_context *rctx)
1018 {
1019 struct r600_pipe_state *rstate = &rctx->config;
1020 unsigned tmp;
1021
1022 tmp = 0x00000000;
1023 tmp |= S_008C00_EXPORT_SRC_C(1);
1024 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1025
1026 r600_pipe_state_add_reg(rstate, CM_R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, (4 << 28), 0xFFFFFFFF, NULL);
1027 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
1028
1029 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1030 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1031
1032 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1033 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1034 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1035 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1036 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1037 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1038 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1039 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1040 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1041 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1042 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1043 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1044 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1045 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1046 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1047 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1048 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1049 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1050
1051 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1052 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1053 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1054 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1055 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1056 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1057 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1058 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1059 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1060 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1061 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1062 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1063 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1064 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1065 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1066 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1067 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1068 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1069 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1070 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1071 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1072 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1073 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1074 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1075 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1076 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1077 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1078 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1079 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1080 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1081 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1082 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1083
1084 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1085
1086 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, 0);
1087 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, 0);
1088
1089 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xffffffff, NULL);
1090 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xffffffff, NULL);
1091
1092 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xffffffff, NULL);
1093 r600_context_pipe_state_set(&rctx->ctx, rstate);
1094 }
1095
1096 void evergreen_init_config(struct r600_pipe_context *rctx)
1097 {
1098 struct r600_pipe_state *rstate = &rctx->config;
1099 int ps_prio;
1100 int vs_prio;
1101 int gs_prio;
1102 int es_prio;
1103 int hs_prio, cs_prio, ls_prio;
1104 int num_ps_gprs;
1105 int num_vs_gprs;
1106 int num_gs_gprs;
1107 int num_es_gprs;
1108 int num_hs_gprs;
1109 int num_ls_gprs;
1110 int num_temp_gprs;
1111 int num_ps_threads;
1112 int num_vs_threads;
1113 int num_gs_threads;
1114 int num_es_threads;
1115 int num_hs_threads;
1116 int num_ls_threads;
1117 int num_ps_stack_entries;
1118 int num_vs_stack_entries;
1119 int num_gs_stack_entries;
1120 int num_es_stack_entries;
1121 int num_hs_stack_entries;
1122 int num_ls_stack_entries;
1123 enum radeon_family family;
1124 unsigned tmp;
1125
1126 family = r600_get_family(rctx->radeon);
1127
1128 if (family == CHIP_CAYMAN) {
1129 cayman_init_config(rctx);
1130 return;
1131 }
1132
1133 ps_prio = 0;
1134 vs_prio = 1;
1135 gs_prio = 2;
1136 es_prio = 3;
1137 hs_prio = 0;
1138 ls_prio = 0;
1139 cs_prio = 0;
1140
1141 switch (family) {
1142 case CHIP_CEDAR:
1143 default:
1144 num_ps_gprs = 93;
1145 num_vs_gprs = 46;
1146 num_temp_gprs = 4;
1147 num_gs_gprs = 31;
1148 num_es_gprs = 31;
1149 num_hs_gprs = 23;
1150 num_ls_gprs = 23;
1151 num_ps_threads = 96;
1152 num_vs_threads = 16;
1153 num_gs_threads = 16;
1154 num_es_threads = 16;
1155 num_hs_threads = 16;
1156 num_ls_threads = 16;
1157 num_ps_stack_entries = 42;
1158 num_vs_stack_entries = 42;
1159 num_gs_stack_entries = 42;
1160 num_es_stack_entries = 42;
1161 num_hs_stack_entries = 42;
1162 num_ls_stack_entries = 42;
1163 break;
1164 case CHIP_REDWOOD:
1165 num_ps_gprs = 93;
1166 num_vs_gprs = 46;
1167 num_temp_gprs = 4;
1168 num_gs_gprs = 31;
1169 num_es_gprs = 31;
1170 num_hs_gprs = 23;
1171 num_ls_gprs = 23;
1172 num_ps_threads = 128;
1173 num_vs_threads = 20;
1174 num_gs_threads = 20;
1175 num_es_threads = 20;
1176 num_hs_threads = 20;
1177 num_ls_threads = 20;
1178 num_ps_stack_entries = 42;
1179 num_vs_stack_entries = 42;
1180 num_gs_stack_entries = 42;
1181 num_es_stack_entries = 42;
1182 num_hs_stack_entries = 42;
1183 num_ls_stack_entries = 42;
1184 break;
1185 case CHIP_JUNIPER:
1186 num_ps_gprs = 93;
1187 num_vs_gprs = 46;
1188 num_temp_gprs = 4;
1189 num_gs_gprs = 31;
1190 num_es_gprs = 31;
1191 num_hs_gprs = 23;
1192 num_ls_gprs = 23;
1193 num_ps_threads = 128;
1194 num_vs_threads = 20;
1195 num_gs_threads = 20;
1196 num_es_threads = 20;
1197 num_hs_threads = 20;
1198 num_ls_threads = 20;
1199 num_ps_stack_entries = 85;
1200 num_vs_stack_entries = 85;
1201 num_gs_stack_entries = 85;
1202 num_es_stack_entries = 85;
1203 num_hs_stack_entries = 85;
1204 num_ls_stack_entries = 85;
1205 break;
1206 case CHIP_CYPRESS:
1207 case CHIP_HEMLOCK:
1208 num_ps_gprs = 93;
1209 num_vs_gprs = 46;
1210 num_temp_gprs = 4;
1211 num_gs_gprs = 31;
1212 num_es_gprs = 31;
1213 num_hs_gprs = 23;
1214 num_ls_gprs = 23;
1215 num_ps_threads = 128;
1216 num_vs_threads = 20;
1217 num_gs_threads = 20;
1218 num_es_threads = 20;
1219 num_hs_threads = 20;
1220 num_ls_threads = 20;
1221 num_ps_stack_entries = 85;
1222 num_vs_stack_entries = 85;
1223 num_gs_stack_entries = 85;
1224 num_es_stack_entries = 85;
1225 num_hs_stack_entries = 85;
1226 num_ls_stack_entries = 85;
1227 break;
1228 case CHIP_PALM:
1229 num_ps_gprs = 93;
1230 num_vs_gprs = 46;
1231 num_temp_gprs = 4;
1232 num_gs_gprs = 31;
1233 num_es_gprs = 31;
1234 num_hs_gprs = 23;
1235 num_ls_gprs = 23;
1236 num_ps_threads = 96;
1237 num_vs_threads = 16;
1238 num_gs_threads = 16;
1239 num_es_threads = 16;
1240 num_hs_threads = 16;
1241 num_ls_threads = 16;
1242 num_ps_stack_entries = 42;
1243 num_vs_stack_entries = 42;
1244 num_gs_stack_entries = 42;
1245 num_es_stack_entries = 42;
1246 num_hs_stack_entries = 42;
1247 num_ls_stack_entries = 42;
1248 break;
1249 case CHIP_SUMO:
1250 num_ps_gprs = 93;
1251 num_vs_gprs = 46;
1252 num_temp_gprs = 4;
1253 num_gs_gprs = 31;
1254 num_es_gprs = 31;
1255 num_hs_gprs = 23;
1256 num_ls_gprs = 23;
1257 num_ps_threads = 96;
1258 num_vs_threads = 25;
1259 num_gs_threads = 25;
1260 num_es_threads = 25;
1261 num_hs_threads = 25;
1262 num_ls_threads = 25;
1263 num_ps_stack_entries = 42;
1264 num_vs_stack_entries = 42;
1265 num_gs_stack_entries = 42;
1266 num_es_stack_entries = 42;
1267 num_hs_stack_entries = 42;
1268 num_ls_stack_entries = 42;
1269 break;
1270 case CHIP_SUMO2:
1271 num_ps_gprs = 93;
1272 num_vs_gprs = 46;
1273 num_temp_gprs = 4;
1274 num_gs_gprs = 31;
1275 num_es_gprs = 31;
1276 num_hs_gprs = 23;
1277 num_ls_gprs = 23;
1278 num_ps_threads = 96;
1279 num_vs_threads = 25;
1280 num_gs_threads = 25;
1281 num_es_threads = 25;
1282 num_hs_threads = 25;
1283 num_ls_threads = 25;
1284 num_ps_stack_entries = 85;
1285 num_vs_stack_entries = 85;
1286 num_gs_stack_entries = 85;
1287 num_es_stack_entries = 85;
1288 num_hs_stack_entries = 85;
1289 num_ls_stack_entries = 85;
1290 break;
1291 case CHIP_BARTS:
1292 num_ps_gprs = 93;
1293 num_vs_gprs = 46;
1294 num_temp_gprs = 4;
1295 num_gs_gprs = 31;
1296 num_es_gprs = 31;
1297 num_hs_gprs = 23;
1298 num_ls_gprs = 23;
1299 num_ps_threads = 128;
1300 num_vs_threads = 20;
1301 num_gs_threads = 20;
1302 num_es_threads = 20;
1303 num_hs_threads = 20;
1304 num_ls_threads = 20;
1305 num_ps_stack_entries = 85;
1306 num_vs_stack_entries = 85;
1307 num_gs_stack_entries = 85;
1308 num_es_stack_entries = 85;
1309 num_hs_stack_entries = 85;
1310 num_ls_stack_entries = 85;
1311 break;
1312 case CHIP_TURKS:
1313 num_ps_gprs = 93;
1314 num_vs_gprs = 46;
1315 num_temp_gprs = 4;
1316 num_gs_gprs = 31;
1317 num_es_gprs = 31;
1318 num_hs_gprs = 23;
1319 num_ls_gprs = 23;
1320 num_ps_threads = 128;
1321 num_vs_threads = 20;
1322 num_gs_threads = 20;
1323 num_es_threads = 20;
1324 num_hs_threads = 20;
1325 num_ls_threads = 20;
1326 num_ps_stack_entries = 42;
1327 num_vs_stack_entries = 42;
1328 num_gs_stack_entries = 42;
1329 num_es_stack_entries = 42;
1330 num_hs_stack_entries = 42;
1331 num_ls_stack_entries = 42;
1332 break;
1333 case CHIP_CAICOS:
1334 num_ps_gprs = 93;
1335 num_vs_gprs = 46;
1336 num_temp_gprs = 4;
1337 num_gs_gprs = 31;
1338 num_es_gprs = 31;
1339 num_hs_gprs = 23;
1340 num_ls_gprs = 23;
1341 num_ps_threads = 128;
1342 num_vs_threads = 10;
1343 num_gs_threads = 10;
1344 num_es_threads = 10;
1345 num_hs_threads = 10;
1346 num_ls_threads = 10;
1347 num_ps_stack_entries = 42;
1348 num_vs_stack_entries = 42;
1349 num_gs_stack_entries = 42;
1350 num_es_stack_entries = 42;
1351 num_hs_stack_entries = 42;
1352 num_ls_stack_entries = 42;
1353 break;
1354 }
1355
1356 tmp = 0x00000000;
1357 switch (family) {
1358 case CHIP_CEDAR:
1359 case CHIP_PALM:
1360 case CHIP_SUMO:
1361 case CHIP_SUMO2:
1362 case CHIP_CAICOS:
1363 break;
1364 default:
1365 tmp |= S_008C00_VC_ENABLE(1);
1366 break;
1367 }
1368 tmp |= S_008C00_EXPORT_SRC_C(1);
1369 tmp |= S_008C00_CS_PRIO(cs_prio);
1370 tmp |= S_008C00_LS_PRIO(ls_prio);
1371 tmp |= S_008C00_HS_PRIO(hs_prio);
1372 tmp |= S_008C00_PS_PRIO(ps_prio);
1373 tmp |= S_008C00_VS_PRIO(vs_prio);
1374 tmp |= S_008C00_GS_PRIO(gs_prio);
1375 tmp |= S_008C00_ES_PRIO(es_prio);
1376 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1377
1378 tmp = 0;
1379 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1380 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1381 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1382 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1383
1384 tmp = 0;
1385 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1386 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1387 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1388
1389 tmp = 0;
1390 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1391 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1392 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1393
1394 tmp = 0;
1395 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1396 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1397 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1398 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1399 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1400
1401 tmp = 0;
1402 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1403 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1404 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1405
1406 tmp = 0;
1407 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1408 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1409 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1410
1411 tmp = 0;
1412 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1413 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1414 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1415
1416 tmp = 0;
1417 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1418 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1419 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1420
1421 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1422 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1423
1424 #if 0
1425 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1426
1427 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1428 #endif
1429 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1430 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1431
1432 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1433 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1435 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1437 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1438
1439 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1440 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1443
1444 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1447 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1448 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1452 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1453 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1454 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1455 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1456 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1459 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1460 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1461 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1462
1463 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1465 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1467 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1468 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1470 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1471 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1472 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1473 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1474 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1475 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1476 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1477 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1478 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1479 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1482 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1484 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1490 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1492 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1493 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1495
1496 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1497
1498 r600_context_pipe_state_set(&rctx->ctx, rstate);
1499 }
1500
1501 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
1502 {
1503 struct r600_pipe_state state;
1504
1505 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
1506 state.nregs = 0;
1507 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1508 float offset_units = rctx->rasterizer->offset_units;
1509 unsigned offset_db_fmt_cntl = 0, depth;
1510
1511 switch (rctx->framebuffer.zsbuf->texture->format) {
1512 case PIPE_FORMAT_Z24X8_UNORM:
1513 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1514 depth = -24;
1515 offset_units *= 2.0f;
1516 break;
1517 case PIPE_FORMAT_Z32_FLOAT:
1518 depth = -23;
1519 offset_units *= 1.0f;
1520 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1521 break;
1522 case PIPE_FORMAT_Z16_UNORM:
1523 depth = -16;
1524 offset_units *= 4.0f;
1525 break;
1526 default:
1527 return;
1528 }
1529 /* FIXME some of those reg can be computed with cso */
1530 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1531 r600_pipe_state_add_reg(&state,
1532 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1533 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1534 r600_pipe_state_add_reg(&state,
1535 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1536 fui(offset_units), 0xFFFFFFFF, NULL);
1537 r600_pipe_state_add_reg(&state,
1538 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1539 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1540 r600_pipe_state_add_reg(&state,
1541 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1542 fui(offset_units), 0xFFFFFFFF, NULL);
1543 r600_pipe_state_add_reg(&state,
1544 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1545 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1546 r600_context_pipe_state_set(&rctx->ctx, &state);
1547 }
1548 }
1549
1550 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1551 {
1552 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1553 struct r600_pipe_state *rstate = &shader->rstate;
1554 struct r600_shader *rshader = &shader->shader;
1555 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1556 int pos_index = -1, face_index = -1;
1557 int ninterp = 0;
1558 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1559 unsigned spi_baryc_cntl;
1560
1561 rstate->nregs = 0;
1562
1563 db_shader_control = 0;
1564 for (i = 0; i < rshader->ninput; i++) {
1565 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1566 POSITION goes via GPRs from the SC so isn't counted */
1567 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1568 pos_index = i;
1569 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1570 face_index = i;
1571 else {
1572 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1573 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1574 ninterp++;
1575 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1576 have_linear = TRUE;
1577 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1578 have_perspective = TRUE;
1579 if (rshader->input[i].centroid)
1580 have_centroid = TRUE;
1581 }
1582 }
1583 for (i = 0; i < rshader->noutput; i++) {
1584 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1585 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1586 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1587 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
1588 }
1589 if (rshader->uses_kill)
1590 db_shader_control |= S_02880C_KILL_ENABLE(1);
1591
1592 exports_ps = 0;
1593 num_cout = 0;
1594 for (i = 0; i < rshader->noutput; i++) {
1595 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1596 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1597 exports_ps |= 1;
1598 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1599 num_cout++;
1600 }
1601 }
1602 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1603 if (!exports_ps) {
1604 /* always at least export 1 component per pixel */
1605 exports_ps = 2;
1606 }
1607
1608 if (ninterp == 0) {
1609 ninterp = 1;
1610 have_perspective = TRUE;
1611 }
1612
1613 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1614 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1615 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1616 spi_input_z = 0;
1617 if (pos_index != -1) {
1618 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1619 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1620 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1621 spi_input_z |= 1;
1622 }
1623
1624 spi_ps_in_control_1 = 0;
1625 if (face_index != -1) {
1626 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1627 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1628 }
1629
1630 spi_baryc_cntl = 0;
1631 if (have_perspective)
1632 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1633 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1634 if (have_linear)
1635 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1636 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1637
1638 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1639 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1640 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1641 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1642 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1643 0, 0xFFFFFFFF, NULL);
1644 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1645 r600_pipe_state_add_reg(rstate,
1646 R_0286E0_SPI_BARYC_CNTL,
1647 spi_baryc_cntl,
1648 0xFFFFFFFF, NULL);
1649
1650 r600_pipe_state_add_reg(rstate,
1651 R_028840_SQ_PGM_START_PS,
1652 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1653 r600_pipe_state_add_reg(rstate,
1654 R_028844_SQ_PGM_RESOURCES_PS,
1655 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1656 S_028844_PRIME_CACHE_ON_DRAW(1) |
1657 S_028844_STACK_SIZE(rshader->bc.nstack),
1658 0xFFFFFFFF, NULL);
1659 r600_pipe_state_add_reg(rstate,
1660 R_028848_SQ_PGM_RESOURCES_2_PS,
1661 0x0, 0xFFFFFFFF, NULL);
1662 r600_pipe_state_add_reg(rstate,
1663 R_02884C_SQ_PGM_EXPORTS_PS,
1664 exports_ps, 0xFFFFFFFF, NULL);
1665 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
1666 /* only set some bits here, the other bits are set in the dsa state */
1667 r600_pipe_state_add_reg(rstate,
1668 R_02880C_DB_SHADER_CONTROL,
1669 db_shader_control,
1670 S_02880C_Z_EXPORT_ENABLE(1) |
1671 S_02880C_STENCIL_EXPORT_ENABLE(1) |
1672 S_02880C_KILL_ENABLE(1),
1673 NULL);
1674 r600_pipe_state_add_reg(rstate,
1675 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1676 0xFFFFFFFF, NULL);
1677 }
1678
1679 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1680 {
1681 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1682 struct r600_pipe_state *rstate = &shader->rstate;
1683 struct r600_shader *rshader = &shader->shader;
1684 unsigned spi_vs_out_id[10];
1685 unsigned i, tmp;
1686
1687 /* clear previous register */
1688 rstate->nregs = 0;
1689
1690 /* so far never got proper semantic id from tgsi */
1691 for (i = 0; i < 10; i++) {
1692 spi_vs_out_id[i] = 0;
1693 }
1694 for (i = 0; i < 32; i++) {
1695 tmp = i << ((i & 3) * 8);
1696 spi_vs_out_id[i / 4] |= tmp;
1697 }
1698 for (i = 0; i < 10; i++) {
1699 r600_pipe_state_add_reg(rstate,
1700 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1701 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1702 }
1703
1704 r600_pipe_state_add_reg(rstate,
1705 R_0286C4_SPI_VS_OUT_CONFIG,
1706 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1707 0xFFFFFFFF, NULL);
1708 r600_pipe_state_add_reg(rstate,
1709 R_028860_SQ_PGM_RESOURCES_VS,
1710 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1711 S_028860_STACK_SIZE(rshader->bc.nstack),
1712 0xFFFFFFFF, NULL);
1713 r600_pipe_state_add_reg(rstate,
1714 R_028864_SQ_PGM_RESOURCES_2_VS,
1715 0x0, 0xFFFFFFFF, NULL);
1716 r600_pipe_state_add_reg(rstate,
1717 R_02885C_SQ_PGM_START_VS,
1718 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1719
1720 r600_pipe_state_add_reg(rstate,
1721 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1722 0xFFFFFFFF, NULL);
1723 }
1724
1725 void evergreen_fetch_shader(struct pipe_context *ctx,
1726 struct r600_vertex_element *ve)
1727 {
1728 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1729 struct r600_pipe_state *rstate = &ve->rstate;
1730 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1731 rstate->nregs = 0;
1732 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
1733 0x00000000, 0xFFFFFFFF, NULL);
1734 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
1735 (r600_bo_offset(ve->fetch_shader)) >> 8,
1736 0xFFFFFFFF, ve->fetch_shader);
1737 }
1738
1739 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1740 {
1741 struct pipe_depth_stencil_alpha_state dsa;
1742 struct r600_pipe_state *rstate;
1743
1744 memset(&dsa, 0, sizeof(dsa));
1745
1746 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1747 r600_pipe_state_add_reg(rstate,
1748 R_02880C_DB_SHADER_CONTROL,
1749 0x0,
1750 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1751 r600_pipe_state_add_reg(rstate,
1752 R_028000_DB_RENDER_CONTROL,
1753 S_028000_DEPTH_COPY_ENABLE(1) |
1754 S_028000_STENCIL_COPY_ENABLE(1) |
1755 S_028000_COPY_CENTROID(1),
1756 S_028000_DEPTH_COPY_ENABLE(1) |
1757 S_028000_STENCIL_COPY_ENABLE(1) |
1758 S_028000_COPY_CENTROID(1), NULL);
1759 return rstate;
1760 }
1761
1762 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
1763 struct r600_pipe_resource_state *rstate)
1764 {
1765 rstate->id = R600_PIPE_STATE_RESOURCE;
1766
1767 rstate->val[0] = 0;
1768 rstate->bo[0] = NULL;
1769 rstate->val[1] = 0;
1770 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
1771 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1772 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1773 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1774 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
1775 rstate->val[4] = 0;
1776 rstate->val[5] = 0;
1777 rstate->val[6] = 0;
1778 rstate->val[7] = 0xc0000000;
1779 }
1780
1781
1782 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
1783 struct r600_resource *rbuffer,
1784 unsigned offset, unsigned stride)
1785 {
1786 rstate->bo[0] = rbuffer->bo;
1787 rstate->val[0] = offset;
1788 rstate->val[1] = rbuffer->bo_size - offset - 1;
1789 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1790 S_030008_STRIDE(stride);
1791 }