2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "evergreend.h"
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
33 static uint32_t eg_num_banks(uint32_t nbanks
)
49 static unsigned eg_tile_split(unsigned tile_split
)
52 case 64: tile_split
= 0; break;
53 case 128: tile_split
= 1; break;
54 case 256: tile_split
= 2; break;
55 case 512: tile_split
= 3; break;
57 case 1024: tile_split
= 4; break;
58 case 2048: tile_split
= 5; break;
59 case 4096: tile_split
= 6; break;
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
66 switch (macro_tile_aspect
) {
68 case 1: macro_tile_aspect
= 0; break;
69 case 2: macro_tile_aspect
= 1; break;
70 case 4: macro_tile_aspect
= 2; break;
71 case 8: macro_tile_aspect
= 3; break;
73 return macro_tile_aspect
;
76 static unsigned eg_bank_wh(unsigned bankwh
)
80 case 1: bankwh
= 0; break;
81 case 2: bankwh
= 1; break;
82 case 4: bankwh
= 2; break;
83 case 8: bankwh
= 3; break;
88 static uint32_t r600_translate_blend_function(int blend_func
)
92 return V_028780_COMB_DST_PLUS_SRC
;
93 case PIPE_BLEND_SUBTRACT
:
94 return V_028780_COMB_SRC_MINUS_DST
;
95 case PIPE_BLEND_REVERSE_SUBTRACT
:
96 return V_028780_COMB_DST_MINUS_SRC
;
98 return V_028780_COMB_MIN_DST_SRC
;
100 return V_028780_COMB_MAX_DST_SRC
;
102 R600_ERR("Unknown blend function %d\n", blend_func
);
109 static uint32_t r600_translate_blend_factor(int blend_fact
)
111 switch (blend_fact
) {
112 case PIPE_BLENDFACTOR_ONE
:
113 return V_028780_BLEND_ONE
;
114 case PIPE_BLENDFACTOR_SRC_COLOR
:
115 return V_028780_BLEND_SRC_COLOR
;
116 case PIPE_BLENDFACTOR_SRC_ALPHA
:
117 return V_028780_BLEND_SRC_ALPHA
;
118 case PIPE_BLENDFACTOR_DST_ALPHA
:
119 return V_028780_BLEND_DST_ALPHA
;
120 case PIPE_BLENDFACTOR_DST_COLOR
:
121 return V_028780_BLEND_DST_COLOR
;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
124 case PIPE_BLENDFACTOR_CONST_COLOR
:
125 return V_028780_BLEND_CONST_COLOR
;
126 case PIPE_BLENDFACTOR_CONST_ALPHA
:
127 return V_028780_BLEND_CONST_ALPHA
;
128 case PIPE_BLENDFACTOR_ZERO
:
129 return V_028780_BLEND_ZERO
;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
142 case PIPE_BLENDFACTOR_SRC1_COLOR
:
143 return V_028780_BLEND_SRC1_COLOR
;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
145 return V_028780_BLEND_SRC1_ALPHA
;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
147 return V_028780_BLEND_INV_SRC1_COLOR
;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
149 return V_028780_BLEND_INV_SRC1_ALPHA
;
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
158 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
162 case PIPE_TEXTURE_1D
:
163 return V_030000_SQ_TEX_DIM_1D
;
164 case PIPE_TEXTURE_1D_ARRAY
:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
166 case PIPE_TEXTURE_2D
:
167 case PIPE_TEXTURE_RECT
:
168 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
169 V_030000_SQ_TEX_DIM_2D
;
170 case PIPE_TEXTURE_2D_ARRAY
:
171 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
172 V_030000_SQ_TEX_DIM_2D_ARRAY
;
173 case PIPE_TEXTURE_3D
:
174 return V_030000_SQ_TEX_DIM_3D
;
175 case PIPE_TEXTURE_CUBE
:
176 return V_030000_SQ_TEX_DIM_CUBEMAP
;
180 static uint32_t r600_translate_dbformat(enum pipe_format format
)
183 case PIPE_FORMAT_Z16_UNORM
:
184 return V_028040_Z_16
;
185 case PIPE_FORMAT_Z24X8_UNORM
:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
187 return V_028040_Z_24
;
188 case PIPE_FORMAT_Z32_FLOAT
:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
190 return V_028040_Z_32_FLOAT
;
196 static uint32_t r600_translate_colorswap(enum pipe_format format
)
200 case PIPE_FORMAT_L4A4_UNORM
:
201 case PIPE_FORMAT_A4R4_UNORM
:
202 return V_028C70_SWAP_ALT
;
204 case PIPE_FORMAT_A8_UNORM
:
205 case PIPE_FORMAT_A8_SNORM
:
206 case PIPE_FORMAT_A8_UINT
:
207 case PIPE_FORMAT_A8_SINT
:
208 case PIPE_FORMAT_A16_UNORM
:
209 case PIPE_FORMAT_A16_SNORM
:
210 case PIPE_FORMAT_A16_UINT
:
211 case PIPE_FORMAT_A16_SINT
:
212 case PIPE_FORMAT_A16_FLOAT
:
213 case PIPE_FORMAT_A32_UINT
:
214 case PIPE_FORMAT_A32_SINT
:
215 case PIPE_FORMAT_A32_FLOAT
:
216 case PIPE_FORMAT_R4A4_UNORM
:
217 return V_028C70_SWAP_ALT_REV
;
218 case PIPE_FORMAT_I8_UNORM
:
219 case PIPE_FORMAT_I8_SNORM
:
220 case PIPE_FORMAT_I8_UINT
:
221 case PIPE_FORMAT_I8_SINT
:
222 case PIPE_FORMAT_I16_UNORM
:
223 case PIPE_FORMAT_I16_SNORM
:
224 case PIPE_FORMAT_I16_UINT
:
225 case PIPE_FORMAT_I16_SINT
:
226 case PIPE_FORMAT_I16_FLOAT
:
227 case PIPE_FORMAT_I32_UINT
:
228 case PIPE_FORMAT_I32_SINT
:
229 case PIPE_FORMAT_I32_FLOAT
:
230 case PIPE_FORMAT_L8_UNORM
:
231 case PIPE_FORMAT_L8_SNORM
:
232 case PIPE_FORMAT_L8_UINT
:
233 case PIPE_FORMAT_L8_SINT
:
234 case PIPE_FORMAT_L8_SRGB
:
235 case PIPE_FORMAT_L16_UNORM
:
236 case PIPE_FORMAT_L16_SNORM
:
237 case PIPE_FORMAT_L16_UINT
:
238 case PIPE_FORMAT_L16_SINT
:
239 case PIPE_FORMAT_L16_FLOAT
:
240 case PIPE_FORMAT_L32_UINT
:
241 case PIPE_FORMAT_L32_SINT
:
242 case PIPE_FORMAT_L32_FLOAT
:
243 case PIPE_FORMAT_R8_UNORM
:
244 case PIPE_FORMAT_R8_SNORM
:
245 case PIPE_FORMAT_R8_UINT
:
246 case PIPE_FORMAT_R8_SINT
:
247 return V_028C70_SWAP_STD
;
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM
:
251 return V_028C70_SWAP_STD_REV
;
253 case PIPE_FORMAT_B5G5R5A1_UNORM
:
254 case PIPE_FORMAT_B5G5R5X1_UNORM
:
255 return V_028C70_SWAP_ALT
;
257 case PIPE_FORMAT_B4G4R4A4_UNORM
:
258 case PIPE_FORMAT_B4G4R4X4_UNORM
:
259 return V_028C70_SWAP_ALT
;
261 case PIPE_FORMAT_Z16_UNORM
:
262 return V_028C70_SWAP_STD
;
264 case PIPE_FORMAT_L8A8_UNORM
:
265 case PIPE_FORMAT_L8A8_SNORM
:
266 case PIPE_FORMAT_L8A8_UINT
:
267 case PIPE_FORMAT_L8A8_SINT
:
268 case PIPE_FORMAT_L8A8_SRGB
:
269 case PIPE_FORMAT_L16A16_UNORM
:
270 case PIPE_FORMAT_L16A16_SNORM
:
271 case PIPE_FORMAT_L16A16_UINT
:
272 case PIPE_FORMAT_L16A16_SINT
:
273 case PIPE_FORMAT_L16A16_FLOAT
:
274 case PIPE_FORMAT_L32A32_UINT
:
275 case PIPE_FORMAT_L32A32_SINT
:
276 case PIPE_FORMAT_L32A32_FLOAT
:
277 return V_028C70_SWAP_ALT
;
278 case PIPE_FORMAT_R8G8_UNORM
:
279 case PIPE_FORMAT_R8G8_SNORM
:
280 case PIPE_FORMAT_R8G8_UINT
:
281 case PIPE_FORMAT_R8G8_SINT
:
282 return V_028C70_SWAP_STD
;
284 case PIPE_FORMAT_R16_UNORM
:
285 case PIPE_FORMAT_R16_SNORM
:
286 case PIPE_FORMAT_R16_UINT
:
287 case PIPE_FORMAT_R16_SINT
:
288 case PIPE_FORMAT_R16_FLOAT
:
289 return V_028C70_SWAP_STD
;
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB
:
293 return V_028C70_SWAP_STD_REV
;
294 case PIPE_FORMAT_B8G8R8A8_SRGB
:
295 return V_028C70_SWAP_ALT
;
297 case PIPE_FORMAT_B8G8R8A8_UNORM
:
298 case PIPE_FORMAT_B8G8R8X8_UNORM
:
299 return V_028C70_SWAP_ALT
;
301 case PIPE_FORMAT_A8R8G8B8_UNORM
:
302 case PIPE_FORMAT_X8R8G8B8_UNORM
:
303 return V_028C70_SWAP_ALT_REV
;
304 case PIPE_FORMAT_R8G8B8A8_SNORM
:
305 case PIPE_FORMAT_R8G8B8A8_UNORM
:
306 case PIPE_FORMAT_R8G8B8A8_SINT
:
307 case PIPE_FORMAT_R8G8B8A8_UINT
:
308 case PIPE_FORMAT_R8G8B8X8_UNORM
:
309 return V_028C70_SWAP_STD
;
311 case PIPE_FORMAT_A8B8G8R8_UNORM
:
312 case PIPE_FORMAT_X8B8G8R8_UNORM
:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV
;
316 case PIPE_FORMAT_Z24X8_UNORM
:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
318 return V_028C70_SWAP_STD
;
320 case PIPE_FORMAT_X8Z24_UNORM
:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
322 return V_028C70_SWAP_STD
;
324 case PIPE_FORMAT_R10G10B10A2_UNORM
:
325 case PIPE_FORMAT_R10G10B10X2_SNORM
:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
327 return V_028C70_SWAP_STD
;
329 case PIPE_FORMAT_B10G10R10A2_UNORM
:
330 case PIPE_FORMAT_B10G10R10A2_UINT
:
331 return V_028C70_SWAP_ALT
;
333 case PIPE_FORMAT_R11G11B10_FLOAT
:
334 case PIPE_FORMAT_R32_FLOAT
:
335 case PIPE_FORMAT_R32_UINT
:
336 case PIPE_FORMAT_R32_SINT
:
337 case PIPE_FORMAT_Z32_FLOAT
:
338 case PIPE_FORMAT_R16G16_FLOAT
:
339 case PIPE_FORMAT_R16G16_UNORM
:
340 case PIPE_FORMAT_R16G16_SNORM
:
341 case PIPE_FORMAT_R16G16_UINT
:
342 case PIPE_FORMAT_R16G16_SINT
:
343 return V_028C70_SWAP_STD
;
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT
:
347 case PIPE_FORMAT_R32G32_UINT
:
348 case PIPE_FORMAT_R32G32_SINT
:
349 case PIPE_FORMAT_R16G16B16A16_UNORM
:
350 case PIPE_FORMAT_R16G16B16A16_SNORM
:
351 case PIPE_FORMAT_R16G16B16A16_UINT
:
352 case PIPE_FORMAT_R16G16B16A16_SINT
:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
358 case PIPE_FORMAT_R32G32B32A32_SNORM
:
359 case PIPE_FORMAT_R32G32B32A32_UNORM
:
360 case PIPE_FORMAT_R32G32B32A32_SINT
:
361 case PIPE_FORMAT_R32G32B32A32_UINT
:
362 return V_028C70_SWAP_STD
;
364 R600_ERR("unsupported colorswap format %d\n", format
);
370 static uint32_t r600_translate_colorformat(enum pipe_format format
)
374 case PIPE_FORMAT_A8_UNORM
:
375 case PIPE_FORMAT_A8_SNORM
:
376 case PIPE_FORMAT_A8_UINT
:
377 case PIPE_FORMAT_A8_SINT
:
378 case PIPE_FORMAT_I8_UNORM
:
379 case PIPE_FORMAT_I8_SNORM
:
380 case PIPE_FORMAT_I8_UINT
:
381 case PIPE_FORMAT_I8_SINT
:
382 case PIPE_FORMAT_L8_UNORM
:
383 case PIPE_FORMAT_L8_SNORM
:
384 case PIPE_FORMAT_L8_UINT
:
385 case PIPE_FORMAT_L8_SINT
:
386 case PIPE_FORMAT_L8_SRGB
:
387 case PIPE_FORMAT_R8_UNORM
:
388 case PIPE_FORMAT_R8_SNORM
:
389 case PIPE_FORMAT_R8_UINT
:
390 case PIPE_FORMAT_R8_SINT
:
391 return V_028C70_COLOR_8
;
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM
:
395 return V_028C70_COLOR_5_6_5
;
397 case PIPE_FORMAT_B5G5R5A1_UNORM
:
398 case PIPE_FORMAT_B5G5R5X1_UNORM
:
399 return V_028C70_COLOR_1_5_5_5
;
401 case PIPE_FORMAT_B4G4R4A4_UNORM
:
402 case PIPE_FORMAT_B4G4R4X4_UNORM
:
403 return V_028C70_COLOR_4_4_4_4
;
405 case PIPE_FORMAT_Z16_UNORM
:
406 return V_028C70_COLOR_16
;
408 case PIPE_FORMAT_L8A8_UNORM
:
409 case PIPE_FORMAT_L8A8_SNORM
:
410 case PIPE_FORMAT_L8A8_UINT
:
411 case PIPE_FORMAT_L8A8_SINT
:
412 case PIPE_FORMAT_L8A8_SRGB
:
413 case PIPE_FORMAT_R8G8_UNORM
:
414 case PIPE_FORMAT_R8G8_SNORM
:
415 case PIPE_FORMAT_R8G8_UINT
:
416 case PIPE_FORMAT_R8G8_SINT
:
417 return V_028C70_COLOR_8_8
;
419 case PIPE_FORMAT_R16_UNORM
:
420 case PIPE_FORMAT_R16_SNORM
:
421 case PIPE_FORMAT_R16_UINT
:
422 case PIPE_FORMAT_R16_SINT
:
423 case PIPE_FORMAT_A16_UNORM
:
424 case PIPE_FORMAT_A16_SNORM
:
425 case PIPE_FORMAT_A16_UINT
:
426 case PIPE_FORMAT_A16_SINT
:
427 case PIPE_FORMAT_L16_UNORM
:
428 case PIPE_FORMAT_L16_SNORM
:
429 case PIPE_FORMAT_L16_UINT
:
430 case PIPE_FORMAT_L16_SINT
:
431 case PIPE_FORMAT_I16_UNORM
:
432 case PIPE_FORMAT_I16_SNORM
:
433 case PIPE_FORMAT_I16_UINT
:
434 case PIPE_FORMAT_I16_SINT
:
435 return V_028C70_COLOR_16
;
437 case PIPE_FORMAT_R16_FLOAT
:
438 case PIPE_FORMAT_A16_FLOAT
:
439 case PIPE_FORMAT_L16_FLOAT
:
440 case PIPE_FORMAT_I16_FLOAT
:
441 return V_028C70_COLOR_16_FLOAT
;
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB
:
445 case PIPE_FORMAT_A8B8G8R8_UNORM
:
446 case PIPE_FORMAT_A8R8G8B8_UNORM
:
447 case PIPE_FORMAT_B8G8R8A8_SRGB
:
448 case PIPE_FORMAT_B8G8R8A8_UNORM
:
449 case PIPE_FORMAT_B8G8R8X8_UNORM
:
450 case PIPE_FORMAT_R8G8B8A8_SNORM
:
451 case PIPE_FORMAT_R8G8B8A8_UNORM
:
452 case PIPE_FORMAT_R8G8B8X8_UNORM
:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
454 case PIPE_FORMAT_X8B8G8R8_UNORM
:
455 case PIPE_FORMAT_X8R8G8B8_UNORM
:
456 case PIPE_FORMAT_R8G8B8_UNORM
:
457 case PIPE_FORMAT_R8G8B8A8_SINT
:
458 case PIPE_FORMAT_R8G8B8A8_UINT
:
459 return V_028C70_COLOR_8_8_8_8
;
461 case PIPE_FORMAT_R10G10B10A2_UNORM
:
462 case PIPE_FORMAT_R10G10B10X2_SNORM
:
463 case PIPE_FORMAT_B10G10R10A2_UNORM
:
464 case PIPE_FORMAT_B10G10R10A2_UINT
:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
466 return V_028C70_COLOR_2_10_10_10
;
468 case PIPE_FORMAT_Z24X8_UNORM
:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
470 return V_028C70_COLOR_8_24
;
472 case PIPE_FORMAT_X8Z24_UNORM
:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
474 return V_028C70_COLOR_24_8
;
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
477 return V_028C70_COLOR_X24_8_32_FLOAT
;
479 case PIPE_FORMAT_R32_UINT
:
480 case PIPE_FORMAT_R32_SINT
:
481 case PIPE_FORMAT_A32_UINT
:
482 case PIPE_FORMAT_A32_SINT
:
483 case PIPE_FORMAT_L32_UINT
:
484 case PIPE_FORMAT_L32_SINT
:
485 case PIPE_FORMAT_I32_UINT
:
486 case PIPE_FORMAT_I32_SINT
:
487 return V_028C70_COLOR_32
;
489 case PIPE_FORMAT_R32_FLOAT
:
490 case PIPE_FORMAT_A32_FLOAT
:
491 case PIPE_FORMAT_L32_FLOAT
:
492 case PIPE_FORMAT_I32_FLOAT
:
493 case PIPE_FORMAT_Z32_FLOAT
:
494 return V_028C70_COLOR_32_FLOAT
;
496 case PIPE_FORMAT_R16G16_FLOAT
:
497 case PIPE_FORMAT_L16A16_FLOAT
:
498 return V_028C70_COLOR_16_16_FLOAT
;
500 case PIPE_FORMAT_R16G16_UNORM
:
501 case PIPE_FORMAT_R16G16_SNORM
:
502 case PIPE_FORMAT_R16G16_UINT
:
503 case PIPE_FORMAT_R16G16_SINT
:
504 case PIPE_FORMAT_L16A16_UNORM
:
505 case PIPE_FORMAT_L16A16_SNORM
:
506 case PIPE_FORMAT_L16A16_UINT
:
507 case PIPE_FORMAT_L16A16_SINT
:
508 return V_028C70_COLOR_16_16
;
510 case PIPE_FORMAT_R11G11B10_FLOAT
:
511 return V_028C70_COLOR_10_11_11_FLOAT
;
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT
:
515 case PIPE_FORMAT_R16G16B16A16_SINT
:
516 case PIPE_FORMAT_R16G16B16A16_UNORM
:
517 case PIPE_FORMAT_R16G16B16A16_SNORM
:
518 return V_028C70_COLOR_16_16_16_16
;
520 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
521 return V_028C70_COLOR_16_16_16_16_FLOAT
;
523 case PIPE_FORMAT_R32G32_FLOAT
:
524 case PIPE_FORMAT_L32A32_FLOAT
:
525 return V_028C70_COLOR_32_32_FLOAT
;
527 case PIPE_FORMAT_R32G32_SINT
:
528 case PIPE_FORMAT_R32G32_UINT
:
529 case PIPE_FORMAT_L32A32_UINT
:
530 case PIPE_FORMAT_L32A32_SINT
:
531 return V_028C70_COLOR_32_32
;
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM
:
535 case PIPE_FORMAT_R32G32B32A32_UNORM
:
536 case PIPE_FORMAT_R32G32B32A32_SINT
:
537 case PIPE_FORMAT_R32G32B32A32_UINT
:
538 return V_028C70_COLOR_32_32_32_32
;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
540 return V_028C70_COLOR_32_32_32_32_FLOAT
;
543 case PIPE_FORMAT_UYVY
:
544 case PIPE_FORMAT_YUYV
:
546 return ~0U; /* Unsupported. */
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
552 if (R600_BIG_ENDIAN
) {
553 switch(colorformat
) {
556 case V_028C70_COLOR_8
:
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5
:
561 case V_028C70_COLOR_1_5_5_5
:
562 case V_028C70_COLOR_4_4_4_4
:
563 case V_028C70_COLOR_16
:
564 case V_028C70_COLOR_8_8
:
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8
:
569 case V_028C70_COLOR_2_10_10_10
:
570 case V_028C70_COLOR_8_24
:
571 case V_028C70_COLOR_24_8
:
572 case V_028C70_COLOR_32_FLOAT
:
573 case V_028C70_COLOR_16_16_FLOAT
:
574 case V_028C70_COLOR_16_16
:
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16
:
579 case V_028C70_COLOR_16_16_16_16_FLOAT
:
582 case V_028C70_COLOR_32_32_FLOAT
:
583 case V_028C70_COLOR_32_32
:
584 case V_028C70_COLOR_X24_8_32_FLOAT
:
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT
:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT
:
591 case V_028C70_COLOR_32_32_32_32
:
594 return ENDIAN_NONE
; /* Unsupported. */
601 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
603 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
608 return r600_translate_colorformat(format
) != ~0U &&
609 r600_translate_colorswap(format
) != ~0U;
612 static bool r600_is_zs_format_supported(enum pipe_format format
)
614 return r600_translate_dbformat(format
) != ~0U;
617 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
618 enum pipe_format format
,
619 enum pipe_texture_target target
,
620 unsigned sample_count
,
623 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
626 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
627 R600_ERR("r600: unsupported texture type %d\n", target
);
631 if (!util_format_is_supported(format
, usage
))
634 if (sample_count
> 1) {
635 if (rscreen
->info
.drm_minor
< 19)
638 if (rscreen
->chip_class
!= EVERGREEN
)
641 switch (sample_count
) {
650 /* require render-target support for multisample resources */
651 if (util_format_is_depth_or_stencil(format
)) {
652 usage
|= PIPE_BIND_DEPTH_STENCIL
;
654 usage
|= PIPE_BIND_RENDER_TARGET
;
658 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
659 r600_is_sampler_format_supported(screen
, format
)) {
660 retval
|= PIPE_BIND_SAMPLER_VIEW
;
663 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
664 PIPE_BIND_DISPLAY_TARGET
|
666 PIPE_BIND_SHARED
)) &&
667 r600_is_colorbuffer_format_supported(format
)) {
669 (PIPE_BIND_RENDER_TARGET
|
670 PIPE_BIND_DISPLAY_TARGET
|
675 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
676 r600_is_zs_format_supported(format
)) {
677 retval
|= PIPE_BIND_DEPTH_STENCIL
;
680 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
681 r600_is_vertex_format_supported(format
)) {
682 retval
|= PIPE_BIND_VERTEX_BUFFER
;
685 if (usage
& PIPE_BIND_TRANSFER_READ
)
686 retval
|= PIPE_BIND_TRANSFER_READ
;
687 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
688 retval
|= PIPE_BIND_TRANSFER_WRITE
;
690 return retval
== usage
;
693 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
694 const struct pipe_blend_state
*state
, int mode
)
696 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
697 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
698 struct r600_pipe_state
*rstate
;
699 uint32_t color_control
= 0, target_mask
;
700 /* XXX there is more then 8 framebuffer */
701 unsigned blend_cntl
[8];
707 rstate
= &blend
->rstate
;
709 rstate
->id
= R600_PIPE_STATE_BLEND
;
712 if (state
->logicop_enable
) {
713 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
715 color_control
|= (0xcc << 16);
717 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
718 if (state
->independent_blend_enable
) {
719 for (int i
= 0; i
< 8; i
++) {
720 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
723 for (int i
= 0; i
< 8; i
++) {
724 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
727 blend
->cb_target_mask
= target_mask
;
730 color_control
|= S_028808_MODE(mode
);
732 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
734 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
736 /* only have dual source on MRT0 */
737 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
738 for (int i
= 0; i
< 8; i
++) {
739 /* state->rt entries > 0 only written if independent blending */
740 const int j
= state
->independent_blend_enable
? i
: 0;
742 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
743 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
744 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
745 unsigned eqA
= state
->rt
[j
].alpha_func
;
746 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
747 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
750 if (!state
->rt
[j
].blend_enable
)
753 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
754 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
755 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
756 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
758 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
759 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
760 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
761 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
762 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
765 for (int i
= 0; i
< 8; i
++) {
766 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
]);
769 r600_pipe_state_add_reg(rstate
, R_028B70_DB_ALPHA_TO_MASK
,
770 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
771 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
772 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
773 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
774 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
776 blend
->alpha_to_one
= state
->alpha_to_one
;
780 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
781 const struct pipe_blend_state
*state
)
784 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
787 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
788 const struct pipe_depth_stencil_alpha_state
*state
)
790 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
791 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
792 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
793 struct r600_pipe_state
*rstate
;
799 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
800 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
801 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
802 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
804 rstate
= &dsa
->rstate
;
806 rstate
->id
= R600_PIPE_STATE_DSA
;
807 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
808 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
809 S_028800_ZFUNC(state
->depth
.func
);
812 if (state
->stencil
[0].enabled
) {
813 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
814 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
815 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
816 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
817 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
819 if (state
->stencil
[1].enabled
) {
820 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
821 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
822 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
823 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
824 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
829 alpha_test_control
= 0;
831 if (state
->alpha
.enabled
) {
832 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
833 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
834 alpha_ref
= fui(state
->alpha
.ref_value
);
836 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
837 dsa
->alpha_ref
= alpha_ref
;
840 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
844 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
845 const struct pipe_rasterizer_state
*state
)
847 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
848 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
849 struct r600_pipe_state
*rstate
;
851 unsigned prov_vtx
= 1, polygon_dual_mode
;
852 float psize_min
, psize_max
;
858 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
859 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
861 if (state
->flatshade_first
)
864 rstate
= &rs
->rstate
;
865 rs
->flatshade
= state
->flatshade
;
866 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
867 rs
->two_side
= state
->light_twoside
;
868 rs
->clip_plane_enable
= state
->clip_plane_enable
;
869 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
870 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
871 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
872 rs
->pa_cl_clip_cntl
=
873 S_028810_PS_UCP_MODE(3) |
874 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
875 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
876 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
877 rs
->multisample_enable
= state
->multisample
;
880 rs
->offset_units
= state
->offset_units
;
881 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
883 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
884 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
885 if (state
->sprite_coord_enable
) {
886 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
887 S_0286D4_PNT_SPRITE_OVRD_X(2) |
888 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
889 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
890 S_0286D4_PNT_SPRITE_OVRD_W(1);
891 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
892 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
895 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
897 /* point size 12.4 fixed point */
898 tmp
= (unsigned)(state
->point_size
* 8.0);
899 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
901 if (state
->point_size_per_vertex
) {
902 psize_min
= util_get_min_point_size(state
);
905 /* Force the point size to be as if the vertex output was disabled. */
906 psize_min
= state
->point_size
;
907 psize_max
= state
->point_size
;
909 /* Divide by two, because 0.5 = 1 pixel. */
910 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
,
911 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
912 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
914 tmp
= (unsigned)state
->line_width
* 8;
915 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
916 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
,
917 S_028A48_MSAA_ENABLE(state
->multisample
) |
918 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
919 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
921 if (rctx
->chip_class
== CAYMAN
) {
922 r600_pipe_state_add_reg(rstate
, CM_R_028BE4_PA_SU_VTX_CNTL
,
923 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
));
925 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
926 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
));
928 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
929 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
930 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
931 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
932 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
933 S_028814_FACE(!state
->front_ccw
) |
934 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
935 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
936 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
937 S_028814_POLY_MODE(polygon_dual_mode
) |
938 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
939 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
940 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
944 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
945 const struct pipe_sampler_state
*state
)
947 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
949 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
955 /* directly into sampler avoid r6xx code to emit useless reg */
956 ss
->seamless_cube_map
= false;
957 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
958 ss
->border_color_use
= false;
959 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
960 ss
->tex_sampler_words
[0] = S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
961 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
962 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
963 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
964 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
965 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
966 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
967 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
968 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
969 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
970 ss
->tex_sampler_words
[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
971 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
972 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
973 ss
->tex_sampler_words
[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
974 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
977 ss
->border_color_use
= true;
978 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
979 ss
->border_color
[0] = fui(state
->border_color
.f
[0]);
980 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
981 ss
->border_color
[1] = fui(state
->border_color
.f
[1]);
982 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
983 ss
->border_color
[2] = fui(state
->border_color
.f
[2]);
984 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
985 ss
->border_color
[3] = fui(state
->border_color
.f
[3]);
990 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
991 struct pipe_resource
*texture
,
992 const struct pipe_sampler_view
*state
)
994 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
995 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
996 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
997 unsigned format
, endian
;
998 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
999 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
1000 unsigned height
, depth
, width
;
1001 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1006 /* initialize base object */
1007 view
->base
= *state
;
1008 view
->base
.texture
= NULL
;
1009 pipe_reference(NULL
, &texture
->reference
);
1010 view
->base
.texture
= texture
;
1011 view
->base
.reference
.count
= 1;
1012 view
->base
.context
= ctx
;
1014 swizzle
[0] = state
->swizzle_r
;
1015 swizzle
[1] = state
->swizzle_g
;
1016 swizzle
[2] = state
->swizzle_b
;
1017 swizzle
[3] = state
->swizzle_a
;
1019 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1021 &word4
, &yuv_format
);
1022 assert(format
!= ~0);
1028 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1029 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
1033 tmp
= tmp
->flushed_depth_texture
;
1036 endian
= r600_colorformat_endian_swap(format
);
1038 width
= tmp
->surface
.level
[0].npix_x
;
1039 height
= tmp
->surface
.level
[0].npix_y
;
1040 depth
= tmp
->surface
.level
[0].npix_z
;
1041 pitch
= tmp
->surface
.level
[0].nblk_x
* util_format_get_blockwidth(state
->format
);
1042 tile_type
= tmp
->tile_type
;
1044 switch (tmp
->surface
.level
[0].mode
) {
1045 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1046 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
1048 case RADEON_SURF_MODE_2D
:
1049 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1051 case RADEON_SURF_MODE_1D
:
1052 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1054 case RADEON_SURF_MODE_LINEAR
:
1056 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
1059 tile_split
= tmp
->surface
.tile_split
;
1060 macro_aspect
= tmp
->surface
.mtilea
;
1061 bankw
= tmp
->surface
.bankw
;
1062 bankh
= tmp
->surface
.bankh
;
1063 tile_split
= eg_tile_split(tile_split
);
1064 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1065 bankw
= eg_bank_wh(bankw
);
1066 bankh
= eg_bank_wh(bankh
);
1068 /* 128 bit formats require tile type = 1 */
1069 if (rscreen
->chip_class
== CAYMAN
) {
1070 if (util_format_get_blocksize(state
->format
) >= 16)
1073 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1075 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1077 depth
= texture
->array_size
;
1078 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1079 depth
= texture
->array_size
;
1082 view
->tex_resource
= &tmp
->resource
;
1083 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1084 S_030000_PITCH((pitch
/ 8) - 1) |
1085 S_030000_TEX_WIDTH(width
- 1));
1086 if (rscreen
->chip_class
== CAYMAN
)
1087 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type
);
1089 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type
);
1090 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1091 S_030004_TEX_DEPTH(depth
- 1) |
1092 S_030004_ARRAY_MODE(array_mode
));
1093 view
->tex_resource_words
[2] = (tmp
->offset
[0] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1094 if (state
->u
.tex
.last_level
&& texture
->nr_samples
<= 1) {
1095 view
->tex_resource_words
[3] = (tmp
->offset
[1] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1097 view
->tex_resource_words
[3] = (tmp
->offset
[0] + r600_resource_va(ctx
->screen
, texture
)) >> 8;
1099 view
->tex_resource_words
[4] = (word4
|
1100 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1101 S_030010_ENDIAN_SWAP(endian
));
1102 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1103 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
1104 if (texture
->nr_samples
> 1) {
1105 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1106 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
1108 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(state
->u
.tex
.first_level
);
1109 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(state
->u
.tex
.last_level
);
1111 /* aniso max 16 samples */
1112 view
->tex_resource_words
[6] = (S_030018_MAX_ANISO(4)) |
1113 (S_030018_TILE_SPLIT(tile_split
));
1114 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
1115 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
1116 S_03001C_BANK_WIDTH(bankw
) |
1117 S_03001C_BANK_HEIGHT(bankh
) |
1118 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
1119 S_03001C_NUM_BANKS(nbanks
);
1123 static void evergreen_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
1124 struct pipe_sampler_view
**views
)
1126 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
1129 static void evergreen_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
1130 struct pipe_sampler_view
**views
)
1132 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
1135 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
1136 const struct pipe_clip_state
*state
)
1138 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1139 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1140 struct pipe_constant_buffer cb
;
1145 rctx
->clip
= *state
;
1146 rstate
->id
= R600_PIPE_STATE_CLIP
;
1147 for (int i
= 0; i
< 6; i
++) {
1148 r600_pipe_state_add_reg(rstate
,
1149 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
1150 fui(state
->ucp
[i
][0]));
1151 r600_pipe_state_add_reg(rstate
,
1152 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
1153 fui(state
->ucp
[i
][1]) );
1154 r600_pipe_state_add_reg(rstate
,
1155 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
1156 fui(state
->ucp
[i
][2]));
1157 r600_pipe_state_add_reg(rstate
,
1158 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
1159 fui(state
->ucp
[i
][3]));
1162 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1163 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1164 r600_context_pipe_state_set(rctx
, rstate
);
1167 cb
.user_buffer
= state
->ucp
;
1168 cb
.buffer_offset
= 0;
1169 cb
.buffer_size
= 4*4*8;
1170 r600_set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
1171 pipe_resource_reference(&cb
.buffer
, NULL
);
1174 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1175 const struct pipe_poly_stipple
*state
)
1179 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1180 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1181 uint32_t *tl
, uint32_t *br
)
1183 /* EG hw workaround */
1189 /* cayman hw workaround */
1190 if (rctx
->chip_class
== CAYMAN
) {
1191 if (br_x
== 1 && br_y
== 1)
1195 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1196 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1199 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1200 const struct pipe_scissor_state
*state
)
1202 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1203 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1209 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
1211 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1212 r600_pipe_state_add_reg(rstate
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
);
1213 r600_pipe_state_add_reg(rstate
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
);
1215 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1216 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1217 r600_context_pipe_state_set(rctx
, rstate
);
1220 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
1221 const struct pipe_viewport_state
*state
)
1223 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1224 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1229 rctx
->viewport
= *state
;
1230 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1231 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
1232 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
1233 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
1234 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
1235 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
1236 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
1238 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1239 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1240 r600_context_pipe_state_set(rctx
, rstate
);
1243 void evergreen_init_color_surface(struct r600_context
*rctx
,
1244 struct r600_surface
*surf
)
1246 struct r600_screen
*rscreen
= rctx
->screen
;
1247 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1248 struct pipe_resource
*pipe_tex
= surf
->base
.texture
;
1249 unsigned level
= surf
->base
.u
.tex
.level
;
1250 unsigned pitch
, slice
;
1251 unsigned color_info
, color_attrib
, color_dim
= 0;
1252 unsigned format
, swap
, ntype
, endian
;
1254 unsigned tile_type
, macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1255 const struct util_format_description
*desc
;
1257 bool blend_clamp
= 0, blend_bypass
= 0;
1259 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1260 r600_init_flushed_depth_texture(&rctx
->context
, pipe_tex
, NULL
);
1261 rtex
= rtex
->flushed_depth_texture
;
1265 offset
= rtex
->surface
.level
[level
].offset
;
1266 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1267 offset
+= rtex
->surface
.level
[level
].slice_size
*
1268 surf
->base
.u
.tex
.first_layer
;
1270 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1271 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1276 switch (rtex
->surface
.level
[level
].mode
) {
1277 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1278 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1281 case RADEON_SURF_MODE_1D
:
1282 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1283 tile_type
= rtex
->tile_type
;
1285 case RADEON_SURF_MODE_2D
:
1286 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1287 tile_type
= rtex
->tile_type
;
1289 case RADEON_SURF_MODE_LINEAR
:
1291 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1295 tile_split
= rtex
->surface
.tile_split
;
1296 macro_aspect
= rtex
->surface
.mtilea
;
1297 bankw
= rtex
->surface
.bankw
;
1298 bankh
= rtex
->surface
.bankh
;
1299 tile_split
= eg_tile_split(tile_split
);
1300 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1301 bankw
= eg_bank_wh(bankw
);
1302 bankh
= eg_bank_wh(bankh
);
1304 /* 128 bit formats require tile type = 1 */
1305 if (rscreen
->chip_class
== CAYMAN
) {
1306 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1309 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1310 desc
= util_format_description(surf
->base
.format
);
1311 for (i
= 0; i
< 4; i
++) {
1312 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1317 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1318 S_028C74_NUM_BANKS(nbanks
) |
1319 S_028C74_BANK_WIDTH(bankw
) |
1320 S_028C74_BANK_HEIGHT(bankh
) |
1321 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1322 S_028C74_NON_DISP_TILING_ORDER(tile_type
);
1324 ntype
= V_028C70_NUMBER_UNORM
;
1325 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1326 ntype
= V_028C70_NUMBER_SRGB
;
1327 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1328 if (desc
->channel
[i
].normalized
)
1329 ntype
= V_028C70_NUMBER_SNORM
;
1330 else if (desc
->channel
[i
].pure_integer
)
1331 ntype
= V_028C70_NUMBER_SINT
;
1332 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1333 if (desc
->channel
[i
].normalized
)
1334 ntype
= V_028C70_NUMBER_UNORM
;
1335 else if (desc
->channel
[i
].pure_integer
)
1336 ntype
= V_028C70_NUMBER_UINT
;
1339 format
= r600_translate_colorformat(surf
->base
.format
);
1340 assert(format
!= ~0);
1342 swap
= r600_translate_colorswap(surf
->base
.format
);
1345 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1346 endian
= ENDIAN_NONE
;
1348 endian
= r600_colorformat_endian_swap(format
);
1351 /* blend clamp should be set for all NORM/SRGB types */
1352 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1353 ntype
== V_028C70_NUMBER_SRGB
)
1356 /* set blend bypass according to docs if SINT/UINT or
1357 8/24 COLOR variants */
1358 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1359 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1360 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1365 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1367 color_info
|= S_028C70_FORMAT(format
) |
1368 S_028C70_COMP_SWAP(swap
) |
1369 S_028C70_BLEND_CLAMP(blend_clamp
) |
1370 S_028C70_BLEND_BYPASS(blend_bypass
) |
1371 S_028C70_NUMBER_TYPE(ntype
) |
1372 S_028C70_ENDIAN(endian
);
1375 color_info
|= S_028C70_RAT(1);
1376 color_dim
= S_028C78_WIDTH_MAX(pipe_tex
->width0
)
1377 | S_028C78_HEIGHT_MAX(pipe_tex
->height0
);
1380 /* EXPORT_NORM is an optimzation that can be enabled for better
1381 * performance in certain cases.
1382 * EXPORT_NORM can be enabled if:
1383 * - 11-bit or smaller UNORM/SNORM/SRGB
1384 * - 16-bit or smaller FLOAT
1386 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1387 ((desc
->channel
[i
].size
< 12 &&
1388 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1389 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1390 (desc
->channel
[i
].size
< 17 &&
1391 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1392 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1393 surf
->export_16bpc
= true;
1396 offset
+= r600_resource_va(rctx
->context
.screen
, pipe_tex
);
1399 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1400 surf
->cb_color_base
= offset
;
1401 surf
->cb_color_dim
= color_dim
;
1402 surf
->cb_color_info
= color_info
;
1403 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1404 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1405 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1406 surf
->cb_color_view
= 0;
1408 surf
->cb_color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1409 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1411 surf
->cb_color_attrib
= color_attrib
;
1413 surf
->color_initialized
= true;
1416 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1417 struct r600_surface
*surf
)
1419 struct r600_screen
*rscreen
= rctx
->screen
;
1420 struct pipe_screen
*screen
= &rscreen
->screen
;
1421 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1423 unsigned level
, pitch
, slice
, format
, array_mode
;
1424 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1426 level
= surf
->base
.u
.tex
.level
;
1427 format
= r600_translate_dbformat(surf
->base
.format
);
1428 assert(format
!= ~0);
1430 offset
= r600_resource_va(screen
, surf
->base
.texture
);
1431 offset
+= rtex
->surface
.level
[level
].offset
;
1432 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1433 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1437 switch (rtex
->surface
.level
[level
].mode
) {
1438 case RADEON_SURF_MODE_2D
:
1439 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1441 case RADEON_SURF_MODE_1D
:
1442 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1443 case RADEON_SURF_MODE_LINEAR
:
1445 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1448 tile_split
= rtex
->surface
.tile_split
;
1449 macro_aspect
= rtex
->surface
.mtilea
;
1450 bankw
= rtex
->surface
.bankw
;
1451 bankh
= rtex
->surface
.bankh
;
1452 tile_split
= eg_tile_split(tile_split
);
1453 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1454 bankw
= eg_bank_wh(bankw
);
1455 bankh
= eg_bank_wh(bankh
);
1456 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1459 surf
->db_depth_info
= S_028040_ARRAY_MODE(array_mode
) |
1460 S_028040_FORMAT(format
) |
1461 S_028040_TILE_SPLIT(tile_split
)|
1462 S_028040_NUM_BANKS(nbanks
) |
1463 S_028040_BANK_WIDTH(bankw
) |
1464 S_028040_BANK_HEIGHT(bankh
) |
1465 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1466 surf
->db_depth_base
= offset
;
1467 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1468 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1469 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1470 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1472 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1473 uint64_t stencil_offset
= rtex
->surface
.stencil_offset
;
1474 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1476 stile_split
= eg_tile_split(stile_split
);
1477 stencil_offset
+= r600_resource_va(screen
, surf
->base
.texture
);
1478 stencil_offset
+= rtex
->surface
.level
[level
].offset
/ 4;
1479 stencil_offset
>>= 8;
1481 surf
->db_stencil_base
= stencil_offset
;
1482 surf
->db_stencil_info
= 1 | S_028044_TILE_SPLIT(stile_split
);
1484 surf
->db_stencil_base
= offset
;
1485 surf
->db_stencil_info
= 1;
1488 surf
->depth_initialized
= true;
1491 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1492 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1493 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1494 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1495 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1497 static uint32_t evergreen_set_ms_pos(struct pipe_context
*ctx
, struct r600_pipe_state
*rstate
, int nsample
)
1500 * There are two locations (-4, 4), (4, -4). */
1501 static uint32_t sample_locs_2x
[] = {
1502 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1503 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1504 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1505 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1507 static unsigned max_dist_2x
= 4;
1509 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1510 static uint32_t sample_locs_4x
[] = {
1511 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1512 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1513 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1514 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1516 static unsigned max_dist_4x
= 6;
1518 static uint32_t eg_sample_locs_8x
[] = {
1519 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1520 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1521 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1522 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1523 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1524 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1525 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1526 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1528 static uint32_t cm_sample_locs_8x
[] = {
1529 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1530 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1531 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1532 FILL_SREG(-2, -5, 4, -4, 1, 6, -6, -2),
1533 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1534 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1535 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1536 FILL_SREG( 6, 1, 0, 0, -5, 4, 7, -8),
1538 static unsigned max_dist_8x
= 8;
1540 static uint32_t cm_sample_locs_16x
[] = {
1541 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1542 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1543 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1544 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1545 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1546 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1547 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1548 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1549 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1550 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1551 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1552 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1553 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1554 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1555 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1556 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1558 static unsigned max_dist_16x
= 8;
1559 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1560 uint32_t max_dist
, num_regs
, *sample_locs
, i
;
1564 sample_locs
= sample_locs_2x
;
1565 num_regs
= Elements(sample_locs_2x
);
1566 max_dist
= max_dist_2x
;
1569 sample_locs
= sample_locs_4x
;
1570 num_regs
= Elements(sample_locs_4x
);
1571 max_dist
= max_dist_4x
;
1574 if (rctx
->chip_class
== CAYMAN
) {
1575 sample_locs
= cm_sample_locs_8x
;
1576 num_regs
= Elements(cm_sample_locs_8x
);
1578 sample_locs
= eg_sample_locs_8x
;
1579 num_regs
= Elements(eg_sample_locs_8x
);
1581 max_dist
= max_dist_8x
;
1584 if (rctx
->chip_class
== CAYMAN
) {
1585 sample_locs
= cm_sample_locs_16x
;
1586 num_regs
= Elements(cm_sample_locs_16x
);
1587 max_dist
= max_dist_16x
;
1592 R600_ERR("Invalid nr_samples %i\n", nsample
);
1596 /* All the regs must be initialized. Otherwise weird rendering may occur. */
1597 if (rctx
->chip_class
== CAYMAN
) {
1598 r600_pipe_state_add_reg(rstate
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs
[0]);
1599 r600_pipe_state_add_reg(rstate
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs
[1]);
1600 r600_pipe_state_add_reg(rstate
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs
[2]);
1601 r600_pipe_state_add_reg(rstate
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs
[3]);
1602 if (num_regs
<= 8) {
1603 r600_pipe_state_add_reg(rstate
, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs
[4]);
1604 r600_pipe_state_add_reg(rstate
, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs
[5]);
1605 r600_pipe_state_add_reg(rstate
, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs
[6]);
1606 r600_pipe_state_add_reg(rstate
, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs
[7]);
1608 if (num_regs
<= 16) {
1609 r600_pipe_state_add_reg(rstate
, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, sample_locs
[8]);
1610 r600_pipe_state_add_reg(rstate
, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, sample_locs
[9]);
1611 r600_pipe_state_add_reg(rstate
, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, sample_locs
[10]);
1612 r600_pipe_state_add_reg(rstate
, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
, sample_locs
[11]);
1613 r600_pipe_state_add_reg(rstate
, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, sample_locs
[12]);
1614 r600_pipe_state_add_reg(rstate
, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, sample_locs
[13]);
1615 r600_pipe_state_add_reg(rstate
, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, sample_locs
[14]);
1616 r600_pipe_state_add_reg(rstate
, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
, sample_locs
[15]);
1619 for (i
= 0; i
< num_regs
; i
++) {
1620 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
+ i
*4,
1627 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1628 const struct pipe_framebuffer_state
*state
)
1630 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1631 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1632 struct r600_surface
*surf
;
1633 struct r600_resource
*res
;
1634 uint32_t tl
, br
, i
, nr_samples
;
1639 r600_flush_framebuffer(rctx
, false);
1641 /* unreference old buffer and reference new one */
1642 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1644 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1647 rctx
->export_16bpc
= true;
1648 rctx
->nr_cbufs
= state
->nr_cbufs
;
1649 rctx
->cb0_is_integer
= state
->nr_cbufs
&&
1650 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1652 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1653 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1654 res
= (struct r600_resource
*)surf
->base
.texture
;
1656 if (!surf
->color_initialized
) {
1657 evergreen_init_color_surface(rctx
, surf
);
1660 if (!surf
->export_16bpc
) {
1661 rctx
->export_16bpc
= false;
1664 r600_pipe_state_add_reg_bo(rstate
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
1665 surf
->cb_color_base
, res
, RADEON_USAGE_READWRITE
);
1666 r600_pipe_state_add_reg(rstate
, R_028C78_CB_COLOR0_DIM
+ i
* 0x3C,
1667 surf
->cb_color_dim
);
1668 r600_pipe_state_add_reg_bo(rstate
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1669 surf
->cb_color_info
, res
, RADEON_USAGE_READWRITE
);
1670 r600_pipe_state_add_reg(rstate
, R_028C64_CB_COLOR0_PITCH
+ i
* 0x3C,
1671 surf
->cb_color_pitch
);
1672 r600_pipe_state_add_reg(rstate
, R_028C68_CB_COLOR0_SLICE
+ i
* 0x3C,
1673 surf
->cb_color_slice
);
1674 r600_pipe_state_add_reg(rstate
, R_028C6C_CB_COLOR0_VIEW
+ i
* 0x3C,
1675 surf
->cb_color_view
);
1676 r600_pipe_state_add_reg_bo(rstate
, R_028C74_CB_COLOR0_ATTRIB
+ i
* 0x3C,
1677 surf
->cb_color_attrib
, res
, RADEON_USAGE_READWRITE
);
1679 /* set CB_COLOR1_INFO for possible dual-src blending */
1680 if (i
== 1 && !((struct r600_resource_texture
*)res
)->is_rat
) {
1681 r600_pipe_state_add_reg_bo(rstate
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1682 surf
->cb_color_info
, res
, RADEON_USAGE_READWRITE
);
1685 for (; i
< 8 ; i
++) {
1686 r600_pipe_state_add_reg(rstate
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1689 /* Update alpha-test state dependencies.
1690 * Alpha-test is done on the first colorbuffer only. */
1691 if (state
->nr_cbufs
) {
1692 surf
= (struct r600_surface
*)state
->cbufs
[0];
1693 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1694 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1695 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1697 if (rctx
->alphatest_state
.cb0_export_16bpc
!= surf
->export_16bpc
) {
1698 rctx
->alphatest_state
.cb0_export_16bpc
= surf
->export_16bpc
;
1699 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1705 surf
= (struct r600_surface
*)state
->zsbuf
;
1706 res
= (struct r600_resource
*)surf
->base
.texture
;
1708 if (!surf
->depth_initialized
) {
1709 evergreen_init_depth_surface(rctx
, surf
);
1712 r600_pipe_state_add_reg_bo(rstate
, R_028048_DB_Z_READ_BASE
, surf
->db_depth_base
,
1713 res
, RADEON_USAGE_READWRITE
);
1714 r600_pipe_state_add_reg_bo(rstate
, R_028050_DB_Z_WRITE_BASE
, surf
->db_depth_base
,
1715 res
, RADEON_USAGE_READWRITE
);
1716 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
, surf
->db_depth_view
);
1718 r600_pipe_state_add_reg_bo(rstate
, R_02804C_DB_STENCIL_READ_BASE
, surf
->db_stencil_base
,
1719 res
, RADEON_USAGE_READWRITE
);
1720 r600_pipe_state_add_reg_bo(rstate
, R_028054_DB_STENCIL_WRITE_BASE
, surf
->db_stencil_base
,
1721 res
, RADEON_USAGE_READWRITE
);
1722 r600_pipe_state_add_reg_bo(rstate
, R_028044_DB_STENCIL_INFO
, surf
->db_stencil_info
,
1723 res
, RADEON_USAGE_READWRITE
);
1725 r600_pipe_state_add_reg_bo(rstate
, R_028040_DB_Z_INFO
, surf
->db_depth_info
,
1726 res
, RADEON_USAGE_READWRITE
);
1727 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
, surf
->db_depth_size
);
1728 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
, surf
->db_depth_slice
);
1731 /* Framebuffer dimensions. */
1732 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1734 r600_pipe_state_add_reg(rstate
,
1735 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
);
1736 r600_pipe_state_add_reg(rstate
,
1737 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
);
1740 if (state
->nr_cbufs
)
1741 nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1742 else if (state
->zsbuf
)
1743 nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1747 if (nr_samples
> 1) {
1748 unsigned log_samples
= util_logbase2(nr_samples
);
1749 unsigned max_dist
, line_cntl
, aa_config
;
1751 max_dist
= evergreen_set_ms_pos(ctx
, rstate
, nr_samples
);
1753 line_cntl
= S_028C00_LAST_PIXEL(1) |
1754 S_028C00_EXPAND_LINE_WIDTH(1);
1755 aa_config
= S_028C04_MSAA_NUM_SAMPLES(log_samples
) |
1756 S_028C04_MAX_SAMPLE_DIST(max_dist
);
1758 if (rctx
->chip_class
== CAYMAN
) {
1759 r600_pipe_state_add_reg(rstate
, CM_R_028BDC_PA_SC_LINE_CNTL
, line_cntl
);
1760 r600_pipe_state_add_reg(rstate
, CM_R_028BE0_PA_SC_AA_CONFIG
, aa_config
);
1762 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, line_cntl
);
1763 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
, aa_config
);
1766 if (rctx
->chip_class
== CAYMAN
) {
1767 r600_pipe_state_add_reg(rstate
, CM_R_028BDC_PA_SC_LINE_CNTL
, S_028C00_LAST_PIXEL(1));
1768 r600_pipe_state_add_reg(rstate
, CM_R_028BE0_PA_SC_AA_CONFIG
, 0);
1770 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, S_028C00_LAST_PIXEL(1));
1771 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
, 0);
1775 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1776 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1777 r600_context_pipe_state_set(rctx
, rstate
);
1780 evergreen_polygon_offset_update(rctx
);
1783 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1784 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1785 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1788 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1789 rctx
->alphatest_state
.bypass
= false;
1790 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1794 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1796 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1797 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1798 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1799 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1801 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1802 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1803 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1804 * will assure that the alpha-test will work even if there is
1805 * no colorbuffer bound. */
1806 r600_write_value(cs
, 0xf | (a
->dual_src_blend
? ps_colormask
: 0) | fb_colormask
); /* R_02823C_CB_SHADER_MASK */
1809 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1811 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1812 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1813 unsigned db_render_control
= 0;
1814 unsigned db_count_control
= 0;
1815 unsigned db_render_override
=
1816 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
1817 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1818 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1820 if (a
->occlusion_query_enabled
) {
1821 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1822 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1825 if (a
->flush_depthstencil_through_cb
) {
1826 assert(a
->copy_depth
|| a
->copy_stencil
);
1828 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1829 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1830 S_028000_COPY_CENTROID(1) |
1831 S_028000_COPY_SAMPLE(a
->copy_sample
);
1834 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1835 r600_write_value(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
1836 r600_write_value(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
1837 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1840 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
1841 struct r600_vertexbuf_state
*state
,
1842 unsigned resource_offset
,
1845 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1846 uint32_t dirty_mask
= state
->dirty_mask
;
1848 while (dirty_mask
) {
1849 struct pipe_vertex_buffer
*vb
;
1850 struct r600_resource
*rbuffer
;
1852 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1854 vb
= &state
->vb
[buffer_index
];
1855 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1858 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
1859 va
+= vb
->buffer_offset
;
1861 /* fetch resources start at index 992 */
1862 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1863 r600_write_value(cs
, (resource_offset
+ buffer_index
) * 8);
1864 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
1865 r600_write_value(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1866 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1867 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1868 S_030008_STRIDE(vb
->stride
) |
1869 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1870 r600_write_value(cs
, /* RESOURCEi_WORD3 */
1871 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1872 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1873 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1874 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1875 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1876 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1877 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
1878 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1880 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1881 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1883 state
->dirty_mask
= 0;
1886 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1888 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
1891 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1893 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
1894 RADEON_CP_PACKET3_COMPUTE_MODE
);
1897 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
1898 struct r600_constbuf_state
*state
,
1899 unsigned buffer_id_base
,
1900 unsigned reg_alu_constbuf_size
,
1901 unsigned reg_alu_const_cache
)
1903 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1904 uint32_t dirty_mask
= state
->dirty_mask
;
1906 while (dirty_mask
) {
1907 struct pipe_constant_buffer
*cb
;
1908 struct r600_resource
*rbuffer
;
1910 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1912 cb
= &state
->cb
[buffer_index
];
1913 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1916 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
1917 va
+= cb
->buffer_offset
;
1919 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1920 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1921 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8);
1923 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1924 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1926 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
1927 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 8);
1928 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
1929 r600_write_value(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1930 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1931 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1932 S_030008_STRIDE(16) |
1933 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1934 r600_write_value(cs
, /* RESOURCEi_WORD3 */
1935 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1936 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1937 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1938 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1939 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1940 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1941 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
1942 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1944 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1945 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1947 dirty_mask
&= ~(1 << buffer_index
);
1949 state
->dirty_mask
= 0;
1952 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1954 evergreen_emit_constant_buffers(rctx
, &rctx
->vs_constbuf_state
, 176,
1955 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1956 R_028980_ALU_CONST_CACHE_VS_0
);
1959 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1961 evergreen_emit_constant_buffers(rctx
, &rctx
->ps_constbuf_state
, 0,
1962 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1963 R_028940_ALU_CONST_CACHE_PS_0
);
1966 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
1967 struct r600_samplerview_state
*state
,
1968 unsigned resource_id_base
)
1970 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1971 uint32_t dirty_mask
= state
->dirty_mask
;
1973 while (dirty_mask
) {
1974 struct r600_pipe_sampler_view
*rview
;
1975 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1978 rview
= state
->views
[resource_index
];
1981 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
1982 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 8);
1983 r600_write_array(cs
, 8, rview
->tex_resource_words
);
1985 /* XXX The kernel needs two relocations. This is stupid. */
1986 reloc
= r600_context_bo_reloc(rctx
, rview
->tex_resource
,
1988 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1989 r600_write_value(cs
, reloc
);
1990 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1991 r600_write_value(cs
, reloc
);
1993 state
->dirty_mask
= 0;
1996 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1998 evergreen_emit_sampler_views(rctx
, &rctx
->vs_samplers
.views
, 176 + R600_MAX_CONST_BUFFERS
);
2001 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2003 evergreen_emit_sampler_views(rctx
, &rctx
->ps_samplers
.views
, R600_MAX_CONST_BUFFERS
);
2006 static void evergreen_emit_sampler(struct r600_context
*rctx
,
2007 struct r600_textures_info
*texinfo
,
2008 unsigned resource_id_base
,
2009 unsigned border_index_reg
)
2011 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2014 for (i
= 0; i
< texinfo
->n_samplers
; i
++) {
2016 if (texinfo
->samplers
[i
] == NULL
) {
2019 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2020 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2021 r600_write_array(cs
, 3, texinfo
->samplers
[i
]->tex_sampler_words
);
2023 if (texinfo
->samplers
[i
]->border_color_use
) {
2024 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2025 r600_write_value(cs
, i
);
2026 r600_write_array(cs
, 4, texinfo
->samplers
[i
]->border_color
);
2031 static void evergreen_emit_vs_sampler(struct r600_context
*rctx
, struct r600_atom
*atom
)
2033 evergreen_emit_sampler(rctx
, &rctx
->vs_samplers
, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
);
2036 static void evergreen_emit_ps_sampler(struct r600_context
*rctx
, struct r600_atom
*atom
)
2038 evergreen_emit_sampler(rctx
, &rctx
->ps_samplers
, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
);
2041 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2043 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2044 uint8_t mask
= s
->sample_mask
;
2046 r600_write_context_reg(rctx
->cs
, R_028C3C_PA_SC_AA_MASK
,
2047 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2050 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2052 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2053 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2054 uint16_t mask
= s
->sample_mask
;
2056 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2057 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2058 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2061 void evergreen_init_state_functions(struct r600_context
*rctx
)
2063 r600_init_atom(&rctx
->cb_misc_state
.atom
, evergreen_emit_cb_misc_state
, 0, 0);
2064 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
2065 r600_init_atom(&rctx
->db_misc_state
.atom
, evergreen_emit_db_misc_state
, 7, 0);
2066 r600_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2067 r600_init_atom(&rctx
->vertex_buffer_state
.atom
, evergreen_fs_emit_vertex_buffers
, 0, 0);
2068 r600_init_atom(&rctx
->cs_vertex_buffer_state
.atom
, evergreen_cs_emit_vertex_buffers
, 0, 0);
2069 r600_init_atom(&rctx
->vs_constbuf_state
.atom
, evergreen_emit_vs_constant_buffers
, 0, 0);
2070 r600_init_atom(&rctx
->ps_constbuf_state
.atom
, evergreen_emit_ps_constant_buffers
, 0, 0);
2071 r600_init_atom(&rctx
->vs_samplers
.views
.atom
, evergreen_emit_vs_sampler_views
, 0, 0);
2072 r600_init_atom(&rctx
->ps_samplers
.views
.atom
, evergreen_emit_ps_sampler_views
, 0, 0);
2073 r600_init_atom(&rctx
->cs_shader_state
.atom
, evergreen_emit_cs_shader
, 0, 0);
2074 r600_init_atom(&rctx
->vs_samplers
.atom_sampler
, evergreen_emit_vs_sampler
, 0, 0);
2075 r600_init_atom(&rctx
->ps_samplers
.atom_sampler
, evergreen_emit_ps_sampler
, 0, 0);
2077 if (rctx
->chip_class
== EVERGREEN
)
2078 r600_init_atom(&rctx
->sample_mask
.atom
, evergreen_emit_sample_mask
, 3, 0);
2080 r600_init_atom(&rctx
->sample_mask
.atom
, cayman_emit_sample_mask
, 4, 0);
2081 rctx
->sample_mask
.sample_mask
= ~0;
2082 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
2084 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
2085 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
2086 rctx
->context
.create_fs_state
= r600_create_shader_state_ps
;
2087 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
2088 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
2089 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
2090 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
2091 rctx
->context
.create_vs_state
= r600_create_shader_state_vs
;
2092 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
2093 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2094 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_samplers
;
2095 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
2096 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
2097 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2098 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_samplers
;
2099 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
2100 rctx
->context
.delete_blend_state
= r600_delete_state
;
2101 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
2102 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
2103 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
2104 rctx
->context
.delete_sampler_state
= r600_delete_sampler
;
2105 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
2106 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
2107 rctx
->context
.set_blend_color
= r600_set_blend_color
;
2108 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
2109 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
2110 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_views
;
2111 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
2112 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
2113 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
2114 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
2115 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2116 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
2117 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
2118 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_views
;
2119 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
2120 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
2121 rctx
->context
.texture_barrier
= r600_texture_barrier
;
2122 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
2123 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
2124 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
2125 evergreen_init_compute_state_functions(rctx
);
2128 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2130 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2132 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
2134 /* This must be first. */
2135 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2136 r600_store_value(cb
, 0x80000000);
2137 r600_store_value(cb
, 0x80000000);
2139 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2140 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2141 /* always set the temp clauses */
2142 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2144 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2145 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2146 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2148 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2150 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2152 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2153 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2154 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2155 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2156 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2157 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2158 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2159 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2160 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2161 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2162 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2163 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2164 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2165 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2167 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2168 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2169 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2171 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2172 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2173 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2175 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2177 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2179 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2180 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2181 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2183 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2184 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2185 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2187 r600_store_context_reg(cb
, CM_R_028804_DB_EQAA
, 0x110000);
2189 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2190 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2191 r600_store_value(cb
, 0);
2192 r600_store_value(cb
, 0);
2193 r600_store_value(cb
, 0);
2194 r600_store_value(cb
, 0);
2195 r600_store_value(cb
, 0);
2196 r600_store_value(cb
, 0);
2197 r600_store_value(cb
, 0);
2198 r600_store_value(cb
, 0);
2199 r600_store_value(cb
, 0);
2200 r600_store_value(cb
, 0);
2201 r600_store_value(cb
, 0);
2202 r600_store_value(cb
, 0);
2203 r600_store_value(cb
, 0);
2204 r600_store_value(cb
, 0);
2205 r600_store_value(cb
, 0);
2206 r600_store_value(cb
, 0);
2207 r600_store_value(cb
, 0);
2208 r600_store_value(cb
, 0);
2209 r600_store_value(cb
, 0);
2210 r600_store_value(cb
, 0);
2211 r600_store_value(cb
, 0);
2212 r600_store_value(cb
, 0);
2213 r600_store_value(cb
, 0);
2214 r600_store_value(cb
, 0);
2215 r600_store_value(cb
, 0);
2216 r600_store_value(cb
, 0);
2217 r600_store_value(cb
, 0);
2218 r600_store_value(cb
, 0);
2219 r600_store_value(cb
, 0);
2220 r600_store_value(cb
, 0);
2221 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2222 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2223 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2225 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2227 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2228 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2229 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2231 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2233 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2234 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2235 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2236 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2238 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2239 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2241 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2242 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2243 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2245 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2246 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2247 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2249 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2250 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2251 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2252 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2253 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2255 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2256 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2257 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2259 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2260 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2261 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2263 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2264 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2265 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2267 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2268 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2269 if (rctx
->screen
->has_streamout
) {
2270 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2273 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2274 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2277 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2279 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2284 int hs_prio
, cs_prio
, ls_prio
;
2298 int num_ps_stack_entries
;
2299 int num_vs_stack_entries
;
2300 int num_gs_stack_entries
;
2301 int num_es_stack_entries
;
2302 int num_hs_stack_entries
;
2303 int num_ls_stack_entries
;
2304 enum radeon_family family
;
2307 if (rctx
->chip_class
== CAYMAN
) {
2308 cayman_init_atom_start_cs(rctx
);
2312 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
2314 /* This must be first. */
2315 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2316 r600_store_value(cb
, 0x80000000);
2317 r600_store_value(cb
, 0x80000000);
2319 family
= rctx
->family
;
2338 num_ps_threads
= 96;
2339 num_vs_threads
= 16;
2340 num_gs_threads
= 16;
2341 num_es_threads
= 16;
2342 num_hs_threads
= 16;
2343 num_ls_threads
= 16;
2344 num_ps_stack_entries
= 42;
2345 num_vs_stack_entries
= 42;
2346 num_gs_stack_entries
= 42;
2347 num_es_stack_entries
= 42;
2348 num_hs_stack_entries
= 42;
2349 num_ls_stack_entries
= 42;
2359 num_ps_threads
= 128;
2360 num_vs_threads
= 20;
2361 num_gs_threads
= 20;
2362 num_es_threads
= 20;
2363 num_hs_threads
= 20;
2364 num_ls_threads
= 20;
2365 num_ps_stack_entries
= 42;
2366 num_vs_stack_entries
= 42;
2367 num_gs_stack_entries
= 42;
2368 num_es_stack_entries
= 42;
2369 num_hs_stack_entries
= 42;
2370 num_ls_stack_entries
= 42;
2380 num_ps_threads
= 128;
2381 num_vs_threads
= 20;
2382 num_gs_threads
= 20;
2383 num_es_threads
= 20;
2384 num_hs_threads
= 20;
2385 num_ls_threads
= 20;
2386 num_ps_stack_entries
= 85;
2387 num_vs_stack_entries
= 85;
2388 num_gs_stack_entries
= 85;
2389 num_es_stack_entries
= 85;
2390 num_hs_stack_entries
= 85;
2391 num_ls_stack_entries
= 85;
2402 num_ps_threads
= 128;
2403 num_vs_threads
= 20;
2404 num_gs_threads
= 20;
2405 num_es_threads
= 20;
2406 num_hs_threads
= 20;
2407 num_ls_threads
= 20;
2408 num_ps_stack_entries
= 85;
2409 num_vs_stack_entries
= 85;
2410 num_gs_stack_entries
= 85;
2411 num_es_stack_entries
= 85;
2412 num_hs_stack_entries
= 85;
2413 num_ls_stack_entries
= 85;
2423 num_ps_threads
= 96;
2424 num_vs_threads
= 16;
2425 num_gs_threads
= 16;
2426 num_es_threads
= 16;
2427 num_hs_threads
= 16;
2428 num_ls_threads
= 16;
2429 num_ps_stack_entries
= 42;
2430 num_vs_stack_entries
= 42;
2431 num_gs_stack_entries
= 42;
2432 num_es_stack_entries
= 42;
2433 num_hs_stack_entries
= 42;
2434 num_ls_stack_entries
= 42;
2444 num_ps_threads
= 96;
2445 num_vs_threads
= 25;
2446 num_gs_threads
= 25;
2447 num_es_threads
= 25;
2448 num_hs_threads
= 25;
2449 num_ls_threads
= 25;
2450 num_ps_stack_entries
= 42;
2451 num_vs_stack_entries
= 42;
2452 num_gs_stack_entries
= 42;
2453 num_es_stack_entries
= 42;
2454 num_hs_stack_entries
= 42;
2455 num_ls_stack_entries
= 42;
2465 num_ps_threads
= 96;
2466 num_vs_threads
= 25;
2467 num_gs_threads
= 25;
2468 num_es_threads
= 25;
2469 num_hs_threads
= 25;
2470 num_ls_threads
= 25;
2471 num_ps_stack_entries
= 85;
2472 num_vs_stack_entries
= 85;
2473 num_gs_stack_entries
= 85;
2474 num_es_stack_entries
= 85;
2475 num_hs_stack_entries
= 85;
2476 num_ls_stack_entries
= 85;
2486 num_ps_threads
= 128;
2487 num_vs_threads
= 20;
2488 num_gs_threads
= 20;
2489 num_es_threads
= 20;
2490 num_hs_threads
= 20;
2491 num_ls_threads
= 20;
2492 num_ps_stack_entries
= 85;
2493 num_vs_stack_entries
= 85;
2494 num_gs_stack_entries
= 85;
2495 num_es_stack_entries
= 85;
2496 num_hs_stack_entries
= 85;
2497 num_ls_stack_entries
= 85;
2507 num_ps_threads
= 128;
2508 num_vs_threads
= 20;
2509 num_gs_threads
= 20;
2510 num_es_threads
= 20;
2511 num_hs_threads
= 20;
2512 num_ls_threads
= 20;
2513 num_ps_stack_entries
= 42;
2514 num_vs_stack_entries
= 42;
2515 num_gs_stack_entries
= 42;
2516 num_es_stack_entries
= 42;
2517 num_hs_stack_entries
= 42;
2518 num_ls_stack_entries
= 42;
2528 num_ps_threads
= 128;
2529 num_vs_threads
= 10;
2530 num_gs_threads
= 10;
2531 num_es_threads
= 10;
2532 num_hs_threads
= 10;
2533 num_ls_threads
= 10;
2534 num_ps_stack_entries
= 42;
2535 num_vs_stack_entries
= 42;
2536 num_gs_stack_entries
= 42;
2537 num_es_stack_entries
= 42;
2538 num_hs_stack_entries
= 42;
2539 num_ls_stack_entries
= 42;
2552 tmp
|= S_008C00_VC_ENABLE(1);
2555 tmp
|= S_008C00_EXPORT_SRC_C(1);
2556 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2557 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2558 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2559 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2560 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2561 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2562 tmp
|= S_008C00_ES_PRIO(es_prio
);
2564 /* enable dynamic GPR resource management */
2565 if (rctx
->screen
->info
.drm_minor
>= 7) {
2566 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2567 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2568 /* always set temp clauses */
2569 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2570 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2571 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2572 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2573 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2574 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2575 S_028838_PS_GPRS(0x1e) |
2576 S_028838_VS_GPRS(0x1e) |
2577 S_028838_GS_GPRS(0x1e) |
2578 S_028838_ES_GPRS(0x1e) |
2579 S_028838_HS_GPRS(0x1e) |
2580 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2582 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2583 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2585 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2586 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2587 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2588 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2590 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2591 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2592 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2594 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2595 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2596 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2599 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2600 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2601 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2602 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2603 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2604 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2606 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2607 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2608 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2610 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2611 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2612 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2614 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2615 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2616 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2618 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2619 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2620 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2622 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2623 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2625 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2626 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2628 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2630 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2631 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2632 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2633 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2634 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2635 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2636 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2638 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2639 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2640 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2641 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2642 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2644 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2645 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2646 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2647 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2648 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2649 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2650 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2651 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2652 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2653 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2654 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2655 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2656 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2657 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2659 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2660 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2661 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2663 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2664 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2665 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2667 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2669 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2670 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2671 r600_store_value(cb
, 0);
2672 r600_store_value(cb
, 0);
2673 r600_store_value(cb
, 0);
2674 r600_store_value(cb
, 0);
2675 r600_store_value(cb
, 0);
2676 r600_store_value(cb
, 0);
2677 r600_store_value(cb
, 0);
2678 r600_store_value(cb
, 0);
2679 r600_store_value(cb
, 0);
2680 r600_store_value(cb
, 0);
2681 r600_store_value(cb
, 0);
2682 r600_store_value(cb
, 0);
2683 r600_store_value(cb
, 0);
2684 r600_store_value(cb
, 0);
2685 r600_store_value(cb
, 0);
2686 r600_store_value(cb
, 0);
2687 r600_store_value(cb
, 0);
2688 r600_store_value(cb
, 0);
2689 r600_store_value(cb
, 0);
2690 r600_store_value(cb
, 0);
2691 r600_store_value(cb
, 0);
2692 r600_store_value(cb
, 0);
2693 r600_store_value(cb
, 0);
2694 r600_store_value(cb
, 0);
2695 r600_store_value(cb
, 0);
2696 r600_store_value(cb
, 0);
2697 r600_store_value(cb
, 0);
2698 r600_store_value(cb
, 0);
2699 r600_store_value(cb
, 0);
2700 r600_store_value(cb
, 0);
2701 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2702 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2703 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2705 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2707 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2708 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2709 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2711 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2712 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2713 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2715 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2716 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2717 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2719 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2720 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2721 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2723 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2724 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2725 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2726 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2728 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2729 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2730 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2731 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2732 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2734 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2735 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2736 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2738 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2739 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2740 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2742 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2743 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2744 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2746 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2747 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2748 if (rctx
->screen
->has_streamout
) {
2749 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2752 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2753 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2756 void evergreen_polygon_offset_update(struct r600_context
*rctx
)
2758 struct r600_pipe_state state
;
2760 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
2762 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
2763 float offset_units
= rctx
->rasterizer
->offset_units
;
2764 unsigned offset_db_fmt_cntl
= 0, depth
;
2766 switch (rctx
->framebuffer
.zsbuf
->format
) {
2767 case PIPE_FORMAT_Z24X8_UNORM
:
2768 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2770 offset_units
*= 2.0f
;
2772 case PIPE_FORMAT_Z32_FLOAT
:
2773 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2775 offset_units
*= 1.0f
;
2776 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2778 case PIPE_FORMAT_Z16_UNORM
:
2780 offset_units
*= 4.0f
;
2785 /* XXX some of those reg can be computed with cso */
2786 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
2787 r600_pipe_state_add_reg(&state
,
2788 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
2789 fui(rctx
->rasterizer
->offset_scale
));
2790 r600_pipe_state_add_reg(&state
,
2791 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
2793 r600_pipe_state_add_reg(&state
,
2794 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
2795 fui(rctx
->rasterizer
->offset_scale
));
2796 r600_pipe_state_add_reg(&state
,
2797 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
2799 r600_pipe_state_add_reg(&state
,
2800 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2801 offset_db_fmt_cntl
);
2802 r600_context_pipe_state_set(rctx
, &state
);
2806 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2808 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2809 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2810 struct r600_shader
*rshader
= &shader
->shader
;
2811 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2812 int pos_index
= -1, face_index
= -1;
2814 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2815 unsigned spi_baryc_cntl
, sid
, tmp
, idx
= 0;
2816 unsigned z_export
= 0, stencil_export
= 0;
2820 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2821 for (i
= 0; i
< rshader
->ninput
; i
++) {
2822 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2823 POSITION goes via GPRs from the SC so isn't counted */
2824 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2826 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2830 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2832 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2833 have_perspective
= TRUE
;
2834 if (rshader
->input
[i
].centroid
)
2835 have_centroid
= TRUE
;
2838 sid
= rshader
->input
[i
].spi_sid
;
2842 tmp
= S_028644_SEMANTIC(sid
);
2844 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2845 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2846 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2847 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
2848 tmp
|= S_028644_FLAT_SHADE(1);
2851 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2852 (rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
2853 tmp
|= S_028644_PT_SPRITE_TEX(1);
2856 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ idx
* 4,
2863 for (i
= 0; i
< rshader
->noutput
; i
++) {
2864 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2866 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2869 if (rshader
->uses_kill
)
2870 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2872 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2873 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
2876 for (i
= 0; i
< rshader
->noutput
; i
++) {
2877 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2878 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2882 num_cout
= rshader
->nr_ps_color_exports
;
2884 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
2886 /* always at least export 1 component per pixel */
2889 shader
->nr_ps_color_outputs
= num_cout
;
2892 have_perspective
= TRUE
;
2895 if (!have_perspective
&& !have_linear
)
2896 have_perspective
= TRUE
;
2898 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
2899 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
2900 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
2902 if (pos_index
!= -1) {
2903 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
2904 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2905 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
2909 spi_ps_in_control_1
= 0;
2910 if (face_index
!= -1) {
2911 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2912 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2916 if (have_perspective
)
2917 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
2918 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
2920 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
2921 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
2923 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
2924 spi_ps_in_control_0
);
2925 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
2926 spi_ps_in_control_1
);
2927 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
2929 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2930 r600_pipe_state_add_reg(rstate
,
2931 R_0286E0_SPI_BARYC_CNTL
,
2934 r600_pipe_state_add_reg_bo(rstate
,
2935 R_028840_SQ_PGM_START_PS
,
2936 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
2937 shader
->bo
, RADEON_USAGE_READ
);
2938 r600_pipe_state_add_reg(rstate
,
2939 R_028844_SQ_PGM_RESOURCES_PS
,
2940 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
2941 S_028844_PRIME_CACHE_ON_DRAW(1) |
2942 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
2943 r600_pipe_state_add_reg(rstate
,
2944 R_02884C_SQ_PGM_EXPORTS_PS
,
2947 shader
->db_shader_control
= db_shader_control
;
2948 shader
->ps_depth_export
= z_export
| stencil_export
;
2950 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
2951 if (rctx
->rasterizer
)
2952 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2955 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2957 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2958 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2959 struct r600_shader
*rshader
= &shader
->shader
;
2960 unsigned spi_vs_out_id
[10] = {};
2961 unsigned i
, tmp
, nparams
= 0;
2963 /* clear previous register */
2966 for (i
= 0; i
< rshader
->noutput
; i
++) {
2967 if (rshader
->output
[i
].spi_sid
) {
2968 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2969 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2974 for (i
= 0; i
< 10; i
++) {
2975 r600_pipe_state_add_reg(rstate
,
2976 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
2980 /* Certain attributes (position, psize, etc.) don't count as params.
2981 * VS is required to export at least one param and r600_shader_from_tgsi()
2982 * takes care of adding a dummy export.
2987 r600_pipe_state_add_reg(rstate
,
2988 R_0286C4_SPI_VS_OUT_CONFIG
,
2989 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2990 r600_pipe_state_add_reg(rstate
,
2991 R_028860_SQ_PGM_RESOURCES_VS
,
2992 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
2993 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
2994 r600_pipe_state_add_reg_bo(rstate
,
2995 R_02885C_SQ_PGM_START_VS
,
2996 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
2997 shader
->bo
, RADEON_USAGE_READ
);
2999 shader
->pa_cl_vs_out_cntl
=
3000 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3001 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3002 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3003 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
3006 void evergreen_fetch_shader(struct pipe_context
*ctx
,
3007 struct r600_vertex_element
*ve
)
3009 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3010 struct r600_pipe_state
*rstate
= &ve
->rstate
;
3011 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
3013 r600_pipe_state_add_reg_bo(rstate
, R_0288A4_SQ_PGM_START_FS
,
3014 r600_resource_va(ctx
->screen
, (void *)ve
->fetch_shader
) >> 8,
3015 ve
->fetch_shader
, RADEON_USAGE_READ
);
3018 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3020 struct pipe_blend_state blend
;
3021 struct r600_pipe_state
*rstate
;
3023 memset(&blend
, 0, sizeof(blend
));
3024 blend
.rt
[0].colormask
= 0xf;
3025 rstate
= evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_RESOLVE
);
3029 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3031 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3033 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
3036 void evergreen_update_dual_export_state(struct r600_context
* rctx
)
3038 unsigned dual_export
= rctx
->export_16bpc
&& rctx
->nr_cbufs
&&
3039 !rctx
->ps_shader
->current
->ps_depth_export
;
3041 unsigned db_source_format
= dual_export
? V_02880C_EXPORT_DB_TWO
:
3042 V_02880C_EXPORT_DB_FULL
;
3044 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3045 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3046 S_02880C_DB_SOURCE_FORMAT(db_source_format
) |
3047 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->cb0_is_integer
);
3049 if (db_shader_control
!= rctx
->db_shader_control
) {
3050 struct r600_pipe_state rstate
;
3052 rctx
->db_shader_control
= db_shader_control
;
3055 r600_pipe_state_add_reg(&rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
3056 r600_context_pipe_state_set(rctx
, &rstate
);