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r600g: remove the "atom" variable from r600_command_buffer
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
158 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169 V_030000_SQ_TEX_DIM_2D;
170 case PIPE_TEXTURE_2D_ARRAY:
171 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172 V_030000_SQ_TEX_DIM_2D_ARRAY;
173 case PIPE_TEXTURE_3D:
174 return V_030000_SQ_TEX_DIM_3D;
175 case PIPE_TEXTURE_CUBE:
176 return V_030000_SQ_TEX_DIM_CUBEMAP;
177 }
178 }
179
180 static uint32_t r600_translate_dbformat(enum pipe_format format)
181 {
182 switch (format) {
183 case PIPE_FORMAT_Z16_UNORM:
184 return V_028040_Z_16;
185 case PIPE_FORMAT_Z24X8_UNORM:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187 return V_028040_Z_24;
188 case PIPE_FORMAT_Z32_FLOAT:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190 return V_028040_Z_32_FLOAT;
191 default:
192 return ~0U;
193 }
194 }
195
196 static uint32_t r600_translate_colorswap(enum pipe_format format)
197 {
198 switch (format) {
199 /* 8-bit buffers. */
200 case PIPE_FORMAT_L4A4_UNORM:
201 case PIPE_FORMAT_A4R4_UNORM:
202 return V_028C70_SWAP_ALT;
203
204 case PIPE_FORMAT_A8_UNORM:
205 case PIPE_FORMAT_A8_SNORM:
206 case PIPE_FORMAT_A8_UINT:
207 case PIPE_FORMAT_A8_SINT:
208 case PIPE_FORMAT_A16_UNORM:
209 case PIPE_FORMAT_A16_SNORM:
210 case PIPE_FORMAT_A16_UINT:
211 case PIPE_FORMAT_A16_SINT:
212 case PIPE_FORMAT_A16_FLOAT:
213 case PIPE_FORMAT_A32_UINT:
214 case PIPE_FORMAT_A32_SINT:
215 case PIPE_FORMAT_A32_FLOAT:
216 case PIPE_FORMAT_R4A4_UNORM:
217 return V_028C70_SWAP_ALT_REV;
218 case PIPE_FORMAT_I8_UNORM:
219 case PIPE_FORMAT_I8_SNORM:
220 case PIPE_FORMAT_I8_UINT:
221 case PIPE_FORMAT_I8_SINT:
222 case PIPE_FORMAT_I16_UNORM:
223 case PIPE_FORMAT_I16_SNORM:
224 case PIPE_FORMAT_I16_UINT:
225 case PIPE_FORMAT_I16_SINT:
226 case PIPE_FORMAT_I16_FLOAT:
227 case PIPE_FORMAT_I32_UINT:
228 case PIPE_FORMAT_I32_SINT:
229 case PIPE_FORMAT_I32_FLOAT:
230 case PIPE_FORMAT_L8_UNORM:
231 case PIPE_FORMAT_L8_SNORM:
232 case PIPE_FORMAT_L8_UINT:
233 case PIPE_FORMAT_L8_SINT:
234 case PIPE_FORMAT_L8_SRGB:
235 case PIPE_FORMAT_L16_UNORM:
236 case PIPE_FORMAT_L16_SNORM:
237 case PIPE_FORMAT_L16_UINT:
238 case PIPE_FORMAT_L16_SINT:
239 case PIPE_FORMAT_L16_FLOAT:
240 case PIPE_FORMAT_L32_UINT:
241 case PIPE_FORMAT_L32_SINT:
242 case PIPE_FORMAT_L32_FLOAT:
243 case PIPE_FORMAT_R8_UNORM:
244 case PIPE_FORMAT_R8_SNORM:
245 case PIPE_FORMAT_R8_UINT:
246 case PIPE_FORMAT_R8_SINT:
247 return V_028C70_SWAP_STD;
248
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM:
251 return V_028C70_SWAP_STD_REV;
252
253 case PIPE_FORMAT_B5G5R5A1_UNORM:
254 case PIPE_FORMAT_B5G5R5X1_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_B4G4R4A4_UNORM:
258 case PIPE_FORMAT_B4G4R4X4_UNORM:
259 return V_028C70_SWAP_ALT;
260
261 case PIPE_FORMAT_Z16_UNORM:
262 return V_028C70_SWAP_STD;
263
264 case PIPE_FORMAT_L8A8_UNORM:
265 case PIPE_FORMAT_L8A8_SNORM:
266 case PIPE_FORMAT_L8A8_UINT:
267 case PIPE_FORMAT_L8A8_SINT:
268 case PIPE_FORMAT_L8A8_SRGB:
269 case PIPE_FORMAT_L16A16_UNORM:
270 case PIPE_FORMAT_L16A16_SNORM:
271 case PIPE_FORMAT_L16A16_UINT:
272 case PIPE_FORMAT_L16A16_SINT:
273 case PIPE_FORMAT_L16A16_FLOAT:
274 case PIPE_FORMAT_L32A32_UINT:
275 case PIPE_FORMAT_L32A32_SINT:
276 case PIPE_FORMAT_L32A32_FLOAT:
277 return V_028C70_SWAP_ALT;
278 case PIPE_FORMAT_R8G8_UNORM:
279 case PIPE_FORMAT_R8G8_SNORM:
280 case PIPE_FORMAT_R8G8_UINT:
281 case PIPE_FORMAT_R8G8_SINT:
282 return V_028C70_SWAP_STD;
283
284 case PIPE_FORMAT_R16_UNORM:
285 case PIPE_FORMAT_R16_SNORM:
286 case PIPE_FORMAT_R16_UINT:
287 case PIPE_FORMAT_R16_SINT:
288 case PIPE_FORMAT_R16_FLOAT:
289 return V_028C70_SWAP_STD;
290
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB:
293 return V_028C70_SWAP_STD_REV;
294 case PIPE_FORMAT_B8G8R8A8_SRGB:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_B8G8R8A8_UNORM:
298 case PIPE_FORMAT_B8G8R8X8_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_A8R8G8B8_UNORM:
302 case PIPE_FORMAT_X8R8G8B8_UNORM:
303 return V_028C70_SWAP_ALT_REV;
304 case PIPE_FORMAT_R8G8B8A8_SNORM:
305 case PIPE_FORMAT_R8G8B8A8_UNORM:
306 case PIPE_FORMAT_R8G8B8A8_SINT:
307 case PIPE_FORMAT_R8G8B8A8_UINT:
308 case PIPE_FORMAT_R8G8B8X8_UNORM:
309 return V_028C70_SWAP_STD;
310
311 case PIPE_FORMAT_A8B8G8R8_UNORM:
312 case PIPE_FORMAT_X8B8G8R8_UNORM:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV;
315
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_X8Z24_UNORM:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R10G10B10A2_UNORM:
325 case PIPE_FORMAT_R10G10B10X2_SNORM:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327 return V_028C70_SWAP_STD;
328
329 case PIPE_FORMAT_B10G10R10A2_UNORM:
330 case PIPE_FORMAT_B10G10R10A2_UINT:
331 return V_028C70_SWAP_ALT;
332
333 case PIPE_FORMAT_R11G11B10_FLOAT:
334 case PIPE_FORMAT_R32_FLOAT:
335 case PIPE_FORMAT_R32_UINT:
336 case PIPE_FORMAT_R32_SINT:
337 case PIPE_FORMAT_Z32_FLOAT:
338 case PIPE_FORMAT_R16G16_FLOAT:
339 case PIPE_FORMAT_R16G16_UNORM:
340 case PIPE_FORMAT_R16G16_SNORM:
341 case PIPE_FORMAT_R16G16_UINT:
342 case PIPE_FORMAT_R16G16_SINT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16A16_FLOAT:
521 return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523 case PIPE_FORMAT_R32G32_FLOAT:
524 case PIPE_FORMAT_L32A32_FLOAT:
525 return V_028C70_COLOR_32_32_FLOAT;
526
527 case PIPE_FORMAT_R32G32_SINT:
528 case PIPE_FORMAT_R32G32_UINT:
529 case PIPE_FORMAT_L32A32_UINT:
530 case PIPE_FORMAT_L32A32_SINT:
531 return V_028C70_COLOR_32_32;
532
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM:
535 case PIPE_FORMAT_R32G32B32A32_UNORM:
536 case PIPE_FORMAT_R32G32B32A32_SINT:
537 case PIPE_FORMAT_R32G32B32A32_UINT:
538 return V_028C70_COLOR_32_32_32_32;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT:
540 return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542 /* YUV buffers. */
543 case PIPE_FORMAT_UYVY:
544 case PIPE_FORMAT_YUYV:
545 default:
546 return ~0U; /* Unsupported. */
547 }
548 }
549
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551 {
552 if (R600_BIG_ENDIAN) {
553 switch(colorformat) {
554
555 /* 8-bit buffers. */
556 case V_028C70_COLOR_8:
557 return ENDIAN_NONE;
558
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5:
561 case V_028C70_COLOR_1_5_5_5:
562 case V_028C70_COLOR_4_4_4_4:
563 case V_028C70_COLOR_16:
564 case V_028C70_COLOR_8_8:
565 return ENDIAN_8IN16;
566
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8:
569 case V_028C70_COLOR_2_10_10_10:
570 case V_028C70_COLOR_8_24:
571 case V_028C70_COLOR_24_8:
572 case V_028C70_COLOR_32_FLOAT:
573 case V_028C70_COLOR_16_16_FLOAT:
574 case V_028C70_COLOR_16_16:
575 return ENDIAN_8IN32;
576
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16:
579 case V_028C70_COLOR_16_16_16_16_FLOAT:
580 return ENDIAN_8IN16;
581
582 case V_028C70_COLOR_32_32_FLOAT:
583 case V_028C70_COLOR_32_32:
584 case V_028C70_COLOR_X24_8_32_FLOAT:
585 return ENDIAN_8IN32;
586
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT:
591 case V_028C70_COLOR_32_32_32_32:
592 return ENDIAN_8IN32;
593 default:
594 return ENDIAN_NONE; /* Unsupported. */
595 }
596 } else {
597 return ENDIAN_NONE;
598 }
599 }
600
601 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602 {
603 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604 }
605
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607 {
608 return r600_translate_colorformat(format) != ~0U &&
609 r600_translate_colorswap(format) != ~0U;
610 }
611
612 static bool r600_is_zs_format_supported(enum pipe_format format)
613 {
614 return r600_translate_dbformat(format) != ~0U;
615 }
616
617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 if (sample_count > 1) {
635 if (rscreen->info.drm_minor < 19)
636 return FALSE;
637
638 switch (sample_count) {
639 case 2:
640 case 4:
641 case 8:
642 break;
643 default:
644 return FALSE;
645 }
646 }
647
648 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
649 r600_is_sampler_format_supported(screen, format)) {
650 retval |= PIPE_BIND_SAMPLER_VIEW;
651 }
652
653 if ((usage & (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED)) &&
657 r600_is_colorbuffer_format_supported(format)) {
658 retval |= usage &
659 (PIPE_BIND_RENDER_TARGET |
660 PIPE_BIND_DISPLAY_TARGET |
661 PIPE_BIND_SCANOUT |
662 PIPE_BIND_SHARED);
663 }
664
665 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
666 r600_is_zs_format_supported(format)) {
667 retval |= PIPE_BIND_DEPTH_STENCIL;
668 }
669
670 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
671 r600_is_vertex_format_supported(format)) {
672 retval |= PIPE_BIND_VERTEX_BUFFER;
673 }
674
675 if (usage & PIPE_BIND_TRANSFER_READ)
676 retval |= PIPE_BIND_TRANSFER_READ;
677 if (usage & PIPE_BIND_TRANSFER_WRITE)
678 retval |= PIPE_BIND_TRANSFER_WRITE;
679
680 return retval == usage;
681 }
682
683 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
684 const struct pipe_blend_state *state, int mode)
685 {
686 struct r600_context *rctx = (struct r600_context *)ctx;
687 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
688 struct r600_pipe_state *rstate;
689 uint32_t color_control = 0, target_mask;
690 /* XXX there is more then 8 framebuffer */
691 unsigned blend_cntl[8];
692
693 if (blend == NULL) {
694 return NULL;
695 }
696
697 rstate = &blend->rstate;
698
699 rstate->id = R600_PIPE_STATE_BLEND;
700
701 target_mask = 0;
702 if (state->logicop_enable) {
703 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
704 } else {
705 color_control |= (0xcc << 16);
706 }
707 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
708 if (state->independent_blend_enable) {
709 for (int i = 0; i < 8; i++) {
710 target_mask |= (state->rt[i].colormask << (4 * i));
711 }
712 } else {
713 for (int i = 0; i < 8; i++) {
714 target_mask |= (state->rt[0].colormask << (4 * i));
715 }
716 }
717 blend->cb_target_mask = target_mask;
718
719 if (target_mask)
720 color_control |= S_028808_MODE(mode);
721 else
722 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
723
724 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
725 color_control);
726 /* only have dual source on MRT0 */
727 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
728 for (int i = 0; i < 8; i++) {
729 /* state->rt entries > 0 only written if independent blending */
730 const int j = state->independent_blend_enable ? i : 0;
731
732 unsigned eqRGB = state->rt[j].rgb_func;
733 unsigned srcRGB = state->rt[j].rgb_src_factor;
734 unsigned dstRGB = state->rt[j].rgb_dst_factor;
735 unsigned eqA = state->rt[j].alpha_func;
736 unsigned srcA = state->rt[j].alpha_src_factor;
737 unsigned dstA = state->rt[j].alpha_dst_factor;
738
739 blend_cntl[i] = 0;
740 if (!state->rt[j].blend_enable)
741 continue;
742
743 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
744 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
745 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
746 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
747
748 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
749 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
750 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
751 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
752 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
753 }
754 }
755 for (int i = 0; i < 8; i++) {
756 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
757 }
758
759 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
760 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
761 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
762 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
763 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
764 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
765
766 blend->alpha_to_one = state->alpha_to_one;
767 return rstate;
768 }
769
770 static void *evergreen_create_blend_state(struct pipe_context *ctx,
771 const struct pipe_blend_state *state)
772 {
773
774 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
775 }
776
777 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
778 const struct pipe_depth_stencil_alpha_state *state)
779 {
780 struct r600_context *rctx = (struct r600_context *)ctx;
781 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
782 unsigned db_depth_control, alpha_test_control, alpha_ref;
783 struct r600_pipe_state *rstate;
784
785 if (dsa == NULL) {
786 return NULL;
787 }
788
789 dsa->valuemask[0] = state->stencil[0].valuemask;
790 dsa->valuemask[1] = state->stencil[1].valuemask;
791 dsa->writemask[0] = state->stencil[0].writemask;
792 dsa->writemask[1] = state->stencil[1].writemask;
793
794 rstate = &dsa->rstate;
795
796 rstate->id = R600_PIPE_STATE_DSA;
797 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
798 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
799 S_028800_ZFUNC(state->depth.func);
800
801 /* stencil */
802 if (state->stencil[0].enabled) {
803 db_depth_control |= S_028800_STENCIL_ENABLE(1);
804 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
805 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
806 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
807 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
808
809 if (state->stencil[1].enabled) {
810 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
811 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
812 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
813 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
814 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
815 }
816 }
817
818 /* alpha */
819 alpha_test_control = 0;
820 alpha_ref = 0;
821 if (state->alpha.enabled) {
822 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
823 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
824 alpha_ref = fui(state->alpha.ref_value);
825 }
826 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
827 dsa->alpha_ref = alpha_ref;
828
829 /* misc */
830 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
831 return rstate;
832 }
833
834 static void *evergreen_create_rs_state(struct pipe_context *ctx,
835 const struct pipe_rasterizer_state *state)
836 {
837 struct r600_context *rctx = (struct r600_context *)ctx;
838 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
839 struct r600_pipe_state *rstate;
840 unsigned tmp;
841 unsigned prov_vtx = 1, polygon_dual_mode;
842 float psize_min, psize_max;
843
844 if (rs == NULL) {
845 return NULL;
846 }
847
848 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
849 state->fill_back != PIPE_POLYGON_MODE_FILL);
850
851 if (state->flatshade_first)
852 prov_vtx = 0;
853
854 rstate = &rs->rstate;
855 rs->flatshade = state->flatshade;
856 rs->sprite_coord_enable = state->sprite_coord_enable;
857 rs->two_side = state->light_twoside;
858 rs->clip_plane_enable = state->clip_plane_enable;
859 rs->pa_sc_line_stipple = state->line_stipple_enable ?
860 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
861 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
862 rs->pa_cl_clip_cntl =
863 S_028810_PS_UCP_MODE(3) |
864 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
865 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
866 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
867 rs->multisample_enable = state->multisample;
868
869 /* offset */
870 rs->offset_units = state->offset_units;
871 rs->offset_scale = state->offset_scale * 12.0f;
872
873 rstate->id = R600_PIPE_STATE_RASTERIZER;
874 tmp = S_0286D4_FLAT_SHADE_ENA(1);
875 if (state->sprite_coord_enable) {
876 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
877 S_0286D4_PNT_SPRITE_OVRD_X(2) |
878 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
879 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
880 S_0286D4_PNT_SPRITE_OVRD_W(1);
881 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
882 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
883 }
884 }
885 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
886
887 /* point size 12.4 fixed point */
888 tmp = (unsigned)(state->point_size * 8.0);
889 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
890
891 if (state->point_size_per_vertex) {
892 psize_min = util_get_min_point_size(state);
893 psize_max = 8192;
894 } else {
895 /* Force the point size to be as if the vertex output was disabled. */
896 psize_min = state->point_size;
897 psize_max = state->point_size;
898 }
899 /* Divide by two, because 0.5 = 1 pixel. */
900 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
901 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
902 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
903
904 tmp = (unsigned)state->line_width * 8;
905 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
906 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
907 S_028A48_MSAA_ENABLE(state->multisample) |
908 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
909 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
910
911 if (rctx->chip_class == CAYMAN) {
912 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
913 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
914 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
915 } else {
916 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
917 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
918 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
919 }
920 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
921 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
922 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
923 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
924 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
925 S_028814_FACE(!state->front_ccw) |
926 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
927 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
928 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
929 S_028814_POLY_MODE(polygon_dual_mode) |
930 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
931 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
932 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
933 return rstate;
934 }
935
936 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
937 const struct pipe_sampler_state *state)
938 {
939 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
940 union util_color uc;
941 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
942
943 if (ss == NULL) {
944 return NULL;
945 }
946
947 /* directly into sampler avoid r6xx code to emit useless reg */
948 ss->seamless_cube_map = false;
949 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
950 ss->border_color_use = false;
951 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
952 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
953 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
954 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
955 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
956 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
957 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
958 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
959 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
960 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
961 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
962 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
963 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
964 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
965 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
966 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
967 S_03C008_TYPE(1);
968 if (uc.ui) {
969 ss->border_color_use = true;
970 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
971 ss->border_color[0] = fui(state->border_color.f[0]);
972 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
973 ss->border_color[1] = fui(state->border_color.f[1]);
974 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
975 ss->border_color[2] = fui(state->border_color.f[2]);
976 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
977 ss->border_color[3] = fui(state->border_color.f[3]);
978 }
979 return ss;
980 }
981
982 struct pipe_sampler_view *
983 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
984 struct pipe_resource *texture,
985 const struct pipe_sampler_view *state,
986 unsigned width0, unsigned height0)
987 {
988 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
989 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
990 struct r600_texture *tmp = (struct r600_texture*)texture;
991 unsigned format, endian;
992 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
993 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
994 unsigned height, depth, width;
995 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
996
997 if (view == NULL)
998 return NULL;
999
1000 /* initialize base object */
1001 view->base = *state;
1002 view->base.texture = NULL;
1003 pipe_reference(NULL, &texture->reference);
1004 view->base.texture = texture;
1005 view->base.reference.count = 1;
1006 view->base.context = ctx;
1007
1008 swizzle[0] = state->swizzle_r;
1009 swizzle[1] = state->swizzle_g;
1010 swizzle[2] = state->swizzle_b;
1011 swizzle[3] = state->swizzle_a;
1012
1013 format = r600_translate_texformat(ctx->screen, state->format,
1014 swizzle,
1015 &word4, &yuv_format);
1016 assert(format != ~0);
1017 if (format == ~0) {
1018 FREE(view);
1019 return NULL;
1020 }
1021
1022 if (tmp->is_depth && !tmp->is_flushing_texture) {
1023 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1024 FREE(view);
1025 return NULL;
1026 }
1027 tmp = tmp->flushed_depth_texture;
1028 }
1029
1030 endian = r600_colorformat_endian_swap(format);
1031
1032 width = width0;
1033 height = height0;
1034 depth = tmp->surface.level[0].npix_z;
1035 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1036 tile_type = tmp->tile_type;
1037
1038 switch (tmp->surface.level[0].mode) {
1039 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1040 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1041 break;
1042 case RADEON_SURF_MODE_2D:
1043 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1044 break;
1045 case RADEON_SURF_MODE_1D:
1046 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1047 break;
1048 case RADEON_SURF_MODE_LINEAR:
1049 default:
1050 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1051 break;
1052 }
1053 tile_split = tmp->surface.tile_split;
1054 macro_aspect = tmp->surface.mtilea;
1055 bankw = tmp->surface.bankw;
1056 bankh = tmp->surface.bankh;
1057 tile_split = eg_tile_split(tile_split);
1058 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1059 bankw = eg_bank_wh(bankw);
1060 bankh = eg_bank_wh(bankh);
1061
1062 /* 128 bit formats require tile type = 1 */
1063 if (rscreen->chip_class == CAYMAN) {
1064 if (util_format_get_blocksize(state->format) >= 16)
1065 tile_type = 1;
1066 }
1067 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1068
1069 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1070 height = 1;
1071 depth = texture->array_size;
1072 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1073 depth = texture->array_size;
1074 }
1075
1076 view->tex_resource = &tmp->resource;
1077 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1078 S_030000_PITCH((pitch / 8) - 1) |
1079 S_030000_TEX_WIDTH(width - 1));
1080 if (rscreen->chip_class == CAYMAN)
1081 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1082 else
1083 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1084 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1085 S_030004_TEX_DEPTH(depth - 1) |
1086 S_030004_ARRAY_MODE(array_mode));
1087 view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1088 if (state->u.tex.last_level && texture->nr_samples <= 1) {
1089 view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1090 } else {
1091 view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1092 }
1093 view->tex_resource_words[4] = (word4 |
1094 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1095 S_030010_ENDIAN_SWAP(endian));
1096 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1097 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1098 if (texture->nr_samples > 1) {
1099 unsigned log_samples = util_logbase2(texture->nr_samples);
1100 if (rscreen->chip_class == CAYMAN) {
1101 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1102 }
1103 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1104 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1105 } else {
1106 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1107 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1108 }
1109 /* aniso max 16 samples */
1110 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1111 (S_030018_TILE_SPLIT(tile_split));
1112 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1113 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1114 S_03001C_BANK_WIDTH(bankw) |
1115 S_03001C_BANK_HEIGHT(bankh) |
1116 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1117 S_03001C_NUM_BANKS(nbanks);
1118 return &view->base;
1119 }
1120
1121 static struct pipe_sampler_view *
1122 evergreen_create_sampler_view(struct pipe_context *ctx,
1123 struct pipe_resource *tex,
1124 const struct pipe_sampler_view *state)
1125 {
1126 return evergreen_create_sampler_view_custom(ctx, tex, state,
1127 tex->width0, tex->height0);
1128 }
1129
1130 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1131 {
1132 struct radeon_winsys_cs *cs = rctx->cs;
1133 struct pipe_clip_state *state = &rctx->clip_state.state;
1134
1135 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1136 r600_write_array(cs, 6*4, (unsigned*)state);
1137 }
1138
1139 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1140 const struct pipe_poly_stipple *state)
1141 {
1142 }
1143
1144 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1145 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1146 uint32_t *tl, uint32_t *br)
1147 {
1148 /* EG hw workaround */
1149 if (br_x == 0)
1150 tl_x = 1;
1151 if (br_y == 0)
1152 tl_y = 1;
1153
1154 /* cayman hw workaround */
1155 if (rctx->chip_class == CAYMAN) {
1156 if (br_x == 1 && br_y == 1)
1157 br_x = 2;
1158 }
1159
1160 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1161 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1162 }
1163
1164 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1165 const struct pipe_scissor_state *state)
1166 {
1167 struct r600_context *rctx = (struct r600_context *)ctx;
1168 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1169 uint32_t tl, br;
1170
1171 rctx->scissor = *state;
1172
1173 if (rstate == NULL)
1174 return;
1175
1176 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1177
1178 rstate->id = R600_PIPE_STATE_SCISSOR;
1179 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1180 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1181
1182 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1183 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1184 r600_context_pipe_state_set(rctx, rstate);
1185 }
1186
1187 /**
1188 * This function intializes the CB* register values for RATs. It is meant
1189 * to be used for 1D aligned buffers that do not have an associated
1190 * radeon_surface.
1191 */
1192 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1193 struct r600_surface *surf)
1194 {
1195 struct pipe_resource *pipe_buffer = surf->base.texture;
1196 unsigned format = r600_translate_colorformat(surf->base.format);
1197 unsigned endian = r600_colorformat_endian_swap(format);
1198 unsigned swap = r600_translate_colorswap(surf->base.format);
1199 unsigned block_size =
1200 align(util_format_get_blocksize(pipe_buffer->format), 4);
1201 unsigned pitch_alignment =
1202 MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
1203 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
1204
1205 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1206 * know why this is necessary.
1207 */
1208 if (pipe_buffer->usage == PIPE_USAGE_STAGING) {
1209 endian = ENDIAN_NONE;
1210 }
1211
1212 surf->cb_color_base =
1213 r600_resource_va(rctx->context.screen, pipe_buffer) >> 8;
1214
1215 surf->cb_color_pitch = (pitch / 8) - 1;
1216
1217 surf->cb_color_slice = 0;
1218
1219 surf->cb_color_view = 0;
1220
1221 surf->cb_color_info =
1222 S_028C70_ENDIAN(endian)
1223 | S_028C70_FORMAT(format)
1224 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED)
1225 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT)
1226 | S_028C70_COMP_SWAP(swap)
1227 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1228 * are using NUMBER_UINT */
1229 | S_028C70_RAT(1)
1230 ;
1231
1232 surf->cb_color_attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1233
1234 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1235 * elements. */
1236 surf->cb_color_dim = pipe_buffer->width0;
1237
1238 surf->cb_color_cmask = surf->cb_color_base;
1239 surf->cb_color_cmask_slice = 0;
1240 surf->cb_color_fmask = surf->cb_color_base;
1241 surf->cb_color_fmask_slice = 0;
1242 }
1243
1244 void evergreen_init_color_surface(struct r600_context *rctx,
1245 struct r600_surface *surf)
1246 {
1247 struct r600_screen *rscreen = rctx->screen;
1248 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1249 struct pipe_resource *pipe_tex = surf->base.texture;
1250 unsigned level = surf->base.u.tex.level;
1251 unsigned pitch, slice;
1252 unsigned color_info, color_attrib, color_dim = 0;
1253 unsigned format, swap, ntype, endian;
1254 uint64_t offset, base_offset;
1255 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1256 const struct util_format_description *desc;
1257 int i;
1258 bool blend_clamp = 0, blend_bypass = 0;
1259
1260 if (rtex->is_depth && !rtex->is_flushing_texture) {
1261 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1262 rtex = rtex->flushed_depth_texture;
1263 assert(rtex);
1264 }
1265
1266 offset = rtex->surface.level[level].offset;
1267 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1268 offset += rtex->surface.level[level].slice_size *
1269 surf->base.u.tex.first_layer;
1270 }
1271 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1272 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1273 if (slice) {
1274 slice = slice - 1;
1275 }
1276 color_info = 0;
1277 switch (rtex->surface.level[level].mode) {
1278 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1279 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1280 tile_type = 1;
1281 break;
1282 case RADEON_SURF_MODE_1D:
1283 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1284 tile_type = rtex->tile_type;
1285 break;
1286 case RADEON_SURF_MODE_2D:
1287 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1288 tile_type = rtex->tile_type;
1289 break;
1290 case RADEON_SURF_MODE_LINEAR:
1291 default:
1292 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1293 tile_type = 1;
1294 break;
1295 }
1296 tile_split = rtex->surface.tile_split;
1297 macro_aspect = rtex->surface.mtilea;
1298 bankw = rtex->surface.bankw;
1299 bankh = rtex->surface.bankh;
1300 fmask_bankh = rtex->fmask_bank_height;
1301 tile_split = eg_tile_split(tile_split);
1302 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1303 bankw = eg_bank_wh(bankw);
1304 bankh = eg_bank_wh(bankh);
1305 fmask_bankh = eg_bank_wh(fmask_bankh);
1306
1307 /* 128 bit formats require tile type = 1 */
1308 if (rscreen->chip_class == CAYMAN) {
1309 if (util_format_get_blocksize(surf->base.format) >= 16)
1310 tile_type = 1;
1311 }
1312 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1313 desc = util_format_description(surf->base.format);
1314 for (i = 0; i < 4; i++) {
1315 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1316 break;
1317 }
1318 }
1319
1320 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1321 S_028C74_NUM_BANKS(nbanks) |
1322 S_028C74_BANK_WIDTH(bankw) |
1323 S_028C74_BANK_HEIGHT(bankh) |
1324 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1325 S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1326 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1327
1328 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1329 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1330 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1331 S_028C74_NUM_FRAGMENTS(log_samples);
1332 }
1333
1334 ntype = V_028C70_NUMBER_UNORM;
1335 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1336 ntype = V_028C70_NUMBER_SRGB;
1337 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1338 if (desc->channel[i].normalized)
1339 ntype = V_028C70_NUMBER_SNORM;
1340 else if (desc->channel[i].pure_integer)
1341 ntype = V_028C70_NUMBER_SINT;
1342 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1343 if (desc->channel[i].normalized)
1344 ntype = V_028C70_NUMBER_UNORM;
1345 else if (desc->channel[i].pure_integer)
1346 ntype = V_028C70_NUMBER_UINT;
1347 }
1348
1349 format = r600_translate_colorformat(surf->base.format);
1350 assert(format != ~0);
1351
1352 swap = r600_translate_colorswap(surf->base.format);
1353 assert(swap != ~0);
1354
1355 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1356 endian = ENDIAN_NONE;
1357 } else {
1358 endian = r600_colorformat_endian_swap(format);
1359 }
1360
1361 /* blend clamp should be set for all NORM/SRGB types */
1362 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1363 ntype == V_028C70_NUMBER_SRGB)
1364 blend_clamp = 1;
1365
1366 /* set blend bypass according to docs if SINT/UINT or
1367 8/24 COLOR variants */
1368 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1369 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1370 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1371 blend_clamp = 0;
1372 blend_bypass = 1;
1373 }
1374
1375 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1376
1377 color_info |= S_028C70_FORMAT(format) |
1378 S_028C70_COMP_SWAP(swap) |
1379 S_028C70_BLEND_CLAMP(blend_clamp) |
1380 S_028C70_BLEND_BYPASS(blend_bypass) |
1381 S_028C70_NUMBER_TYPE(ntype) |
1382 S_028C70_ENDIAN(endian);
1383
1384 if (rtex->is_rat) {
1385 color_info |= S_028C70_RAT(1);
1386 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
1387 | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
1388 }
1389
1390 /* EXPORT_NORM is an optimzation that can be enabled for better
1391 * performance in certain cases.
1392 * EXPORT_NORM can be enabled if:
1393 * - 11-bit or smaller UNORM/SNORM/SRGB
1394 * - 16-bit or smaller FLOAT
1395 */
1396 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1397 ((desc->channel[i].size < 12 &&
1398 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1399 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1400 (desc->channel[i].size < 17 &&
1401 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1402 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1403 surf->export_16bpc = true;
1404 }
1405
1406 if (rtex->fmask_size && rtex->cmask_size) {
1407 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1408 }
1409
1410 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1411
1412 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1413 surf->cb_color_base = (base_offset + offset) >> 8;
1414 surf->cb_color_dim = color_dim;
1415 surf->cb_color_info = color_info;
1416 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1417 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1418 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1419 surf->cb_color_view = 0;
1420 } else {
1421 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1422 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1423 }
1424 surf->cb_color_attrib = color_attrib;
1425 if (rtex->fmask_size && rtex->cmask_size) {
1426 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1427 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1428 } else {
1429 surf->cb_color_fmask = surf->cb_color_base;
1430 surf->cb_color_cmask = surf->cb_color_base;
1431 }
1432 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1433 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1434
1435 surf->color_initialized = true;
1436 }
1437
1438 static void evergreen_init_depth_surface(struct r600_context *rctx,
1439 struct r600_surface *surf)
1440 {
1441 struct r600_screen *rscreen = rctx->screen;
1442 struct pipe_screen *screen = &rscreen->screen;
1443 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1444 uint64_t offset;
1445 unsigned level, pitch, slice, format, array_mode;
1446 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1447
1448 level = surf->base.u.tex.level;
1449 format = r600_translate_dbformat(surf->base.format);
1450 assert(format != ~0);
1451
1452 offset = r600_resource_va(screen, surf->base.texture);
1453 offset += rtex->surface.level[level].offset;
1454 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1455 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1456 if (slice) {
1457 slice = slice - 1;
1458 }
1459 switch (rtex->surface.level[level].mode) {
1460 case RADEON_SURF_MODE_2D:
1461 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1462 break;
1463 case RADEON_SURF_MODE_1D:
1464 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1465 case RADEON_SURF_MODE_LINEAR:
1466 default:
1467 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1468 break;
1469 }
1470 tile_split = rtex->surface.tile_split;
1471 macro_aspect = rtex->surface.mtilea;
1472 bankw = rtex->surface.bankw;
1473 bankh = rtex->surface.bankh;
1474 tile_split = eg_tile_split(tile_split);
1475 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1476 bankw = eg_bank_wh(bankw);
1477 bankh = eg_bank_wh(bankh);
1478 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1479 offset >>= 8;
1480
1481 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1482 S_028040_FORMAT(format) |
1483 S_028040_TILE_SPLIT(tile_split)|
1484 S_028040_NUM_BANKS(nbanks) |
1485 S_028040_BANK_WIDTH(bankw) |
1486 S_028040_BANK_HEIGHT(bankh) |
1487 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1488 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1489 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1490 }
1491 surf->db_depth_base = offset;
1492 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1493 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1494 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1495 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1496
1497 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1498 uint64_t stencil_offset = rtex->surface.stencil_offset;
1499 unsigned i, stile_split = rtex->surface.stencil_tile_split;
1500
1501 stile_split = eg_tile_split(stile_split);
1502 stencil_offset += r600_resource_va(screen, surf->base.texture);
1503 stencil_offset += rtex->surface.level[level].offset / 4;
1504 stencil_offset >>= 8;
1505
1506 /* We're guessing the stencil offset from the depth offset.
1507 * Make sure each mipmap level has a unique offset. */
1508 for (i = 1; i <= level; i++) {
1509 /* If two levels have the same address, add 256
1510 * to the offset of the smaller level. */
1511 if ((rtex->surface.level[i-1].offset / 4) >> 8 ==
1512 (rtex->surface.level[i].offset / 4) >> 8) {
1513 stencil_offset++;
1514 }
1515 }
1516
1517 surf->db_stencil_base = stencil_offset;
1518 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1519 S_028044_TILE_SPLIT(stile_split);
1520 } else {
1521 surf->db_stencil_base = offset;
1522 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1523 * Older kernels are out of luck. */
1524 surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
1525 S_028044_FORMAT(V_028044_STENCIL_INVALID) :
1526 S_028044_FORMAT(V_028044_STENCIL_8);
1527 }
1528
1529 surf->depth_initialized = true;
1530 }
1531
1532 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1533 const struct pipe_framebuffer_state *state)
1534 {
1535 struct r600_context *rctx = (struct r600_context *)ctx;
1536 struct r600_surface *surf;
1537 struct r600_texture *rtex;
1538 uint32_t i, log_samples;
1539
1540 if (rctx->framebuffer.state.nr_cbufs) {
1541 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1542
1543 if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1544 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1545 }
1546 }
1547 if (rctx->framebuffer.state.zsbuf) {
1548 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1549 }
1550
1551 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1552
1553 /* Colorbuffers. */
1554 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1555 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1556 util_format_is_pure_integer(state->cbufs[0]->format);
1557 rctx->framebuffer.compressed_cb_mask = 0;
1558
1559 if (state->nr_cbufs)
1560 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1561 else if (state->zsbuf)
1562 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1563 else
1564 rctx->framebuffer.nr_samples = 0;
1565
1566 for (i = 0; i < state->nr_cbufs; i++) {
1567 surf = (struct r600_surface*)state->cbufs[i];
1568 rtex = (struct r600_texture*)surf->base.texture;
1569
1570 if (!surf->color_initialized) {
1571 evergreen_init_color_surface(rctx, surf);
1572 }
1573
1574 if (!surf->export_16bpc) {
1575 rctx->framebuffer.export_16bpc = false;
1576 }
1577
1578 /* Cayman can fetch from a compressed MSAA colorbuffer,
1579 * so it's pointless to track them. */
1580 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1581 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1582 }
1583 }
1584
1585 /* Update alpha-test state dependencies.
1586 * Alpha-test is done on the first colorbuffer only. */
1587 if (state->nr_cbufs) {
1588 surf = (struct r600_surface*)state->cbufs[0];
1589 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1590 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1591 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1592 }
1593 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1594 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1595 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1596 }
1597 }
1598
1599 /* ZS buffer. */
1600 if (state->zsbuf) {
1601 surf = (struct r600_surface*)state->zsbuf;
1602
1603 if (!surf->depth_initialized) {
1604 evergreen_init_depth_surface(rctx, surf);
1605 }
1606
1607 evergreen_polygon_offset_update(rctx);
1608 }
1609
1610 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1611 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1612 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1613 }
1614
1615 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1616 rctx->alphatest_state.bypass = false;
1617 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1618 }
1619
1620 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1621 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1622 rctx->db_misc_state.log_samples = log_samples;
1623 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1624 }
1625
1626 /* Calculate the CS size. */
1627 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1628
1629 /* MSAA. */
1630 if (rctx->chip_class == EVERGREEN) {
1631 switch (rctx->framebuffer.nr_samples) {
1632 case 2:
1633 case 4:
1634 rctx->framebuffer.atom.num_dw += 6;
1635 break;
1636 case 8:
1637 rctx->framebuffer.atom.num_dw += 10;
1638 break;
1639 }
1640 rctx->framebuffer.atom.num_dw += 4;
1641 } else {
1642 switch (rctx->framebuffer.nr_samples) {
1643 case 2:
1644 case 4:
1645 rctx->framebuffer.atom.num_dw += 12;
1646 break;
1647 case 8:
1648 rctx->framebuffer.atom.num_dw += 16;
1649 break;
1650 case 16:
1651 rctx->framebuffer.atom.num_dw += 18;
1652 break;
1653 }
1654 rctx->framebuffer.atom.num_dw += 7;
1655 }
1656
1657 /* Colorbuffers. */
1658 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
1659 if (rctx->keep_tiling_flags)
1660 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1661 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1662
1663 /* ZS buffer. */
1664 if (state->zsbuf) {
1665 rctx->framebuffer.atom.num_dw += 21;
1666 if (rctx->keep_tiling_flags)
1667 rctx->framebuffer.atom.num_dw += 2;
1668 } else if (rctx->screen->info.drm_minor >= 18) {
1669 rctx->framebuffer.atom.num_dw += 4;
1670 }
1671
1672 r600_atom_dirty(rctx, &rctx->framebuffer.atom);
1673 }
1674
1675 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1676 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1677 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1678 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1679 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1680
1681 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1682 {
1683 /* 2xMSAA
1684 * There are two locations (-4, 4), (4, -4). */
1685 static uint32_t sample_locs_2x[] = {
1686 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1687 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1688 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1689 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1690 };
1691 static unsigned max_dist_2x = 4;
1692 /* 4xMSAA
1693 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1694 static uint32_t sample_locs_4x[] = {
1695 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1696 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1697 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1698 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1699 };
1700 static unsigned max_dist_4x = 6;
1701 /* 8xMSAA */
1702 static uint32_t sample_locs_8x[] = {
1703 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1704 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1705 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1706 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1707 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1708 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1709 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1710 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1711 };
1712 static unsigned max_dist_8x = 8;
1713
1714 struct radeon_winsys_cs *cs = rctx->cs;
1715 unsigned max_dist = 0;
1716
1717 switch (nr_samples) {
1718 default:
1719 nr_samples = 0;
1720 break;
1721 case 2:
1722 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
1723 r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
1724 max_dist = max_dist_2x;
1725 break;
1726 case 4:
1727 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
1728 r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
1729 max_dist = max_dist_4x;
1730 break;
1731 case 8:
1732 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
1733 r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
1734 max_dist = max_dist_8x;
1735 break;
1736 }
1737
1738 if (nr_samples > 1) {
1739 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1740 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1741 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1742 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1743 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1744 } else {
1745 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1746 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1747 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1748 }
1749 }
1750
1751 static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1752 {
1753 /* 2xMSAA
1754 * There are two locations (-4, 4), (4, -4). */
1755 static uint32_t sample_locs_2x[] = {
1756 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1757 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1758 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1759 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1760 };
1761 static unsigned max_dist_2x = 4;
1762 /* 4xMSAA
1763 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1764 static uint32_t sample_locs_4x[] = {
1765 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1766 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1767 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1768 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1769 };
1770 static unsigned max_dist_4x = 6;
1771 /* 8xMSAA */
1772 static uint32_t sample_locs_8x[] = {
1773 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1774 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1775 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1776 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1777 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1778 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1779 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1780 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1781 };
1782 static unsigned max_dist_8x = 8;
1783 /* 16xMSAA */
1784 static uint32_t sample_locs_16x[] = {
1785 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1786 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1787 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1788 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1789 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1790 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1791 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1792 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1793 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1794 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1795 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1796 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1797 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1798 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1799 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1800 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1801 };
1802 static unsigned max_dist_16x = 8;
1803
1804 struct radeon_winsys_cs *cs = rctx->cs;
1805 unsigned max_dist = 0;
1806
1807 switch (nr_samples) {
1808 default:
1809 nr_samples = 0;
1810 break;
1811 case 2:
1812 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1813 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1814 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1815 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1816 max_dist = max_dist_2x;
1817 break;
1818 case 4:
1819 r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1820 r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1821 r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1822 r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1823 max_dist = max_dist_4x;
1824 break;
1825 case 8:
1826 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1827 r600_write_value(cs, sample_locs_8x[0]);
1828 r600_write_value(cs, sample_locs_8x[4]);
1829 r600_write_value(cs, 0);
1830 r600_write_value(cs, 0);
1831 r600_write_value(cs, sample_locs_8x[1]);
1832 r600_write_value(cs, sample_locs_8x[5]);
1833 r600_write_value(cs, 0);
1834 r600_write_value(cs, 0);
1835 r600_write_value(cs, sample_locs_8x[2]);
1836 r600_write_value(cs, sample_locs_8x[6]);
1837 r600_write_value(cs, 0);
1838 r600_write_value(cs, 0);
1839 r600_write_value(cs, sample_locs_8x[3]);
1840 r600_write_value(cs, sample_locs_8x[7]);
1841 max_dist = max_dist_8x;
1842 break;
1843 case 16:
1844 r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1845 r600_write_value(cs, sample_locs_16x[0]);
1846 r600_write_value(cs, sample_locs_16x[4]);
1847 r600_write_value(cs, sample_locs_16x[8]);
1848 r600_write_value(cs, sample_locs_16x[12]);
1849 r600_write_value(cs, sample_locs_16x[1]);
1850 r600_write_value(cs, sample_locs_16x[5]);
1851 r600_write_value(cs, sample_locs_16x[9]);
1852 r600_write_value(cs, sample_locs_16x[13]);
1853 r600_write_value(cs, sample_locs_16x[2]);
1854 r600_write_value(cs, sample_locs_16x[6]);
1855 r600_write_value(cs, sample_locs_16x[10]);
1856 r600_write_value(cs, sample_locs_16x[14]);
1857 r600_write_value(cs, sample_locs_16x[3]);
1858 r600_write_value(cs, sample_locs_16x[7]);
1859 r600_write_value(cs, sample_locs_16x[11]);
1860 r600_write_value(cs, sample_locs_16x[15]);
1861 max_dist = max_dist_16x;
1862 break;
1863 }
1864
1865 if (nr_samples > 1) {
1866 unsigned log_samples = util_logbase2(nr_samples);
1867
1868 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1869 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1870 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1871 r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1872 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1873 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1874
1875 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1876 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1877 S_028804_PS_ITER_SAMPLES(log_samples) |
1878 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1879 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1880 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1881 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1882 } else {
1883 r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
1884 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1885 r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1886
1887 r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
1888 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1889 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1890 }
1891 }
1892
1893 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1894 {
1895 struct radeon_winsys_cs *cs = rctx->cs;
1896 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1897 unsigned nr_cbufs = state->nr_cbufs;
1898 unsigned i, tl, br;
1899
1900 /* XXX support more colorbuffers once we need them */
1901 assert(nr_cbufs <= 8);
1902 if (nr_cbufs > 8)
1903 nr_cbufs = 8;
1904
1905 /* Colorbuffers. */
1906 for (i = 0; i < nr_cbufs; i++) {
1907 struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
1908 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)cb->base.texture,
1909 RADEON_USAGE_READWRITE);
1910
1911 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
1912 r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1913 r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1914 r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1915 r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1916 r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1917 r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1918 r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1919 r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
1920 r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1921 r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1922 r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1923
1924 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1925 r600_write_value(cs, reloc);
1926
1927 if (!rctx->keep_tiling_flags) {
1928 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1929 r600_write_value(cs, reloc);
1930 }
1931
1932 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1933 r600_write_value(cs, reloc);
1934
1935 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1936 r600_write_value(cs, reloc);
1937
1938 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1939 r600_write_value(cs, reloc);
1940 }
1941 /* set CB_COLOR1_INFO for possible dual-src blending */
1942 if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
1943 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1944 ((struct r600_surface*)state->cbufs[0])->cb_color_info);
1945
1946 if (!rctx->keep_tiling_flags) {
1947 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->cbufs[0]->texture,
1948 RADEON_USAGE_READWRITE);
1949
1950 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
1951 r600_write_value(cs, reloc);
1952 }
1953 i++;
1954 }
1955 if (rctx->keep_tiling_flags) {
1956 for (; i < 8 ; i++) {
1957 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1958 }
1959 for (; i < 12; i++) {
1960 r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1961 }
1962 }
1963
1964 /* ZS buffer. */
1965 if (state->zsbuf) {
1966 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1967 unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->zsbuf->texture,
1968 RADEON_USAGE_READWRITE);
1969
1970 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1971
1972 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1973 r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
1974 r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1975 r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1976 r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1977 r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1978 r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1979 r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1980 r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1981
1982 if (!rctx->keep_tiling_flags) {
1983 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
1984 r600_write_value(cs, reloc);
1985 }
1986
1987 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1988 r600_write_value(cs, reloc);
1989
1990 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1991 r600_write_value(cs, reloc);
1992
1993 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1994 r600_write_value(cs, reloc);
1995
1996 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1997 r600_write_value(cs, reloc);
1998 } else if (rctx->screen->info.drm_minor >= 18) {
1999 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2000 * Older kernels are out of luck. */
2001 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2002 r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2003 r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2004 }
2005
2006 /* Framebuffer dimensions. */
2007 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
2008
2009 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
2010 r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2011 r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2012
2013 if (rctx->chip_class == EVERGREEN) {
2014 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2015 } else {
2016 cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
2017 }
2018 }
2019
2020 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2021 {
2022 struct radeon_winsys_cs *cs = rctx->cs;
2023 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2024 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
2025 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
2026
2027 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2028 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
2029 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2030 * will assure that the alpha-test will work even if there is
2031 * no colorbuffer bound. */
2032 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
2033 }
2034
2035 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2036 {
2037 struct radeon_winsys_cs *cs = rctx->cs;
2038 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2039 unsigned db_render_control = 0;
2040 unsigned db_count_control = 0;
2041 unsigned db_render_override =
2042 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
2043 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2044 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2045
2046 if (a->occlusion_query_enabled) {
2047 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2048 if (rctx->chip_class == CAYMAN) {
2049 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2050 }
2051 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2052 }
2053
2054 if (a->flush_depthstencil_through_cb) {
2055 assert(a->copy_depth || a->copy_stencil);
2056
2057 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2058 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2059 S_028000_COPY_CENTROID(1) |
2060 S_028000_COPY_SAMPLE(a->copy_sample);
2061 }
2062
2063 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2064 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2065 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2066 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2067 }
2068
2069 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2070 struct r600_vertexbuf_state *state,
2071 unsigned resource_offset,
2072 unsigned pkt_flags)
2073 {
2074 struct radeon_winsys_cs *cs = rctx->cs;
2075 uint32_t dirty_mask = state->dirty_mask;
2076
2077 while (dirty_mask) {
2078 struct pipe_vertex_buffer *vb;
2079 struct r600_resource *rbuffer;
2080 uint64_t va;
2081 unsigned buffer_index = u_bit_scan(&dirty_mask);
2082
2083 vb = &state->vb[buffer_index];
2084 rbuffer = (struct r600_resource*)vb->buffer;
2085 assert(rbuffer);
2086
2087 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2088 va += vb->buffer_offset;
2089
2090 /* fetch resources start at index 992 */
2091 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2092 r600_write_value(cs, (resource_offset + buffer_index) * 8);
2093 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2094 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2095 r600_write_value(cs, /* RESOURCEi_WORD2 */
2096 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2097 S_030008_STRIDE(vb->stride) |
2098 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2099 r600_write_value(cs, /* RESOURCEi_WORD3 */
2100 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2101 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2102 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2103 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2104 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2105 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2106 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2107 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2108
2109 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2110 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2111 }
2112 state->dirty_mask = 0;
2113 }
2114
2115 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2116 {
2117 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
2118 }
2119
2120 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2121 {
2122 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2123 RADEON_CP_PACKET3_COMPUTE_MODE);
2124 }
2125
2126 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2127 struct r600_constbuf_state *state,
2128 unsigned buffer_id_base,
2129 unsigned reg_alu_constbuf_size,
2130 unsigned reg_alu_const_cache)
2131 {
2132 struct radeon_winsys_cs *cs = rctx->cs;
2133 uint32_t dirty_mask = state->dirty_mask;
2134
2135 while (dirty_mask) {
2136 struct pipe_constant_buffer *cb;
2137 struct r600_resource *rbuffer;
2138 uint64_t va;
2139 unsigned buffer_index = ffs(dirty_mask) - 1;
2140
2141 cb = &state->cb[buffer_index];
2142 rbuffer = (struct r600_resource*)cb->buffer;
2143 assert(rbuffer);
2144
2145 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2146 va += cb->buffer_offset;
2147
2148 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2149 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2150 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2151
2152 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2153 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2154
2155 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2156 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2157 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2158 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2159 r600_write_value(cs, /* RESOURCEi_WORD2 */
2160 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2161 S_030008_STRIDE(16) |
2162 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2163 r600_write_value(cs, /* RESOURCEi_WORD3 */
2164 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2165 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2166 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2167 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2168 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2169 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2170 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2171 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2172
2173 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2174 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2175
2176 dirty_mask &= ~(1 << buffer_index);
2177 }
2178 state->dirty_mask = 0;
2179 }
2180
2181 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2182 {
2183 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 176,
2184 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2185 R_028980_ALU_CONST_CACHE_VS_0);
2186 }
2187
2188 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2189 {
2190 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2191 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2192 R_0289C0_ALU_CONST_CACHE_GS_0);
2193 }
2194
2195 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2196 {
2197 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2198 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2199 R_028940_ALU_CONST_CACHE_PS_0);
2200 }
2201
2202 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2203 struct r600_samplerview_state *state,
2204 unsigned resource_id_base)
2205 {
2206 struct radeon_winsys_cs *cs = rctx->cs;
2207 uint32_t dirty_mask = state->dirty_mask;
2208
2209 while (dirty_mask) {
2210 struct r600_pipe_sampler_view *rview;
2211 unsigned resource_index = u_bit_scan(&dirty_mask);
2212 unsigned reloc;
2213
2214 rview = state->views[resource_index];
2215 assert(rview);
2216
2217 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2218 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2219 r600_write_array(cs, 8, rview->tex_resource_words);
2220
2221 /* XXX The kernel needs two relocations. This is stupid. */
2222 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2223 RADEON_USAGE_READ);
2224 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2225 r600_write_value(cs, reloc);
2226 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2227 r600_write_value(cs, reloc);
2228 }
2229 state->dirty_mask = 0;
2230 }
2231
2232 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2233 {
2234 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
2235 }
2236
2237 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2238 {
2239 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2240 }
2241
2242 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2243 {
2244 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2245 }
2246
2247 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2248 struct r600_textures_info *texinfo,
2249 unsigned resource_id_base,
2250 unsigned border_index_reg)
2251 {
2252 struct radeon_winsys_cs *cs = rctx->cs;
2253 uint32_t dirty_mask = texinfo->states.dirty_mask;
2254
2255 while (dirty_mask) {
2256 struct r600_pipe_sampler_state *rstate;
2257 unsigned i = u_bit_scan(&dirty_mask);
2258
2259 rstate = texinfo->states.states[i];
2260 assert(rstate);
2261
2262 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2263 r600_write_value(cs, (resource_id_base + i) * 3);
2264 r600_write_array(cs, 3, rstate->tex_sampler_words);
2265
2266 if (rstate->border_color_use) {
2267 r600_write_config_reg_seq(cs, border_index_reg, 5);
2268 r600_write_value(cs, i);
2269 r600_write_array(cs, 4, rstate->border_color);
2270 }
2271 }
2272 texinfo->states.dirty_mask = 0;
2273 }
2274
2275 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2276 {
2277 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2278 }
2279
2280 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2281 {
2282 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
2283 }
2284
2285 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2286 {
2287 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2288 }
2289
2290 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2291 {
2292 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2293 uint8_t mask = s->sample_mask;
2294
2295 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2296 mask | (mask << 8) | (mask << 16) | (mask << 24));
2297 }
2298
2299 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2300 {
2301 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2302 struct radeon_winsys_cs *cs = rctx->cs;
2303 uint16_t mask = s->sample_mask;
2304
2305 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2306 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2307 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2308 }
2309
2310 void evergreen_init_state_functions(struct r600_context *rctx)
2311 {
2312 unsigned id = 4;
2313
2314 /* !!!
2315 * To avoid GPU lockup registers must be emited in a specific order
2316 * (no kidding ...). The order below is important and have been
2317 * partialy infered from analyzing fglrx command stream.
2318 *
2319 * Don't reorder atom without carefully checking the effect (GPU lockup
2320 * or piglit regression).
2321 * !!!
2322 */
2323
2324 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
2325 /* shader const */
2326 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
2327 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
2328 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
2329 /* shader program */
2330 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
2331 /* sampler */
2332 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
2333 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
2334 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
2335 /* resources */
2336 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
2337 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
2338 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
2339 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
2340 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
2341
2342 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2343 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2344
2345 if (rctx->chip_class == EVERGREEN) {
2346 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
2347 } else {
2348 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
2349 }
2350 rctx->sample_mask.sample_mask = ~0;
2351
2352 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2353 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2354 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
2355 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2356 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
2357 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
2358 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2359 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2360
2361 rctx->context.create_blend_state = evergreen_create_blend_state;
2362 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2363 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2364 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2365 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2366 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2367 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2368 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2369 evergreen_init_compute_state_functions(rctx);
2370 }
2371
2372 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2373 {
2374 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2375
2376 r600_init_command_buffer(cb, 256);
2377
2378 /* This must be first. */
2379 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2380 r600_store_value(cb, 0x80000000);
2381 r600_store_value(cb, 0x80000000);
2382
2383 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2384 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2385 /* always set the temp clauses */
2386 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2387
2388 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2389 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2390 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2391
2392 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2393
2394 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2395
2396 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2397 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2398 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2399 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2400 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2401 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2402 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2403 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2404 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2405 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2406 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2407 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2408 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2409 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2410
2411 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2412 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2413 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2414
2415 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2416 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2417 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2418
2419 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2420
2421 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2422
2423 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2424 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2425 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2426
2427 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2428 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2429 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2430
2431 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2432 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2433 r600_store_value(cb, 0);
2434 r600_store_value(cb, 0);
2435 r600_store_value(cb, 0);
2436 r600_store_value(cb, 0);
2437 r600_store_value(cb, 0);
2438 r600_store_value(cb, 0);
2439 r600_store_value(cb, 0);
2440 r600_store_value(cb, 0);
2441 r600_store_value(cb, 0);
2442 r600_store_value(cb, 0);
2443 r600_store_value(cb, 0);
2444 r600_store_value(cb, 0);
2445 r600_store_value(cb, 0);
2446 r600_store_value(cb, 0);
2447 r600_store_value(cb, 0);
2448 r600_store_value(cb, 0);
2449 r600_store_value(cb, 0);
2450 r600_store_value(cb, 0);
2451 r600_store_value(cb, 0);
2452 r600_store_value(cb, 0);
2453 r600_store_value(cb, 0);
2454 r600_store_value(cb, 0);
2455 r600_store_value(cb, 0);
2456 r600_store_value(cb, 0);
2457 r600_store_value(cb, 0);
2458 r600_store_value(cb, 0);
2459 r600_store_value(cb, 0);
2460 r600_store_value(cb, 0);
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2464 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2465 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2466
2467 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2468
2469 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2470 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2471 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2472
2473 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2474
2475 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2476 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2477 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2478 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2479
2480 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2481 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2482
2483 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2484 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2485 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2486
2487 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2488 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2489 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2490
2491 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2492 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2493 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2494 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2495 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2496
2497 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2498 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2499 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2500
2501 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2502 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2503 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2504
2505 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2506 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2507 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2508
2509 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2510 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2511 if (rctx->screen->has_streamout) {
2512 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2513 }
2514
2515 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2516 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2517 }
2518
2519 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2520 enum chip_class ctx_chip_class,
2521 enum radeon_family ctx_family,
2522 int ctx_drm_minor)
2523 {
2524 int ps_prio;
2525 int vs_prio;
2526 int gs_prio;
2527 int es_prio;
2528
2529 int hs_prio;
2530 int cs_prio;
2531 int ls_prio;
2532
2533 int num_ps_gprs;
2534 int num_vs_gprs;
2535 int num_gs_gprs;
2536 int num_es_gprs;
2537 int num_hs_gprs;
2538 int num_ls_gprs;
2539 int num_temp_gprs;
2540
2541 unsigned tmp;
2542
2543 ps_prio = 0;
2544 vs_prio = 1;
2545 gs_prio = 2;
2546 es_prio = 3;
2547 hs_prio = 0;
2548 ls_prio = 0;
2549 cs_prio = 0;
2550
2551 switch (ctx_family) {
2552 case CHIP_CEDAR:
2553 default:
2554 num_ps_gprs = 93;
2555 num_vs_gprs = 46;
2556 num_temp_gprs = 4;
2557 num_gs_gprs = 31;
2558 num_es_gprs = 31;
2559 num_hs_gprs = 23;
2560 num_ls_gprs = 23;
2561 break;
2562 case CHIP_REDWOOD:
2563 num_ps_gprs = 93;
2564 num_vs_gprs = 46;
2565 num_temp_gprs = 4;
2566 num_gs_gprs = 31;
2567 num_es_gprs = 31;
2568 num_hs_gprs = 23;
2569 num_ls_gprs = 23;
2570 break;
2571 case CHIP_JUNIPER:
2572 num_ps_gprs = 93;
2573 num_vs_gprs = 46;
2574 num_temp_gprs = 4;
2575 num_gs_gprs = 31;
2576 num_es_gprs = 31;
2577 num_hs_gprs = 23;
2578 num_ls_gprs = 23;
2579 break;
2580 case CHIP_CYPRESS:
2581 case CHIP_HEMLOCK:
2582 num_ps_gprs = 93;
2583 num_vs_gprs = 46;
2584 num_temp_gprs = 4;
2585 num_gs_gprs = 31;
2586 num_es_gprs = 31;
2587 num_hs_gprs = 23;
2588 num_ls_gprs = 23;
2589 break;
2590 case CHIP_PALM:
2591 num_ps_gprs = 93;
2592 num_vs_gprs = 46;
2593 num_temp_gprs = 4;
2594 num_gs_gprs = 31;
2595 num_es_gprs = 31;
2596 num_hs_gprs = 23;
2597 num_ls_gprs = 23;
2598 break;
2599 case CHIP_SUMO:
2600 num_ps_gprs = 93;
2601 num_vs_gprs = 46;
2602 num_temp_gprs = 4;
2603 num_gs_gprs = 31;
2604 num_es_gprs = 31;
2605 num_hs_gprs = 23;
2606 num_ls_gprs = 23;
2607 break;
2608 case CHIP_SUMO2:
2609 num_ps_gprs = 93;
2610 num_vs_gprs = 46;
2611 num_temp_gprs = 4;
2612 num_gs_gprs = 31;
2613 num_es_gprs = 31;
2614 num_hs_gprs = 23;
2615 num_ls_gprs = 23;
2616 break;
2617 case CHIP_BARTS:
2618 num_ps_gprs = 93;
2619 num_vs_gprs = 46;
2620 num_temp_gprs = 4;
2621 num_gs_gprs = 31;
2622 num_es_gprs = 31;
2623 num_hs_gprs = 23;
2624 num_ls_gprs = 23;
2625 break;
2626 case CHIP_TURKS:
2627 num_ps_gprs = 93;
2628 num_vs_gprs = 46;
2629 num_temp_gprs = 4;
2630 num_gs_gprs = 31;
2631 num_es_gprs = 31;
2632 num_hs_gprs = 23;
2633 num_ls_gprs = 23;
2634 break;
2635 case CHIP_CAICOS:
2636 num_ps_gprs = 93;
2637 num_vs_gprs = 46;
2638 num_temp_gprs = 4;
2639 num_gs_gprs = 31;
2640 num_es_gprs = 31;
2641 num_hs_gprs = 23;
2642 num_ls_gprs = 23;
2643 break;
2644 }
2645
2646 tmp = 0;
2647 switch (ctx_family) {
2648 case CHIP_CEDAR:
2649 case CHIP_PALM:
2650 case CHIP_SUMO:
2651 case CHIP_SUMO2:
2652 case CHIP_CAICOS:
2653 break;
2654 default:
2655 tmp |= S_008C00_VC_ENABLE(1);
2656 break;
2657 }
2658 tmp |= S_008C00_EXPORT_SRC_C(1);
2659 tmp |= S_008C00_CS_PRIO(cs_prio);
2660 tmp |= S_008C00_LS_PRIO(ls_prio);
2661 tmp |= S_008C00_HS_PRIO(hs_prio);
2662 tmp |= S_008C00_PS_PRIO(ps_prio);
2663 tmp |= S_008C00_VS_PRIO(vs_prio);
2664 tmp |= S_008C00_GS_PRIO(gs_prio);
2665 tmp |= S_008C00_ES_PRIO(es_prio);
2666
2667 /* enable dynamic GPR resource management */
2668 if (ctx_drm_minor >= 7) {
2669 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2670 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2671 /* always set temp clauses */
2672 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2673 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2674 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2675 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2676 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2677 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2678 S_028838_PS_GPRS(0x1e) |
2679 S_028838_VS_GPRS(0x1e) |
2680 S_028838_GS_GPRS(0x1e) |
2681 S_028838_ES_GPRS(0x1e) |
2682 S_028838_HS_GPRS(0x1e) |
2683 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2684 } else {
2685 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2686 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2687
2688 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2689 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2690 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2691 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2692
2693 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2694 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2695 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2696
2697 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2698 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2699 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2700 }
2701
2702 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2703 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2704
2705 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2706
2707 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2708 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2709 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2710
2711 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2712
2713 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2714 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2715 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2716
2717 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2718 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2719 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2720 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2721
2722 /* The cs checker requires this register to be set. */
2723 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2724
2725 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2726 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2727
2728 /* to avoid GPU doing any preloading of constant from random address */
2729 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2730 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2731 r600_store_value(cb, 0);
2732 r600_store_value(cb, 0);
2733 r600_store_value(cb, 0);
2734 r600_store_value(cb, 0);
2735 r600_store_value(cb, 0);
2736 r600_store_value(cb, 0);
2737 r600_store_value(cb, 0);
2738 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2739 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2740 r600_store_value(cb, 0);
2741 r600_store_value(cb, 0);
2742 r600_store_value(cb, 0);
2743 r600_store_value(cb, 0);
2744 r600_store_value(cb, 0);
2745 r600_store_value(cb, 0);
2746 r600_store_value(cb, 0);
2747
2748 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2749
2750 return;
2751 }
2752
2753 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2754 {
2755 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2756 int num_ps_threads;
2757 int num_vs_threads;
2758 int num_gs_threads;
2759 int num_es_threads;
2760 int num_hs_threads;
2761 int num_ls_threads;
2762
2763 int num_ps_stack_entries;
2764 int num_vs_stack_entries;
2765 int num_gs_stack_entries;
2766 int num_es_stack_entries;
2767 int num_hs_stack_entries;
2768 int num_ls_stack_entries;
2769 enum radeon_family family;
2770 unsigned tmp;
2771
2772 if (rctx->chip_class == CAYMAN) {
2773 cayman_init_atom_start_cs(rctx);
2774 return;
2775 }
2776
2777 r600_init_command_buffer(cb, 256);
2778
2779 /* This must be first. */
2780 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2781 r600_store_value(cb, 0x80000000);
2782 r600_store_value(cb, 0x80000000);
2783
2784 evergreen_init_common_regs(cb, rctx->chip_class
2785 , rctx->family, rctx->screen->info.drm_minor);
2786
2787 family = rctx->family;
2788 switch (family) {
2789 case CHIP_CEDAR:
2790 default:
2791 num_ps_threads = 96;
2792 num_vs_threads = 16;
2793 num_gs_threads = 16;
2794 num_es_threads = 16;
2795 num_hs_threads = 16;
2796 num_ls_threads = 16;
2797 num_ps_stack_entries = 42;
2798 num_vs_stack_entries = 42;
2799 num_gs_stack_entries = 42;
2800 num_es_stack_entries = 42;
2801 num_hs_stack_entries = 42;
2802 num_ls_stack_entries = 42;
2803 break;
2804 case CHIP_REDWOOD:
2805 num_ps_threads = 128;
2806 num_vs_threads = 20;
2807 num_gs_threads = 20;
2808 num_es_threads = 20;
2809 num_hs_threads = 20;
2810 num_ls_threads = 20;
2811 num_ps_stack_entries = 42;
2812 num_vs_stack_entries = 42;
2813 num_gs_stack_entries = 42;
2814 num_es_stack_entries = 42;
2815 num_hs_stack_entries = 42;
2816 num_ls_stack_entries = 42;
2817 break;
2818 case CHIP_JUNIPER:
2819 num_ps_threads = 128;
2820 num_vs_threads = 20;
2821 num_gs_threads = 20;
2822 num_es_threads = 20;
2823 num_hs_threads = 20;
2824 num_ls_threads = 20;
2825 num_ps_stack_entries = 85;
2826 num_vs_stack_entries = 85;
2827 num_gs_stack_entries = 85;
2828 num_es_stack_entries = 85;
2829 num_hs_stack_entries = 85;
2830 num_ls_stack_entries = 85;
2831 break;
2832 case CHIP_CYPRESS:
2833 case CHIP_HEMLOCK:
2834 num_ps_threads = 128;
2835 num_vs_threads = 20;
2836 num_gs_threads = 20;
2837 num_es_threads = 20;
2838 num_hs_threads = 20;
2839 num_ls_threads = 20;
2840 num_ps_stack_entries = 85;
2841 num_vs_stack_entries = 85;
2842 num_gs_stack_entries = 85;
2843 num_es_stack_entries = 85;
2844 num_hs_stack_entries = 85;
2845 num_ls_stack_entries = 85;
2846 break;
2847 case CHIP_PALM:
2848 num_ps_threads = 96;
2849 num_vs_threads = 16;
2850 num_gs_threads = 16;
2851 num_es_threads = 16;
2852 num_hs_threads = 16;
2853 num_ls_threads = 16;
2854 num_ps_stack_entries = 42;
2855 num_vs_stack_entries = 42;
2856 num_gs_stack_entries = 42;
2857 num_es_stack_entries = 42;
2858 num_hs_stack_entries = 42;
2859 num_ls_stack_entries = 42;
2860 break;
2861 case CHIP_SUMO:
2862 num_ps_threads = 96;
2863 num_vs_threads = 25;
2864 num_gs_threads = 25;
2865 num_es_threads = 25;
2866 num_hs_threads = 25;
2867 num_ls_threads = 25;
2868 num_ps_stack_entries = 42;
2869 num_vs_stack_entries = 42;
2870 num_gs_stack_entries = 42;
2871 num_es_stack_entries = 42;
2872 num_hs_stack_entries = 42;
2873 num_ls_stack_entries = 42;
2874 break;
2875 case CHIP_SUMO2:
2876 num_ps_threads = 96;
2877 num_vs_threads = 25;
2878 num_gs_threads = 25;
2879 num_es_threads = 25;
2880 num_hs_threads = 25;
2881 num_ls_threads = 25;
2882 num_ps_stack_entries = 85;
2883 num_vs_stack_entries = 85;
2884 num_gs_stack_entries = 85;
2885 num_es_stack_entries = 85;
2886 num_hs_stack_entries = 85;
2887 num_ls_stack_entries = 85;
2888 break;
2889 case CHIP_BARTS:
2890 num_ps_threads = 128;
2891 num_vs_threads = 20;
2892 num_gs_threads = 20;
2893 num_es_threads = 20;
2894 num_hs_threads = 20;
2895 num_ls_threads = 20;
2896 num_ps_stack_entries = 85;
2897 num_vs_stack_entries = 85;
2898 num_gs_stack_entries = 85;
2899 num_es_stack_entries = 85;
2900 num_hs_stack_entries = 85;
2901 num_ls_stack_entries = 85;
2902 break;
2903 case CHIP_TURKS:
2904 num_ps_threads = 128;
2905 num_vs_threads = 20;
2906 num_gs_threads = 20;
2907 num_es_threads = 20;
2908 num_hs_threads = 20;
2909 num_ls_threads = 20;
2910 num_ps_stack_entries = 42;
2911 num_vs_stack_entries = 42;
2912 num_gs_stack_entries = 42;
2913 num_es_stack_entries = 42;
2914 num_hs_stack_entries = 42;
2915 num_ls_stack_entries = 42;
2916 break;
2917 case CHIP_CAICOS:
2918 num_ps_threads = 128;
2919 num_vs_threads = 10;
2920 num_gs_threads = 10;
2921 num_es_threads = 10;
2922 num_hs_threads = 10;
2923 num_ls_threads = 10;
2924 num_ps_stack_entries = 42;
2925 num_vs_stack_entries = 42;
2926 num_gs_stack_entries = 42;
2927 num_es_stack_entries = 42;
2928 num_hs_stack_entries = 42;
2929 num_ls_stack_entries = 42;
2930 break;
2931 }
2932
2933 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2934 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2935 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2936 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2937
2938 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2939 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2940
2941 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2942 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2943 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2944
2945 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2946 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2947 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2948
2949 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2950 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2951 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2952
2953 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2954 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2955 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2956
2957 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2958 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2959
2960 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2961 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2962 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2963 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2964 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2965 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2966 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2967
2968 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2969 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2970 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2971 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2972 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2973
2974 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2975 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2976 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2977 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2978 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2979 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2980 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2981 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2982 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2983 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2984 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2985 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2986 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2987 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2988
2989 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2990 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2991 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2992
2993 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2994
2995 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2996 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2997 r600_store_value(cb, 0);
2998 r600_store_value(cb, 0);
2999 r600_store_value(cb, 0);
3000 r600_store_value(cb, 0);
3001 r600_store_value(cb, 0);
3002 r600_store_value(cb, 0);
3003 r600_store_value(cb, 0);
3004 r600_store_value(cb, 0);
3005 r600_store_value(cb, 0);
3006 r600_store_value(cb, 0);
3007 r600_store_value(cb, 0);
3008 r600_store_value(cb, 0);
3009 r600_store_value(cb, 0);
3010 r600_store_value(cb, 0);
3011 r600_store_value(cb, 0);
3012 r600_store_value(cb, 0);
3013 r600_store_value(cb, 0);
3014 r600_store_value(cb, 0);
3015 r600_store_value(cb, 0);
3016 r600_store_value(cb, 0);
3017 r600_store_value(cb, 0);
3018 r600_store_value(cb, 0);
3019 r600_store_value(cb, 0);
3020 r600_store_value(cb, 0);
3021 r600_store_value(cb, 0);
3022 r600_store_value(cb, 0);
3023 r600_store_value(cb, 0);
3024 r600_store_value(cb, 0);
3025 r600_store_value(cb, 0);
3026 r600_store_value(cb, 0);
3027 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
3028 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3029 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3030
3031 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3032
3033 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
3034 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
3035 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
3036
3037 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3038 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3039
3040 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3041 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3042 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3043
3044 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3045 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3046 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3047 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3048
3049 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
3050 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3051 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3052 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3053 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3054
3055 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3056 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3057 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3058
3059 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3060 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3061 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3062
3063 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3064
3065 if (rctx->screen->has_streamout) {
3066 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3067 }
3068
3069 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3070 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3071 }
3072
3073 void evergreen_polygon_offset_update(struct r600_context *rctx)
3074 {
3075 struct r600_pipe_state state;
3076
3077 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
3078 state.nregs = 0;
3079 if (rctx->rasterizer && rctx->framebuffer.state.zsbuf) {
3080 float offset_units = rctx->rasterizer->offset_units;
3081 unsigned offset_db_fmt_cntl = 0, depth;
3082
3083 switch (rctx->framebuffer.state.zsbuf->format) {
3084 case PIPE_FORMAT_Z24X8_UNORM:
3085 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
3086 depth = -24;
3087 offset_units *= 2.0f;
3088 break;
3089 case PIPE_FORMAT_Z32_FLOAT:
3090 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3091 depth = -23;
3092 offset_units *= 1.0f;
3093 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3094 break;
3095 case PIPE_FORMAT_Z16_UNORM:
3096 depth = -16;
3097 offset_units *= 4.0f;
3098 break;
3099 default:
3100 return;
3101 }
3102 /* XXX some of those reg can be computed with cso */
3103 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
3104 r600_pipe_state_add_reg(&state,
3105 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
3106 fui(rctx->rasterizer->offset_scale));
3107 r600_pipe_state_add_reg(&state,
3108 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
3109 fui(offset_units));
3110 r600_pipe_state_add_reg(&state,
3111 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
3112 fui(rctx->rasterizer->offset_scale));
3113 r600_pipe_state_add_reg(&state,
3114 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
3115 fui(offset_units));
3116 r600_pipe_state_add_reg(&state,
3117 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
3118 offset_db_fmt_cntl);
3119 r600_context_pipe_state_set(rctx, &state);
3120 }
3121 }
3122
3123 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3124 {
3125 struct r600_context *rctx = (struct r600_context *)ctx;
3126 struct r600_pipe_state *rstate = &shader->rstate;
3127 struct r600_shader *rshader = &shader->shader;
3128 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
3129 int pos_index = -1, face_index = -1;
3130 int ninterp = 0;
3131 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
3132 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
3133 unsigned z_export = 0, stencil_export = 0;
3134
3135 rstate->nregs = 0;
3136
3137 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3138 for (i = 0; i < rshader->ninput; i++) {
3139 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3140 POSITION goes via GPRs from the SC so isn't counted */
3141 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
3142 pos_index = i;
3143 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
3144 face_index = i;
3145 else {
3146 ninterp++;
3147 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
3148 have_linear = TRUE;
3149 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
3150 have_perspective = TRUE;
3151 if (rshader->input[i].centroid)
3152 have_centroid = TRUE;
3153 }
3154
3155 sid = rshader->input[i].spi_sid;
3156
3157 if (sid) {
3158
3159 tmp = S_028644_SEMANTIC(sid);
3160
3161 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3162 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3163 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3164 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3165 tmp |= S_028644_FLAT_SHADE(1);
3166 }
3167
3168 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3169 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
3170 tmp |= S_028644_PT_SPRITE_TEX(1);
3171 }
3172
3173 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3174 tmp);
3175
3176 idx++;
3177 }
3178 }
3179
3180 for (i = 0; i < rshader->noutput; i++) {
3181 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3182 z_export = 1;
3183 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3184 stencil_export = 1;
3185 }
3186 if (rshader->uses_kill)
3187 db_shader_control |= S_02880C_KILL_ENABLE(1);
3188
3189 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3190 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3191
3192 exports_ps = 0;
3193 for (i = 0; i < rshader->noutput; i++) {
3194 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3195 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3196 exports_ps |= 1;
3197 }
3198
3199 num_cout = rshader->nr_ps_color_exports;
3200
3201 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3202 if (!exports_ps) {
3203 /* always at least export 1 component per pixel */
3204 exports_ps = 2;
3205 }
3206 shader->nr_ps_color_outputs = num_cout;
3207 if (ninterp == 0) {
3208 ninterp = 1;
3209 have_perspective = TRUE;
3210 }
3211
3212 if (!have_perspective && !have_linear)
3213 have_perspective = TRUE;
3214
3215 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3216 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3217 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3218 spi_input_z = 0;
3219 if (pos_index != -1) {
3220 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3221 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3222 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3223 spi_input_z |= 1;
3224 }
3225
3226 spi_ps_in_control_1 = 0;
3227 if (face_index != -1) {
3228 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3229 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3230 }
3231
3232 spi_baryc_cntl = 0;
3233 if (have_perspective)
3234 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3235 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3236 if (have_linear)
3237 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3238 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3239
3240 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3241 spi_ps_in_control_0);
3242 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3243 spi_ps_in_control_1);
3244 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3245 0);
3246 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3247 r600_pipe_state_add_reg(rstate,
3248 R_0286E0_SPI_BARYC_CNTL,
3249 spi_baryc_cntl);
3250
3251 r600_pipe_state_add_reg_bo(rstate,
3252 R_028840_SQ_PGM_START_PS,
3253 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3254 shader->bo, RADEON_USAGE_READ);
3255 r600_pipe_state_add_reg(rstate,
3256 R_028844_SQ_PGM_RESOURCES_PS,
3257 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3258 S_028844_PRIME_CACHE_ON_DRAW(1) |
3259 S_028844_STACK_SIZE(rshader->bc.nstack));
3260 r600_pipe_state_add_reg(rstate,
3261 R_02884C_SQ_PGM_EXPORTS_PS,
3262 exports_ps);
3263
3264 shader->db_shader_control = db_shader_control;
3265 shader->ps_depth_export = z_export | stencil_export;
3266
3267 shader->sprite_coord_enable = rctx->sprite_coord_enable;
3268 if (rctx->rasterizer)
3269 shader->flatshade = rctx->rasterizer->flatshade;
3270 }
3271
3272 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3273 {
3274 struct r600_context *rctx = (struct r600_context *)ctx;
3275 struct r600_pipe_state *rstate = &shader->rstate;
3276 struct r600_shader *rshader = &shader->shader;
3277 unsigned spi_vs_out_id[10] = {};
3278 unsigned i, tmp, nparams = 0;
3279
3280 /* clear previous register */
3281 rstate->nregs = 0;
3282
3283 for (i = 0; i < rshader->noutput; i++) {
3284 if (rshader->output[i].spi_sid) {
3285 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3286 spi_vs_out_id[nparams / 4] |= tmp;
3287 nparams++;
3288 }
3289 }
3290
3291 for (i = 0; i < 10; i++) {
3292 r600_pipe_state_add_reg(rstate,
3293 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3294 spi_vs_out_id[i]);
3295 }
3296
3297 /* Certain attributes (position, psize, etc.) don't count as params.
3298 * VS is required to export at least one param and r600_shader_from_tgsi()
3299 * takes care of adding a dummy export.
3300 */
3301 if (nparams < 1)
3302 nparams = 1;
3303
3304 r600_pipe_state_add_reg(rstate,
3305 R_0286C4_SPI_VS_OUT_CONFIG,
3306 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3307 r600_pipe_state_add_reg(rstate,
3308 R_028860_SQ_PGM_RESOURCES_VS,
3309 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3310 S_028860_STACK_SIZE(rshader->bc.nstack));
3311 r600_pipe_state_add_reg_bo(rstate,
3312 R_02885C_SQ_PGM_START_VS,
3313 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3314 shader->bo, RADEON_USAGE_READ);
3315
3316 shader->pa_cl_vs_out_cntl =
3317 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3318 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3319 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3320 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3321 }
3322
3323 void evergreen_fetch_shader(struct pipe_context *ctx,
3324 struct r600_vertex_element *ve)
3325 {
3326 struct r600_context *rctx = (struct r600_context *)ctx;
3327 struct r600_pipe_state *rstate = &ve->rstate;
3328 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
3329 rstate->nregs = 0;
3330 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
3331 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
3332 ve->fetch_shader, RADEON_USAGE_READ);
3333 }
3334
3335 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3336 {
3337 struct pipe_blend_state blend;
3338 struct r600_pipe_state *rstate;
3339
3340 memset(&blend, 0, sizeof(blend));
3341 blend.independent_blend_enable = true;
3342 blend.rt[0].colormask = 0xf;
3343 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3344 return rstate;
3345 }
3346
3347 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3348 {
3349 struct pipe_blend_state blend;
3350 struct r600_pipe_state *rstate;
3351
3352 memset(&blend, 0, sizeof(blend));
3353 blend.independent_blend_enable = true;
3354 blend.rt[0].colormask = 0xf;
3355 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3356 return rstate;
3357 }
3358
3359 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3360 {
3361 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3362
3363 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3364 }
3365
3366 void evergreen_update_dual_export_state(struct r600_context * rctx)
3367 {
3368 bool dual_export = rctx->framebuffer.export_16bpc &&
3369 !rctx->ps_shader->current->ps_depth_export;
3370
3371 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3372 V_02880C_EXPORT_DB_FULL;
3373
3374 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3375 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3376 S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3377 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3378
3379 if (db_shader_control != rctx->db_shader_control) {
3380 struct r600_pipe_state rstate;
3381
3382 rctx->db_shader_control = db_shader_control;
3383
3384 rstate.nregs = 0;
3385 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3386 r600_context_pipe_state_set(rctx, &rstate);
3387 }
3388 }