2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
51 static void evergreen_set_blend_color(struct pipe_context
*ctx
,
52 const struct pipe_blend_color
*state
)
54 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
55 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
60 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
61 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
);
62 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
);
63 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
);
64 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
);
66 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
67 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
68 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
71 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
72 const struct pipe_blend_state
*state
)
74 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
75 struct r600_pipe_state
*rstate
;
76 u32 color_control
, target_mask
;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl
[8];
83 rstate
= &blend
->rstate
;
85 rstate
->id
= R600_PIPE_STATE_BLEND
;
88 color_control
= S_028808_MODE(1);
89 if (state
->logicop_enable
) {
90 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
92 color_control
|= (0xcc << 16);
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state
->independent_blend_enable
) {
96 for (int i
= 0; i
< 8; i
++) {
97 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
100 for (int i
= 0; i
< 8; i
++) {
101 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
104 blend
->cb_target_mask
= target_mask
;
105 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
106 color_control
, 0xFFFFFFFD, NULL
);
107 r600_pipe_state_add_reg(rstate
, R_028C3C_PA_SC_AA_MASK
, 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
109 for (int i
= 0; i
< 8; i
++) {
110 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
111 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
112 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
113 unsigned eqA
= state
->rt
[i
].alpha_func
;
114 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
115 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
118 if (!state
->rt
[i
].blend_enable
)
121 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
123 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
124 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
126 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
127 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
129 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
130 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
133 for (int i
= 0; i
< 8; i
++) {
134 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
], 0xFFFFFFFF, NULL
);
140 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
141 const struct pipe_depth_stencil_alpha_state
*state
)
143 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
144 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
145 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
147 if (rstate
== NULL
) {
151 rstate
->id
= R600_PIPE_STATE_DSA
;
152 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
153 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
154 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
155 * be set if shader use texkill instruction
157 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
158 stencil_ref_mask
= 0;
159 stencil_ref_mask_bf
= 0;
160 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
161 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
162 S_028800_ZFUNC(state
->depth
.func
);
165 if (state
->stencil
[0].enabled
) {
166 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
167 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
168 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
169 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
170 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
173 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
174 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
175 if (state
->stencil
[1].enabled
) {
176 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
177 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
178 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
179 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
180 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
181 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
182 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
187 alpha_test_control
= 0;
189 if (state
->alpha
.enabled
) {
190 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
191 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
192 alpha_ref
= fui(state
->alpha
.ref_value
);
196 db_render_control
= 0;
197 db_render_override
= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
198 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
199 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
200 /* TODO db_render_override depends on query */
201 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
);
202 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
);
203 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
);
204 r600_pipe_state_add_reg(rstate
,
205 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
206 0xFFFFFFFF & C_028430_STENCILREF
, NULL
);
207 r600_pipe_state_add_reg(rstate
,
208 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
209 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
);
210 r600_pipe_state_add_reg(rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
, 0xFFFFFFFF, NULL
);
211 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
212 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
);
213 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBE, NULL
);
214 r600_pipe_state_add_reg(rstate
, R_028000_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
);
215 r600_pipe_state_add_reg(rstate
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
);
216 r600_pipe_state_add_reg(rstate
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0, 0xFFFFFFFF, NULL
);
217 r600_pipe_state_add_reg(rstate
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0, 0xFFFFFFFF, NULL
);
218 r600_pipe_state_add_reg(rstate
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0, 0xFFFFFFFF, NULL
);
219 r600_pipe_state_add_reg(rstate
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
);
224 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
225 const struct pipe_rasterizer_state
*state
)
227 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
228 struct r600_pipe_state
*rstate
;
230 unsigned prov_vtx
= 1, polygon_dual_mode
;
237 rstate
= &rs
->rstate
;
238 rs
->flatshade
= state
->flatshade
;
239 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
241 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
244 rs
->offset_units
= state
->offset_units
;
245 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
247 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
248 if (state
->flatshade_first
)
250 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
251 if (state
->sprite_coord_enable
) {
252 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
253 S_0286D4_PNT_SPRITE_OVRD_X(2) |
254 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
255 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
256 S_0286D4_PNT_SPRITE_OVRD_W(1);
257 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
258 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
261 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
);
263 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
264 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
265 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
266 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
267 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
268 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
269 S_028814_FACE(!state
->front_ccw
) |
270 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
271 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
272 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
273 S_028814_POLY_MODE(polygon_dual_mode
) |
274 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
275 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
);
276 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
277 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
278 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
);
279 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
280 /* point size 12.4 fixed point */
281 tmp
= (unsigned)(state
->point_size
* 8.0);
282 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
283 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
);
285 tmp
= (unsigned)state
->line_width
* 8;
286 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
288 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
289 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
290 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
291 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
292 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
293 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 0x0, 0xFFFFFFFF, NULL
);
295 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
296 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
299 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
);
303 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
304 const struct pipe_sampler_state
*state
)
306 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
309 if (rstate
== NULL
) {
313 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
314 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
315 r600_pipe_state_add_reg(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
316 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
317 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
318 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
319 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
320 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
321 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
322 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
323 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
);
324 /* FIXME LOD it depends on texture base level ... */
325 r600_pipe_state_add_reg(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
326 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
327 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)),
329 r600_pipe_state_add_reg(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
,
330 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
335 r600_pipe_state_add_reg(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
);
336 r600_pipe_state_add_reg(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
);
337 r600_pipe_state_add_reg(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
);
338 r600_pipe_state_add_reg(rstate
, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
);
343 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
344 struct pipe_resource
*texture
,
345 const struct pipe_sampler_view
*state
)
347 struct r600_pipe_sampler_view
*resource
= CALLOC_STRUCT(r600_pipe_sampler_view
);
348 struct r600_pipe_state
*rstate
;
349 const struct util_format_description
*desc
;
350 struct r600_resource_texture
*tmp
;
351 struct r600_resource
*rbuffer
;
353 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
354 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
355 struct r600_bo
*bo
[2];
357 if (resource
== NULL
)
359 rstate
= &resource
->state
;
361 /* initialize base object */
362 resource
->base
= *state
;
363 resource
->base
.texture
= NULL
;
364 pipe_reference(NULL
, &texture
->reference
);
365 resource
->base
.texture
= texture
;
366 resource
->base
.reference
.count
= 1;
367 resource
->base
.context
= ctx
;
369 swizzle
[0] = state
->swizzle_r
;
370 swizzle
[1] = state
->swizzle_g
;
371 swizzle
[2] = state
->swizzle_b
;
372 swizzle
[3] = state
->swizzle_a
;
373 format
= r600_translate_texformat(state
->format
,
375 &word4
, &yuv_format
);
379 desc
= util_format_description(state
->format
);
381 R600_ERR("unknow format %d\n", state
->format
);
383 tmp
= (struct r600_resource_texture
*)texture
;
384 if (tmp
->depth
&& !tmp
->is_flushing_texture
) {
385 r600_texture_depth_flush(ctx
, texture
, TRUE
);
386 tmp
= tmp
->flushed_depth_texture
;
388 rbuffer
= &tmp
->resource
;
392 pitch
= align(tmp
->pitch_in_pixels
[0], 8);
393 array_mode
= tmp
->array_mode
[0];
394 tile_type
= tmp
->tile_type
;
396 /* FIXME properly handle first level != 0 */
397 r600_pipe_state_add_reg(rstate
, R_030000_RESOURCE0_WORD0
,
398 S_030000_DIM(r600_tex_dim(texture
->target
)) |
399 S_030000_PITCH((pitch
/ 8) - 1) |
400 S_030000_NON_DISP_TILING_ORDER(tile_type
) |
401 S_030000_TEX_WIDTH(texture
->width0
- 1), 0xFFFFFFFF, NULL
);
402 r600_pipe_state_add_reg(rstate
, R_030004_RESOURCE0_WORD1
,
403 S_030004_TEX_HEIGHT(texture
->height0
- 1) |
404 S_030004_TEX_DEPTH(texture
->depth0
- 1) |
405 S_030004_ARRAY_MODE(array_mode
),
407 r600_pipe_state_add_reg(rstate
, R_030008_RESOURCE0_WORD2
,
408 (tmp
->offset
[0] + r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
409 r600_pipe_state_add_reg(rstate
, R_03000C_RESOURCE0_WORD3
,
410 (tmp
->offset
[1] + r600_bo_offset(bo
[1])) >> 8, 0xFFFFFFFF, bo
[1]);
411 r600_pipe_state_add_reg(rstate
, R_030010_RESOURCE0_WORD4
,
413 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO
) |
414 S_030010_BASE_LEVEL(state
->u
.tex
.first_level
), 0xFFFFFFFF, NULL
);
415 r600_pipe_state_add_reg(rstate
, R_030014_RESOURCE0_WORD5
,
416 S_030014_LAST_LEVEL(state
->u
.tex
.last_level
) |
417 S_030014_BASE_ARRAY(0) |
418 S_030014_LAST_ARRAY(0), 0xffffffff, NULL
);
419 r600_pipe_state_add_reg(rstate
, R_030018_RESOURCE0_WORD6
, 0x0, 0xFFFFFFFF, NULL
);
420 r600_pipe_state_add_reg(rstate
, R_03001C_RESOURCE0_WORD7
,
421 S_03001C_DATA_FORMAT(format
) |
422 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
), 0xFFFFFFFF, NULL
);
424 return &resource
->base
;
427 static void evergreen_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
428 struct pipe_sampler_view
**views
)
430 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
431 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
433 for (int i
= 0; i
< count
; i
++) {
435 evergreen_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
,
436 i
+ R600_MAX_CONST_BUFFERS
);
441 static void evergreen_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
442 struct pipe_sampler_view
**views
)
444 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
445 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
448 for (i
= 0; i
< count
; i
++) {
449 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
451 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
,
452 i
+ R600_MAX_CONST_BUFFERS
);
454 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
455 i
+ R600_MAX_CONST_BUFFERS
);
457 pipe_sampler_view_reference(
458 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
462 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
463 if (rctx
->ps_samplers
.views
[i
]) {
464 evergreen_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
465 i
+ R600_MAX_CONST_BUFFERS
);
466 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
469 rctx
->ps_samplers
.n_views
= count
;
472 static void evergreen_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
474 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
475 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
478 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
479 rctx
->ps_samplers
.n_samplers
= count
;
481 for (int i
= 0; i
< count
; i
++) {
482 evergreen_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
486 static void evergreen_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
488 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
489 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
491 for (int i
= 0; i
< count
; i
++) {
492 evergreen_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
496 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
497 const struct pipe_clip_state
*state
)
499 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
500 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
506 rstate
->id
= R600_PIPE_STATE_CLIP
;
507 for (int i
= 0; i
< state
->nr
; i
++) {
508 r600_pipe_state_add_reg(rstate
,
509 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
510 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
);
511 r600_pipe_state_add_reg(rstate
,
512 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
513 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
);
514 r600_pipe_state_add_reg(rstate
,
515 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
516 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
);
517 r600_pipe_state_add_reg(rstate
,
518 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
519 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
);
521 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
522 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
523 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
524 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
);
526 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
527 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
528 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
531 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
532 const struct pipe_poly_stipple
*state
)
536 static void evergreen_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
540 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
541 const struct pipe_scissor_state
*state
)
543 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
544 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
550 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
551 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
552 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
553 r600_pipe_state_add_reg(rstate
,
554 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
556 r600_pipe_state_add_reg(rstate
,
557 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
559 r600_pipe_state_add_reg(rstate
,
560 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
562 r600_pipe_state_add_reg(rstate
,
563 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
565 r600_pipe_state_add_reg(rstate
,
566 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
568 r600_pipe_state_add_reg(rstate
,
569 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
571 r600_pipe_state_add_reg(rstate
,
572 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
574 r600_pipe_state_add_reg(rstate
,
575 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
578 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
579 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
580 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
583 static void evergreen_set_stencil_ref(struct pipe_context
*ctx
,
584 const struct pipe_stencil_ref
*state
)
586 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
587 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
593 rctx
->stencil_ref
= *state
;
594 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
595 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
596 r600_pipe_state_add_reg(rstate
,
597 R_028430_DB_STENCILREFMASK
, tmp
,
598 ~C_028430_STENCILREF
, NULL
);
599 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
600 r600_pipe_state_add_reg(rstate
,
601 R_028434_DB_STENCILREFMASK_BF
, tmp
,
602 ~C_028434_STENCILREF_BF
, NULL
);
604 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
605 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
606 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
609 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
610 const struct pipe_viewport_state
*state
)
612 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
613 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
618 rctx
->viewport
= *state
;
619 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
620 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
);
621 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
);
622 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
);
623 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
);
624 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
);
625 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
);
626 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
);
627 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
);
628 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
);
630 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
631 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
632 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
635 static void evergreen_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
636 const struct pipe_framebuffer_state
*state
, int cb
)
638 struct r600_resource_texture
*rtex
;
639 struct r600_resource
*rbuffer
;
640 struct r600_surface
*surf
;
641 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
642 unsigned pitch
, slice
;
644 unsigned format
, swap
, ntype
;
647 const struct util_format_description
*desc
;
648 struct r600_bo
*bo
[3];
651 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
652 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
654 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
655 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
656 rtex
= rtex
->flushed_depth_texture
;
659 rbuffer
= &rtex
->resource
;
664 /* XXX quite sure for dx10+ hw don't need any offset hacks */
665 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
,
666 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
667 pitch
= rtex
->pitch_in_pixels
[level
] / 8 - 1;
668 slice
= rtex
->pitch_in_pixels
[level
] * surf
->aligned_height
/ 64 - 1;
670 desc
= util_format_description(surf
->base
.format
);
671 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
672 ntype
= V_028C70_NUMBER_SRGB
;
674 format
= r600_translate_colorformat(surf
->base
.format
);
675 swap
= r600_translate_colorswap(surf
->base
.format
);
676 color_info
= S_028C70_FORMAT(format
) |
677 S_028C70_COMP_SWAP(swap
) |
678 S_028C70_ARRAY_MODE(rtex
->array_mode
[level
]) |
679 S_028C70_BLEND_CLAMP(1) |
680 S_028C70_NUMBER_TYPE(ntype
);
682 for (i
= 0; i
< 4; i
++) {
683 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
688 /* we can only set the export size if any thing is snorm/unorm component is > 11 bits,
689 if we aren't a float, sint or uint */
690 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
691 desc
->channel
[i
].size
< 12 && desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
692 ntype
!= 4 && ntype
!= 5)
693 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
695 if (rtex
->array_mode
[level
] > V_028C70_ARRAY_LINEAR_ALIGNED
) {
696 tile_type
= rtex
->tile_type
;
697 } else /* workaround for linear buffers */
700 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
701 r600_pipe_state_add_reg(rstate
,
702 R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C,
703 (offset
+ r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
704 r600_pipe_state_add_reg(rstate
,
705 R_028C78_CB_COLOR0_DIM
+ cb
* 0x3C,
706 0x0, 0xFFFFFFFF, NULL
);
707 r600_pipe_state_add_reg(rstate
,
708 R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C,
709 color_info
, 0xFFFFFFFF, bo
[0]);
710 r600_pipe_state_add_reg(rstate
,
711 R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C,
712 S_028C64_PITCH_TILE_MAX(pitch
),
714 r600_pipe_state_add_reg(rstate
,
715 R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C,
716 S_028C68_SLICE_TILE_MAX(slice
),
718 r600_pipe_state_add_reg(rstate
,
719 R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
720 0x00000000, 0xFFFFFFFF, NULL
);
721 r600_pipe_state_add_reg(rstate
,
722 R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
723 S_028C74_NON_DISP_TILING_ORDER(tile_type
),
727 static void evergreen_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
728 const struct pipe_framebuffer_state
*state
)
730 struct r600_resource_texture
*rtex
;
731 struct r600_resource
*rbuffer
;
732 struct r600_surface
*surf
;
734 unsigned pitch
, slice
, format
, stencil_format
;
737 if (state
->zsbuf
== NULL
)
740 level
= state
->zsbuf
->u
.tex
.level
;
742 surf
= (struct r600_surface
*)state
->zsbuf
;
743 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
745 rbuffer
= &rtex
->resource
;
747 /* XXX quite sure for dx10+ hw don't need any offset hacks */
748 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->zsbuf
->texture
,
749 level
, state
->zsbuf
->u
.tex
.first_layer
);
750 pitch
= rtex
->pitch_in_pixels
[level
] / 8 - 1;
751 slice
= rtex
->pitch_in_pixels
[level
] * surf
->aligned_height
/ 64 - 1;
752 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
753 stencil_format
= r600_translate_stencilformat(state
->zsbuf
->texture
->format
);
755 r600_pipe_state_add_reg(rstate
, R_028048_DB_Z_READ_BASE
,
756 (offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
757 r600_pipe_state_add_reg(rstate
, R_028050_DB_Z_WRITE_BASE
,
758 (offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
760 if (stencil_format
) {
761 uint32_t stencil_offset
;
763 stencil_offset
= ((surf
->aligned_height
* rtex
->pitch_in_bytes
[level
]) + 255) & ~255;
764 r600_pipe_state_add_reg(rstate
, R_02804C_DB_STENCIL_READ_BASE
,
765 (offset
+ stencil_offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
766 r600_pipe_state_add_reg(rstate
, R_028054_DB_STENCIL_WRITE_BASE
,
767 (offset
+ stencil_offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
770 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
);
771 r600_pipe_state_add_reg(rstate
, R_028044_DB_STENCIL_INFO
,
772 S_028044_FORMAT(stencil_format
), 0xFFFFFFFF, rbuffer
->bo
);
774 r600_pipe_state_add_reg(rstate
, R_028040_DB_Z_INFO
,
775 S_028040_ARRAY_MODE(rtex
->array_mode
[level
]) | S_028040_FORMAT(format
),
776 0xFFFFFFFF, rbuffer
->bo
);
777 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
,
778 S_028058_PITCH_TILE_MAX(pitch
),
780 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
,
781 S_02805C_SLICE_TILE_MAX(slice
),
785 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
786 const struct pipe_framebuffer_state
*state
)
788 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
789 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
790 u32 shader_mask
, tl
, br
, target_mask
;
795 /* unreference old buffer and reference new one */
796 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
798 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
801 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
802 evergreen_cb(rctx
, rstate
, state
, i
);
805 evergreen_db(rctx
, rstate
, state
);
808 target_mask
= 0x00000000;
809 target_mask
= 0xFFFFFFFF;
811 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
812 target_mask
^= 0xf << (i
* 4);
813 shader_mask
|= 0xf << (i
* 4);
815 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0);
816 br
= S_028244_BR_X(state
->width
) | S_028244_BR_Y(state
->height
);
818 r600_pipe_state_add_reg(rstate
,
819 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
821 r600_pipe_state_add_reg(rstate
,
822 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
824 r600_pipe_state_add_reg(rstate
,
825 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
827 r600_pipe_state_add_reg(rstate
,
828 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
830 r600_pipe_state_add_reg(rstate
,
831 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
833 r600_pipe_state_add_reg(rstate
,
834 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
836 r600_pipe_state_add_reg(rstate
,
837 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
839 r600_pipe_state_add_reg(rstate
,
840 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
842 r600_pipe_state_add_reg(rstate
,
843 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
845 r600_pipe_state_add_reg(rstate
,
846 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
849 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
850 0x00000000, target_mask
, NULL
);
851 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
852 shader_mask
, 0xFFFFFFFF, NULL
);
853 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
854 0x00000000, 0xFFFFFFFF, NULL
);
855 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
856 0x00000000, 0xFFFFFFFF, NULL
);
858 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
859 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
860 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
863 evergreen_polygon_offset_update(rctx
);
867 void evergreen_init_state_functions(struct r600_pipe_context
*rctx
)
869 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
870 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
871 rctx
->context
.create_fs_state
= r600_create_shader_state
;
872 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
873 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
874 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
875 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
876 rctx
->context
.create_vs_state
= r600_create_shader_state
;
877 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
878 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
879 rctx
->context
.bind_fragment_sampler_states
= evergreen_bind_ps_sampler
;
880 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
881 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
882 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
883 rctx
->context
.bind_vertex_sampler_states
= evergreen_bind_vs_sampler
;
884 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
885 rctx
->context
.delete_blend_state
= r600_delete_state
;
886 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
887 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
888 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
889 rctx
->context
.delete_sampler_state
= r600_delete_state
;
890 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
891 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
892 rctx
->context
.set_blend_color
= evergreen_set_blend_color
;
893 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
894 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
895 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_view
;
896 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
897 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
898 rctx
->context
.set_sample_mask
= evergreen_set_sample_mask
;
899 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
900 rctx
->context
.set_stencil_ref
= evergreen_set_stencil_ref
;
901 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
902 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
903 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_view
;
904 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
905 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
906 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
909 void evergreen_init_config(struct r600_pipe_context
*rctx
)
911 struct r600_pipe_state
*rstate
= &rctx
->config
;
916 int hs_prio
, cs_prio
, ls_prio
;
930 int num_ps_stack_entries
;
931 int num_vs_stack_entries
;
932 int num_gs_stack_entries
;
933 int num_es_stack_entries
;
934 int num_hs_stack_entries
;
935 int num_ls_stack_entries
;
936 enum radeon_family family
;
939 family
= r600_get_family(rctx
->radeon
);
964 num_ps_stack_entries
= 42;
965 num_vs_stack_entries
= 42;
966 num_gs_stack_entries
= 42;
967 num_es_stack_entries
= 42;
968 num_hs_stack_entries
= 42;
969 num_ls_stack_entries
= 42;
979 num_ps_threads
= 128;
985 num_ps_stack_entries
= 42;
986 num_vs_stack_entries
= 42;
987 num_gs_stack_entries
= 42;
988 num_es_stack_entries
= 42;
989 num_hs_stack_entries
= 42;
990 num_ls_stack_entries
= 42;
1000 num_ps_threads
= 128;
1001 num_vs_threads
= 20;
1002 num_gs_threads
= 20;
1003 num_es_threads
= 20;
1004 num_hs_threads
= 20;
1005 num_ls_threads
= 20;
1006 num_ps_stack_entries
= 85;
1007 num_vs_stack_entries
= 85;
1008 num_gs_stack_entries
= 85;
1009 num_es_stack_entries
= 85;
1010 num_hs_stack_entries
= 85;
1011 num_ls_stack_entries
= 85;
1022 num_ps_threads
= 128;
1023 num_vs_threads
= 20;
1024 num_gs_threads
= 20;
1025 num_es_threads
= 20;
1026 num_hs_threads
= 20;
1027 num_ls_threads
= 20;
1028 num_ps_stack_entries
= 85;
1029 num_vs_stack_entries
= 85;
1030 num_gs_stack_entries
= 85;
1031 num_es_stack_entries
= 85;
1032 num_hs_stack_entries
= 85;
1033 num_ls_stack_entries
= 85;
1043 num_ps_threads
= 96;
1044 num_vs_threads
= 16;
1045 num_gs_threads
= 16;
1046 num_es_threads
= 16;
1047 num_hs_threads
= 16;
1048 num_ls_threads
= 16;
1049 num_ps_stack_entries
= 42;
1050 num_vs_stack_entries
= 42;
1051 num_gs_stack_entries
= 42;
1052 num_es_stack_entries
= 42;
1053 num_hs_stack_entries
= 42;
1054 num_ls_stack_entries
= 42;
1064 num_ps_threads
= 128;
1065 num_vs_threads
= 20;
1066 num_gs_threads
= 20;
1067 num_es_threads
= 20;
1068 num_hs_threads
= 20;
1069 num_ls_threads
= 20;
1070 num_ps_stack_entries
= 85;
1071 num_vs_stack_entries
= 85;
1072 num_gs_stack_entries
= 85;
1073 num_es_stack_entries
= 85;
1074 num_hs_stack_entries
= 85;
1075 num_ls_stack_entries
= 85;
1085 num_ps_threads
= 128;
1086 num_vs_threads
= 20;
1087 num_gs_threads
= 20;
1088 num_es_threads
= 20;
1089 num_hs_threads
= 20;
1090 num_ls_threads
= 20;
1091 num_ps_stack_entries
= 42;
1092 num_vs_stack_entries
= 42;
1093 num_gs_stack_entries
= 42;
1094 num_es_stack_entries
= 42;
1095 num_hs_stack_entries
= 42;
1096 num_ls_stack_entries
= 42;
1106 num_ps_threads
= 128;
1107 num_vs_threads
= 10;
1108 num_gs_threads
= 10;
1109 num_es_threads
= 10;
1110 num_hs_threads
= 10;
1111 num_ls_threads
= 10;
1112 num_ps_stack_entries
= 42;
1113 num_vs_stack_entries
= 42;
1114 num_gs_stack_entries
= 42;
1115 num_es_stack_entries
= 42;
1116 num_hs_stack_entries
= 42;
1117 num_ls_stack_entries
= 42;
1128 tmp
|= S_008C00_VC_ENABLE(1);
1131 tmp
|= S_008C00_EXPORT_SRC_C(1);
1132 tmp
|= S_008C00_CS_PRIO(cs_prio
);
1133 tmp
|= S_008C00_LS_PRIO(ls_prio
);
1134 tmp
|= S_008C00_HS_PRIO(hs_prio
);
1135 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1136 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1137 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1138 tmp
|= S_008C00_ES_PRIO(es_prio
);
1139 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1142 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1143 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1144 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
1145 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1148 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
1149 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
1150 r600_pipe_state_add_reg(rstate
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1153 tmp
|= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
1154 tmp
|= S_008C0C_NUM_LS_GPRS(num_ls_gprs
);
1155 r600_pipe_state_add_reg(rstate
, R_008C0C_SQ_GPR_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
);
1158 tmp
|= S_008C18_NUM_PS_THREADS(num_ps_threads
);
1159 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
1160 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
1161 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
1162 r600_pipe_state_add_reg(rstate
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1165 tmp
|= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
1166 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
1167 r600_pipe_state_add_reg(rstate
, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1170 tmp
|= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
1171 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
1172 r600_pipe_state_add_reg(rstate
, R_008C20_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1175 tmp
|= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
1176 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
1177 r600_pipe_state_add_reg(rstate
, R_008C24_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1180 tmp
|= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
1181 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
1182 r600_pipe_state_add_reg(rstate
, R_008C28_SQ_STACK_RESOURCE_MGMT_3
, tmp
, 0xFFFFFFFF, NULL
);
1184 r600_pipe_state_add_reg(rstate
, R_009100_SPI_CONFIG_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1185 r600_pipe_state_add_reg(rstate
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL
);
1187 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1189 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1190 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
, 0x0, 0xFFFFFFFF, NULL
);
1191 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0, 0xFFFFFFFF, NULL
);
1193 r600_pipe_state_add_reg(rstate
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1194 r600_pipe_state_add_reg(rstate
, R_028904_SQ_GSVS_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1195 r600_pipe_state_add_reg(rstate
, R_028908_SQ_ESTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1196 r600_pipe_state_add_reg(rstate
, R_02890C_SQ_GSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1197 r600_pipe_state_add_reg(rstate
, R_028910_SQ_VSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1198 r600_pipe_state_add_reg(rstate
, R_028914_SQ_PSTMP_RING_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1200 r600_pipe_state_add_reg(rstate
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 0x0, 0xFFFFFFFF, NULL
);
1201 r600_pipe_state_add_reg(rstate
, R_028920_SQ_GS_VERT_ITEMSIZE_1
, 0x0, 0xFFFFFFFF, NULL
);
1202 r600_pipe_state_add_reg(rstate
, R_028924_SQ_GS_VERT_ITEMSIZE_2
, 0x0, 0xFFFFFFFF, NULL
);
1203 r600_pipe_state_add_reg(rstate
, R_028928_SQ_GS_VERT_ITEMSIZE_3
, 0x0, 0xFFFFFFFF, NULL
);
1205 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1206 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1207 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1208 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0, 0xFFFFFFFF, NULL
);
1209 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0, 0xFFFFFFFF, NULL
);
1210 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0, 0xFFFFFFFF, NULL
);
1211 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1212 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x0, 0xFFFFFFFF, NULL
);
1213 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1214 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1215 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1216 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1217 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x0, 0xFFFFFFFF, NULL
);
1218 r600_pipe_state_add_reg(rstate
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1219 r600_pipe_state_add_reg(rstate
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0, 0xFFFFFFFF, NULL
);
1220 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000000, 0xFFFFFFFF, NULL
);
1221 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x0, 0xFFFFFFFF, NULL
);
1222 r600_pipe_state_add_reg(rstate
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1, 0xFFFFFFFF, NULL
);
1224 r600_pipe_state_add_reg(rstate
, R_028380_SQ_VTX_SEMANTIC_0
, 0x0, 0xFFFFFFFF, NULL
);
1225 r600_pipe_state_add_reg(rstate
, R_028384_SQ_VTX_SEMANTIC_1
, 0x0, 0xFFFFFFFF, NULL
);
1226 r600_pipe_state_add_reg(rstate
, R_028388_SQ_VTX_SEMANTIC_2
, 0x0, 0xFFFFFFFF, NULL
);
1227 r600_pipe_state_add_reg(rstate
, R_02838C_SQ_VTX_SEMANTIC_3
, 0x0, 0xFFFFFFFF, NULL
);
1228 r600_pipe_state_add_reg(rstate
, R_028390_SQ_VTX_SEMANTIC_4
, 0x0, 0xFFFFFFFF, NULL
);
1229 r600_pipe_state_add_reg(rstate
, R_028394_SQ_VTX_SEMANTIC_5
, 0x0, 0xFFFFFFFF, NULL
);
1230 r600_pipe_state_add_reg(rstate
, R_028398_SQ_VTX_SEMANTIC_6
, 0x0, 0xFFFFFFFF, NULL
);
1231 r600_pipe_state_add_reg(rstate
, R_02839C_SQ_VTX_SEMANTIC_7
, 0x0, 0xFFFFFFFF, NULL
);
1232 r600_pipe_state_add_reg(rstate
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0x0, 0xFFFFFFFF, NULL
);
1233 r600_pipe_state_add_reg(rstate
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0x0, 0xFFFFFFFF, NULL
);
1234 r600_pipe_state_add_reg(rstate
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0x0, 0xFFFFFFFF, NULL
);
1235 r600_pipe_state_add_reg(rstate
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0x0, 0xFFFFFFFF, NULL
);
1236 r600_pipe_state_add_reg(rstate
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0x0, 0xFFFFFFFF, NULL
);
1237 r600_pipe_state_add_reg(rstate
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0x0, 0xFFFFFFFF, NULL
);
1238 r600_pipe_state_add_reg(rstate
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0x0, 0xFFFFFFFF, NULL
);
1239 r600_pipe_state_add_reg(rstate
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0x0, 0xFFFFFFFF, NULL
);
1240 r600_pipe_state_add_reg(rstate
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0x0, 0xFFFFFFFF, NULL
);
1241 r600_pipe_state_add_reg(rstate
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0x0, 0xFFFFFFFF, NULL
);
1242 r600_pipe_state_add_reg(rstate
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0x0, 0xFFFFFFFF, NULL
);
1243 r600_pipe_state_add_reg(rstate
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0x0, 0xFFFFFFFF, NULL
);
1244 r600_pipe_state_add_reg(rstate
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0x0, 0xFFFFFFFF, NULL
);
1245 r600_pipe_state_add_reg(rstate
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0x0, 0xFFFFFFFF, NULL
);
1246 r600_pipe_state_add_reg(rstate
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0x0, 0xFFFFFFFF, NULL
);
1247 r600_pipe_state_add_reg(rstate
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0x0, 0xFFFFFFFF, NULL
);
1248 r600_pipe_state_add_reg(rstate
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0x0, 0xFFFFFFFF, NULL
);
1249 r600_pipe_state_add_reg(rstate
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0x0, 0xFFFFFFFF, NULL
);
1250 r600_pipe_state_add_reg(rstate
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0x0, 0xFFFFFFFF, NULL
);
1251 r600_pipe_state_add_reg(rstate
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0x0, 0xFFFFFFFF, NULL
);
1252 r600_pipe_state_add_reg(rstate
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0x0, 0xFFFFFFFF, NULL
);
1253 r600_pipe_state_add_reg(rstate
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0x0, 0xFFFFFFFF, NULL
);
1254 r600_pipe_state_add_reg(rstate
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0x0, 0xFFFFFFFF, NULL
);
1255 r600_pipe_state_add_reg(rstate
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0x0, 0xFFFFFFFF, NULL
);
1257 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
, 0x0, 0xFFFFFFFF, NULL
);
1259 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1262 void evergreen_polygon_offset_update(struct r600_pipe_context
*rctx
)
1264 struct r600_pipe_state state
;
1266 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
1268 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
1269 float offset_units
= rctx
->rasterizer
->offset_units
;
1270 unsigned offset_db_fmt_cntl
= 0, depth
;
1272 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
1273 case PIPE_FORMAT_Z24X8_UNORM
:
1274 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
1276 offset_units
*= 2.0f
;
1278 case PIPE_FORMAT_Z32_FLOAT
:
1280 offset_units
*= 1.0f
;
1281 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1283 case PIPE_FORMAT_Z16_UNORM
:
1285 offset_units
*= 4.0f
;
1290 /* FIXME some of those reg can be computed with cso */
1291 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
1292 r600_pipe_state_add_reg(&state
,
1293 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1294 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
1295 r600_pipe_state_add_reg(&state
,
1296 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1297 fui(offset_units
), 0xFFFFFFFF, NULL
);
1298 r600_pipe_state_add_reg(&state
,
1299 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1300 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
1301 r600_pipe_state_add_reg(&state
,
1302 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1303 fui(offset_units
), 0xFFFFFFFF, NULL
);
1304 r600_pipe_state_add_reg(&state
,
1305 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1306 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
);
1307 r600_context_pipe_state_set(&rctx
->ctx
, &state
);
1311 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1313 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1314 struct r600_shader
*rshader
= &shader
->shader
;
1315 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
;
1316 int pos_index
= -1, face_index
= -1;
1318 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
1319 unsigned spi_baryc_cntl
;
1323 for (i
= 0; i
< rshader
->ninput
; i
++) {
1324 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1325 POSITION goes via GPRs from the SC so isn't counted */
1326 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
1328 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
1331 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
||
1332 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
1334 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
1336 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
1337 have_perspective
= TRUE
;
1338 if (rshader
->input
[i
].centroid
)
1339 have_centroid
= TRUE
;
1342 for (i
= 0; i
< rshader
->noutput
; i
++) {
1343 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
1344 r600_pipe_state_add_reg(rstate
,
1345 R_02880C_DB_SHADER_CONTROL
,
1346 S_02880C_Z_EXPORT_ENABLE(1),
1347 S_02880C_Z_EXPORT_ENABLE(1), NULL
);
1348 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1349 r600_pipe_state_add_reg(rstate
,
1350 R_02880C_DB_SHADER_CONTROL
,
1351 S_02880C_STENCIL_EXPORT_ENABLE(1),
1352 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL
);
1357 for (i
= 0; i
< rshader
->noutput
; i
++) {
1358 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
1359 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1361 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1365 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
1367 /* always at least export 1 component per pixel */
1373 have_perspective
= TRUE
;
1376 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
1377 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
1378 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
1380 if (pos_index
!= -1) {
1381 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
1382 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
1383 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
1387 spi_ps_in_control_1
= 0;
1388 if (face_index
!= -1) {
1389 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
1390 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
1394 if (have_perspective
)
1395 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
1396 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
1398 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
1399 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
1401 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
1402 spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
1403 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
1404 spi_ps_in_control_1
, 0xFFFFFFFF, NULL
);
1405 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
1406 0, 0xFFFFFFFF, NULL
);
1407 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
1408 r600_pipe_state_add_reg(rstate
,
1409 R_0286E0_SPI_BARYC_CNTL
,
1413 r600_pipe_state_add_reg(rstate
,
1414 R_028840_SQ_PGM_START_PS
,
1415 (r600_bo_offset(shader
->bo
)) >> 8, 0xFFFFFFFF, shader
->bo
);
1416 r600_pipe_state_add_reg(rstate
,
1417 R_028844_SQ_PGM_RESOURCES_PS
,
1418 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
1419 S_028844_PRIME_CACHE_ON_DRAW(1) |
1420 S_028844_STACK_SIZE(rshader
->bc
.nstack
),
1422 r600_pipe_state_add_reg(rstate
,
1423 R_028848_SQ_PGM_RESOURCES_2_PS
,
1424 0x0, 0xFFFFFFFF, NULL
);
1425 r600_pipe_state_add_reg(rstate
,
1426 R_02884C_SQ_PGM_EXPORTS_PS
,
1427 exports_ps
, 0xFFFFFFFF, NULL
);
1429 if (rshader
->uses_kill
) {
1430 /* only set some bits here, the other bits are set in the dsa state */
1431 r600_pipe_state_add_reg(rstate
,
1432 R_02880C_DB_SHADER_CONTROL
,
1433 S_02880C_KILL_ENABLE(1),
1434 S_02880C_KILL_ENABLE(1), NULL
);
1437 r600_pipe_state_add_reg(rstate
,
1438 R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF,
1442 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1444 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1445 struct r600_shader
*rshader
= &shader
->shader
;
1446 unsigned spi_vs_out_id
[10];
1449 /* clear previous register */
1452 /* so far never got proper semantic id from tgsi */
1453 for (i
= 0; i
< 10; i
++) {
1454 spi_vs_out_id
[i
] = 0;
1456 for (i
= 0; i
< 32; i
++) {
1457 tmp
= i
<< ((i
& 3) * 8);
1458 spi_vs_out_id
[i
/ 4] |= tmp
;
1460 for (i
= 0; i
< 10; i
++) {
1461 r600_pipe_state_add_reg(rstate
,
1462 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
1463 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
1466 r600_pipe_state_add_reg(rstate
,
1467 R_0286C4_SPI_VS_OUT_CONFIG
,
1468 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
1470 r600_pipe_state_add_reg(rstate
,
1471 R_028860_SQ_PGM_RESOURCES_VS
,
1472 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
1473 S_028860_STACK_SIZE(rshader
->bc
.nstack
),
1475 r600_pipe_state_add_reg(rstate
,
1476 R_028864_SQ_PGM_RESOURCES_2_VS
,
1477 0x0, 0xFFFFFFFF, NULL
);
1478 r600_pipe_state_add_reg(rstate
,
1479 R_02885C_SQ_PGM_START_VS
,
1480 (r600_bo_offset(shader
->bo
)) >> 8, 0xFFFFFFFF, shader
->bo
);
1482 r600_pipe_state_add_reg(rstate
,
1483 R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
1487 void *evergreen_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
1489 struct pipe_depth_stencil_alpha_state dsa
;
1490 struct r600_pipe_state
*rstate
;
1492 memset(&dsa
, 0, sizeof(dsa
));
1494 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
1495 r600_pipe_state_add_reg(rstate
,
1496 R_02880C_DB_SHADER_CONTROL
,
1498 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
);
1499 r600_pipe_state_add_reg(rstate
,
1500 R_028000_DB_RENDER_CONTROL
,
1501 S_028000_DEPTH_COPY_ENABLE(1) |
1502 S_028000_STENCIL_COPY_ENABLE(1) |
1503 S_028000_COPY_CENTROID(1),
1504 S_028000_DEPTH_COPY_ENABLE(1) |
1505 S_028000_STENCIL_COPY_ENABLE(1) |
1506 S_028000_COPY_CENTROID(1), NULL
);
1510 void evergreen_pipe_set_buffer_resource(struct r600_pipe_context
*rctx
,
1511 struct r600_pipe_state
*rstate
,
1512 struct r600_resource
*rbuffer
,
1513 unsigned offset
, unsigned stride
)
1515 r600_pipe_state_add_reg(rstate
, R_030000_RESOURCE0_WORD0
,
1516 offset
, 0xFFFFFFFF, rbuffer
->bo
);
1517 r600_pipe_state_add_reg(rstate
, R_030004_RESOURCE0_WORD1
,
1518 rbuffer
->bo_size
- offset
- 1, 0xFFFFFFFF, NULL
);
1519 r600_pipe_state_add_reg(rstate
, R_030008_RESOURCE0_WORD2
,
1520 S_030008_STRIDE(stride
),
1522 r600_pipe_state_add_reg(rstate
, R_03000C_RESOURCE0_WORD3
,
1523 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1524 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1525 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1526 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
),
1528 r600_pipe_state_add_reg(rstate
, R_030010_RESOURCE0_WORD4
,
1529 0x00000000, 0xFFFFFFFF, NULL
);
1530 r600_pipe_state_add_reg(rstate
, R_030014_RESOURCE0_WORD5
,
1531 0x00000000, 0xFFFFFFFF, NULL
);
1532 r600_pipe_state_add_reg(rstate
, R_030018_RESOURCE0_WORD6
,
1533 0x00000000, 0xFFFFFFFF, NULL
);
1534 r600_pipe_state_add_reg(rstate
, R_03001C_RESOURCE0_WORD7
,
1535 0xC0000000, 0xFFFFFFFF, NULL
);