2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static INLINE
unsigned evergreen_array_mode(unsigned mode
)
38 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
40 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
42 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
44 case RADEON_SURF_MODE_LINEAR
: return V_028C70_ARRAY_LINEAR_GENERAL
;
48 static uint32_t eg_num_banks(uint32_t nbanks
)
64 static unsigned eg_tile_split(unsigned tile_split
)
67 case 64: tile_split
= 0; break;
68 case 128: tile_split
= 1; break;
69 case 256: tile_split
= 2; break;
70 case 512: tile_split
= 3; break;
72 case 1024: tile_split
= 4; break;
73 case 2048: tile_split
= 5; break;
74 case 4096: tile_split
= 6; break;
79 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
81 switch (macro_tile_aspect
) {
83 case 1: macro_tile_aspect
= 0; break;
84 case 2: macro_tile_aspect
= 1; break;
85 case 4: macro_tile_aspect
= 2; break;
86 case 8: macro_tile_aspect
= 3; break;
88 return macro_tile_aspect
;
91 static unsigned eg_bank_wh(unsigned bankwh
)
95 case 1: bankwh
= 0; break;
96 case 2: bankwh
= 1; break;
97 case 4: bankwh
= 2; break;
98 case 8: bankwh
= 3; break;
103 static uint32_t r600_translate_blend_function(int blend_func
)
105 switch (blend_func
) {
107 return V_028780_COMB_DST_PLUS_SRC
;
108 case PIPE_BLEND_SUBTRACT
:
109 return V_028780_COMB_SRC_MINUS_DST
;
110 case PIPE_BLEND_REVERSE_SUBTRACT
:
111 return V_028780_COMB_DST_MINUS_SRC
;
113 return V_028780_COMB_MIN_DST_SRC
;
115 return V_028780_COMB_MAX_DST_SRC
;
117 R600_ERR("Unknown blend function %d\n", blend_func
);
124 static uint32_t r600_translate_blend_factor(int blend_fact
)
126 switch (blend_fact
) {
127 case PIPE_BLENDFACTOR_ONE
:
128 return V_028780_BLEND_ONE
;
129 case PIPE_BLENDFACTOR_SRC_COLOR
:
130 return V_028780_BLEND_SRC_COLOR
;
131 case PIPE_BLENDFACTOR_SRC_ALPHA
:
132 return V_028780_BLEND_SRC_ALPHA
;
133 case PIPE_BLENDFACTOR_DST_ALPHA
:
134 return V_028780_BLEND_DST_ALPHA
;
135 case PIPE_BLENDFACTOR_DST_COLOR
:
136 return V_028780_BLEND_DST_COLOR
;
137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
138 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
139 case PIPE_BLENDFACTOR_CONST_COLOR
:
140 return V_028780_BLEND_CONST_COLOR
;
141 case PIPE_BLENDFACTOR_CONST_ALPHA
:
142 return V_028780_BLEND_CONST_ALPHA
;
143 case PIPE_BLENDFACTOR_ZERO
:
144 return V_028780_BLEND_ZERO
;
145 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
149 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
151 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
152 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
153 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
157 case PIPE_BLENDFACTOR_SRC1_COLOR
:
158 return V_028780_BLEND_SRC1_COLOR
;
159 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
160 return V_028780_BLEND_SRC1_ALPHA
;
161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
162 return V_028780_BLEND_INV_SRC1_COLOR
;
163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
164 return V_028780_BLEND_INV_SRC1_ALPHA
;
166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
173 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
177 case PIPE_TEXTURE_1D
:
178 return V_030000_SQ_TEX_DIM_1D
;
179 case PIPE_TEXTURE_1D_ARRAY
:
180 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
181 case PIPE_TEXTURE_2D
:
182 case PIPE_TEXTURE_RECT
:
183 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
184 V_030000_SQ_TEX_DIM_2D
;
185 case PIPE_TEXTURE_2D_ARRAY
:
186 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
187 V_030000_SQ_TEX_DIM_2D_ARRAY
;
188 case PIPE_TEXTURE_3D
:
189 return V_030000_SQ_TEX_DIM_3D
;
190 case PIPE_TEXTURE_CUBE
:
191 case PIPE_TEXTURE_CUBE_ARRAY
:
192 return V_030000_SQ_TEX_DIM_CUBEMAP
;
196 static uint32_t r600_translate_dbformat(enum pipe_format format
)
199 case PIPE_FORMAT_Z16_UNORM
:
200 return V_028040_Z_16
;
201 case PIPE_FORMAT_Z24X8_UNORM
:
202 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
203 case PIPE_FORMAT_X8Z24_UNORM
:
204 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
205 return V_028040_Z_24
;
206 case PIPE_FORMAT_Z32_FLOAT
:
207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
208 return V_028040_Z_32_FLOAT
;
214 static uint32_t r600_translate_colorswap(enum pipe_format format
)
218 case PIPE_FORMAT_L4A4_UNORM
:
219 case PIPE_FORMAT_A4R4_UNORM
:
220 return V_028C70_SWAP_ALT
;
222 case PIPE_FORMAT_A8_UNORM
:
223 case PIPE_FORMAT_A8_SNORM
:
224 case PIPE_FORMAT_A8_UINT
:
225 case PIPE_FORMAT_A8_SINT
:
226 case PIPE_FORMAT_A16_UNORM
:
227 case PIPE_FORMAT_A16_SNORM
:
228 case PIPE_FORMAT_A16_UINT
:
229 case PIPE_FORMAT_A16_SINT
:
230 case PIPE_FORMAT_A16_FLOAT
:
231 case PIPE_FORMAT_A32_UINT
:
232 case PIPE_FORMAT_A32_SINT
:
233 case PIPE_FORMAT_A32_FLOAT
:
234 case PIPE_FORMAT_R4A4_UNORM
:
235 return V_028C70_SWAP_ALT_REV
;
236 case PIPE_FORMAT_I8_UNORM
:
237 case PIPE_FORMAT_I8_SNORM
:
238 case PIPE_FORMAT_I8_UINT
:
239 case PIPE_FORMAT_I8_SINT
:
240 case PIPE_FORMAT_I16_UNORM
:
241 case PIPE_FORMAT_I16_SNORM
:
242 case PIPE_FORMAT_I16_UINT
:
243 case PIPE_FORMAT_I16_SINT
:
244 case PIPE_FORMAT_I16_FLOAT
:
245 case PIPE_FORMAT_I32_UINT
:
246 case PIPE_FORMAT_I32_SINT
:
247 case PIPE_FORMAT_I32_FLOAT
:
248 case PIPE_FORMAT_L8_UNORM
:
249 case PIPE_FORMAT_L8_SNORM
:
250 case PIPE_FORMAT_L8_UINT
:
251 case PIPE_FORMAT_L8_SINT
:
252 case PIPE_FORMAT_L8_SRGB
:
253 case PIPE_FORMAT_L16_UNORM
:
254 case PIPE_FORMAT_L16_SNORM
:
255 case PIPE_FORMAT_L16_UINT
:
256 case PIPE_FORMAT_L16_SINT
:
257 case PIPE_FORMAT_L16_FLOAT
:
258 case PIPE_FORMAT_L32_UINT
:
259 case PIPE_FORMAT_L32_SINT
:
260 case PIPE_FORMAT_L32_FLOAT
:
261 case PIPE_FORMAT_R8_UNORM
:
262 case PIPE_FORMAT_R8_SNORM
:
263 case PIPE_FORMAT_R8_UINT
:
264 case PIPE_FORMAT_R8_SINT
:
265 return V_028C70_SWAP_STD
;
267 /* 16-bit buffers. */
268 case PIPE_FORMAT_B5G6R5_UNORM
:
269 return V_028C70_SWAP_STD_REV
;
271 case PIPE_FORMAT_B5G5R5A1_UNORM
:
272 case PIPE_FORMAT_B5G5R5X1_UNORM
:
273 return V_028C70_SWAP_ALT
;
275 case PIPE_FORMAT_B4G4R4A4_UNORM
:
276 case PIPE_FORMAT_B4G4R4X4_UNORM
:
277 return V_028C70_SWAP_ALT
;
279 case PIPE_FORMAT_Z16_UNORM
:
280 return V_028C70_SWAP_STD
;
282 case PIPE_FORMAT_L8A8_UNORM
:
283 case PIPE_FORMAT_L8A8_SNORM
:
284 case PIPE_FORMAT_L8A8_UINT
:
285 case PIPE_FORMAT_L8A8_SINT
:
286 case PIPE_FORMAT_L8A8_SRGB
:
287 case PIPE_FORMAT_L16A16_UNORM
:
288 case PIPE_FORMAT_L16A16_SNORM
:
289 case PIPE_FORMAT_L16A16_UINT
:
290 case PIPE_FORMAT_L16A16_SINT
:
291 case PIPE_FORMAT_L16A16_FLOAT
:
292 case PIPE_FORMAT_L32A32_UINT
:
293 case PIPE_FORMAT_L32A32_SINT
:
294 case PIPE_FORMAT_L32A32_FLOAT
:
295 case PIPE_FORMAT_R8A8_UNORM
:
296 case PIPE_FORMAT_R8A8_SNORM
:
297 case PIPE_FORMAT_R8A8_UINT
:
298 case PIPE_FORMAT_R8A8_SINT
:
299 case PIPE_FORMAT_R16A16_UNORM
:
300 case PIPE_FORMAT_R16A16_SNORM
:
301 case PIPE_FORMAT_R16A16_UINT
:
302 case PIPE_FORMAT_R16A16_SINT
:
303 case PIPE_FORMAT_R16A16_FLOAT
:
304 case PIPE_FORMAT_R32A32_UINT
:
305 case PIPE_FORMAT_R32A32_SINT
:
306 case PIPE_FORMAT_R32A32_FLOAT
:
307 return V_028C70_SWAP_ALT
;
308 case PIPE_FORMAT_R8G8_UNORM
:
309 case PIPE_FORMAT_R8G8_SNORM
:
310 case PIPE_FORMAT_R8G8_UINT
:
311 case PIPE_FORMAT_R8G8_SINT
:
312 return V_028C70_SWAP_STD
;
314 case PIPE_FORMAT_R16_UNORM
:
315 case PIPE_FORMAT_R16_SNORM
:
316 case PIPE_FORMAT_R16_UINT
:
317 case PIPE_FORMAT_R16_SINT
:
318 case PIPE_FORMAT_R16_FLOAT
:
319 return V_028C70_SWAP_STD
;
321 /* 32-bit buffers. */
322 case PIPE_FORMAT_A8B8G8R8_SRGB
:
323 return V_028C70_SWAP_STD_REV
;
324 case PIPE_FORMAT_B8G8R8A8_SRGB
:
325 return V_028C70_SWAP_ALT
;
327 case PIPE_FORMAT_B8G8R8A8_UNORM
:
328 case PIPE_FORMAT_B8G8R8X8_UNORM
:
329 return V_028C70_SWAP_ALT
;
331 case PIPE_FORMAT_A8R8G8B8_UNORM
:
332 case PIPE_FORMAT_X8R8G8B8_UNORM
:
333 return V_028C70_SWAP_ALT_REV
;
334 case PIPE_FORMAT_R8G8B8A8_SNORM
:
335 case PIPE_FORMAT_R8G8B8A8_UNORM
:
336 case PIPE_FORMAT_R8G8B8A8_SINT
:
337 case PIPE_FORMAT_R8G8B8A8_UINT
:
338 case PIPE_FORMAT_R8G8B8X8_UNORM
:
339 case PIPE_FORMAT_R8G8B8X8_SNORM
:
340 case PIPE_FORMAT_R8G8B8X8_SRGB
:
341 case PIPE_FORMAT_R8G8B8X8_UINT
:
342 case PIPE_FORMAT_R8G8B8X8_SINT
:
343 return V_028C70_SWAP_STD
;
345 case PIPE_FORMAT_A8B8G8R8_UNORM
:
346 case PIPE_FORMAT_X8B8G8R8_UNORM
:
347 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
348 return V_028C70_SWAP_STD_REV
;
350 case PIPE_FORMAT_Z24X8_UNORM
:
351 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
352 return V_028C70_SWAP_STD
;
354 case PIPE_FORMAT_X8Z24_UNORM
:
355 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
356 return V_028C70_SWAP_STD_REV
;
358 case PIPE_FORMAT_R10G10B10A2_UNORM
:
359 case PIPE_FORMAT_R10G10B10X2_SNORM
:
360 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
361 return V_028C70_SWAP_STD
;
363 case PIPE_FORMAT_B10G10R10A2_UNORM
:
364 case PIPE_FORMAT_B10G10R10A2_UINT
:
365 case PIPE_FORMAT_B10G10R10X2_UNORM
:
366 return V_028C70_SWAP_ALT
;
368 case PIPE_FORMAT_R11G11B10_FLOAT
:
369 case PIPE_FORMAT_R32_FLOAT
:
370 case PIPE_FORMAT_R32_UINT
:
371 case PIPE_FORMAT_R32_SINT
:
372 case PIPE_FORMAT_Z32_FLOAT
:
373 case PIPE_FORMAT_R16G16_FLOAT
:
374 case PIPE_FORMAT_R16G16_UNORM
:
375 case PIPE_FORMAT_R16G16_SNORM
:
376 case PIPE_FORMAT_R16G16_UINT
:
377 case PIPE_FORMAT_R16G16_SINT
:
378 return V_028C70_SWAP_STD
;
380 /* 64-bit buffers. */
381 case PIPE_FORMAT_R32G32_FLOAT
:
382 case PIPE_FORMAT_R32G32_UINT
:
383 case PIPE_FORMAT_R32G32_SINT
:
384 case PIPE_FORMAT_R16G16B16A16_UNORM
:
385 case PIPE_FORMAT_R16G16B16A16_SNORM
:
386 case PIPE_FORMAT_R16G16B16A16_UINT
:
387 case PIPE_FORMAT_R16G16B16A16_SINT
:
388 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
389 case PIPE_FORMAT_R16G16B16X16_UNORM
:
390 case PIPE_FORMAT_R16G16B16X16_SNORM
:
391 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
392 case PIPE_FORMAT_R16G16B16X16_UINT
:
393 case PIPE_FORMAT_R16G16B16X16_SINT
:
394 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
396 /* 128-bit buffers. */
397 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
398 case PIPE_FORMAT_R32G32B32A32_SNORM
:
399 case PIPE_FORMAT_R32G32B32A32_UNORM
:
400 case PIPE_FORMAT_R32G32B32A32_SINT
:
401 case PIPE_FORMAT_R32G32B32A32_UINT
:
402 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
403 case PIPE_FORMAT_R32G32B32X32_UINT
:
404 case PIPE_FORMAT_R32G32B32X32_SINT
:
405 return V_028C70_SWAP_STD
;
407 R600_ERR("unsupported colorswap format %d\n", format
);
413 static uint32_t r600_translate_colorformat(enum pipe_format format
)
417 case PIPE_FORMAT_A8_UNORM
:
418 case PIPE_FORMAT_A8_SNORM
:
419 case PIPE_FORMAT_A8_UINT
:
420 case PIPE_FORMAT_A8_SINT
:
421 case PIPE_FORMAT_I8_UNORM
:
422 case PIPE_FORMAT_I8_SNORM
:
423 case PIPE_FORMAT_I8_UINT
:
424 case PIPE_FORMAT_I8_SINT
:
425 case PIPE_FORMAT_L8_UNORM
:
426 case PIPE_FORMAT_L8_SNORM
:
427 case PIPE_FORMAT_L8_UINT
:
428 case PIPE_FORMAT_L8_SINT
:
429 case PIPE_FORMAT_L8_SRGB
:
430 case PIPE_FORMAT_R8_UNORM
:
431 case PIPE_FORMAT_R8_SNORM
:
432 case PIPE_FORMAT_R8_UINT
:
433 case PIPE_FORMAT_R8_SINT
:
434 return V_028C70_COLOR_8
;
436 /* 16-bit buffers. */
437 case PIPE_FORMAT_B5G6R5_UNORM
:
438 return V_028C70_COLOR_5_6_5
;
440 case PIPE_FORMAT_B5G5R5A1_UNORM
:
441 case PIPE_FORMAT_B5G5R5X1_UNORM
:
442 return V_028C70_COLOR_1_5_5_5
;
444 case PIPE_FORMAT_B4G4R4A4_UNORM
:
445 case PIPE_FORMAT_B4G4R4X4_UNORM
:
446 return V_028C70_COLOR_4_4_4_4
;
448 case PIPE_FORMAT_Z16_UNORM
:
449 return V_028C70_COLOR_16
;
451 case PIPE_FORMAT_L8A8_UNORM
:
452 case PIPE_FORMAT_L8A8_SNORM
:
453 case PIPE_FORMAT_L8A8_UINT
:
454 case PIPE_FORMAT_L8A8_SINT
:
455 case PIPE_FORMAT_L8A8_SRGB
:
456 case PIPE_FORMAT_R8G8_UNORM
:
457 case PIPE_FORMAT_R8G8_SNORM
:
458 case PIPE_FORMAT_R8G8_UINT
:
459 case PIPE_FORMAT_R8G8_SINT
:
460 case PIPE_FORMAT_R8A8_UNORM
:
461 case PIPE_FORMAT_R8A8_SNORM
:
462 case PIPE_FORMAT_R8A8_UINT
:
463 case PIPE_FORMAT_R8A8_SINT
:
464 return V_028C70_COLOR_8_8
;
466 case PIPE_FORMAT_R16_UNORM
:
467 case PIPE_FORMAT_R16_SNORM
:
468 case PIPE_FORMAT_R16_UINT
:
469 case PIPE_FORMAT_R16_SINT
:
470 case PIPE_FORMAT_A16_UNORM
:
471 case PIPE_FORMAT_A16_SNORM
:
472 case PIPE_FORMAT_A16_UINT
:
473 case PIPE_FORMAT_A16_SINT
:
474 case PIPE_FORMAT_L16_UNORM
:
475 case PIPE_FORMAT_L16_SNORM
:
476 case PIPE_FORMAT_L16_UINT
:
477 case PIPE_FORMAT_L16_SINT
:
478 case PIPE_FORMAT_I16_UNORM
:
479 case PIPE_FORMAT_I16_SNORM
:
480 case PIPE_FORMAT_I16_UINT
:
481 case PIPE_FORMAT_I16_SINT
:
482 return V_028C70_COLOR_16
;
484 case PIPE_FORMAT_R16_FLOAT
:
485 case PIPE_FORMAT_A16_FLOAT
:
486 case PIPE_FORMAT_L16_FLOAT
:
487 case PIPE_FORMAT_I16_FLOAT
:
488 return V_028C70_COLOR_16_FLOAT
;
490 /* 32-bit buffers. */
491 case PIPE_FORMAT_A8B8G8R8_SRGB
:
492 case PIPE_FORMAT_A8B8G8R8_UNORM
:
493 case PIPE_FORMAT_A8R8G8B8_UNORM
:
494 case PIPE_FORMAT_B8G8R8A8_SRGB
:
495 case PIPE_FORMAT_B8G8R8A8_UNORM
:
496 case PIPE_FORMAT_B8G8R8X8_UNORM
:
497 case PIPE_FORMAT_R8G8B8A8_SNORM
:
498 case PIPE_FORMAT_R8G8B8A8_UNORM
:
499 case PIPE_FORMAT_R8G8B8X8_UNORM
:
500 case PIPE_FORMAT_R8G8B8X8_SNORM
:
501 case PIPE_FORMAT_R8G8B8X8_SRGB
:
502 case PIPE_FORMAT_R8G8B8X8_UINT
:
503 case PIPE_FORMAT_R8G8B8X8_SINT
:
504 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
505 case PIPE_FORMAT_X8B8G8R8_UNORM
:
506 case PIPE_FORMAT_X8R8G8B8_UNORM
:
507 case PIPE_FORMAT_R8G8B8_UNORM
:
508 case PIPE_FORMAT_R8G8B8A8_SINT
:
509 case PIPE_FORMAT_R8G8B8A8_UINT
:
510 return V_028C70_COLOR_8_8_8_8
;
512 case PIPE_FORMAT_R10G10B10A2_UNORM
:
513 case PIPE_FORMAT_R10G10B10X2_SNORM
:
514 case PIPE_FORMAT_B10G10R10A2_UNORM
:
515 case PIPE_FORMAT_B10G10R10A2_UINT
:
516 case PIPE_FORMAT_B10G10R10X2_UNORM
:
517 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
518 return V_028C70_COLOR_2_10_10_10
;
520 case PIPE_FORMAT_Z24X8_UNORM
:
521 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
522 return V_028C70_COLOR_8_24
;
524 case PIPE_FORMAT_X8Z24_UNORM
:
525 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
526 return V_028C70_COLOR_24_8
;
528 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
529 return V_028C70_COLOR_X24_8_32_FLOAT
;
531 case PIPE_FORMAT_R32_UINT
:
532 case PIPE_FORMAT_R32_SINT
:
533 case PIPE_FORMAT_A32_UINT
:
534 case PIPE_FORMAT_A32_SINT
:
535 case PIPE_FORMAT_L32_UINT
:
536 case PIPE_FORMAT_L32_SINT
:
537 case PIPE_FORMAT_I32_UINT
:
538 case PIPE_FORMAT_I32_SINT
:
539 return V_028C70_COLOR_32
;
541 case PIPE_FORMAT_R32_FLOAT
:
542 case PIPE_FORMAT_A32_FLOAT
:
543 case PIPE_FORMAT_L32_FLOAT
:
544 case PIPE_FORMAT_I32_FLOAT
:
545 case PIPE_FORMAT_Z32_FLOAT
:
546 return V_028C70_COLOR_32_FLOAT
;
548 case PIPE_FORMAT_R16G16_FLOAT
:
549 case PIPE_FORMAT_L16A16_FLOAT
:
550 case PIPE_FORMAT_R16A16_FLOAT
:
551 return V_028C70_COLOR_16_16_FLOAT
;
553 case PIPE_FORMAT_R16G16_UNORM
:
554 case PIPE_FORMAT_R16G16_SNORM
:
555 case PIPE_FORMAT_R16G16_UINT
:
556 case PIPE_FORMAT_R16G16_SINT
:
557 case PIPE_FORMAT_L16A16_UNORM
:
558 case PIPE_FORMAT_L16A16_SNORM
:
559 case PIPE_FORMAT_L16A16_UINT
:
560 case PIPE_FORMAT_L16A16_SINT
:
561 case PIPE_FORMAT_R16A16_UNORM
:
562 case PIPE_FORMAT_R16A16_SNORM
:
563 case PIPE_FORMAT_R16A16_UINT
:
564 case PIPE_FORMAT_R16A16_SINT
:
565 return V_028C70_COLOR_16_16
;
567 case PIPE_FORMAT_R11G11B10_FLOAT
:
568 return V_028C70_COLOR_10_11_11_FLOAT
;
570 /* 64-bit buffers. */
571 case PIPE_FORMAT_R16G16B16A16_UINT
:
572 case PIPE_FORMAT_R16G16B16A16_SINT
:
573 case PIPE_FORMAT_R16G16B16A16_UNORM
:
574 case PIPE_FORMAT_R16G16B16A16_SNORM
:
575 case PIPE_FORMAT_R16G16B16X16_UNORM
:
576 case PIPE_FORMAT_R16G16B16X16_SNORM
:
577 case PIPE_FORMAT_R16G16B16X16_UINT
:
578 case PIPE_FORMAT_R16G16B16X16_SINT
:
579 return V_028C70_COLOR_16_16_16_16
;
581 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
582 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
583 return V_028C70_COLOR_16_16_16_16_FLOAT
;
585 case PIPE_FORMAT_R32G32_FLOAT
:
586 case PIPE_FORMAT_L32A32_FLOAT
:
587 case PIPE_FORMAT_R32A32_FLOAT
:
588 return V_028C70_COLOR_32_32_FLOAT
;
590 case PIPE_FORMAT_R32G32_SINT
:
591 case PIPE_FORMAT_R32G32_UINT
:
592 case PIPE_FORMAT_L32A32_UINT
:
593 case PIPE_FORMAT_L32A32_SINT
:
594 return V_028C70_COLOR_32_32
;
596 /* 128-bit buffers. */
597 case PIPE_FORMAT_R32G32B32A32_SNORM
:
598 case PIPE_FORMAT_R32G32B32A32_UNORM
:
599 case PIPE_FORMAT_R32G32B32A32_SINT
:
600 case PIPE_FORMAT_R32G32B32A32_UINT
:
601 case PIPE_FORMAT_R32G32B32X32_UINT
:
602 case PIPE_FORMAT_R32G32B32X32_SINT
:
603 return V_028C70_COLOR_32_32_32_32
;
604 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
605 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
606 return V_028C70_COLOR_32_32_32_32_FLOAT
;
609 case PIPE_FORMAT_UYVY
:
610 case PIPE_FORMAT_YUYV
:
612 return ~0U; /* Unsupported. */
616 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
618 if (R600_BIG_ENDIAN
) {
619 switch(colorformat
) {
622 case V_028C70_COLOR_8
:
625 /* 16-bit buffers. */
626 case V_028C70_COLOR_5_6_5
:
627 case V_028C70_COLOR_1_5_5_5
:
628 case V_028C70_COLOR_4_4_4_4
:
629 case V_028C70_COLOR_16
:
630 case V_028C70_COLOR_8_8
:
633 /* 32-bit buffers. */
634 case V_028C70_COLOR_8_8_8_8
:
635 case V_028C70_COLOR_2_10_10_10
:
636 case V_028C70_COLOR_8_24
:
637 case V_028C70_COLOR_24_8
:
638 case V_028C70_COLOR_32_FLOAT
:
639 case V_028C70_COLOR_16_16_FLOAT
:
640 case V_028C70_COLOR_16_16
:
643 /* 64-bit buffers. */
644 case V_028C70_COLOR_16_16_16_16
:
645 case V_028C70_COLOR_16_16_16_16_FLOAT
:
648 case V_028C70_COLOR_32_32_FLOAT
:
649 case V_028C70_COLOR_32_32
:
650 case V_028C70_COLOR_X24_8_32_FLOAT
:
653 /* 96-bit buffers. */
654 case V_028C70_COLOR_32_32_32_FLOAT
:
655 /* 128-bit buffers. */
656 case V_028C70_COLOR_32_32_32_32_FLOAT
:
657 case V_028C70_COLOR_32_32_32_32
:
660 return ENDIAN_NONE
; /* Unsupported. */
667 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
669 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
672 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
674 return r600_translate_colorformat(format
) != ~0U &&
675 r600_translate_colorswap(format
) != ~0U;
678 static bool r600_is_zs_format_supported(enum pipe_format format
)
680 return r600_translate_dbformat(format
) != ~0U;
683 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
684 enum pipe_format format
,
685 enum pipe_texture_target target
,
686 unsigned sample_count
,
689 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
692 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
693 R600_ERR("r600: unsupported texture type %d\n", target
);
697 if (!util_format_is_supported(format
, usage
))
700 if (sample_count
> 1) {
701 if (!rscreen
->has_msaa
)
704 switch (sample_count
) {
714 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
715 r600_is_sampler_format_supported(screen
, format
)) {
716 retval
|= PIPE_BIND_SAMPLER_VIEW
;
719 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
720 PIPE_BIND_DISPLAY_TARGET
|
722 PIPE_BIND_SHARED
)) &&
723 r600_is_colorbuffer_format_supported(format
)) {
725 (PIPE_BIND_RENDER_TARGET
|
726 PIPE_BIND_DISPLAY_TARGET
|
731 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
732 r600_is_zs_format_supported(format
)) {
733 retval
|= PIPE_BIND_DEPTH_STENCIL
;
736 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
737 r600_is_vertex_format_supported(format
)) {
738 retval
|= PIPE_BIND_VERTEX_BUFFER
;
741 if (usage
& PIPE_BIND_TRANSFER_READ
)
742 retval
|= PIPE_BIND_TRANSFER_READ
;
743 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
744 retval
|= PIPE_BIND_TRANSFER_WRITE
;
746 return retval
== usage
;
749 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
750 const struct pipe_blend_state
*state
, int mode
)
752 uint32_t color_control
= 0, target_mask
= 0;
753 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
759 r600_init_command_buffer(&blend
->buffer
, 20);
760 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
762 if (state
->logicop_enable
) {
763 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
765 color_control
|= (0xcc << 16);
767 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
768 if (state
->independent_blend_enable
) {
769 for (int i
= 0; i
< 8; i
++) {
770 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
773 for (int i
= 0; i
< 8; i
++) {
774 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
778 /* only have dual source on MRT0 */
779 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
780 blend
->cb_target_mask
= target_mask
;
781 blend
->alpha_to_one
= state
->alpha_to_one
;
784 color_control
|= S_028808_MODE(mode
);
786 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
789 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
790 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
791 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
792 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
793 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
794 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
795 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
796 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
798 /* Copy over the dwords set so far into buffer_no_blend.
799 * Only the CB_BLENDi_CONTROL registers must be set after this. */
800 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
801 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
803 for (int i
= 0; i
< 8; i
++) {
804 /* state->rt entries > 0 only written if independent blending */
805 const int j
= state
->independent_blend_enable
? i
: 0;
807 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
808 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
809 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
810 unsigned eqA
= state
->rt
[j
].alpha_func
;
811 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
812 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
815 r600_store_value(&blend
->buffer_no_blend
, 0);
817 if (!state
->rt
[j
].blend_enable
) {
818 r600_store_value(&blend
->buffer
, 0);
822 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
823 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
824 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
825 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
827 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
828 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
829 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
830 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
831 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
833 r600_store_value(&blend
->buffer
, bc
);
838 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
839 const struct pipe_blend_state
*state
)
842 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
845 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
846 const struct pipe_depth_stencil_alpha_state
*state
)
848 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
849 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
855 r600_init_command_buffer(&dsa
->buffer
, 3);
857 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
858 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
859 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
860 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
861 dsa
->zwritemask
= state
->depth
.writemask
;
863 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
864 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
865 S_028800_ZFUNC(state
->depth
.func
);
868 if (state
->stencil
[0].enabled
) {
869 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
870 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
871 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
872 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
873 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
875 if (state
->stencil
[1].enabled
) {
876 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
877 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
878 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
879 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
880 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
885 alpha_test_control
= 0;
887 if (state
->alpha
.enabled
) {
888 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
889 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
890 alpha_ref
= fui(state
->alpha
.ref_value
);
892 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
893 dsa
->alpha_ref
= alpha_ref
;
896 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
900 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
901 const struct pipe_rasterizer_state
*state
)
903 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
904 unsigned tmp
, spi_interp
;
905 float psize_min
, psize_max
;
906 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
912 r600_init_command_buffer(&rs
->buffer
, 30);
914 rs
->flatshade
= state
->flatshade
;
915 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
916 rs
->two_side
= state
->light_twoside
;
917 rs
->clip_plane_enable
= state
->clip_plane_enable
;
918 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
919 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
920 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
921 rs
->pa_cl_clip_cntl
=
922 S_028810_PS_UCP_MODE(3) |
923 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
924 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
925 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
926 rs
->multisample_enable
= state
->multisample
;
929 rs
->offset_units
= state
->offset_units
;
930 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
931 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
933 if (state
->point_size_per_vertex
) {
934 psize_min
= util_get_min_point_size(state
);
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min
= state
->point_size
;
939 psize_max
= state
->point_size
;
942 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
943 if (state
->sprite_coord_enable
) {
944 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
945 S_0286D4_PNT_SPRITE_OVRD_X(2) |
946 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
947 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
948 S_0286D4_PNT_SPRITE_OVRD_W(1);
949 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
950 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
954 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
955 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
956 tmp
= r600_pack_float_12p4(state
->point_size
/2);
957 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
958 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
959 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
960 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
961 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
962 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
963 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
965 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
966 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
967 S_028A48_MSAA_ENABLE(state
->multisample
) |
968 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
969 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
971 if (rctx
->b
.chip_class
== CAYMAN
) {
972 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
973 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
974 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
976 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
977 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
978 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
981 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
982 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
983 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
984 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
985 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
986 S_028814_FACE(!state
->front_ccw
) |
987 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
988 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
989 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
990 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
991 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
992 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
993 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
994 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
998 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
999 const struct pipe_sampler_state
*state
)
1001 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
1002 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
1008 ss
->border_color_use
= sampler_state_needs_border_color(state
);
1010 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
1011 ss
->tex_sampler_words
[0] =
1012 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
1013 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
1014 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1015 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
1016 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
1017 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1018 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
1019 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
1020 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
1021 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1022 ss
->tex_sampler_words
[1] =
1023 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
1024 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
1025 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1026 ss
->tex_sampler_words
[2] =
1027 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
1028 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1031 if (ss
->border_color_use
) {
1032 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
1037 static struct pipe_sampler_view
*
1038 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
1039 unsigned width0
, unsigned height0
)
1042 struct pipe_context
*ctx
= view
->base
.context
;
1043 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
1045 int stride
= util_format_get_blocksize(view
->base
.format
);
1046 unsigned format
, num_format
, format_comp
, endian
;
1047 unsigned swizzle_res
;
1048 unsigned char swizzle
[4];
1049 const struct util_format_description
*desc
;
1050 unsigned offset
= view
->base
.u
.buf
.first_element
* stride
;
1051 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
1053 swizzle
[0] = view
->base
.swizzle_r
;
1054 swizzle
[1] = view
->base
.swizzle_g
;
1055 swizzle
[2] = view
->base
.swizzle_b
;
1056 swizzle
[3] = view
->base
.swizzle_a
;
1058 r600_vertex_data_type(view
->base
.format
,
1059 &format
, &num_format
, &format_comp
,
1062 desc
= util_format_description(view
->base
.format
);
1064 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, swizzle
, TRUE
);
1066 va
= r600_resource_va(ctx
->screen
, view
->base
.texture
) + offset
;
1067 view
->tex_resource
= &tmp
->resource
;
1069 view
->skip_mip_address_reloc
= true;
1070 view
->tex_resource_words
[0] = va
;
1071 view
->tex_resource_words
[1] = size
- 1;
1072 view
->tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
1073 S_030008_STRIDE(stride
) |
1074 S_030008_DATA_FORMAT(format
) |
1075 S_030008_NUM_FORMAT_ALL(num_format
) |
1076 S_030008_FORMAT_COMP_ALL(format_comp
) |
1077 S_030008_SRF_MODE_ALL(1) |
1078 S_030008_ENDIAN_SWAP(endian
);
1079 view
->tex_resource_words
[3] = swizzle_res
;
1081 * in theory dword 4 is for number of elements, for use with resinfo,
1082 * but it seems to utterly fail to work, the amd gpu shader analyser
1083 * uses a const buffer to store the element sizes for buffer txq
1085 view
->tex_resource_words
[4] = 0;
1086 view
->tex_resource_words
[5] = view
->tex_resource_words
[6] = 0;
1087 view
->tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
1091 struct pipe_sampler_view
*
1092 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
1093 struct pipe_resource
*texture
,
1094 const struct pipe_sampler_view
*state
,
1095 unsigned width0
, unsigned height0
)
1097 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
1098 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
1099 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
1100 unsigned format
, endian
;
1101 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1102 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
1103 unsigned height
, depth
, width
;
1104 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
1105 enum pipe_format pipe_format
= state
->format
;
1106 struct radeon_surface_level
*surflevel
;
1111 /* initialize base object */
1112 view
->base
= *state
;
1113 view
->base
.texture
= NULL
;
1114 pipe_reference(NULL
, &texture
->reference
);
1115 view
->base
.texture
= texture
;
1116 view
->base
.reference
.count
= 1;
1117 view
->base
.context
= ctx
;
1119 if (texture
->target
== PIPE_BUFFER
)
1120 return texture_buffer_sampler_view(view
, width0
, height0
);
1122 swizzle
[0] = state
->swizzle_r
;
1123 swizzle
[1] = state
->swizzle_g
;
1124 swizzle
[2] = state
->swizzle_b
;
1125 swizzle
[3] = state
->swizzle_a
;
1127 tile_split
= tmp
->surface
.tile_split
;
1128 surflevel
= tmp
->surface
.level
;
1130 /* Texturing with separate depth and stencil. */
1131 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1132 switch (pipe_format
) {
1133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1134 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1136 case PIPE_FORMAT_X8Z24_UNORM
:
1137 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1138 /* Z24 is always stored like this. */
1139 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1141 case PIPE_FORMAT_X24S8_UINT
:
1142 case PIPE_FORMAT_S8X24_UINT
:
1143 case PIPE_FORMAT_X32_S8X24_UINT
:
1144 pipe_format
= PIPE_FORMAT_S8_UINT
;
1145 tile_split
= tmp
->surface
.stencil_tile_split
;
1146 surflevel
= tmp
->surface
.stencil_level
;
1152 format
= r600_translate_texformat(ctx
->screen
, pipe_format
,
1154 &word4
, &yuv_format
);
1155 assert(format
!= ~0);
1161 endian
= r600_colorformat_endian_swap(format
);
1165 depth
= texture
->depth0
;
1166 pitch
= surflevel
[0].nblk_x
* util_format_get_blockwidth(pipe_format
);
1167 non_disp_tiling
= tmp
->non_disp_tiling
;
1169 switch (surflevel
[0].mode
) {
1170 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1171 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
1173 case RADEON_SURF_MODE_2D
:
1174 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1176 case RADEON_SURF_MODE_1D
:
1177 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1179 case RADEON_SURF_MODE_LINEAR
:
1181 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
1184 macro_aspect
= tmp
->surface
.mtilea
;
1185 bankw
= tmp
->surface
.bankw
;
1186 bankh
= tmp
->surface
.bankh
;
1187 tile_split
= eg_tile_split(tile_split
);
1188 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1189 bankw
= eg_bank_wh(bankw
);
1190 bankh
= eg_bank_wh(bankh
);
1191 fmask_bankh
= eg_bank_wh(tmp
->fmask_bank_height
);
1193 /* 128 bit formats require tile type = 1 */
1194 if (rscreen
->b
.chip_class
== CAYMAN
) {
1195 if (util_format_get_blocksize(pipe_format
) >= 16)
1196 non_disp_tiling
= 1;
1198 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1200 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1202 depth
= texture
->array_size
;
1203 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1204 depth
= texture
->array_size
;
1205 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
1206 depth
= texture
->array_size
/ 6;
1208 view
->tex_resource
= &tmp
->resource
;
1209 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1210 S_030000_PITCH((pitch
/ 8) - 1) |
1211 S_030000_TEX_WIDTH(width
- 1));
1212 if (rscreen
->b
.chip_class
== CAYMAN
)
1213 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
1215 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
1216 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1217 S_030004_TEX_DEPTH(depth
- 1) |
1218 S_030004_ARRAY_MODE(array_mode
));
1219 view
->tex_resource_words
[2] = (surflevel
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1221 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
1222 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
1223 if (tmp
->is_depth
) {
1224 /* disable FMASK (0 = disabled) */
1225 view
->tex_resource_words
[3] = 0;
1226 view
->skip_mip_address_reloc
= true;
1228 /* FMASK should be in MIP_ADDRESS for multisample textures */
1229 view
->tex_resource_words
[3] = (tmp
->fmask_offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1231 } else if (state
->u
.tex
.last_level
&& texture
->nr_samples
<= 1) {
1232 view
->tex_resource_words
[3] = (surflevel
[1].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1234 view
->tex_resource_words
[3] = (surflevel
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1237 view
->tex_resource_words
[4] = (word4
|
1238 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1239 S_030010_ENDIAN_SWAP(endian
));
1240 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1241 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
1242 view
->tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
1244 if (texture
->nr_samples
> 1) {
1245 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
1246 if (rscreen
->b
.chip_class
== CAYMAN
) {
1247 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
1249 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1250 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
1251 view
->tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
1253 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(state
->u
.tex
.first_level
);
1254 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(state
->u
.tex
.last_level
);
1255 /* aniso max 16 samples */
1256 view
->tex_resource_words
[6] |= S_030018_MAX_ANISO(4);
1259 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
1260 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
1261 S_03001C_BANK_WIDTH(bankw
) |
1262 S_03001C_BANK_HEIGHT(bankh
) |
1263 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
1264 S_03001C_NUM_BANKS(nbanks
) |
1265 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
1269 static struct pipe_sampler_view
*
1270 evergreen_create_sampler_view(struct pipe_context
*ctx
,
1271 struct pipe_resource
*tex
,
1272 const struct pipe_sampler_view
*state
)
1274 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
1275 tex
->width0
, tex
->height0
);
1278 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1280 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1281 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1283 r600_write_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
1284 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
1287 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1288 const struct pipe_poly_stipple
*state
)
1292 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1293 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1294 uint32_t *tl
, uint32_t *br
)
1296 /* EG hw workaround */
1302 /* cayman hw workaround */
1303 if (rctx
->b
.chip_class
== CAYMAN
) {
1304 if (br_x
== 1 && br_y
== 1)
1308 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1309 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1312 static void evergreen_set_scissor_states(struct pipe_context
*ctx
,
1313 unsigned start_slot
,
1314 unsigned num_scissors
,
1315 const struct pipe_scissor_state
*state
)
1317 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1319 rctx
->scissor
.scissor
= *state
;
1320 rctx
->scissor
.atom
.dirty
= true;
1323 static void evergreen_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1325 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1326 struct pipe_scissor_state
*state
= &rctx
->scissor
.scissor
;
1329 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
1331 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1332 radeon_emit(cs
, tl
);
1333 radeon_emit(cs
, br
);
1337 * This function intializes the CB* register values for RATs. It is meant
1338 * to be used for 1D aligned buffers that do not have an associated
1341 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
1342 struct r600_surface
*surf
)
1344 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
1345 unsigned format
= r600_translate_colorformat(surf
->base
.format
);
1346 unsigned endian
= r600_colorformat_endian_swap(format
);
1347 unsigned swap
= r600_translate_colorswap(surf
->base
.format
);
1348 unsigned block_size
=
1349 align(util_format_get_blocksize(pipe_buffer
->format
), 4);
1350 unsigned pitch_alignment
=
1351 MAX2(64, rctx
->screen
->tiling_info
.group_bytes
/ block_size
);
1352 unsigned pitch
= align(pipe_buffer
->width0
, pitch_alignment
);
1354 /* XXX: This is copied from evergreen_init_color_surface(). I don't
1355 * know why this is necessary.
1357 if (pipe_buffer
->usage
== PIPE_USAGE_STAGING
) {
1358 endian
= ENDIAN_NONE
;
1361 surf
->cb_color_base
=
1362 r600_resource_va(rctx
->b
.b
.screen
, pipe_buffer
) >> 8;
1364 surf
->cb_color_pitch
= (pitch
/ 8) - 1;
1366 surf
->cb_color_slice
= 0;
1368 surf
->cb_color_view
= 0;
1370 surf
->cb_color_info
=
1371 S_028C70_ENDIAN(endian
)
1372 | S_028C70_FORMAT(format
)
1373 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
)
1374 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT
)
1375 | S_028C70_COMP_SWAP(swap
)
1376 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
1377 * are using NUMBER_UINT */
1381 surf
->cb_color_attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
1383 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
1385 surf
->cb_color_dim
= pipe_buffer
->width0
;
1387 /* Set the buffer range the GPU will have access to: */
1388 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
1389 0, pipe_buffer
->width0
);
1391 surf
->cb_color_cmask
= surf
->cb_color_base
;
1392 surf
->cb_color_cmask_slice
= 0;
1393 surf
->cb_color_fmask
= surf
->cb_color_base
;
1394 surf
->cb_color_fmask_slice
= 0;
1397 void evergreen_init_color_surface(struct r600_context
*rctx
,
1398 struct r600_surface
*surf
)
1400 struct r600_screen
*rscreen
= rctx
->screen
;
1401 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1402 struct pipe_resource
*pipe_tex
= surf
->base
.texture
;
1403 unsigned level
= surf
->base
.u
.tex
.level
;
1404 unsigned pitch
, slice
;
1405 unsigned color_info
, color_attrib
, color_dim
= 0;
1406 unsigned format
, swap
, ntype
, endian
;
1407 uint64_t offset
, base_offset
;
1408 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1409 const struct util_format_description
*desc
;
1411 bool blend_clamp
= 0, blend_bypass
= 0;
1413 offset
= rtex
->surface
.level
[level
].offset
;
1414 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1415 offset
+= rtex
->surface
.level
[level
].slice_size
*
1416 surf
->base
.u
.tex
.first_layer
;
1418 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1419 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1424 switch (rtex
->surface
.level
[level
].mode
) {
1425 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1426 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1427 non_disp_tiling
= 1;
1429 case RADEON_SURF_MODE_1D
:
1430 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1431 non_disp_tiling
= rtex
->non_disp_tiling
;
1433 case RADEON_SURF_MODE_2D
:
1434 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1435 non_disp_tiling
= rtex
->non_disp_tiling
;
1437 case RADEON_SURF_MODE_LINEAR
:
1439 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1440 non_disp_tiling
= 1;
1443 tile_split
= rtex
->surface
.tile_split
;
1444 macro_aspect
= rtex
->surface
.mtilea
;
1445 bankw
= rtex
->surface
.bankw
;
1446 bankh
= rtex
->surface
.bankh
;
1447 fmask_bankh
= rtex
->fmask_bank_height
;
1448 tile_split
= eg_tile_split(tile_split
);
1449 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1450 bankw
= eg_bank_wh(bankw
);
1451 bankh
= eg_bank_wh(bankh
);
1452 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1454 /* 128 bit formats require tile type = 1 */
1455 if (rscreen
->b
.chip_class
== CAYMAN
) {
1456 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1457 non_disp_tiling
= 1;
1459 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1460 desc
= util_format_description(surf
->base
.format
);
1461 for (i
= 0; i
< 4; i
++) {
1462 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1467 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1468 S_028C74_NUM_BANKS(nbanks
) |
1469 S_028C74_BANK_WIDTH(bankw
) |
1470 S_028C74_BANK_HEIGHT(bankh
) |
1471 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1472 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1473 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1475 if (rctx
->b
.chip_class
== CAYMAN
) {
1476 color_attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1477 UTIL_FORMAT_SWIZZLE_1
);
1479 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1480 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1481 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1482 S_028C74_NUM_FRAGMENTS(log_samples
);
1486 ntype
= V_028C70_NUMBER_UNORM
;
1487 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1488 ntype
= V_028C70_NUMBER_SRGB
;
1489 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1490 if (desc
->channel
[i
].normalized
)
1491 ntype
= V_028C70_NUMBER_SNORM
;
1492 else if (desc
->channel
[i
].pure_integer
)
1493 ntype
= V_028C70_NUMBER_SINT
;
1494 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1495 if (desc
->channel
[i
].normalized
)
1496 ntype
= V_028C70_NUMBER_UNORM
;
1497 else if (desc
->channel
[i
].pure_integer
)
1498 ntype
= V_028C70_NUMBER_UINT
;
1501 format
= r600_translate_colorformat(surf
->base
.format
);
1502 assert(format
!= ~0);
1504 swap
= r600_translate_colorswap(surf
->base
.format
);
1507 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1508 endian
= ENDIAN_NONE
;
1510 endian
= r600_colorformat_endian_swap(format
);
1513 /* blend clamp should be set for all NORM/SRGB types */
1514 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1515 ntype
== V_028C70_NUMBER_SRGB
)
1518 /* set blend bypass according to docs if SINT/UINT or
1519 8/24 COLOR variants */
1520 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1521 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1522 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1527 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1529 color_info
|= S_028C70_FORMAT(format
) |
1530 S_028C70_COMP_SWAP(swap
) |
1531 S_028C70_BLEND_CLAMP(blend_clamp
) |
1532 S_028C70_BLEND_BYPASS(blend_bypass
) |
1533 S_028C70_NUMBER_TYPE(ntype
) |
1534 S_028C70_ENDIAN(endian
);
1537 color_info
|= S_028C70_RAT(1);
1538 color_dim
= S_028C78_WIDTH_MAX(pipe_tex
->width0
& 0xffff)
1539 | S_028C78_HEIGHT_MAX((pipe_tex
->width0
>> 16) & 0xffff);
1542 /* EXPORT_NORM is an optimzation that can be enabled for better
1543 * performance in certain cases.
1544 * EXPORT_NORM can be enabled if:
1545 * - 11-bit or smaller UNORM/SNORM/SRGB
1546 * - 16-bit or smaller FLOAT
1548 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1549 ((desc
->channel
[i
].size
< 12 &&
1550 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1551 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1552 (desc
->channel
[i
].size
< 17 &&
1553 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1554 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1555 surf
->export_16bpc
= true;
1558 if (rtex
->fmask_size
) {
1559 color_info
|= S_028C70_COMPRESSION(1);
1561 if (rtex
->cmask_size
) {
1562 color_info
|= S_028C70_FAST_CLEAR(1);
1565 base_offset
= r600_resource_va(rctx
->b
.b
.screen
, pipe_tex
);
1567 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1568 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1569 surf
->cb_color_dim
= color_dim
;
1570 surf
->cb_color_info
= color_info
;
1571 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1572 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1573 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1574 surf
->cb_color_view
= 0;
1576 surf
->cb_color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1577 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1579 surf
->cb_color_attrib
= color_attrib
;
1580 if (rtex
->fmask_size
) {
1581 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask_offset
) >> 8;
1583 surf
->cb_color_fmask
= surf
->cb_color_base
;
1585 if (rtex
->cmask_size
) {
1586 uint64_t va
= r600_resource_va(rctx
->b
.b
.screen
, &rtex
->cmask
->b
.b
);
1587 surf
->cb_color_cmask
= (va
+ rtex
->cmask_offset
) >> 8;
1589 surf
->cb_color_cmask
= surf
->cb_color_base
;
1591 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask_slice_tile_max
);
1592 surf
->cb_color_cmask_slice
= S_028C80_TILE_MAX(rtex
->cmask_slice_tile_max
);
1594 surf
->color_initialized
= true;
1597 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1598 struct r600_surface
*surf
)
1600 struct r600_screen
*rscreen
= rctx
->screen
;
1601 struct pipe_screen
*screen
= &rscreen
->b
.b
;
1602 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1604 unsigned level
, pitch
, slice
, format
, array_mode
;
1605 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1607 level
= surf
->base
.u
.tex
.level
;
1608 format
= r600_translate_dbformat(surf
->base
.format
);
1609 assert(format
!= ~0);
1611 offset
= r600_resource_va(screen
, surf
->base
.texture
);
1612 offset
+= rtex
->surface
.level
[level
].offset
;
1613 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1614 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1618 switch (rtex
->surface
.level
[level
].mode
) {
1619 case RADEON_SURF_MODE_2D
:
1620 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1622 case RADEON_SURF_MODE_1D
:
1623 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1624 case RADEON_SURF_MODE_LINEAR
:
1626 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1629 tile_split
= rtex
->surface
.tile_split
;
1630 macro_aspect
= rtex
->surface
.mtilea
;
1631 bankw
= rtex
->surface
.bankw
;
1632 bankh
= rtex
->surface
.bankh
;
1633 tile_split
= eg_tile_split(tile_split
);
1634 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1635 bankw
= eg_bank_wh(bankw
);
1636 bankh
= eg_bank_wh(bankh
);
1637 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1640 surf
->db_depth_info
= S_028040_ARRAY_MODE(array_mode
) |
1641 S_028040_FORMAT(format
) |
1642 S_028040_TILE_SPLIT(tile_split
)|
1643 S_028040_NUM_BANKS(nbanks
) |
1644 S_028040_BANK_WIDTH(bankw
) |
1645 S_028040_BANK_HEIGHT(bankh
) |
1646 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1647 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1648 surf
->db_depth_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1650 surf
->db_depth_base
= offset
;
1651 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1652 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1653 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1654 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1656 switch (surf
->base
.format
) {
1657 case PIPE_FORMAT_Z24X8_UNORM
:
1658 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1659 case PIPE_FORMAT_X8Z24_UNORM
:
1660 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1661 surf
->pa_su_poly_offset_db_fmt_cntl
=
1662 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1664 case PIPE_FORMAT_Z32_FLOAT
:
1665 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1666 surf
->pa_su_poly_offset_db_fmt_cntl
=
1667 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1668 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1670 case PIPE_FORMAT_Z16_UNORM
:
1671 surf
->pa_su_poly_offset_db_fmt_cntl
=
1672 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1677 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1678 uint64_t stencil_offset
;
1679 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1681 stile_split
= eg_tile_split(stile_split
);
1683 stencil_offset
= rtex
->surface
.stencil_level
[level
].offset
;
1684 stencil_offset
+= r600_resource_va(screen
, surf
->base
.texture
);
1686 surf
->db_stencil_base
= stencil_offset
>> 8;
1687 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1688 S_028044_TILE_SPLIT(stile_split
);
1690 surf
->db_stencil_base
= offset
;
1691 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1692 * Older kernels are out of luck. */
1693 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1694 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1695 S_028044_FORMAT(V_028044_STENCIL_8
);
1698 surf
->htile_enabled
= 0;
1699 /* use htile only for first level */
1700 if (rtex
->htile
&& !level
) {
1701 uint64_t va
= r600_resource_va(&rctx
->screen
->b
.b
, &rtex
->htile
->b
.b
);
1702 surf
->htile_enabled
= 1;
1703 surf
->db_htile_data_base
= va
>> 8;
1704 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1705 S_028ABC_HTILE_HEIGHT(1) |
1706 S_028ABC_FULL_CACHE(1) |
1708 surf
->db_depth_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1709 surf
->db_preload_control
= 0;
1712 surf
->depth_initialized
= true;
1715 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1716 const struct pipe_framebuffer_state
*state
)
1718 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1719 struct r600_surface
*surf
;
1720 struct r600_texture
*rtex
;
1721 uint32_t i
, log_samples
;
1723 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1724 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1725 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
;
1727 if (rctx
->framebuffer
.state
.cbufs
[0]->texture
->nr_samples
> 1) {
1728 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1731 if (rctx
->framebuffer
.state
.zsbuf
) {
1732 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1733 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
1735 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1737 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1741 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1744 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1745 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1746 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1747 rctx
->framebuffer
.compressed_cb_mask
= 0;
1749 if (state
->nr_cbufs
)
1750 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1751 else if (state
->zsbuf
)
1752 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1754 rctx
->framebuffer
.nr_samples
= 0;
1756 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1757 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1758 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1760 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1762 if (!surf
->color_initialized
) {
1763 evergreen_init_color_surface(rctx
, surf
);
1766 if (!surf
->export_16bpc
) {
1767 rctx
->framebuffer
.export_16bpc
= false;
1770 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1771 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1775 /* Update alpha-test state dependencies.
1776 * Alpha-test is done on the first colorbuffer only. */
1777 if (state
->nr_cbufs
) {
1778 surf
= (struct r600_surface
*)state
->cbufs
[0];
1779 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1780 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1781 rctx
->alphatest_state
.atom
.dirty
= true;
1783 if (rctx
->alphatest_state
.cb0_export_16bpc
!= surf
->export_16bpc
) {
1784 rctx
->alphatest_state
.cb0_export_16bpc
= surf
->export_16bpc
;
1785 rctx
->alphatest_state
.atom
.dirty
= true;
1791 surf
= (struct r600_surface
*)state
->zsbuf
;
1793 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1795 if (!surf
->depth_initialized
) {
1796 evergreen_init_depth_surface(rctx
, surf
);
1799 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1800 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1801 rctx
->poly_offset_state
.atom
.dirty
= true;
1804 if (rctx
->db_state
.rsurf
!= surf
) {
1805 rctx
->db_state
.rsurf
= surf
;
1806 rctx
->db_state
.atom
.dirty
= true;
1807 rctx
->db_misc_state
.atom
.dirty
= true;
1809 } else if (rctx
->db_state
.rsurf
) {
1810 rctx
->db_state
.rsurf
= NULL
;
1811 rctx
->db_state
.atom
.dirty
= true;
1812 rctx
->db_misc_state
.atom
.dirty
= true;
1815 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1816 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1817 rctx
->cb_misc_state
.atom
.dirty
= true;
1820 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1821 rctx
->alphatest_state
.bypass
= false;
1822 rctx
->alphatest_state
.atom
.dirty
= true;
1825 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1826 if (rctx
->b
.chip_class
== CAYMAN
&& rctx
->db_misc_state
.log_samples
!= log_samples
) {
1827 rctx
->db_misc_state
.log_samples
= log_samples
;
1828 rctx
->db_misc_state
.atom
.dirty
= true;
1831 evergreen_update_db_shader_control(rctx
);
1833 /* Calculate the CS size. */
1834 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1837 if (rctx
->b
.chip_class
== EVERGREEN
) {
1838 switch (rctx
->framebuffer
.nr_samples
) {
1841 rctx
->framebuffer
.atom
.num_dw
+= 6;
1844 rctx
->framebuffer
.atom
.num_dw
+= 10;
1847 rctx
->framebuffer
.atom
.num_dw
+= 4;
1849 switch (rctx
->framebuffer
.nr_samples
) {
1852 rctx
->framebuffer
.atom
.num_dw
+= 12;
1855 rctx
->framebuffer
.atom
.num_dw
+= 16;
1858 rctx
->framebuffer
.atom
.num_dw
+= 18;
1861 rctx
->framebuffer
.atom
.num_dw
+= 7;
1865 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1866 if (rctx
->keep_tiling_flags
)
1867 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1868 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1872 rctx
->framebuffer
.atom
.num_dw
+= 24;
1873 if (rctx
->keep_tiling_flags
)
1874 rctx
->framebuffer
.atom
.num_dw
+= 2;
1875 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1876 rctx
->framebuffer
.atom
.num_dw
+= 4;
1879 rctx
->framebuffer
.atom
.dirty
= true;
1882 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1883 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1884 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1885 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1886 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1889 * There are two locations (-4, 4), (4, -4). */
1890 static uint32_t sample_locs_2x
[] = {
1891 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1892 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1893 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1894 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1896 static unsigned max_dist_2x
= 4;
1898 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1899 static uint32_t sample_locs_4x
[] = {
1900 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1901 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1902 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1903 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1905 static unsigned max_dist_4x
= 6;
1907 static uint32_t sample_locs_8x
[] = {
1908 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1909 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1910 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1911 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1912 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1913 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1914 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1915 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1917 static unsigned max_dist_8x
= 7;
1919 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1920 unsigned sample_count
,
1921 unsigned sample_index
,
1928 switch (sample_count
) {
1931 out_value
[0] = out_value
[1] = 0.5;
1934 offset
= 4 * (sample_index
* 2);
1935 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1936 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1937 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1938 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1941 offset
= 4 * (sample_index
* 2);
1942 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1943 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1944 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1945 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1948 offset
= 4 * (sample_index
% 4 * 2);
1949 index
= (sample_index
/ 4);
1950 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1951 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1952 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1953 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1958 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1961 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1962 unsigned max_dist
= 0;
1964 switch (nr_samples
) {
1969 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_2x
));
1970 radeon_emit_array(cs
, sample_locs_2x
, Elements(sample_locs_2x
));
1971 max_dist
= max_dist_2x
;
1974 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_4x
));
1975 radeon_emit_array(cs
, sample_locs_4x
, Elements(sample_locs_4x
));
1976 max_dist
= max_dist_4x
;
1979 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, Elements(sample_locs_8x
));
1980 radeon_emit_array(cs
, sample_locs_8x
, Elements(sample_locs_8x
));
1981 max_dist
= max_dist_8x
;
1985 if (nr_samples
> 1) {
1986 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1987 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1988 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1989 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1990 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1992 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1993 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1994 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1999 static uint32_t cm_sample_locs_8x
[] = {
2000 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2001 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2002 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2003 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2004 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2005 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2006 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2007 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2009 static unsigned cm_max_dist_8x
= 8;
2010 /* Cayman 16xMSAA */
2011 static uint32_t cm_sample_locs_16x
[] = {
2012 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2013 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2014 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2015 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2016 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2017 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2018 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2019 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2020 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2021 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2022 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2023 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2024 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2025 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2026 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2027 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2029 static unsigned cm_max_dist_16x
= 8;
2030 static void cayman_get_sample_position(struct pipe_context
*ctx
,
2031 unsigned sample_count
,
2032 unsigned sample_index
,
2039 switch (sample_count
) {
2042 out_value
[0] = out_value
[1] = 0.5;
2045 offset
= 4 * (sample_index
* 2);
2046 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
2047 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
2048 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
2049 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
2052 offset
= 4 * (sample_index
* 2);
2053 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
2054 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
2055 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
2056 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
2059 offset
= 4 * (sample_index
% 4 * 2);
2060 index
= (sample_index
/ 4) * 4;
2061 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
2062 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
2063 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
2064 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
2067 offset
= 4 * (sample_index
% 4 * 2);
2068 index
= (sample_index
/ 4) * 4;
2069 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
2070 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
2071 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
2072 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
2077 static void cayman_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
2081 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2082 unsigned max_dist
= 0;
2084 switch (nr_samples
) {
2089 r600_write_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
[0]);
2090 r600_write_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
[1]);
2091 r600_write_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
[2]);
2092 r600_write_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
[3]);
2093 max_dist
= max_dist_2x
;
2096 r600_write_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
[0]);
2097 r600_write_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
[1]);
2098 r600_write_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
[2]);
2099 r600_write_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
[3]);
2100 max_dist
= max_dist_4x
;
2103 r600_write_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
2104 radeon_emit(cs
, cm_sample_locs_8x
[0]);
2105 radeon_emit(cs
, cm_sample_locs_8x
[4]);
2108 radeon_emit(cs
, cm_sample_locs_8x
[1]);
2109 radeon_emit(cs
, cm_sample_locs_8x
[5]);
2112 radeon_emit(cs
, cm_sample_locs_8x
[2]);
2113 radeon_emit(cs
, cm_sample_locs_8x
[6]);
2116 radeon_emit(cs
, cm_sample_locs_8x
[3]);
2117 radeon_emit(cs
, cm_sample_locs_8x
[7]);
2118 max_dist
= cm_max_dist_8x
;
2121 r600_write_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
2122 radeon_emit(cs
, cm_sample_locs_16x
[0]);
2123 radeon_emit(cs
, cm_sample_locs_16x
[4]);
2124 radeon_emit(cs
, cm_sample_locs_16x
[8]);
2125 radeon_emit(cs
, cm_sample_locs_16x
[12]);
2126 radeon_emit(cs
, cm_sample_locs_16x
[1]);
2127 radeon_emit(cs
, cm_sample_locs_16x
[5]);
2128 radeon_emit(cs
, cm_sample_locs_16x
[9]);
2129 radeon_emit(cs
, cm_sample_locs_16x
[13]);
2130 radeon_emit(cs
, cm_sample_locs_16x
[2]);
2131 radeon_emit(cs
, cm_sample_locs_16x
[6]);
2132 radeon_emit(cs
, cm_sample_locs_16x
[10]);
2133 radeon_emit(cs
, cm_sample_locs_16x
[14]);
2134 radeon_emit(cs
, cm_sample_locs_16x
[3]);
2135 radeon_emit(cs
, cm_sample_locs_16x
[7]);
2136 radeon_emit(cs
, cm_sample_locs_16x
[11]);
2137 radeon_emit(cs
, cm_sample_locs_16x
[15]);
2138 max_dist
= cm_max_dist_16x
;
2142 if (nr_samples
> 1) {
2143 unsigned log_samples
= util_logbase2(nr_samples
);
2145 r600_write_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
2146 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
2147 S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2148 radeon_emit(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
2149 S_028BE0_MAX_SAMPLE_DIST(max_dist
) |
2150 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2152 r600_write_context_reg(cs
, CM_R_028804_DB_EQAA
,
2153 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
2154 S_028804_PS_ITER_SAMPLES(log_samples
) |
2155 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
2156 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
2157 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2158 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2160 r600_write_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
2161 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2162 radeon_emit(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2164 r600_write_context_reg(cs
, CM_R_028804_DB_EQAA
,
2165 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2166 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2170 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2172 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2173 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
2174 unsigned nr_cbufs
= state
->nr_cbufs
;
2177 /* XXX support more colorbuffers once we need them */
2178 assert(nr_cbufs
<= 8);
2183 for (i
= 0; i
< nr_cbufs
; i
++) {
2184 struct r600_surface
*cb
= (struct r600_surface
*)state
->cbufs
[i
];
2185 struct r600_texture
*tex
= (struct r600_texture
*)cb
->base
.texture
;
2186 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
2188 (struct r600_resource
*)cb
->base
.texture
,
2189 RADEON_USAGE_READWRITE
);
2190 unsigned cmask_reloc
= 0;
2191 if (tex
->cmask
&& tex
->cmask
!= &tex
->resource
) {
2192 cmask_reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
2193 tex
->cmask
, RADEON_USAGE_READWRITE
);
2195 cmask_reloc
= reloc
;
2198 r600_write_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
2199 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2200 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2201 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2202 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2203 radeon_emit(cs
, cb
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2204 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2205 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
2206 radeon_emit(cs
, cb
->cb_color_cmask
); /* R_028C7C_CB_COLOR0_CMASK */
2207 radeon_emit(cs
, cb
->cb_color_cmask_slice
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2208 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2209 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2210 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2211 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2213 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
2214 radeon_emit(cs
, reloc
);
2216 if (!rctx
->keep_tiling_flags
) {
2217 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2218 radeon_emit(cs
, reloc
);
2221 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
2222 radeon_emit(cs
, reloc
);
2224 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
2225 radeon_emit(cs
, cmask_reloc
);
2227 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
2228 radeon_emit(cs
, reloc
);
2230 /* set CB_COLOR1_INFO for possible dual-src blending */
2231 if (i
== 1 && !((struct r600_texture
*)state
->cbufs
[0]->texture
)->is_rat
) {
2232 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
2233 ((struct r600_surface
*)state
->cbufs
[0])->cb_color_info
);
2235 if (!rctx
->keep_tiling_flags
) {
2236 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
2238 (struct r600_resource
*)state
->cbufs
[0]->texture
,
2239 RADEON_USAGE_READWRITE
);
2241 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
2242 radeon_emit(cs
, reloc
);
2246 if (rctx
->keep_tiling_flags
) {
2247 for (; i
< 8 ; i
++) {
2248 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2250 for (; i
< 12; i
++) {
2251 r600_write_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
2257 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2258 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
2260 (struct r600_resource
*)state
->zsbuf
->texture
,
2261 RADEON_USAGE_READWRITE
);
2263 r600_write_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2264 zb
->pa_su_poly_offset_db_fmt_cntl
);
2265 r600_write_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2267 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
2268 radeon_emit(cs
, zb
->db_depth_info
); /* R_028040_DB_Z_INFO */
2269 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2270 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2271 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2272 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2273 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2274 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2275 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2277 if (!rctx
->keep_tiling_flags
) {
2278 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028040_DB_Z_INFO */
2279 radeon_emit(cs
, reloc
);
2282 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
2283 radeon_emit(cs
, reloc
);
2285 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
2286 radeon_emit(cs
, reloc
);
2288 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
2289 radeon_emit(cs
, reloc
);
2291 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
2292 radeon_emit(cs
, reloc
);
2293 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
2294 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
2295 * Older kernels are out of luck. */
2296 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2297 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2298 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2301 /* Framebuffer dimensions. */
2302 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
2304 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
2305 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
2306 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
2308 if (rctx
->b
.chip_class
== EVERGREEN
) {
2309 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
2311 cayman_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
2315 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
2317 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2318 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
2319 float offset_units
= state
->offset_units
;
2320 float offset_scale
= state
->offset_scale
;
2322 switch (state
->zs_format
) {
2323 case PIPE_FORMAT_Z24X8_UNORM
:
2324 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2325 case PIPE_FORMAT_X8Z24_UNORM
:
2326 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2327 offset_units
*= 2.0f
;
2329 case PIPE_FORMAT_Z16_UNORM
:
2330 offset_units
*= 4.0f
;
2335 r600_write_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
2336 radeon_emit(cs
, fui(offset_scale
));
2337 radeon_emit(cs
, fui(offset_units
));
2338 radeon_emit(cs
, fui(offset_scale
));
2339 radeon_emit(cs
, fui(offset_units
));
2342 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2344 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2345 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
2346 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
2347 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
2349 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
2350 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
2351 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
2352 * will assure that the alpha-test will work even if there is
2353 * no colorbuffer bound. */
2354 radeon_emit(cs
, 0xf | (a
->dual_src_blend
? ps_colormask
: 0) | fb_colormask
); /* R_02823C_CB_SHADER_MASK */
2357 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2359 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2360 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
2362 if (a
->rsurf
&& a
->rsurf
->htile_enabled
) {
2363 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
2366 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear
));
2367 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
2368 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
2369 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
2370 reloc_idx
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rtex
->htile
, RADEON_USAGE_READWRITE
);
2371 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
2372 cs
->buf
[cs
->cdw
++] = reloc_idx
;
2374 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
2375 r600_write_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
2379 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2381 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2382 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
2383 unsigned db_render_control
= 0;
2384 unsigned db_count_control
= 0;
2385 unsigned db_render_override
=
2386 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2387 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2389 if (a
->occlusion_query_enabled
) {
2390 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
2391 if (rctx
->b
.chip_class
== CAYMAN
) {
2392 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
2394 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
2396 /* FIXME we should be able to use hyperz even if we are not writing to
2397 * zbuffer but somehow this trigger GPU lockup. See :
2399 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
2401 * Disable hyperz for now if not writing to zbuffer.
2403 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->htile_enabled
&& rctx
->zwritemask
) {
2404 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2405 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF
);
2406 /* This is to fix a lockup when hyperz and alpha test are enabled at
2407 * the same time somehow GPU get confuse on which order to pick for
2410 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
2411 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
2414 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
);
2416 if (a
->flush_depthstencil_through_cb
) {
2417 assert(a
->copy_depth
|| a
->copy_stencil
);
2419 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
2420 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
2421 S_028000_COPY_CENTROID(1) |
2422 S_028000_COPY_SAMPLE(a
->copy_sample
);
2423 } else if (a
->flush_depthstencil_in_place
) {
2424 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(1) |
2425 S_028000_STENCIL_COMPRESS_DISABLE(1);
2426 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2428 if (a
->htile_clear
) {
2429 /* FIXME we might want to disable cliprect here */
2430 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
2433 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
2434 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
2435 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
2436 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2437 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
2440 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
2441 struct r600_vertexbuf_state
*state
,
2442 unsigned resource_offset
,
2445 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2446 uint32_t dirty_mask
= state
->dirty_mask
;
2448 while (dirty_mask
) {
2449 struct pipe_vertex_buffer
*vb
;
2450 struct r600_resource
*rbuffer
;
2452 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
2454 vb
= &state
->vb
[buffer_index
];
2455 rbuffer
= (struct r600_resource
*)vb
->buffer
;
2458 va
= r600_resource_va(&rctx
->screen
->b
.b
, &rbuffer
->b
.b
);
2459 va
+= vb
->buffer_offset
;
2461 /* fetch resources start at index 992 */
2462 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2463 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
2464 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
2465 radeon_emit(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2466 radeon_emit(cs
, /* RESOURCEi_WORD2 */
2467 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2468 S_030008_STRIDE(vb
->stride
) |
2469 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2470 radeon_emit(cs
, /* RESOURCEi_WORD3 */
2471 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2472 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2473 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2474 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2475 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
2476 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
2477 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
2478 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2480 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2481 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2483 state
->dirty_mask
= 0;
2486 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2488 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
2491 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
2493 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
2494 RADEON_CP_PACKET3_COMPUTE_MODE
);
2497 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
2498 struct r600_constbuf_state
*state
,
2499 unsigned buffer_id_base
,
2500 unsigned reg_alu_constbuf_size
,
2501 unsigned reg_alu_const_cache
,
2504 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2505 uint32_t dirty_mask
= state
->dirty_mask
;
2507 while (dirty_mask
) {
2508 struct pipe_constant_buffer
*cb
;
2509 struct r600_resource
*rbuffer
;
2511 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2513 cb
= &state
->cb
[buffer_index
];
2514 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2517 va
= r600_resource_va(&rctx
->screen
->b
.b
, &rbuffer
->b
.b
);
2518 va
+= cb
->buffer_offset
;
2520 r600_write_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2521 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16), pkt_flags
);
2522 r600_write_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
2525 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2526 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2528 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
2529 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
2530 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
2531 radeon_emit(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2532 radeon_emit(cs
, /* RESOURCEi_WORD2 */
2533 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2534 S_030008_STRIDE(16) |
2535 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2536 radeon_emit(cs
, /* RESOURCEi_WORD3 */
2537 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2538 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2539 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2540 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2541 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
2542 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
2543 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
2544 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2546 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2547 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2549 dirty_mask
&= ~(1 << buffer_index
);
2551 state
->dirty_mask
= 0;
2554 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2556 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 176,
2557 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2558 R_028980_ALU_CONST_CACHE_VS_0
,
2559 0 /* PKT3 flags */);
2562 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2564 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
2565 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2566 R_0289C0_ALU_CONST_CACHE_GS_0
,
2567 0 /* PKT3 flags */);
2570 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2572 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
2573 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2574 R_028940_ALU_CONST_CACHE_PS_0
,
2575 0 /* PKT3 flags */);
2578 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2580 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
], 816,
2581 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
2582 R_028F40_ALU_CONST_CACHE_LS_0
,
2583 RADEON_CP_PACKET3_COMPUTE_MODE
);
2586 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
2587 struct r600_samplerview_state
*state
,
2588 unsigned resource_id_base
)
2590 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2591 uint32_t dirty_mask
= state
->dirty_mask
;
2593 while (dirty_mask
) {
2594 struct r600_pipe_sampler_view
*rview
;
2595 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2598 rview
= state
->views
[resource_index
];
2601 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
2602 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
2603 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
2605 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rview
->tex_resource
,
2607 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2608 radeon_emit(cs
, reloc
);
2610 if (!rview
->skip_mip_address_reloc
) {
2611 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2612 radeon_emit(cs
, reloc
);
2615 state
->dirty_mask
= 0;
2618 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2620 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 176 + R600_MAX_CONST_BUFFERS
);
2623 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2625 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2628 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2630 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2633 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2634 struct r600_textures_info
*texinfo
,
2635 unsigned resource_id_base
,
2636 unsigned border_index_reg
)
2638 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2639 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2641 while (dirty_mask
) {
2642 struct r600_pipe_sampler_state
*rstate
;
2643 unsigned i
= u_bit_scan(&dirty_mask
);
2645 rstate
= texinfo
->states
.states
[i
];
2648 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2649 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2650 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2652 if (rstate
->border_color_use
) {
2653 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2655 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2658 texinfo
->states
.dirty_mask
= 0;
2661 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2663 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
);
2666 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2668 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
);
2671 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2673 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
);
2676 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2678 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2679 uint8_t mask
= s
->sample_mask
;
2681 r600_write_context_reg(rctx
->b
.rings
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2682 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2685 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2687 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2688 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2689 uint16_t mask
= s
->sample_mask
;
2691 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2692 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2693 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2696 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2698 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2699 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2700 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2702 r600_write_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2703 (r600_resource_va(rctx
->b
.b
.screen
, &shader
->buffer
->b
.b
) + shader
->offset
) >> 8);
2704 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2705 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->buffer
, RADEON_USAGE_READ
));
2708 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2709 enum chip_class ctx_chip_class
,
2710 enum radeon_family ctx_family
,
2713 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2714 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2715 /* always set the temp clauses */
2716 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2718 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2719 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2720 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2722 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2724 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2726 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2728 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2731 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2733 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2735 r600_init_command_buffer(cb
, 256);
2737 /* This must be first. */
2738 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2739 r600_store_value(cb
, 0x80000000);
2740 r600_store_value(cb
, 0x80000000);
2742 /* We're setting config registers here. */
2743 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2744 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2746 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2747 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2749 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2750 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2752 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2753 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2754 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2755 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2756 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2757 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2758 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2760 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2761 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2762 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2763 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2764 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2766 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2767 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2768 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2769 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2770 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2771 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2772 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2773 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2774 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2775 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2776 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2777 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2778 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2779 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2781 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2782 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2783 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2785 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2786 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2787 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2789 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2791 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2793 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2794 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2795 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2797 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2798 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2799 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2801 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2803 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2804 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2805 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2807 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2809 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2811 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2813 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2814 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2815 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2816 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2818 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2819 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2821 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2822 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2823 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2825 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2826 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2827 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2829 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2830 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2831 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2832 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2833 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2835 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2836 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2837 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2839 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2840 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2841 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2843 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2844 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2845 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2847 /* to avoid GPU doing any preloading of constant from random address */
2848 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2849 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2850 r600_store_value(cb
, 0);
2851 r600_store_value(cb
, 0);
2852 r600_store_value(cb
, 0);
2853 r600_store_value(cb
, 0);
2854 r600_store_value(cb
, 0);
2855 r600_store_value(cb
, 0);
2856 r600_store_value(cb
, 0);
2857 r600_store_value(cb
, 0);
2858 r600_store_value(cb
, 0);
2859 r600_store_value(cb
, 0);
2860 r600_store_value(cb
, 0);
2861 r600_store_value(cb
, 0);
2862 r600_store_value(cb
, 0);
2863 r600_store_value(cb
, 0);
2864 r600_store_value(cb
, 0);
2866 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2867 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2868 r600_store_value(cb
, 0);
2869 r600_store_value(cb
, 0);
2870 r600_store_value(cb
, 0);
2871 r600_store_value(cb
, 0);
2872 r600_store_value(cb
, 0);
2873 r600_store_value(cb
, 0);
2874 r600_store_value(cb
, 0);
2875 r600_store_value(cb
, 0);
2876 r600_store_value(cb
, 0);
2877 r600_store_value(cb
, 0);
2878 r600_store_value(cb
, 0);
2879 r600_store_value(cb
, 0);
2880 r600_store_value(cb
, 0);
2881 r600_store_value(cb
, 0);
2882 r600_store_value(cb
, 0);
2884 if (rctx
->screen
->has_streamout
) {
2885 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2888 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2889 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2890 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2891 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2892 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2893 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2894 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2896 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2897 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2900 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
2901 enum chip_class ctx_chip_class
,
2902 enum radeon_family ctx_family
,
2941 switch (ctx_family
) {
2949 tmp
|= S_008C00_VC_ENABLE(1);
2952 tmp
|= S_008C00_EXPORT_SRC_C(1);
2953 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2954 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2955 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2956 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2957 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2958 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2959 tmp
|= S_008C00_ES_PRIO(es_prio
);
2961 /* enable dynamic GPR resource management */
2962 if (ctx_drm_minor
>= 7) {
2963 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2964 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2965 /* always set temp clauses */
2966 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2967 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2968 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2969 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2970 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2971 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2972 S_028838_PS_GPRS(0x1e) |
2973 S_028838_VS_GPRS(0x1e) |
2974 S_028838_GS_GPRS(0x1e) |
2975 S_028838_ES_GPRS(0x1e) |
2976 S_028838_HS_GPRS(0x1e) |
2977 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2979 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2980 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2982 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2983 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2984 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2985 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2987 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2988 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2989 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2991 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2992 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2993 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2996 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2998 /* The cs checker requires this register to be set. */
2999 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
3001 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
3006 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
3008 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
3016 int num_ps_stack_entries
;
3017 int num_vs_stack_entries
;
3018 int num_gs_stack_entries
;
3019 int num_es_stack_entries
;
3020 int num_hs_stack_entries
;
3021 int num_ls_stack_entries
;
3022 enum radeon_family family
;
3025 if (rctx
->b
.chip_class
== CAYMAN
) {
3026 cayman_init_atom_start_cs(rctx
);
3030 r600_init_command_buffer(cb
, 256);
3032 /* This must be first. */
3033 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
3034 r600_store_value(cb
, 0x80000000);
3035 r600_store_value(cb
, 0x80000000);
3037 /* We're setting config registers here. */
3038 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3039 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3041 evergreen_init_common_regs(cb
, rctx
->b
.chip_class
,
3042 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
3044 family
= rctx
->b
.family
;
3048 num_ps_threads
= 96;
3049 num_vs_threads
= 16;
3050 num_gs_threads
= 16;
3051 num_es_threads
= 16;
3052 num_hs_threads
= 16;
3053 num_ls_threads
= 16;
3054 num_ps_stack_entries
= 42;
3055 num_vs_stack_entries
= 42;
3056 num_gs_stack_entries
= 42;
3057 num_es_stack_entries
= 42;
3058 num_hs_stack_entries
= 42;
3059 num_ls_stack_entries
= 42;
3062 num_ps_threads
= 128;
3063 num_vs_threads
= 20;
3064 num_gs_threads
= 20;
3065 num_es_threads
= 20;
3066 num_hs_threads
= 20;
3067 num_ls_threads
= 20;
3068 num_ps_stack_entries
= 42;
3069 num_vs_stack_entries
= 42;
3070 num_gs_stack_entries
= 42;
3071 num_es_stack_entries
= 42;
3072 num_hs_stack_entries
= 42;
3073 num_ls_stack_entries
= 42;
3076 num_ps_threads
= 128;
3077 num_vs_threads
= 20;
3078 num_gs_threads
= 20;
3079 num_es_threads
= 20;
3080 num_hs_threads
= 20;
3081 num_ls_threads
= 20;
3082 num_ps_stack_entries
= 85;
3083 num_vs_stack_entries
= 85;
3084 num_gs_stack_entries
= 85;
3085 num_es_stack_entries
= 85;
3086 num_hs_stack_entries
= 85;
3087 num_ls_stack_entries
= 85;
3091 num_ps_threads
= 128;
3092 num_vs_threads
= 20;
3093 num_gs_threads
= 20;
3094 num_es_threads
= 20;
3095 num_hs_threads
= 20;
3096 num_ls_threads
= 20;
3097 num_ps_stack_entries
= 85;
3098 num_vs_stack_entries
= 85;
3099 num_gs_stack_entries
= 85;
3100 num_es_stack_entries
= 85;
3101 num_hs_stack_entries
= 85;
3102 num_ls_stack_entries
= 85;
3105 num_ps_threads
= 96;
3106 num_vs_threads
= 16;
3107 num_gs_threads
= 16;
3108 num_es_threads
= 16;
3109 num_hs_threads
= 16;
3110 num_ls_threads
= 16;
3111 num_ps_stack_entries
= 42;
3112 num_vs_stack_entries
= 42;
3113 num_gs_stack_entries
= 42;
3114 num_es_stack_entries
= 42;
3115 num_hs_stack_entries
= 42;
3116 num_ls_stack_entries
= 42;
3119 num_ps_threads
= 96;
3120 num_vs_threads
= 25;
3121 num_gs_threads
= 25;
3122 num_es_threads
= 25;
3123 num_hs_threads
= 25;
3124 num_ls_threads
= 25;
3125 num_ps_stack_entries
= 42;
3126 num_vs_stack_entries
= 42;
3127 num_gs_stack_entries
= 42;
3128 num_es_stack_entries
= 42;
3129 num_hs_stack_entries
= 42;
3130 num_ls_stack_entries
= 42;
3133 num_ps_threads
= 96;
3134 num_vs_threads
= 25;
3135 num_gs_threads
= 25;
3136 num_es_threads
= 25;
3137 num_hs_threads
= 25;
3138 num_ls_threads
= 25;
3139 num_ps_stack_entries
= 85;
3140 num_vs_stack_entries
= 85;
3141 num_gs_stack_entries
= 85;
3142 num_es_stack_entries
= 85;
3143 num_hs_stack_entries
= 85;
3144 num_ls_stack_entries
= 85;
3147 num_ps_threads
= 128;
3148 num_vs_threads
= 20;
3149 num_gs_threads
= 20;
3150 num_es_threads
= 20;
3151 num_hs_threads
= 20;
3152 num_ls_threads
= 20;
3153 num_ps_stack_entries
= 85;
3154 num_vs_stack_entries
= 85;
3155 num_gs_stack_entries
= 85;
3156 num_es_stack_entries
= 85;
3157 num_hs_stack_entries
= 85;
3158 num_ls_stack_entries
= 85;
3161 num_ps_threads
= 128;
3162 num_vs_threads
= 20;
3163 num_gs_threads
= 20;
3164 num_es_threads
= 20;
3165 num_hs_threads
= 20;
3166 num_ls_threads
= 20;
3167 num_ps_stack_entries
= 42;
3168 num_vs_stack_entries
= 42;
3169 num_gs_stack_entries
= 42;
3170 num_es_stack_entries
= 42;
3171 num_hs_stack_entries
= 42;
3172 num_ls_stack_entries
= 42;
3175 num_ps_threads
= 128;
3176 num_vs_threads
= 10;
3177 num_gs_threads
= 10;
3178 num_es_threads
= 10;
3179 num_hs_threads
= 10;
3180 num_ls_threads
= 10;
3181 num_ps_stack_entries
= 42;
3182 num_vs_stack_entries
= 42;
3183 num_gs_stack_entries
= 42;
3184 num_es_stack_entries
= 42;
3185 num_hs_stack_entries
= 42;
3186 num_ls_stack_entries
= 42;
3190 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
3191 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
3192 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
3193 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
3195 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
3196 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3198 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
3199 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
3200 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3202 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
3203 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
3204 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3206 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
3207 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
3208 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3210 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
3211 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
3212 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3214 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
3215 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3217 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
3218 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
3220 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
3221 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3222 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3223 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3224 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3225 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3226 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3228 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3229 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3230 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3231 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3232 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3234 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
3235 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3236 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
3237 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3238 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3239 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3240 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3241 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3242 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
3243 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3244 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3245 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3246 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3247 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
3249 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
3250 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
3251 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
3253 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
3255 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
3257 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
3258 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3259 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
3261 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
3263 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
3265 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
3266 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3267 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3269 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
3270 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
3271 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
3273 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
3274 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
3275 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
3277 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
3278 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3279 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3280 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3282 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
3283 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
3284 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
3285 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
3286 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
3288 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
3289 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3290 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3292 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
3293 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3294 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3296 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3297 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
3298 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
3300 /* to avoid GPU doing any preloading of constant from random address */
3301 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
3302 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
3303 r600_store_value(cb
, 0);
3304 r600_store_value(cb
, 0);
3305 r600_store_value(cb
, 0);
3306 r600_store_value(cb
, 0);
3307 r600_store_value(cb
, 0);
3308 r600_store_value(cb
, 0);
3309 r600_store_value(cb
, 0);
3310 r600_store_value(cb
, 0);
3311 r600_store_value(cb
, 0);
3312 r600_store_value(cb
, 0);
3313 r600_store_value(cb
, 0);
3314 r600_store_value(cb
, 0);
3315 r600_store_value(cb
, 0);
3316 r600_store_value(cb
, 0);
3317 r600_store_value(cb
, 0);
3319 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
3320 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
3321 r600_store_value(cb
, 0);
3322 r600_store_value(cb
, 0);
3323 r600_store_value(cb
, 0);
3324 r600_store_value(cb
, 0);
3325 r600_store_value(cb
, 0);
3326 r600_store_value(cb
, 0);
3327 r600_store_value(cb
, 0);
3328 r600_store_value(cb
, 0);
3329 r600_store_value(cb
, 0);
3330 r600_store_value(cb
, 0);
3331 r600_store_value(cb
, 0);
3332 r600_store_value(cb
, 0);
3333 r600_store_value(cb
, 0);
3334 r600_store_value(cb
, 0);
3335 r600_store_value(cb
, 0);
3337 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
3338 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
3339 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
3341 if (rctx
->screen
->has_streamout
) {
3342 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3345 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
3346 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3347 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
3348 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
3349 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3350 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3351 r600_store_context_reg(cb
, R_0288EC_SQ_LDS_ALLOC_PS
, 0);
3352 r600_store_context_reg(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
3354 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
3355 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
3358 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3360 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3361 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3362 struct r600_shader
*rshader
= &shader
->shader
;
3363 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
3364 int pos_index
= -1, face_index
= -1;
3366 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
3367 unsigned spi_baryc_cntl
, sid
, tmp
, num
= 0;
3368 unsigned z_export
= 0, stencil_export
= 0;
3369 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
3370 uint32_t spi_ps_input_cntl
[32];
3373 r600_init_command_buffer(cb
, 64);
3378 for (i
= 0; i
< rshader
->ninput
; i
++) {
3379 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3380 POSITION goes via GPRs from the SC so isn't counted */
3381 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
3383 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
3387 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
3389 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
3390 have_perspective
= TRUE
;
3391 if (rshader
->input
[i
].centroid
)
3392 have_centroid
= TRUE
;
3395 sid
= rshader
->input
[i
].spi_sid
;
3398 tmp
= S_028644_SEMANTIC(sid
);
3400 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
3401 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3402 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
3403 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
3404 tmp
|= S_028644_FLAT_SHADE(1);
3407 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
3408 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
3409 tmp
|= S_028644_PT_SPRITE_TEX(1);
3412 spi_ps_input_cntl
[num
++] = tmp
;
3416 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
3417 r600_store_array(cb
, num
, spi_ps_input_cntl
);
3419 for (i
= 0; i
< rshader
->noutput
; i
++) {
3420 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3422 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3425 if (rshader
->uses_kill
)
3426 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3428 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3429 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3432 for (i
= 0; i
< rshader
->noutput
; i
++) {
3433 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3434 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3438 num_cout
= rshader
->nr_ps_color_exports
;
3440 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3442 /* always at least export 1 component per pixel */
3445 shader
->nr_ps_color_outputs
= num_cout
;
3448 have_perspective
= TRUE
;
3451 if (!have_perspective
&& !have_linear
)
3452 have_perspective
= TRUE
;
3454 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3455 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3456 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3458 if (pos_index
!= -1) {
3459 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3460 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
3461 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3462 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
3465 spi_ps_in_control_1
= 0;
3466 if (face_index
!= -1) {
3467 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3468 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3472 if (have_perspective
)
3473 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
3474 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
3476 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
3477 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
3479 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
3480 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3481 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3483 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
3484 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3485 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
3487 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
3488 r600_store_value(cb
, r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3489 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
3490 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3491 S_028844_PRIME_CACHE_ON_DRAW(1) |
3492 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3493 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3495 shader
->db_shader_control
= db_shader_control
;
3496 shader
->ps_depth_export
= z_export
| stencil_export
;
3498 shader
->sprite_coord_enable
= sprite_coord_enable
;
3499 if (rctx
->rasterizer
)
3500 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3503 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3505 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3506 struct r600_shader
*rshader
= &shader
->shader
;
3507 unsigned spi_vs_out_id
[10] = {};
3508 unsigned i
, tmp
, nparams
= 0;
3510 for (i
= 0; i
< rshader
->noutput
; i
++) {
3511 if (rshader
->output
[i
].spi_sid
) {
3512 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3513 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3518 r600_init_command_buffer(cb
, 32);
3520 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3521 for (i
= 0; i
< 10; i
++) {
3522 r600_store_value(cb
, spi_vs_out_id
[i
]);
3525 /* Certain attributes (position, psize, etc.) don't count as params.
3526 * VS is required to export at least one param and r600_shader_from_tgsi()
3527 * takes care of adding a dummy export.
3532 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3533 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3534 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3535 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3536 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3537 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3538 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
3539 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3541 shader
->pa_cl_vs_out_cntl
=
3542 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3543 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3544 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3545 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
3548 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3550 struct pipe_blend_state blend
;
3552 memset(&blend
, 0, sizeof(blend
));
3553 blend
.independent_blend_enable
= true;
3554 blend
.rt
[0].colormask
= 0xf;
3555 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3558 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3560 struct pipe_blend_state blend
;
3561 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3562 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3564 memset(&blend
, 0, sizeof(blend
));
3565 blend
.independent_blend_enable
= true;
3566 blend
.rt
[0].colormask
= 0xf;
3567 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3570 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3572 struct pipe_blend_state blend
;
3573 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3575 memset(&blend
, 0, sizeof(blend
));
3576 blend
.independent_blend_enable
= true;
3577 blend
.rt
[0].colormask
= 0xf;
3578 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3581 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3583 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3585 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3588 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3590 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
3591 !rctx
->ps_shader
->current
->ps_depth_export
;
3593 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3594 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3595 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3596 V_02880C_EXPORT_DB_FULL
) |
3597 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3599 /* When alpha test is enabled we can't trust the hw to make the proper
3600 * decision on the order in which ztest should be run related to fragment
3603 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3604 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3605 * execution and thus after alpha test so if discarded by the alpha test
3606 * the z value is not written.
3607 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3608 * get a hang unless you flush the DB in between. For now just use
3611 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3612 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3614 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3617 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3618 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3619 rctx
->db_misc_state
.atom
.dirty
= true;
3623 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3624 struct pipe_resource
*dst
,
3629 struct pipe_resource
*src
,
3634 unsigned copy_height
,
3638 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
3639 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3640 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3641 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3642 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3643 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3644 uint64_t base
, addr
;
3646 /* make sure that the dma ring is only one active */
3647 rctx
->b
.rings
.gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
);
3649 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3650 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3651 /* downcast linear aligned to linear to simplify test */
3652 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3653 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3654 assert(dst_mode
!= src_mode
);
3656 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3657 if (util_format_has_depth(util_format_description(src
->format
)))
3658 non_disp_tiling
= 1;
3662 lbpp
= util_logbase2(bpp
);
3663 pitch_tile_max
= ((pitch
/ bpp
) >> 3) - 1;
3664 nbanks
= eg_num_banks(rctx
->screen
->tiling_info
.num_banks
);
3666 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
3668 array_mode
= evergreen_array_mode(src_mode
);
3669 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) >> 6;
3670 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3671 /* linear height must be the same as the slice tile max height, it's ok even
3672 * if the linear destination/source have smaller heigh as the size of the
3673 * dma packet will be using the copy_height which is always smaller or equal
3674 * to the linear height
3676 height
= rsrc
->surface
.level
[src_level
].npix_y
;
3681 base
= rsrc
->surface
.level
[src_level
].offset
;
3682 addr
= rdst
->surface
.level
[dst_level
].offset
;
3683 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3684 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3685 bank_h
= eg_bank_wh(rsrc
->surface
.bankh
);
3686 bank_w
= eg_bank_wh(rsrc
->surface
.bankw
);
3687 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.mtilea
);
3688 tile_split
= eg_tile_split(rsrc
->surface
.tile_split
);
3689 base
+= r600_resource_va(&rctx
->screen
->b
.b
, src
);
3690 addr
+= r600_resource_va(&rctx
->screen
->b
.b
, dst
);
3693 array_mode
= evergreen_array_mode(dst_mode
);
3694 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) >> 6;
3695 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3696 /* linear height must be the same as the slice tile max height, it's ok even
3697 * if the linear destination/source have smaller heigh as the size of the
3698 * dma packet will be using the copy_height which is always smaller or equal
3699 * to the linear height
3701 height
= rdst
->surface
.level
[dst_level
].npix_y
;
3706 base
= rdst
->surface
.level
[dst_level
].offset
;
3707 addr
= rsrc
->surface
.level
[src_level
].offset
;
3708 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
3709 addr
+= src_y
* pitch
+ src_x
* bpp
;
3710 bank_h
= eg_bank_wh(rdst
->surface
.bankh
);
3711 bank_w
= eg_bank_wh(rdst
->surface
.bankw
);
3712 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.mtilea
);
3713 tile_split
= eg_tile_split(rdst
->surface
.tile_split
);
3714 base
+= r600_resource_va(&rctx
->screen
->b
.b
, dst
);
3715 addr
+= r600_resource_va(&rctx
->screen
->b
.b
, src
);
3718 size
= (copy_height
* pitch
) >> 2;
3719 ncopy
= (size
/ 0x000fffff) + !!(size
% 0x000fffff);
3720 r600_need_dma_space(rctx
, ncopy
* 9);
3722 for (i
= 0; i
< ncopy
; i
++) {
3723 cheight
= copy_height
;
3724 if (((cheight
* pitch
) >> 2) > 0x000fffff) {
3725 cheight
= (0x000fffff << 2) / pitch
;
3727 size
= (cheight
* pitch
) >> 2;
3728 /* emit reloc before writting cs so that cs is always in consistent state */
3729 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rsrc
->resource
, RADEON_USAGE_READ
);
3730 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rdst
->resource
, RADEON_USAGE_WRITE
);
3731 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
);
3732 cs
->buf
[cs
->cdw
++] = base
>> 8;
3733 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
3734 (lbpp
<< 24) | (bank_h
<< 21) |
3735 (bank_w
<< 18) | (mt_aspect
<< 16);
3736 cs
->buf
[cs
->cdw
++] = (pitch_tile_max
<< 0) | ((height
- 1) << 16);
3737 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 0);
3738 cs
->buf
[cs
->cdw
++] = (x
<< 0) | (z
<< 18);
3739 cs
->buf
[cs
->cdw
++] = (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28);
3740 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
3741 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
3742 copy_height
-= cheight
;
3743 addr
+= cheight
* pitch
;
3748 boolean
evergreen_dma_blit(struct pipe_context
*ctx
,
3749 struct pipe_resource
*dst
,
3751 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
3752 struct pipe_resource
*src
,
3754 const struct pipe_box
*src_box
)
3756 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3757 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3758 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3759 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3760 unsigned src_w
, dst_w
;
3761 unsigned src_x
, src_y
;
3763 if (rctx
->b
.rings
.dma
.cs
== NULL
) {
3766 if (src
->format
!= dst
->format
) {
3769 if (rdst
->dirty_level_mask
!= 0) {
3772 if (rsrc
->dirty_level_mask
) {
3773 ctx
->flush_resource(ctx
, src
);
3776 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3777 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3778 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3779 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3781 bpp
= rdst
->surface
.bpe
;
3782 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3783 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3784 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3785 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3786 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3788 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3789 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3790 /* downcast linear aligned to linear to simplify test */
3791 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3792 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3794 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3795 /* FIXME evergreen can do partial blit */
3798 /* the x test here are currently useless (because we don't support partial blit)
3799 * but keep them around so we don't forget about those
3801 if ((src_pitch
& 0x7) || (src_box
->x
& 0x7) || (dst_x
& 0x7) || (src_box
->y
& 0x7) || (dst_y
& 0x7)) {
3805 /* 128 bpp surfaces require non_disp_tiling for both
3806 * tiled and linear buffers on cayman. However, async
3807 * DMA only supports it on the tiled side. As such
3808 * the tile order is backwards after a L2T/T2L packet.
3810 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3811 (src_mode
!= dst_mode
) &&
3812 (util_format_get_blocksize(src
->format
) >= 16)) {
3816 if (src_mode
== dst_mode
) {
3817 uint64_t dst_offset
, src_offset
;
3818 /* simple dma blit would do NOTE code here assume :
3821 * dst_pitch == src_pitch
3823 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3824 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3825 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3826 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3827 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3828 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3829 evergreen_dma_copy(rctx
, dst
, src
, dst_offset
, src_offset
,
3830 src_box
->height
* src_pitch
);
3832 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3833 src
, src_level
, src_x
, src_y
, src_box
->z
,
3834 copy_height
, dst_pitch
, bpp
);
3839 void evergreen_init_state_functions(struct r600_context
*rctx
)
3844 * To avoid GPU lockup registers must be emited in a specific order
3845 * (no kidding ...). The order below is important and have been
3846 * partialy infered from analyzing fglrx command stream.
3848 * Don't reorder atom without carefully checking the effect (GPU lockup
3849 * or piglit regression).
3853 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
3855 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
3856 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
3857 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
3858 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
3859 /* shader program */
3860 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
3862 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
3863 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
3864 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
3866 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
3867 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
3868 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
3869 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
3870 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
3872 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 7);
3874 if (rctx
->b
.chip_class
== EVERGREEN
) {
3875 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
3877 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
3879 rctx
->sample_mask
.sample_mask
= ~0;
3881 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3882 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3883 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3884 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
3885 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3886 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
3887 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
3888 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
3889 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3890 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 6);
3891 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3892 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, evergreen_emit_scissor_state
, 4);
3893 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3894 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
3895 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
3896 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.begin_atom
;
3897 r600_init_atom(rctx
, &rctx
->vertex_shader
.atom
, id
++, r600_emit_shader
, 23);
3898 r600_init_atom(rctx
, &rctx
->pixel_shader
.atom
, id
++, r600_emit_shader
, 0);
3900 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
3901 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
3902 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
3903 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
3904 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
3905 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
3906 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
3907 rctx
->b
.b
.set_scissor_states
= evergreen_set_scissor_states
;
3909 if (rctx
->b
.chip_class
== EVERGREEN
)
3910 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
3912 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3913 evergreen_init_compute_state_functions(rctx
);