2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "evergreend.h"
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
33 static uint32_t eg_num_banks(uint32_t nbanks
)
49 static unsigned eg_tile_split(unsigned tile_split
)
52 case 64: tile_split
= 0; break;
53 case 128: tile_split
= 1; break;
54 case 256: tile_split
= 2; break;
55 case 512: tile_split
= 3; break;
57 case 1024: tile_split
= 4; break;
58 case 2048: tile_split
= 5; break;
59 case 4096: tile_split
= 6; break;
64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
66 switch (macro_tile_aspect
) {
68 case 1: macro_tile_aspect
= 0; break;
69 case 2: macro_tile_aspect
= 1; break;
70 case 4: macro_tile_aspect
= 2; break;
71 case 8: macro_tile_aspect
= 3; break;
73 return macro_tile_aspect
;
76 static unsigned eg_bank_wh(unsigned bankwh
)
80 case 1: bankwh
= 0; break;
81 case 2: bankwh
= 1; break;
82 case 4: bankwh
= 2; break;
83 case 8: bankwh
= 3; break;
88 static uint32_t r600_translate_blend_function(int blend_func
)
92 return V_028780_COMB_DST_PLUS_SRC
;
93 case PIPE_BLEND_SUBTRACT
:
94 return V_028780_COMB_SRC_MINUS_DST
;
95 case PIPE_BLEND_REVERSE_SUBTRACT
:
96 return V_028780_COMB_DST_MINUS_SRC
;
98 return V_028780_COMB_MIN_DST_SRC
;
100 return V_028780_COMB_MAX_DST_SRC
;
102 R600_ERR("Unknown blend function %d\n", blend_func
);
109 static uint32_t r600_translate_blend_factor(int blend_fact
)
111 switch (blend_fact
) {
112 case PIPE_BLENDFACTOR_ONE
:
113 return V_028780_BLEND_ONE
;
114 case PIPE_BLENDFACTOR_SRC_COLOR
:
115 return V_028780_BLEND_SRC_COLOR
;
116 case PIPE_BLENDFACTOR_SRC_ALPHA
:
117 return V_028780_BLEND_SRC_ALPHA
;
118 case PIPE_BLENDFACTOR_DST_ALPHA
:
119 return V_028780_BLEND_DST_ALPHA
;
120 case PIPE_BLENDFACTOR_DST_COLOR
:
121 return V_028780_BLEND_DST_COLOR
;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
124 case PIPE_BLENDFACTOR_CONST_COLOR
:
125 return V_028780_BLEND_CONST_COLOR
;
126 case PIPE_BLENDFACTOR_CONST_ALPHA
:
127 return V_028780_BLEND_CONST_ALPHA
;
128 case PIPE_BLENDFACTOR_ZERO
:
129 return V_028780_BLEND_ZERO
;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
142 case PIPE_BLENDFACTOR_SRC1_COLOR
:
143 return V_028780_BLEND_SRC1_COLOR
;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
145 return V_028780_BLEND_SRC1_ALPHA
;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
147 return V_028780_BLEND_INV_SRC1_COLOR
;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
149 return V_028780_BLEND_INV_SRC1_ALPHA
;
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
158 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
162 case PIPE_TEXTURE_1D
:
163 return V_030000_SQ_TEX_DIM_1D
;
164 case PIPE_TEXTURE_1D_ARRAY
:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
166 case PIPE_TEXTURE_2D
:
167 case PIPE_TEXTURE_RECT
:
168 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
169 V_030000_SQ_TEX_DIM_2D
;
170 case PIPE_TEXTURE_2D_ARRAY
:
171 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
172 V_030000_SQ_TEX_DIM_2D_ARRAY
;
173 case PIPE_TEXTURE_3D
:
174 return V_030000_SQ_TEX_DIM_3D
;
175 case PIPE_TEXTURE_CUBE
:
176 return V_030000_SQ_TEX_DIM_CUBEMAP
;
180 static uint32_t r600_translate_dbformat(enum pipe_format format
)
183 case PIPE_FORMAT_Z16_UNORM
:
184 return V_028040_Z_16
;
185 case PIPE_FORMAT_Z24X8_UNORM
:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
187 return V_028040_Z_24
;
188 case PIPE_FORMAT_Z32_FLOAT
:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
190 return V_028040_Z_32_FLOAT
;
196 static uint32_t r600_translate_colorswap(enum pipe_format format
)
200 case PIPE_FORMAT_L4A4_UNORM
:
201 case PIPE_FORMAT_A4R4_UNORM
:
202 return V_028C70_SWAP_ALT
;
204 case PIPE_FORMAT_A8_UNORM
:
205 case PIPE_FORMAT_A8_SNORM
:
206 case PIPE_FORMAT_A8_UINT
:
207 case PIPE_FORMAT_A8_SINT
:
208 case PIPE_FORMAT_A16_UNORM
:
209 case PIPE_FORMAT_A16_SNORM
:
210 case PIPE_FORMAT_A16_UINT
:
211 case PIPE_FORMAT_A16_SINT
:
212 case PIPE_FORMAT_A16_FLOAT
:
213 case PIPE_FORMAT_A32_UINT
:
214 case PIPE_FORMAT_A32_SINT
:
215 case PIPE_FORMAT_A32_FLOAT
:
216 case PIPE_FORMAT_R4A4_UNORM
:
217 return V_028C70_SWAP_ALT_REV
;
218 case PIPE_FORMAT_I8_UNORM
:
219 case PIPE_FORMAT_I8_SNORM
:
220 case PIPE_FORMAT_I8_UINT
:
221 case PIPE_FORMAT_I8_SINT
:
222 case PIPE_FORMAT_I16_UNORM
:
223 case PIPE_FORMAT_I16_SNORM
:
224 case PIPE_FORMAT_I16_UINT
:
225 case PIPE_FORMAT_I16_SINT
:
226 case PIPE_FORMAT_I16_FLOAT
:
227 case PIPE_FORMAT_I32_UINT
:
228 case PIPE_FORMAT_I32_SINT
:
229 case PIPE_FORMAT_I32_FLOAT
:
230 case PIPE_FORMAT_L8_UNORM
:
231 case PIPE_FORMAT_L8_SNORM
:
232 case PIPE_FORMAT_L8_UINT
:
233 case PIPE_FORMAT_L8_SINT
:
234 case PIPE_FORMAT_L8_SRGB
:
235 case PIPE_FORMAT_L16_UNORM
:
236 case PIPE_FORMAT_L16_SNORM
:
237 case PIPE_FORMAT_L16_UINT
:
238 case PIPE_FORMAT_L16_SINT
:
239 case PIPE_FORMAT_L16_FLOAT
:
240 case PIPE_FORMAT_L32_UINT
:
241 case PIPE_FORMAT_L32_SINT
:
242 case PIPE_FORMAT_L32_FLOAT
:
243 case PIPE_FORMAT_R8_UNORM
:
244 case PIPE_FORMAT_R8_SNORM
:
245 case PIPE_FORMAT_R8_UINT
:
246 case PIPE_FORMAT_R8_SINT
:
247 return V_028C70_SWAP_STD
;
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM
:
251 return V_028C70_SWAP_STD_REV
;
253 case PIPE_FORMAT_B5G5R5A1_UNORM
:
254 case PIPE_FORMAT_B5G5R5X1_UNORM
:
255 return V_028C70_SWAP_ALT
;
257 case PIPE_FORMAT_B4G4R4A4_UNORM
:
258 case PIPE_FORMAT_B4G4R4X4_UNORM
:
259 return V_028C70_SWAP_ALT
;
261 case PIPE_FORMAT_Z16_UNORM
:
262 return V_028C70_SWAP_STD
;
264 case PIPE_FORMAT_L8A8_UNORM
:
265 case PIPE_FORMAT_L8A8_SNORM
:
266 case PIPE_FORMAT_L8A8_UINT
:
267 case PIPE_FORMAT_L8A8_SINT
:
268 case PIPE_FORMAT_L8A8_SRGB
:
269 case PIPE_FORMAT_L16A16_UNORM
:
270 case PIPE_FORMAT_L16A16_SNORM
:
271 case PIPE_FORMAT_L16A16_UINT
:
272 case PIPE_FORMAT_L16A16_SINT
:
273 case PIPE_FORMAT_L16A16_FLOAT
:
274 case PIPE_FORMAT_L32A32_UINT
:
275 case PIPE_FORMAT_L32A32_SINT
:
276 case PIPE_FORMAT_L32A32_FLOAT
:
277 return V_028C70_SWAP_ALT
;
278 case PIPE_FORMAT_R8G8_UNORM
:
279 case PIPE_FORMAT_R8G8_SNORM
:
280 case PIPE_FORMAT_R8G8_UINT
:
281 case PIPE_FORMAT_R8G8_SINT
:
282 return V_028C70_SWAP_STD
;
284 case PIPE_FORMAT_R16_UNORM
:
285 case PIPE_FORMAT_R16_SNORM
:
286 case PIPE_FORMAT_R16_UINT
:
287 case PIPE_FORMAT_R16_SINT
:
288 case PIPE_FORMAT_R16_FLOAT
:
289 return V_028C70_SWAP_STD
;
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB
:
293 return V_028C70_SWAP_STD_REV
;
294 case PIPE_FORMAT_B8G8R8A8_SRGB
:
295 return V_028C70_SWAP_ALT
;
297 case PIPE_FORMAT_B8G8R8A8_UNORM
:
298 case PIPE_FORMAT_B8G8R8X8_UNORM
:
299 return V_028C70_SWAP_ALT
;
301 case PIPE_FORMAT_A8R8G8B8_UNORM
:
302 case PIPE_FORMAT_X8R8G8B8_UNORM
:
303 return V_028C70_SWAP_ALT_REV
;
304 case PIPE_FORMAT_R8G8B8A8_SNORM
:
305 case PIPE_FORMAT_R8G8B8A8_UNORM
:
306 case PIPE_FORMAT_R8G8B8A8_SINT
:
307 case PIPE_FORMAT_R8G8B8A8_UINT
:
308 case PIPE_FORMAT_R8G8B8X8_UNORM
:
309 return V_028C70_SWAP_STD
;
311 case PIPE_FORMAT_A8B8G8R8_UNORM
:
312 case PIPE_FORMAT_X8B8G8R8_UNORM
:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV
;
316 case PIPE_FORMAT_Z24X8_UNORM
:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
318 return V_028C70_SWAP_STD
;
320 case PIPE_FORMAT_X8Z24_UNORM
:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
322 return V_028C70_SWAP_STD
;
324 case PIPE_FORMAT_R10G10B10A2_UNORM
:
325 case PIPE_FORMAT_R10G10B10X2_SNORM
:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
327 return V_028C70_SWAP_STD
;
329 case PIPE_FORMAT_B10G10R10A2_UNORM
:
330 case PIPE_FORMAT_B10G10R10A2_UINT
:
331 return V_028C70_SWAP_ALT
;
333 case PIPE_FORMAT_R11G11B10_FLOAT
:
334 case PIPE_FORMAT_R32_FLOAT
:
335 case PIPE_FORMAT_R32_UINT
:
336 case PIPE_FORMAT_R32_SINT
:
337 case PIPE_FORMAT_Z32_FLOAT
:
338 case PIPE_FORMAT_R16G16_FLOAT
:
339 case PIPE_FORMAT_R16G16_UNORM
:
340 case PIPE_FORMAT_R16G16_SNORM
:
341 case PIPE_FORMAT_R16G16_UINT
:
342 case PIPE_FORMAT_R16G16_SINT
:
343 return V_028C70_SWAP_STD
;
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT
:
347 case PIPE_FORMAT_R32G32_UINT
:
348 case PIPE_FORMAT_R32G32_SINT
:
349 case PIPE_FORMAT_R16G16B16A16_UNORM
:
350 case PIPE_FORMAT_R16G16B16A16_SNORM
:
351 case PIPE_FORMAT_R16G16B16A16_UINT
:
352 case PIPE_FORMAT_R16G16B16A16_SINT
:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
358 case PIPE_FORMAT_R32G32B32A32_SNORM
:
359 case PIPE_FORMAT_R32G32B32A32_UNORM
:
360 case PIPE_FORMAT_R32G32B32A32_SINT
:
361 case PIPE_FORMAT_R32G32B32A32_UINT
:
362 return V_028C70_SWAP_STD
;
364 R600_ERR("unsupported colorswap format %d\n", format
);
370 static uint32_t r600_translate_colorformat(enum pipe_format format
)
374 case PIPE_FORMAT_A8_UNORM
:
375 case PIPE_FORMAT_A8_SNORM
:
376 case PIPE_FORMAT_A8_UINT
:
377 case PIPE_FORMAT_A8_SINT
:
378 case PIPE_FORMAT_I8_UNORM
:
379 case PIPE_FORMAT_I8_SNORM
:
380 case PIPE_FORMAT_I8_UINT
:
381 case PIPE_FORMAT_I8_SINT
:
382 case PIPE_FORMAT_L8_UNORM
:
383 case PIPE_FORMAT_L8_SNORM
:
384 case PIPE_FORMAT_L8_UINT
:
385 case PIPE_FORMAT_L8_SINT
:
386 case PIPE_FORMAT_L8_SRGB
:
387 case PIPE_FORMAT_R8_UNORM
:
388 case PIPE_FORMAT_R8_SNORM
:
389 case PIPE_FORMAT_R8_UINT
:
390 case PIPE_FORMAT_R8_SINT
:
391 return V_028C70_COLOR_8
;
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM
:
395 return V_028C70_COLOR_5_6_5
;
397 case PIPE_FORMAT_B5G5R5A1_UNORM
:
398 case PIPE_FORMAT_B5G5R5X1_UNORM
:
399 return V_028C70_COLOR_1_5_5_5
;
401 case PIPE_FORMAT_B4G4R4A4_UNORM
:
402 case PIPE_FORMAT_B4G4R4X4_UNORM
:
403 return V_028C70_COLOR_4_4_4_4
;
405 case PIPE_FORMAT_Z16_UNORM
:
406 return V_028C70_COLOR_16
;
408 case PIPE_FORMAT_L8A8_UNORM
:
409 case PIPE_FORMAT_L8A8_SNORM
:
410 case PIPE_FORMAT_L8A8_UINT
:
411 case PIPE_FORMAT_L8A8_SINT
:
412 case PIPE_FORMAT_L8A8_SRGB
:
413 case PIPE_FORMAT_R8G8_UNORM
:
414 case PIPE_FORMAT_R8G8_SNORM
:
415 case PIPE_FORMAT_R8G8_UINT
:
416 case PIPE_FORMAT_R8G8_SINT
:
417 return V_028C70_COLOR_8_8
;
419 case PIPE_FORMAT_R16_UNORM
:
420 case PIPE_FORMAT_R16_SNORM
:
421 case PIPE_FORMAT_R16_UINT
:
422 case PIPE_FORMAT_R16_SINT
:
423 case PIPE_FORMAT_A16_UNORM
:
424 case PIPE_FORMAT_A16_SNORM
:
425 case PIPE_FORMAT_A16_UINT
:
426 case PIPE_FORMAT_A16_SINT
:
427 case PIPE_FORMAT_L16_UNORM
:
428 case PIPE_FORMAT_L16_SNORM
:
429 case PIPE_FORMAT_L16_UINT
:
430 case PIPE_FORMAT_L16_SINT
:
431 case PIPE_FORMAT_I16_UNORM
:
432 case PIPE_FORMAT_I16_SNORM
:
433 case PIPE_FORMAT_I16_UINT
:
434 case PIPE_FORMAT_I16_SINT
:
435 return V_028C70_COLOR_16
;
437 case PIPE_FORMAT_R16_FLOAT
:
438 case PIPE_FORMAT_A16_FLOAT
:
439 case PIPE_FORMAT_L16_FLOAT
:
440 case PIPE_FORMAT_I16_FLOAT
:
441 return V_028C70_COLOR_16_FLOAT
;
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB
:
445 case PIPE_FORMAT_A8B8G8R8_UNORM
:
446 case PIPE_FORMAT_A8R8G8B8_UNORM
:
447 case PIPE_FORMAT_B8G8R8A8_SRGB
:
448 case PIPE_FORMAT_B8G8R8A8_UNORM
:
449 case PIPE_FORMAT_B8G8R8X8_UNORM
:
450 case PIPE_FORMAT_R8G8B8A8_SNORM
:
451 case PIPE_FORMAT_R8G8B8A8_UNORM
:
452 case PIPE_FORMAT_R8G8B8X8_UNORM
:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
454 case PIPE_FORMAT_X8B8G8R8_UNORM
:
455 case PIPE_FORMAT_X8R8G8B8_UNORM
:
456 case PIPE_FORMAT_R8G8B8_UNORM
:
457 case PIPE_FORMAT_R8G8B8A8_SINT
:
458 case PIPE_FORMAT_R8G8B8A8_UINT
:
459 return V_028C70_COLOR_8_8_8_8
;
461 case PIPE_FORMAT_R10G10B10A2_UNORM
:
462 case PIPE_FORMAT_R10G10B10X2_SNORM
:
463 case PIPE_FORMAT_B10G10R10A2_UNORM
:
464 case PIPE_FORMAT_B10G10R10A2_UINT
:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
466 return V_028C70_COLOR_2_10_10_10
;
468 case PIPE_FORMAT_Z24X8_UNORM
:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
470 return V_028C70_COLOR_8_24
;
472 case PIPE_FORMAT_X8Z24_UNORM
:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
474 return V_028C70_COLOR_24_8
;
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
477 return V_028C70_COLOR_X24_8_32_FLOAT
;
479 case PIPE_FORMAT_R32_UINT
:
480 case PIPE_FORMAT_R32_SINT
:
481 case PIPE_FORMAT_A32_UINT
:
482 case PIPE_FORMAT_A32_SINT
:
483 case PIPE_FORMAT_L32_UINT
:
484 case PIPE_FORMAT_L32_SINT
:
485 case PIPE_FORMAT_I32_UINT
:
486 case PIPE_FORMAT_I32_SINT
:
487 return V_028C70_COLOR_32
;
489 case PIPE_FORMAT_R32_FLOAT
:
490 case PIPE_FORMAT_A32_FLOAT
:
491 case PIPE_FORMAT_L32_FLOAT
:
492 case PIPE_FORMAT_I32_FLOAT
:
493 case PIPE_FORMAT_Z32_FLOAT
:
494 return V_028C70_COLOR_32_FLOAT
;
496 case PIPE_FORMAT_R16G16_FLOAT
:
497 case PIPE_FORMAT_L16A16_FLOAT
:
498 return V_028C70_COLOR_16_16_FLOAT
;
500 case PIPE_FORMAT_R16G16_UNORM
:
501 case PIPE_FORMAT_R16G16_SNORM
:
502 case PIPE_FORMAT_R16G16_UINT
:
503 case PIPE_FORMAT_R16G16_SINT
:
504 case PIPE_FORMAT_L16A16_UNORM
:
505 case PIPE_FORMAT_L16A16_SNORM
:
506 case PIPE_FORMAT_L16A16_UINT
:
507 case PIPE_FORMAT_L16A16_SINT
:
508 return V_028C70_COLOR_16_16
;
510 case PIPE_FORMAT_R11G11B10_FLOAT
:
511 return V_028C70_COLOR_10_11_11_FLOAT
;
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT
:
515 case PIPE_FORMAT_R16G16B16A16_SINT
:
516 case PIPE_FORMAT_R16G16B16A16_UNORM
:
517 case PIPE_FORMAT_R16G16B16A16_SNORM
:
518 return V_028C70_COLOR_16_16_16_16
;
520 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
521 return V_028C70_COLOR_16_16_16_16_FLOAT
;
523 case PIPE_FORMAT_R32G32_FLOAT
:
524 case PIPE_FORMAT_L32A32_FLOAT
:
525 return V_028C70_COLOR_32_32_FLOAT
;
527 case PIPE_FORMAT_R32G32_SINT
:
528 case PIPE_FORMAT_R32G32_UINT
:
529 case PIPE_FORMAT_L32A32_UINT
:
530 case PIPE_FORMAT_L32A32_SINT
:
531 return V_028C70_COLOR_32_32
;
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM
:
535 case PIPE_FORMAT_R32G32B32A32_UNORM
:
536 case PIPE_FORMAT_R32G32B32A32_SINT
:
537 case PIPE_FORMAT_R32G32B32A32_UINT
:
538 return V_028C70_COLOR_32_32_32_32
;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
540 return V_028C70_COLOR_32_32_32_32_FLOAT
;
543 case PIPE_FORMAT_UYVY
:
544 case PIPE_FORMAT_YUYV
:
546 return ~0U; /* Unsupported. */
550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
552 if (R600_BIG_ENDIAN
) {
553 switch(colorformat
) {
556 case V_028C70_COLOR_8
:
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5
:
561 case V_028C70_COLOR_1_5_5_5
:
562 case V_028C70_COLOR_4_4_4_4
:
563 case V_028C70_COLOR_16
:
564 case V_028C70_COLOR_8_8
:
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8
:
569 case V_028C70_COLOR_2_10_10_10
:
570 case V_028C70_COLOR_8_24
:
571 case V_028C70_COLOR_24_8
:
572 case V_028C70_COLOR_32_FLOAT
:
573 case V_028C70_COLOR_16_16_FLOAT
:
574 case V_028C70_COLOR_16_16
:
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16
:
579 case V_028C70_COLOR_16_16_16_16_FLOAT
:
582 case V_028C70_COLOR_32_32_FLOAT
:
583 case V_028C70_COLOR_32_32
:
584 case V_028C70_COLOR_X24_8_32_FLOAT
:
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT
:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT
:
591 case V_028C70_COLOR_32_32_32_32
:
594 return ENDIAN_NONE
; /* Unsupported. */
601 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
603 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
608 return r600_translate_colorformat(format
) != ~0U &&
609 r600_translate_colorswap(format
) != ~0U;
612 static bool r600_is_zs_format_supported(enum pipe_format format
)
614 return r600_translate_dbformat(format
) != ~0U;
617 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
618 enum pipe_format format
,
619 enum pipe_texture_target target
,
620 unsigned sample_count
,
623 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
626 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
627 R600_ERR("r600: unsupported texture type %d\n", target
);
631 if (!util_format_is_supported(format
, usage
))
634 if (sample_count
> 1) {
635 if (rscreen
->info
.drm_minor
< 19)
638 switch (sample_count
) {
647 /* require render-target support for multisample resources */
648 if (util_format_is_depth_or_stencil(format
)) {
649 usage
|= PIPE_BIND_DEPTH_STENCIL
;
651 usage
|= PIPE_BIND_RENDER_TARGET
;
655 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
656 r600_is_sampler_format_supported(screen
, format
)) {
657 retval
|= PIPE_BIND_SAMPLER_VIEW
;
660 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
661 PIPE_BIND_DISPLAY_TARGET
|
663 PIPE_BIND_SHARED
)) &&
664 r600_is_colorbuffer_format_supported(format
)) {
666 (PIPE_BIND_RENDER_TARGET
|
667 PIPE_BIND_DISPLAY_TARGET
|
672 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
673 r600_is_zs_format_supported(format
)) {
674 retval
|= PIPE_BIND_DEPTH_STENCIL
;
677 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
678 r600_is_vertex_format_supported(format
)) {
679 retval
|= PIPE_BIND_VERTEX_BUFFER
;
682 if (usage
& PIPE_BIND_TRANSFER_READ
)
683 retval
|= PIPE_BIND_TRANSFER_READ
;
684 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
685 retval
|= PIPE_BIND_TRANSFER_WRITE
;
687 return retval
== usage
;
690 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
691 const struct pipe_blend_state
*state
, int mode
)
693 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
694 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
695 struct r600_pipe_state
*rstate
;
696 uint32_t color_control
= 0, target_mask
;
697 /* XXX there is more then 8 framebuffer */
698 unsigned blend_cntl
[8];
704 rstate
= &blend
->rstate
;
706 rstate
->id
= R600_PIPE_STATE_BLEND
;
709 if (state
->logicop_enable
) {
710 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
712 color_control
|= (0xcc << 16);
714 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
715 if (state
->independent_blend_enable
) {
716 for (int i
= 0; i
< 8; i
++) {
717 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
720 for (int i
= 0; i
< 8; i
++) {
721 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
724 blend
->cb_target_mask
= target_mask
;
727 color_control
|= S_028808_MODE(mode
);
729 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
731 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
733 /* only have dual source on MRT0 */
734 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
735 for (int i
= 0; i
< 8; i
++) {
736 /* state->rt entries > 0 only written if independent blending */
737 const int j
= state
->independent_blend_enable
? i
: 0;
739 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
740 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
741 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
742 unsigned eqA
= state
->rt
[j
].alpha_func
;
743 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
744 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
747 if (!state
->rt
[j
].blend_enable
)
750 blend_cntl
[i
] |= S_028780_BLEND_CONTROL_ENABLE(1);
751 blend_cntl
[i
] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
752 blend_cntl
[i
] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
753 blend_cntl
[i
] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
755 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
756 blend_cntl
[i
] |= S_028780_SEPARATE_ALPHA_BLEND(1);
757 blend_cntl
[i
] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
758 blend_cntl
[i
] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
759 blend_cntl
[i
] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
762 for (int i
= 0; i
< 8; i
++) {
763 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
[i
]);
766 r600_pipe_state_add_reg(rstate
, R_028B70_DB_ALPHA_TO_MASK
,
767 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
768 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
769 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
770 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
771 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
773 blend
->alpha_to_one
= state
->alpha_to_one
;
777 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
778 const struct pipe_blend_state
*state
)
781 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
784 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
785 const struct pipe_depth_stencil_alpha_state
*state
)
787 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
788 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
789 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
790 struct r600_pipe_state
*rstate
;
796 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
797 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
798 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
799 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
801 rstate
= &dsa
->rstate
;
803 rstate
->id
= R600_PIPE_STATE_DSA
;
804 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
805 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
806 S_028800_ZFUNC(state
->depth
.func
);
809 if (state
->stencil
[0].enabled
) {
810 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
811 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
812 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
813 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
814 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
816 if (state
->stencil
[1].enabled
) {
817 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
818 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
819 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
820 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
821 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
826 alpha_test_control
= 0;
828 if (state
->alpha
.enabled
) {
829 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
830 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
831 alpha_ref
= fui(state
->alpha
.ref_value
);
833 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
834 dsa
->alpha_ref
= alpha_ref
;
837 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
841 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
842 const struct pipe_rasterizer_state
*state
)
844 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
845 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
846 struct r600_pipe_state
*rstate
;
848 unsigned prov_vtx
= 1, polygon_dual_mode
;
849 float psize_min
, psize_max
;
855 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
856 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
858 if (state
->flatshade_first
)
861 rstate
= &rs
->rstate
;
862 rs
->flatshade
= state
->flatshade
;
863 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
864 rs
->two_side
= state
->light_twoside
;
865 rs
->clip_plane_enable
= state
->clip_plane_enable
;
866 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
867 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
868 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
869 rs
->pa_cl_clip_cntl
=
870 S_028810_PS_UCP_MODE(3) |
871 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
872 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
873 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
874 rs
->multisample_enable
= state
->multisample
;
877 rs
->offset_units
= state
->offset_units
;
878 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
880 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
881 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
882 if (state
->sprite_coord_enable
) {
883 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
884 S_0286D4_PNT_SPRITE_OVRD_X(2) |
885 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
886 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
887 S_0286D4_PNT_SPRITE_OVRD_W(1);
888 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
889 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
892 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
894 /* point size 12.4 fixed point */
895 tmp
= (unsigned)(state
->point_size
* 8.0);
896 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
898 if (state
->point_size_per_vertex
) {
899 psize_min
= util_get_min_point_size(state
);
902 /* Force the point size to be as if the vertex output was disabled. */
903 psize_min
= state
->point_size
;
904 psize_max
= state
->point_size
;
906 /* Divide by two, because 0.5 = 1 pixel. */
907 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
,
908 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
909 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
911 tmp
= (unsigned)state
->line_width
* 8;
912 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
913 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MODE_CNTL_0
,
914 S_028A48_MSAA_ENABLE(state
->multisample
) |
915 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
) |
916 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
918 if (rctx
->chip_class
== CAYMAN
) {
919 r600_pipe_state_add_reg(rstate
, CM_R_028BE4_PA_SU_VTX_CNTL
,
920 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
));
922 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
923 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
924 S_028C08_QUANT_MODE(V_028C08_X_1_4096TH
));
926 r600_pipe_state_add_reg(rstate
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
927 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
928 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
929 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
930 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
931 S_028814_FACE(!state
->front_ccw
) |
932 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
933 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
934 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
935 S_028814_POLY_MODE(polygon_dual_mode
) |
936 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
937 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
938 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
942 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
943 const struct pipe_sampler_state
*state
)
945 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
947 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
953 /* directly into sampler avoid r6xx code to emit useless reg */
954 ss
->seamless_cube_map
= false;
955 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
956 ss
->border_color_use
= false;
957 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
958 ss
->tex_sampler_words
[0] = S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
959 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
960 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
961 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
962 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
963 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
964 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
965 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
966 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
967 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
968 ss
->tex_sampler_words
[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
969 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
970 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
971 ss
->tex_sampler_words
[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
972 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
975 ss
->border_color_use
= true;
976 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
977 ss
->border_color
[0] = fui(state
->border_color
.f
[0]);
978 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
979 ss
->border_color
[1] = fui(state
->border_color
.f
[1]);
980 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
981 ss
->border_color
[2] = fui(state
->border_color
.f
[2]);
982 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
983 ss
->border_color
[3] = fui(state
->border_color
.f
[3]);
988 static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_context
*ctx
,
989 struct pipe_resource
*texture
,
990 const struct pipe_sampler_view
*state
)
992 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
993 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
994 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
995 unsigned format
, endian
;
996 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
997 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
998 unsigned height
, depth
, width
;
999 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1004 /* initialize base object */
1005 view
->base
= *state
;
1006 view
->base
.texture
= NULL
;
1007 pipe_reference(NULL
, &texture
->reference
);
1008 view
->base
.texture
= texture
;
1009 view
->base
.reference
.count
= 1;
1010 view
->base
.context
= ctx
;
1012 swizzle
[0] = state
->swizzle_r
;
1013 swizzle
[1] = state
->swizzle_g
;
1014 swizzle
[2] = state
->swizzle_b
;
1015 swizzle
[3] = state
->swizzle_a
;
1017 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1019 &word4
, &yuv_format
);
1020 assert(format
!= ~0);
1026 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1027 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
1031 tmp
= tmp
->flushed_depth_texture
;
1034 endian
= r600_colorformat_endian_swap(format
);
1036 width
= tmp
->surface
.level
[0].npix_x
;
1037 height
= tmp
->surface
.level
[0].npix_y
;
1038 depth
= tmp
->surface
.level
[0].npix_z
;
1039 pitch
= tmp
->surface
.level
[0].nblk_x
* util_format_get_blockwidth(state
->format
);
1040 tile_type
= tmp
->tile_type
;
1042 switch (tmp
->surface
.level
[0].mode
) {
1043 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1044 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
1046 case RADEON_SURF_MODE_2D
:
1047 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1049 case RADEON_SURF_MODE_1D
:
1050 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1052 case RADEON_SURF_MODE_LINEAR
:
1054 array_mode
= V_028C70_ARRAY_LINEAR_GENERAL
;
1057 tile_split
= tmp
->surface
.tile_split
;
1058 macro_aspect
= tmp
->surface
.mtilea
;
1059 bankw
= tmp
->surface
.bankw
;
1060 bankh
= tmp
->surface
.bankh
;
1061 tile_split
= eg_tile_split(tile_split
);
1062 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1063 bankw
= eg_bank_wh(bankw
);
1064 bankh
= eg_bank_wh(bankh
);
1066 /* 128 bit formats require tile type = 1 */
1067 if (rscreen
->chip_class
== CAYMAN
) {
1068 if (util_format_get_blocksize(state
->format
) >= 16)
1071 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1073 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1075 depth
= texture
->array_size
;
1076 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1077 depth
= texture
->array_size
;
1080 view
->tex_resource
= &tmp
->resource
;
1081 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1082 S_030000_PITCH((pitch
/ 8) - 1) |
1083 S_030000_TEX_WIDTH(width
- 1));
1084 if (rscreen
->chip_class
== CAYMAN
)
1085 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type
);
1087 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type
);
1088 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
1089 S_030004_TEX_DEPTH(depth
- 1) |
1090 S_030004_ARRAY_MODE(array_mode
));
1091 view
->tex_resource_words
[2] = (tmp
->surface
.level
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1092 if (state
->u
.tex
.last_level
&& texture
->nr_samples
<= 1) {
1093 view
->tex_resource_words
[3] = (tmp
->surface
.level
[1].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1095 view
->tex_resource_words
[3] = (tmp
->surface
.level
[0].offset
+ r600_resource_va(ctx
->screen
, texture
)) >> 8;
1097 view
->tex_resource_words
[4] = (word4
|
1098 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1099 S_030010_ENDIAN_SWAP(endian
));
1100 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1101 S_030014_LAST_ARRAY(state
->u
.tex
.last_layer
);
1102 if (texture
->nr_samples
> 1) {
1103 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
1104 if (rscreen
->chip_class
== CAYMAN
) {
1105 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
1107 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1108 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
1110 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(state
->u
.tex
.first_level
);
1111 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(state
->u
.tex
.last_level
);
1113 /* aniso max 16 samples */
1114 view
->tex_resource_words
[6] = (S_030018_MAX_ANISO(4)) |
1115 (S_030018_TILE_SPLIT(tile_split
));
1116 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
1117 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
1118 S_03001C_BANK_WIDTH(bankw
) |
1119 S_03001C_BANK_HEIGHT(bankh
) |
1120 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
1121 S_03001C_NUM_BANKS(nbanks
);
1125 static void evergreen_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
1126 struct pipe_sampler_view
**views
)
1128 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
1131 static void evergreen_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
1132 struct pipe_sampler_view
**views
)
1134 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
1137 static void evergreen_set_clip_state(struct pipe_context
*ctx
,
1138 const struct pipe_clip_state
*state
)
1140 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1141 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1142 struct pipe_constant_buffer cb
;
1147 rctx
->clip
= *state
;
1148 rstate
->id
= R600_PIPE_STATE_CLIP
;
1149 for (int i
= 0; i
< 6; i
++) {
1150 r600_pipe_state_add_reg(rstate
,
1151 R_0285BC_PA_CL_UCP0_X
+ i
* 16,
1152 fui(state
->ucp
[i
][0]));
1153 r600_pipe_state_add_reg(rstate
,
1154 R_0285C0_PA_CL_UCP0_Y
+ i
* 16,
1155 fui(state
->ucp
[i
][1]) );
1156 r600_pipe_state_add_reg(rstate
,
1157 R_0285C4_PA_CL_UCP0_Z
+ i
* 16,
1158 fui(state
->ucp
[i
][2]));
1159 r600_pipe_state_add_reg(rstate
,
1160 R_0285C8_PA_CL_UCP0_W
+ i
* 16,
1161 fui(state
->ucp
[i
][3]));
1164 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1165 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1166 r600_context_pipe_state_set(rctx
, rstate
);
1169 cb
.user_buffer
= state
->ucp
;
1170 cb
.buffer_offset
= 0;
1171 cb
.buffer_size
= 4*4*8;
1172 r600_set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
1173 pipe_resource_reference(&cb
.buffer
, NULL
);
1176 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
1177 const struct pipe_poly_stipple
*state
)
1181 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
1182 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
1183 uint32_t *tl
, uint32_t *br
)
1185 /* EG hw workaround */
1191 /* cayman hw workaround */
1192 if (rctx
->chip_class
== CAYMAN
) {
1193 if (br_x
== 1 && br_y
== 1)
1197 *tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1198 *br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1201 static void evergreen_set_scissor_state(struct pipe_context
*ctx
,
1202 const struct pipe_scissor_state
*state
)
1204 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1205 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1211 evergreen_get_scissor_rect(rctx
, state
->minx
, state
->miny
, state
->maxx
, state
->maxy
, &tl
, &br
);
1213 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1214 r600_pipe_state_add_reg(rstate
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
);
1215 r600_pipe_state_add_reg(rstate
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
);
1217 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1218 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1219 r600_context_pipe_state_set(rctx
, rstate
);
1222 static void evergreen_set_viewport_state(struct pipe_context
*ctx
,
1223 const struct pipe_viewport_state
*state
)
1225 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1226 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1231 rctx
->viewport
= *state
;
1232 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1233 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
1234 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
1235 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
1236 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
1237 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
1238 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
1240 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1241 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1242 r600_context_pipe_state_set(rctx
, rstate
);
1245 void evergreen_init_color_surface(struct r600_context
*rctx
,
1246 struct r600_surface
*surf
)
1248 struct r600_screen
*rscreen
= rctx
->screen
;
1249 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1250 struct pipe_resource
*pipe_tex
= surf
->base
.texture
;
1251 unsigned level
= surf
->base
.u
.tex
.level
;
1252 unsigned pitch
, slice
;
1253 unsigned color_info
, color_attrib
, color_dim
= 0;
1254 unsigned format
, swap
, ntype
, endian
;
1255 uint64_t offset
, base_offset
;
1256 unsigned tile_type
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1257 const struct util_format_description
*desc
;
1259 bool blend_clamp
= 0, blend_bypass
= 0;
1261 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1262 r600_init_flushed_depth_texture(&rctx
->context
, pipe_tex
, NULL
);
1263 rtex
= rtex
->flushed_depth_texture
;
1267 offset
= rtex
->surface
.level
[level
].offset
;
1268 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1269 offset
+= rtex
->surface
.level
[level
].slice_size
*
1270 surf
->base
.u
.tex
.first_layer
;
1272 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1273 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1278 switch (rtex
->surface
.level
[level
].mode
) {
1279 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1280 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1283 case RADEON_SURF_MODE_1D
:
1284 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1285 tile_type
= rtex
->tile_type
;
1287 case RADEON_SURF_MODE_2D
:
1288 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1289 tile_type
= rtex
->tile_type
;
1291 case RADEON_SURF_MODE_LINEAR
:
1293 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL
);
1297 tile_split
= rtex
->surface
.tile_split
;
1298 macro_aspect
= rtex
->surface
.mtilea
;
1299 bankw
= rtex
->surface
.bankw
;
1300 bankh
= rtex
->surface
.bankh
;
1301 fmask_bankh
= rtex
->fmask_bank_height
;
1302 tile_split
= eg_tile_split(tile_split
);
1303 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1304 bankw
= eg_bank_wh(bankw
);
1305 bankh
= eg_bank_wh(bankh
);
1306 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1308 /* 128 bit formats require tile type = 1 */
1309 if (rscreen
->chip_class
== CAYMAN
) {
1310 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1313 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1314 desc
= util_format_description(surf
->base
.format
);
1315 for (i
= 0; i
< 4; i
++) {
1316 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1321 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1322 S_028C74_NUM_BANKS(nbanks
) |
1323 S_028C74_BANK_WIDTH(bankw
) |
1324 S_028C74_BANK_HEIGHT(bankh
) |
1325 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1326 S_028C74_NON_DISP_TILING_ORDER(tile_type
) |
1327 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1329 if (rctx
->chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1330 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1331 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1332 S_028C74_NUM_FRAGMENTS(log_samples
);
1335 ntype
= V_028C70_NUMBER_UNORM
;
1336 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1337 ntype
= V_028C70_NUMBER_SRGB
;
1338 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1339 if (desc
->channel
[i
].normalized
)
1340 ntype
= V_028C70_NUMBER_SNORM
;
1341 else if (desc
->channel
[i
].pure_integer
)
1342 ntype
= V_028C70_NUMBER_SINT
;
1343 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1344 if (desc
->channel
[i
].normalized
)
1345 ntype
= V_028C70_NUMBER_UNORM
;
1346 else if (desc
->channel
[i
].pure_integer
)
1347 ntype
= V_028C70_NUMBER_UINT
;
1350 format
= r600_translate_colorformat(surf
->base
.format
);
1351 assert(format
!= ~0);
1353 swap
= r600_translate_colorswap(surf
->base
.format
);
1356 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1357 endian
= ENDIAN_NONE
;
1359 endian
= r600_colorformat_endian_swap(format
);
1362 /* blend clamp should be set for all NORM/SRGB types */
1363 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1364 ntype
== V_028C70_NUMBER_SRGB
)
1367 /* set blend bypass according to docs if SINT/UINT or
1368 8/24 COLOR variants */
1369 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1370 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1371 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1376 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1378 color_info
|= S_028C70_FORMAT(format
) |
1379 S_028C70_COMP_SWAP(swap
) |
1380 S_028C70_BLEND_CLAMP(blend_clamp
) |
1381 S_028C70_BLEND_BYPASS(blend_bypass
) |
1382 S_028C70_NUMBER_TYPE(ntype
) |
1383 S_028C70_ENDIAN(endian
);
1386 color_info
|= S_028C70_RAT(1);
1387 color_dim
= S_028C78_WIDTH_MAX(pipe_tex
->width0
)
1388 | S_028C78_HEIGHT_MAX(pipe_tex
->height0
);
1391 /* EXPORT_NORM is an optimzation that can be enabled for better
1392 * performance in certain cases.
1393 * EXPORT_NORM can be enabled if:
1394 * - 11-bit or smaller UNORM/SNORM/SRGB
1395 * - 16-bit or smaller FLOAT
1397 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1398 ((desc
->channel
[i
].size
< 12 &&
1399 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1400 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1401 (desc
->channel
[i
].size
< 17 &&
1402 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1403 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1404 surf
->export_16bpc
= true;
1407 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1408 color_info
|= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1411 base_offset
= r600_resource_va(rctx
->context
.screen
, pipe_tex
);
1413 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1414 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1415 surf
->cb_color_dim
= color_dim
;
1416 surf
->cb_color_info
= color_info
;
1417 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1418 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1419 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1420 surf
->cb_color_view
= 0;
1422 surf
->cb_color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1423 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1425 surf
->cb_color_attrib
= color_attrib
;
1426 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1427 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask_offset
) >> 8;
1428 surf
->cb_color_cmask
= (base_offset
+ rtex
->cmask_offset
) >> 8;
1430 surf
->cb_color_fmask
= surf
->cb_color_base
;
1431 surf
->cb_color_cmask
= surf
->cb_color_base
;
1433 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice
);
1434 surf
->cb_color_cmask_slice
= S_028C80_TILE_MAX(rtex
->cmask_slice_tile_max
);
1436 surf
->color_initialized
= true;
1439 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1440 struct r600_surface
*surf
)
1442 struct r600_screen
*rscreen
= rctx
->screen
;
1443 struct pipe_screen
*screen
= &rscreen
->screen
;
1444 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1446 unsigned level
, pitch
, slice
, format
, array_mode
;
1447 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1449 level
= surf
->base
.u
.tex
.level
;
1450 format
= r600_translate_dbformat(surf
->base
.format
);
1451 assert(format
!= ~0);
1453 offset
= r600_resource_va(screen
, surf
->base
.texture
);
1454 offset
+= rtex
->surface
.level
[level
].offset
;
1455 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1456 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1460 switch (rtex
->surface
.level
[level
].mode
) {
1461 case RADEON_SURF_MODE_2D
:
1462 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1464 case RADEON_SURF_MODE_1D
:
1465 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1466 case RADEON_SURF_MODE_LINEAR
:
1468 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1471 tile_split
= rtex
->surface
.tile_split
;
1472 macro_aspect
= rtex
->surface
.mtilea
;
1473 bankw
= rtex
->surface
.bankw
;
1474 bankh
= rtex
->surface
.bankh
;
1475 tile_split
= eg_tile_split(tile_split
);
1476 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1477 bankw
= eg_bank_wh(bankw
);
1478 bankh
= eg_bank_wh(bankh
);
1479 nbanks
= eg_num_banks(rscreen
->tiling_info
.num_banks
);
1482 surf
->db_depth_info
= S_028040_ARRAY_MODE(array_mode
) |
1483 S_028040_FORMAT(format
) |
1484 S_028040_TILE_SPLIT(tile_split
)|
1485 S_028040_NUM_BANKS(nbanks
) |
1486 S_028040_BANK_WIDTH(bankw
) |
1487 S_028040_BANK_HEIGHT(bankh
) |
1488 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1489 if (rscreen
->chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1490 surf
->db_depth_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1492 surf
->db_depth_base
= offset
;
1493 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1494 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1495 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(pitch
);
1496 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(slice
);
1498 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1499 uint64_t stencil_offset
= rtex
->surface
.stencil_offset
;
1500 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1502 stile_split
= eg_tile_split(stile_split
);
1503 stencil_offset
+= r600_resource_va(screen
, surf
->base
.texture
);
1504 stencil_offset
+= rtex
->surface
.level
[level
].offset
/ 4;
1505 stencil_offset
>>= 8;
1507 surf
->db_stencil_base
= stencil_offset
;
1508 surf
->db_stencil_info
= 1 | S_028044_TILE_SPLIT(stile_split
);
1510 surf
->db_stencil_base
= offset
;
1511 surf
->db_stencil_info
= 1;
1514 surf
->depth_initialized
= true;
1517 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1518 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1519 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1520 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1521 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1523 static uint32_t evergreen_set_ms_pos(struct pipe_context
*ctx
, struct r600_pipe_state
*rstate
, int nsample
)
1526 * There are two locations (-4, 4), (4, -4). */
1527 static uint32_t sample_locs_2x
[] = {
1528 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1529 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1530 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1531 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1533 static unsigned max_dist_2x
= 4;
1535 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1536 static uint32_t sample_locs_4x
[] = {
1537 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1538 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1539 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1540 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1542 static unsigned max_dist_4x
= 6;
1544 static uint32_t sample_locs_8x
[] = {
1545 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1546 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1547 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1548 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1549 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1550 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1551 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1552 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1554 static unsigned max_dist_8x
= 8;
1555 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1560 for (i
= 0; i
< Elements(sample_locs_2x
); i
++) {
1561 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
+ i
*4,
1566 for (i
= 0; i
< Elements(sample_locs_4x
); i
++) {
1567 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
+ i
*4,
1572 for (i
= 0; i
< Elements(sample_locs_8x
); i
++) {
1573 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
+ i
*4,
1578 R600_ERR("Invalid nr_samples %i\n", nsample
);
1583 static uint32_t cayman_set_ms_pos(struct pipe_context
*ctx
, struct r600_pipe_state
*rstate
, int nsample
)
1586 * There are two locations (-4, 4), (4, -4). */
1587 static uint32_t sample_locs_2x
[] = {
1588 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1589 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1590 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1591 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1593 static unsigned max_dist_2x
= 4;
1595 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1596 static uint32_t sample_locs_4x
[] = {
1597 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1598 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1599 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1600 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1602 static unsigned max_dist_4x
= 6;
1604 static uint32_t sample_locs_8x
[] = {
1605 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1606 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1607 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1608 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1609 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1610 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1611 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1612 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1614 static unsigned max_dist_8x
= 8;
1616 static uint32_t sample_locs_16x
[] = {
1617 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1618 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1619 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1620 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1621 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1622 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1623 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1624 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1625 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1626 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1627 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1628 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1629 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1630 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1631 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1632 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1634 static unsigned max_dist_16x
= 8;
1635 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1636 uint32_t max_dist
, num_regs
, *sample_locs
;
1640 sample_locs
= sample_locs_2x
;
1641 num_regs
= Elements(sample_locs_2x
);
1642 max_dist
= max_dist_2x
;
1645 sample_locs
= sample_locs_4x
;
1646 num_regs
= Elements(sample_locs_4x
);
1647 max_dist
= max_dist_4x
;
1650 sample_locs
= sample_locs_8x
;
1651 num_regs
= Elements(sample_locs_8x
);
1652 max_dist
= max_dist_8x
;
1655 sample_locs
= sample_locs_16x
;
1656 num_regs
= Elements(sample_locs_16x
);
1657 max_dist
= max_dist_16x
;
1660 R600_ERR("Invalid nr_samples %i\n", nsample
);
1664 r600_pipe_state_add_reg(rstate
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs
[0]);
1665 r600_pipe_state_add_reg(rstate
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs
[1]);
1666 r600_pipe_state_add_reg(rstate
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs
[2]);
1667 r600_pipe_state_add_reg(rstate
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs
[3]);
1668 if (num_regs
<= 8) {
1669 r600_pipe_state_add_reg(rstate
, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs
[4]);
1670 r600_pipe_state_add_reg(rstate
, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs
[5]);
1671 r600_pipe_state_add_reg(rstate
, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs
[6]);
1672 r600_pipe_state_add_reg(rstate
, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs
[7]);
1674 if (num_regs
<= 16) {
1675 r600_pipe_state_add_reg(rstate
, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, sample_locs
[8]);
1676 r600_pipe_state_add_reg(rstate
, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, sample_locs
[9]);
1677 r600_pipe_state_add_reg(rstate
, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, sample_locs
[10]);
1678 r600_pipe_state_add_reg(rstate
, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
, sample_locs
[11]);
1679 r600_pipe_state_add_reg(rstate
, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, sample_locs
[12]);
1680 r600_pipe_state_add_reg(rstate
, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, sample_locs
[13]);
1681 r600_pipe_state_add_reg(rstate
, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, sample_locs
[14]);
1682 r600_pipe_state_add_reg(rstate
, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
, sample_locs
[15]);
1687 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1688 const struct pipe_framebuffer_state
*state
)
1690 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1691 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1692 struct r600_surface
*surf
;
1693 struct r600_resource
*res
;
1694 struct r600_texture
*rtex
;
1695 uint32_t tl
, br
, i
, nr_samples
, log_samples
;
1700 r600_flush_framebuffer(rctx
, false);
1702 /* unreference old buffer and reference new one */
1703 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1705 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1708 rctx
->export_16bpc
= true;
1709 rctx
->nr_cbufs
= state
->nr_cbufs
;
1710 rctx
->cb0_is_integer
= state
->nr_cbufs
&&
1711 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1712 rctx
->compressed_cb_mask
= 0;
1714 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1715 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1716 res
= (struct r600_resource
*)surf
->base
.texture
;
1717 rtex
= (struct r600_texture
*)res
;
1719 if (!surf
->color_initialized
) {
1720 evergreen_init_color_surface(rctx
, surf
);
1723 if (!surf
->export_16bpc
) {
1724 rctx
->export_16bpc
= false;
1727 r600_pipe_state_add_reg_bo(rstate
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
1728 surf
->cb_color_base
, res
, RADEON_USAGE_READWRITE
);
1729 r600_pipe_state_add_reg(rstate
, R_028C78_CB_COLOR0_DIM
+ i
* 0x3C,
1730 surf
->cb_color_dim
);
1731 r600_pipe_state_add_reg_bo(rstate
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1732 surf
->cb_color_info
, res
, RADEON_USAGE_READWRITE
);
1733 r600_pipe_state_add_reg(rstate
, R_028C64_CB_COLOR0_PITCH
+ i
* 0x3C,
1734 surf
->cb_color_pitch
);
1735 r600_pipe_state_add_reg(rstate
, R_028C68_CB_COLOR0_SLICE
+ i
* 0x3C,
1736 surf
->cb_color_slice
);
1737 r600_pipe_state_add_reg(rstate
, R_028C6C_CB_COLOR0_VIEW
+ i
* 0x3C,
1738 surf
->cb_color_view
);
1739 r600_pipe_state_add_reg_bo(rstate
, R_028C74_CB_COLOR0_ATTRIB
+ i
* 0x3C,
1740 surf
->cb_color_attrib
, res
, RADEON_USAGE_READWRITE
);
1741 r600_pipe_state_add_reg_bo(rstate
, R_028C7C_CB_COLOR0_CMASK
+ i
* 0x3c,
1742 surf
->cb_color_cmask
, res
, RADEON_USAGE_READWRITE
);
1743 r600_pipe_state_add_reg(rstate
, R_028C80_CB_COLOR0_CMASK_SLICE
+ i
* 0x3c,
1744 surf
->cb_color_cmask_slice
);
1745 r600_pipe_state_add_reg_bo(rstate
, R_028C84_CB_COLOR0_FMASK
+ i
* 0x3c,
1746 surf
->cb_color_fmask
, res
, RADEON_USAGE_READWRITE
);
1747 r600_pipe_state_add_reg(rstate
, R_028C88_CB_COLOR0_FMASK_SLICE
+ i
* 0x3c,
1748 surf
->cb_color_fmask_slice
);
1750 /* Cayman can fetch from a compressed MSAA colorbuffer,
1751 * so it's pointless to track them. */
1752 if (rctx
->chip_class
!= CAYMAN
&& rtex
->fmask_size
&& rtex
->cmask_size
) {
1753 rctx
->compressed_cb_mask
|= 1 << i
;
1756 /* set CB_COLOR1_INFO for possible dual-src blending */
1757 if (i
== 1 && !((struct r600_texture
*)res
)->is_rat
) {
1758 r600_pipe_state_add_reg_bo(rstate
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1759 surf
->cb_color_info
, res
, RADEON_USAGE_READWRITE
);
1762 for (; i
< 8 ; i
++) {
1763 r600_pipe_state_add_reg(rstate
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1766 /* Update alpha-test state dependencies.
1767 * Alpha-test is done on the first colorbuffer only. */
1768 if (state
->nr_cbufs
) {
1769 surf
= (struct r600_surface
*)state
->cbufs
[0];
1770 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1771 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1772 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1774 if (rctx
->alphatest_state
.cb0_export_16bpc
!= surf
->export_16bpc
) {
1775 rctx
->alphatest_state
.cb0_export_16bpc
= surf
->export_16bpc
;
1776 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1782 surf
= (struct r600_surface
*)state
->zsbuf
;
1783 res
= (struct r600_resource
*)surf
->base
.texture
;
1785 if (!surf
->depth_initialized
) {
1786 evergreen_init_depth_surface(rctx
, surf
);
1789 r600_pipe_state_add_reg_bo(rstate
, R_028048_DB_Z_READ_BASE
, surf
->db_depth_base
,
1790 res
, RADEON_USAGE_READWRITE
);
1791 r600_pipe_state_add_reg_bo(rstate
, R_028050_DB_Z_WRITE_BASE
, surf
->db_depth_base
,
1792 res
, RADEON_USAGE_READWRITE
);
1793 r600_pipe_state_add_reg(rstate
, R_028008_DB_DEPTH_VIEW
, surf
->db_depth_view
);
1795 r600_pipe_state_add_reg_bo(rstate
, R_02804C_DB_STENCIL_READ_BASE
, surf
->db_stencil_base
,
1796 res
, RADEON_USAGE_READWRITE
);
1797 r600_pipe_state_add_reg_bo(rstate
, R_028054_DB_STENCIL_WRITE_BASE
, surf
->db_stencil_base
,
1798 res
, RADEON_USAGE_READWRITE
);
1799 r600_pipe_state_add_reg_bo(rstate
, R_028044_DB_STENCIL_INFO
, surf
->db_stencil_info
,
1800 res
, RADEON_USAGE_READWRITE
);
1802 r600_pipe_state_add_reg_bo(rstate
, R_028040_DB_Z_INFO
, surf
->db_depth_info
,
1803 res
, RADEON_USAGE_READWRITE
);
1804 r600_pipe_state_add_reg(rstate
, R_028058_DB_DEPTH_SIZE
, surf
->db_depth_size
);
1805 r600_pipe_state_add_reg(rstate
, R_02805C_DB_DEPTH_SLICE
, surf
->db_depth_slice
);
1808 /* Framebuffer dimensions. */
1809 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1811 r600_pipe_state_add_reg(rstate
,
1812 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
);
1813 r600_pipe_state_add_reg(rstate
,
1814 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
);
1817 if (state
->nr_cbufs
)
1818 nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1819 else if (state
->zsbuf
)
1820 nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1824 if (nr_samples
> 1) {
1825 unsigned line_cntl
= S_028C00_LAST_PIXEL(1) |
1826 S_028C00_EXPAND_LINE_WIDTH(1);
1827 log_samples
= util_logbase2(nr_samples
);
1829 if (rctx
->chip_class
== CAYMAN
) {
1830 unsigned max_dist
= cayman_set_ms_pos(ctx
, rstate
, nr_samples
);
1832 r600_pipe_state_add_reg(rstate
, CM_R_028BDC_PA_SC_LINE_CNTL
, line_cntl
);
1833 r600_pipe_state_add_reg(rstate
, CM_R_028BE0_PA_SC_AA_CONFIG
,
1834 S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1835 S_028BE0_MAX_SAMPLE_DIST(max_dist
) |
1836 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
));
1837 r600_pipe_state_add_reg(rstate
, CM_R_028804_DB_EQAA
,
1838 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1839 S_028804_PS_ITER_SAMPLES(log_samples
) |
1840 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1841 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
1842 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1843 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1845 unsigned max_dist
= evergreen_set_ms_pos(ctx
, rstate
, nr_samples
);
1847 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, line_cntl
);
1848 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
1849 S_028C04_MSAA_NUM_SAMPLES(log_samples
) |
1850 S_028C04_MAX_SAMPLE_DIST(max_dist
));
1855 if (rctx
->chip_class
== CAYMAN
) {
1856 r600_pipe_state_add_reg(rstate
, CM_R_028BDC_PA_SC_LINE_CNTL
, S_028C00_LAST_PIXEL(1));
1857 r600_pipe_state_add_reg(rstate
, CM_R_028BE0_PA_SC_AA_CONFIG
, 0);
1858 r600_pipe_state_add_reg(rstate
, CM_R_028804_DB_EQAA
,
1859 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1860 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1863 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, S_028C00_LAST_PIXEL(1));
1864 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
, 0);
1868 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1869 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1870 r600_context_pipe_state_set(rctx
, rstate
);
1873 evergreen_polygon_offset_update(rctx
);
1876 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1877 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1878 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1881 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1882 rctx
->alphatest_state
.bypass
= false;
1883 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1886 if (rctx
->chip_class
== CAYMAN
&& rctx
->db_misc_state
.log_samples
!= log_samples
) {
1887 rctx
->db_misc_state
.log_samples
= log_samples
;
1888 r600_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1892 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1894 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1895 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1896 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1897 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1899 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1900 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1901 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1902 * will assure that the alpha-test will work even if there is
1903 * no colorbuffer bound. */
1904 r600_write_value(cs
, 0xf | (a
->dual_src_blend
? ps_colormask
: 0) | fb_colormask
); /* R_02823C_CB_SHADER_MASK */
1907 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1909 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1910 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1911 unsigned db_render_control
= 0;
1912 unsigned db_count_control
= 0;
1913 unsigned db_render_override
=
1914 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
1915 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1916 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1918 if (a
->occlusion_query_enabled
) {
1919 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1920 if (rctx
->chip_class
== CAYMAN
) {
1921 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
1923 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1926 if (a
->flush_depthstencil_through_cb
) {
1927 assert(a
->copy_depth
|| a
->copy_stencil
);
1929 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1930 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1931 S_028000_COPY_CENTROID(1) |
1932 S_028000_COPY_SAMPLE(a
->copy_sample
);
1935 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1936 r600_write_value(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
1937 r600_write_value(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
1938 r600_write_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1941 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
1942 struct r600_vertexbuf_state
*state
,
1943 unsigned resource_offset
,
1946 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1947 uint32_t dirty_mask
= state
->dirty_mask
;
1949 while (dirty_mask
) {
1950 struct pipe_vertex_buffer
*vb
;
1951 struct r600_resource
*rbuffer
;
1953 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1955 vb
= &state
->vb
[buffer_index
];
1956 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1959 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
1960 va
+= vb
->buffer_offset
;
1962 /* fetch resources start at index 992 */
1963 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1964 r600_write_value(cs
, (resource_offset
+ buffer_index
) * 8);
1965 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
1966 r600_write_value(cs
, rbuffer
->buf
->size
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1967 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1968 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1969 S_030008_STRIDE(vb
->stride
) |
1970 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1971 r600_write_value(cs
, /* RESOURCEi_WORD3 */
1972 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1973 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1974 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1975 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1976 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1977 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1978 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
1979 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1981 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1982 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1984 state
->dirty_mask
= 0;
1987 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1989 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, 992, 0);
1992 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1994 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, 816,
1995 RADEON_CP_PACKET3_COMPUTE_MODE
);
1998 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
1999 struct r600_constbuf_state
*state
,
2000 unsigned buffer_id_base
,
2001 unsigned reg_alu_constbuf_size
,
2002 unsigned reg_alu_const_cache
)
2004 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2005 uint32_t dirty_mask
= state
->dirty_mask
;
2007 while (dirty_mask
) {
2008 struct pipe_constant_buffer
*cb
;
2009 struct r600_resource
*rbuffer
;
2011 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2013 cb
= &state
->cb
[buffer_index
];
2014 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2017 va
= r600_resource_va(&rctx
->screen
->screen
, &rbuffer
->b
.b
);
2018 va
+= cb
->buffer_offset
;
2020 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2021 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
2022 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8);
2024 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2025 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
2027 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
2028 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 8);
2029 r600_write_value(cs
, va
); /* RESOURCEi_WORD0 */
2030 r600_write_value(cs
, rbuffer
->buf
->size
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
2031 r600_write_value(cs
, /* RESOURCEi_WORD2 */
2032 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2033 S_030008_STRIDE(16) |
2034 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
2035 r600_write_value(cs
, /* RESOURCEi_WORD3 */
2036 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
2037 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
2038 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
2039 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
2040 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
2041 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2042 r600_write_value(cs
, 0); /* RESOURCEi_WORD6 */
2043 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
2045 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2046 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
2048 dirty_mask
&= ~(1 << buffer_index
);
2050 state
->dirty_mask
= 0;
2053 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2055 evergreen_emit_constant_buffers(rctx
, &rctx
->vs_constbuf_state
, 176,
2056 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2057 R_028980_ALU_CONST_CACHE_VS_0
);
2060 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2062 evergreen_emit_constant_buffers(rctx
, &rctx
->ps_constbuf_state
, 0,
2063 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2064 R_028940_ALU_CONST_CACHE_PS_0
);
2067 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
2068 struct r600_samplerview_state
*state
,
2069 unsigned resource_id_base
)
2071 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2072 uint32_t dirty_mask
= state
->dirty_mask
;
2074 while (dirty_mask
) {
2075 struct r600_pipe_sampler_view
*rview
;
2076 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2079 rview
= state
->views
[resource_index
];
2082 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0));
2083 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 8);
2084 r600_write_array(cs
, 8, rview
->tex_resource_words
);
2086 /* XXX The kernel needs two relocations. This is stupid. */
2087 reloc
= r600_context_bo_reloc(rctx
, rview
->tex_resource
,
2089 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2090 r600_write_value(cs
, reloc
);
2091 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2092 r600_write_value(cs
, reloc
);
2094 state
->dirty_mask
= 0;
2097 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2099 evergreen_emit_sampler_views(rctx
, &rctx
->vs_samplers
.views
, 176 + R600_MAX_CONST_BUFFERS
);
2102 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2104 evergreen_emit_sampler_views(rctx
, &rctx
->ps_samplers
.views
, R600_MAX_CONST_BUFFERS
);
2107 static void evergreen_emit_sampler(struct r600_context
*rctx
,
2108 struct r600_textures_info
*texinfo
,
2109 unsigned resource_id_base
,
2110 unsigned border_index_reg
)
2112 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2115 for (i
= 0; i
< texinfo
->n_samplers
; i
++) {
2117 if (texinfo
->samplers
[i
] == NULL
) {
2120 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2121 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2122 r600_write_array(cs
, 3, texinfo
->samplers
[i
]->tex_sampler_words
);
2124 if (texinfo
->samplers
[i
]->border_color_use
) {
2125 r600_write_config_reg_seq(cs
, border_index_reg
, 5);
2126 r600_write_value(cs
, i
);
2127 r600_write_array(cs
, 4, texinfo
->samplers
[i
]->border_color
);
2132 static void evergreen_emit_vs_sampler(struct r600_context
*rctx
, struct r600_atom
*atom
)
2134 evergreen_emit_sampler(rctx
, &rctx
->vs_samplers
, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
);
2137 static void evergreen_emit_ps_sampler(struct r600_context
*rctx
, struct r600_atom
*atom
)
2139 evergreen_emit_sampler(rctx
, &rctx
->ps_samplers
, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
);
2142 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2144 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2145 uint8_t mask
= s
->sample_mask
;
2147 r600_write_context_reg(rctx
->cs
, R_028C3C_PA_SC_AA_MASK
,
2148 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2151 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2153 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2154 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2155 uint16_t mask
= s
->sample_mask
;
2157 r600_write_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2158 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2159 r600_write_value(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2162 void evergreen_init_state_functions(struct r600_context
*rctx
)
2164 r600_init_atom(&rctx
->cb_misc_state
.atom
, evergreen_emit_cb_misc_state
, 0, 0);
2165 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
2166 r600_init_atom(&rctx
->db_misc_state
.atom
, evergreen_emit_db_misc_state
, 7, 0);
2167 r600_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2168 r600_init_atom(&rctx
->vertex_buffer_state
.atom
, evergreen_fs_emit_vertex_buffers
, 0, 0);
2169 r600_init_atom(&rctx
->cs_vertex_buffer_state
.atom
, evergreen_cs_emit_vertex_buffers
, 0, 0);
2170 r600_init_atom(&rctx
->vs_constbuf_state
.atom
, evergreen_emit_vs_constant_buffers
, 0, 0);
2171 r600_init_atom(&rctx
->ps_constbuf_state
.atom
, evergreen_emit_ps_constant_buffers
, 0, 0);
2172 r600_init_atom(&rctx
->vs_samplers
.views
.atom
, evergreen_emit_vs_sampler_views
, 0, 0);
2173 r600_init_atom(&rctx
->ps_samplers
.views
.atom
, evergreen_emit_ps_sampler_views
, 0, 0);
2174 r600_init_atom(&rctx
->cs_shader_state
.atom
, evergreen_emit_cs_shader
, 0, 0);
2175 r600_init_atom(&rctx
->vs_samplers
.atom_sampler
, evergreen_emit_vs_sampler
, 0, 0);
2176 r600_init_atom(&rctx
->ps_samplers
.atom_sampler
, evergreen_emit_ps_sampler
, 0, 0);
2178 if (rctx
->chip_class
== EVERGREEN
)
2179 r600_init_atom(&rctx
->sample_mask
.atom
, evergreen_emit_sample_mask
, 3, 0);
2181 r600_init_atom(&rctx
->sample_mask
.atom
, cayman_emit_sample_mask
, 4, 0);
2182 rctx
->sample_mask
.sample_mask
= ~0;
2183 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
2185 rctx
->context
.create_blend_state
= evergreen_create_blend_state
;
2186 rctx
->context
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
2187 rctx
->context
.create_fs_state
= r600_create_shader_state_ps
;
2188 rctx
->context
.create_rasterizer_state
= evergreen_create_rs_state
;
2189 rctx
->context
.create_sampler_state
= evergreen_create_sampler_state
;
2190 rctx
->context
.create_sampler_view
= evergreen_create_sampler_view
;
2191 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
2192 rctx
->context
.create_vs_state
= r600_create_shader_state_vs
;
2193 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
2194 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2195 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_samplers
;
2196 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
2197 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
2198 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2199 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_samplers
;
2200 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
2201 rctx
->context
.delete_blend_state
= r600_delete_state
;
2202 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
2203 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
2204 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
2205 rctx
->context
.delete_sampler_state
= r600_delete_sampler
;
2206 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
2207 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
2208 rctx
->context
.set_blend_color
= r600_set_blend_color
;
2209 rctx
->context
.set_clip_state
= evergreen_set_clip_state
;
2210 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
2211 rctx
->context
.set_fragment_sampler_views
= evergreen_set_ps_sampler_views
;
2212 rctx
->context
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
2213 rctx
->context
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
2214 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
2215 rctx
->context
.set_scissor_state
= evergreen_set_scissor_state
;
2216 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2217 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
2218 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
2219 rctx
->context
.set_vertex_sampler_views
= evergreen_set_vs_sampler_views
;
2220 rctx
->context
.set_viewport_state
= evergreen_set_viewport_state
;
2221 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
2222 rctx
->context
.texture_barrier
= r600_texture_barrier
;
2223 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
2224 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
2225 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
2226 evergreen_init_compute_state_functions(rctx
);
2229 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2231 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2233 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
2235 /* This must be first. */
2236 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2237 r600_store_value(cb
, 0x80000000);
2238 r600_store_value(cb
, 0x80000000);
2240 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2241 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2242 /* always set the temp clauses */
2243 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2245 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2246 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2247 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2249 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2251 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2253 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2254 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2255 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2256 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2257 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2258 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2259 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2260 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2261 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2262 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2263 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2264 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2265 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2266 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2268 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2269 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2270 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2272 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2273 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2274 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2276 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2278 r600_store_context_reg(cb
, CM_R_028AA8_IA_MULTI_VGT_PARAM
, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2280 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2281 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2282 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2284 r600_store_context_reg_seq(cb
, CM_R_0288E8_SQ_LDS_ALLOC
, 2);
2285 r600_store_value(cb
, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2286 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2288 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2289 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2290 r600_store_value(cb
, 0);
2291 r600_store_value(cb
, 0);
2292 r600_store_value(cb
, 0);
2293 r600_store_value(cb
, 0);
2294 r600_store_value(cb
, 0);
2295 r600_store_value(cb
, 0);
2296 r600_store_value(cb
, 0);
2297 r600_store_value(cb
, 0);
2298 r600_store_value(cb
, 0);
2299 r600_store_value(cb
, 0);
2300 r600_store_value(cb
, 0);
2301 r600_store_value(cb
, 0);
2302 r600_store_value(cb
, 0);
2303 r600_store_value(cb
, 0);
2304 r600_store_value(cb
, 0);
2305 r600_store_value(cb
, 0);
2306 r600_store_value(cb
, 0);
2307 r600_store_value(cb
, 0);
2308 r600_store_value(cb
, 0);
2309 r600_store_value(cb
, 0);
2310 r600_store_value(cb
, 0);
2311 r600_store_value(cb
, 0);
2312 r600_store_value(cb
, 0);
2313 r600_store_value(cb
, 0);
2314 r600_store_value(cb
, 0);
2315 r600_store_value(cb
, 0);
2316 r600_store_value(cb
, 0);
2317 r600_store_value(cb
, 0);
2318 r600_store_value(cb
, 0);
2319 r600_store_value(cb
, 0);
2320 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2321 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2322 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2324 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2326 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2327 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2328 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2330 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2332 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2333 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2334 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2335 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2337 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2338 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2340 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2341 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2342 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2344 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2345 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2346 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2348 r600_store_context_reg_seq(cb
, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2349 r600_store_value(cb
, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2350 r600_store_value(cb
, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2351 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2352 r600_store_value(cb
, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2354 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2355 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2356 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2358 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2359 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2360 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2362 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2363 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2364 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2366 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2367 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2368 if (rctx
->screen
->has_streamout
) {
2369 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2372 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2373 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2376 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
2377 enum chip_class ctx_chip_class
,
2378 enum radeon_family ctx_family
,
2408 switch (ctx_family
) {
2504 switch (ctx_family
) {
2512 tmp
|= S_008C00_VC_ENABLE(1);
2515 tmp
|= S_008C00_EXPORT_SRC_C(1);
2516 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2517 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2518 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2519 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2520 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2521 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2522 tmp
|= S_008C00_ES_PRIO(es_prio
);
2524 /* enable dynamic GPR resource management */
2525 if (ctx_drm_minor
>= 7) {
2526 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2527 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2528 /* always set temp clauses */
2529 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2530 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2531 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2532 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2533 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2534 r600_store_context_reg(cb
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
2535 S_028838_PS_GPRS(0x1e) |
2536 S_028838_VS_GPRS(0x1e) |
2537 S_028838_GS_GPRS(0x1e) |
2538 S_028838_ES_GPRS(0x1e) |
2539 S_028838_HS_GPRS(0x1e) |
2540 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2542 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 4);
2543 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2545 tmp
= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2546 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2547 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2548 r600_store_value(cb
, tmp
); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2550 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2551 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2552 r600_store_value(cb
, tmp
); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2554 tmp
= S_008C0C_NUM_HS_GPRS(num_hs_gprs
);
2555 tmp
|= S_008C0C_NUM_HS_GPRS(num_ls_gprs
);
2556 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2559 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2560 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2562 r600_store_context_reg(cb
, R_028A4C_PA_SC_MODE_CNTL_1
, 0);
2564 r600_store_context_reg_seq(cb
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
2565 r600_store_value(cb
, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2566 r600_store_value(cb
, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2568 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2570 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2571 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2572 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2574 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2575 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2576 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2577 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2579 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2580 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2582 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2587 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2589 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2597 int num_ps_stack_entries
;
2598 int num_vs_stack_entries
;
2599 int num_gs_stack_entries
;
2600 int num_es_stack_entries
;
2601 int num_hs_stack_entries
;
2602 int num_ls_stack_entries
;
2603 enum radeon_family family
;
2606 if (rctx
->chip_class
== CAYMAN
) {
2607 cayman_init_atom_start_cs(rctx
);
2611 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
2613 /* This must be first. */
2614 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2615 r600_store_value(cb
, 0x80000000);
2616 r600_store_value(cb
, 0x80000000);
2618 evergreen_init_common_regs(cb
, rctx
->chip_class
2619 , rctx
->family
, rctx
->screen
->info
.drm_minor
);
2621 family
= rctx
->family
;
2625 num_ps_threads
= 96;
2626 num_vs_threads
= 16;
2627 num_gs_threads
= 16;
2628 num_es_threads
= 16;
2629 num_hs_threads
= 16;
2630 num_ls_threads
= 16;
2631 num_ps_stack_entries
= 42;
2632 num_vs_stack_entries
= 42;
2633 num_gs_stack_entries
= 42;
2634 num_es_stack_entries
= 42;
2635 num_hs_stack_entries
= 42;
2636 num_ls_stack_entries
= 42;
2639 num_ps_threads
= 128;
2640 num_vs_threads
= 20;
2641 num_gs_threads
= 20;
2642 num_es_threads
= 20;
2643 num_hs_threads
= 20;
2644 num_ls_threads
= 20;
2645 num_ps_stack_entries
= 42;
2646 num_vs_stack_entries
= 42;
2647 num_gs_stack_entries
= 42;
2648 num_es_stack_entries
= 42;
2649 num_hs_stack_entries
= 42;
2650 num_ls_stack_entries
= 42;
2653 num_ps_threads
= 128;
2654 num_vs_threads
= 20;
2655 num_gs_threads
= 20;
2656 num_es_threads
= 20;
2657 num_hs_threads
= 20;
2658 num_ls_threads
= 20;
2659 num_ps_stack_entries
= 85;
2660 num_vs_stack_entries
= 85;
2661 num_gs_stack_entries
= 85;
2662 num_es_stack_entries
= 85;
2663 num_hs_stack_entries
= 85;
2664 num_ls_stack_entries
= 85;
2668 num_ps_threads
= 128;
2669 num_vs_threads
= 20;
2670 num_gs_threads
= 20;
2671 num_es_threads
= 20;
2672 num_hs_threads
= 20;
2673 num_ls_threads
= 20;
2674 num_ps_stack_entries
= 85;
2675 num_vs_stack_entries
= 85;
2676 num_gs_stack_entries
= 85;
2677 num_es_stack_entries
= 85;
2678 num_hs_stack_entries
= 85;
2679 num_ls_stack_entries
= 85;
2682 num_ps_threads
= 96;
2683 num_vs_threads
= 16;
2684 num_gs_threads
= 16;
2685 num_es_threads
= 16;
2686 num_hs_threads
= 16;
2687 num_ls_threads
= 16;
2688 num_ps_stack_entries
= 42;
2689 num_vs_stack_entries
= 42;
2690 num_gs_stack_entries
= 42;
2691 num_es_stack_entries
= 42;
2692 num_hs_stack_entries
= 42;
2693 num_ls_stack_entries
= 42;
2696 num_ps_threads
= 96;
2697 num_vs_threads
= 25;
2698 num_gs_threads
= 25;
2699 num_es_threads
= 25;
2700 num_hs_threads
= 25;
2701 num_ls_threads
= 25;
2702 num_ps_stack_entries
= 42;
2703 num_vs_stack_entries
= 42;
2704 num_gs_stack_entries
= 42;
2705 num_es_stack_entries
= 42;
2706 num_hs_stack_entries
= 42;
2707 num_ls_stack_entries
= 42;
2710 num_ps_threads
= 96;
2711 num_vs_threads
= 25;
2712 num_gs_threads
= 25;
2713 num_es_threads
= 25;
2714 num_hs_threads
= 25;
2715 num_ls_threads
= 25;
2716 num_ps_stack_entries
= 85;
2717 num_vs_stack_entries
= 85;
2718 num_gs_stack_entries
= 85;
2719 num_es_stack_entries
= 85;
2720 num_hs_stack_entries
= 85;
2721 num_ls_stack_entries
= 85;
2724 num_ps_threads
= 128;
2725 num_vs_threads
= 20;
2726 num_gs_threads
= 20;
2727 num_es_threads
= 20;
2728 num_hs_threads
= 20;
2729 num_ls_threads
= 20;
2730 num_ps_stack_entries
= 85;
2731 num_vs_stack_entries
= 85;
2732 num_gs_stack_entries
= 85;
2733 num_es_stack_entries
= 85;
2734 num_hs_stack_entries
= 85;
2735 num_ls_stack_entries
= 85;
2738 num_ps_threads
= 128;
2739 num_vs_threads
= 20;
2740 num_gs_threads
= 20;
2741 num_es_threads
= 20;
2742 num_hs_threads
= 20;
2743 num_ls_threads
= 20;
2744 num_ps_stack_entries
= 42;
2745 num_vs_stack_entries
= 42;
2746 num_gs_stack_entries
= 42;
2747 num_es_stack_entries
= 42;
2748 num_hs_stack_entries
= 42;
2749 num_ls_stack_entries
= 42;
2752 num_ps_threads
= 128;
2753 num_vs_threads
= 10;
2754 num_gs_threads
= 10;
2755 num_es_threads
= 10;
2756 num_hs_threads
= 10;
2757 num_ls_threads
= 10;
2758 num_ps_stack_entries
= 42;
2759 num_vs_stack_entries
= 42;
2760 num_gs_stack_entries
= 42;
2761 num_es_stack_entries
= 42;
2762 num_hs_stack_entries
= 42;
2763 num_ls_stack_entries
= 42;
2767 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2768 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2769 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2770 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2772 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2773 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2775 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2776 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2777 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2779 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2780 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2781 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2783 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2784 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2785 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2787 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2788 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2789 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2791 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2792 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2794 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2795 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2796 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2797 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2798 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2799 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2800 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2802 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2803 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2804 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2805 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2806 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2808 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2809 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2810 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2811 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2812 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2813 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2814 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2815 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2816 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2817 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2818 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2819 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2820 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2821 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2823 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2824 r600_store_value(cb
, 0); /* R_028AB4_VGT_REUSE_OFF */
2825 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2827 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2829 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2830 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2831 r600_store_value(cb
, 0);
2832 r600_store_value(cb
, 0);
2833 r600_store_value(cb
, 0);
2834 r600_store_value(cb
, 0);
2835 r600_store_value(cb
, 0);
2836 r600_store_value(cb
, 0);
2837 r600_store_value(cb
, 0);
2838 r600_store_value(cb
, 0);
2839 r600_store_value(cb
, 0);
2840 r600_store_value(cb
, 0);
2841 r600_store_value(cb
, 0);
2842 r600_store_value(cb
, 0);
2843 r600_store_value(cb
, 0);
2844 r600_store_value(cb
, 0);
2845 r600_store_value(cb
, 0);
2846 r600_store_value(cb
, 0);
2847 r600_store_value(cb
, 0);
2848 r600_store_value(cb
, 0);
2849 r600_store_value(cb
, 0);
2850 r600_store_value(cb
, 0);
2851 r600_store_value(cb
, 0);
2852 r600_store_value(cb
, 0);
2853 r600_store_value(cb
, 0);
2854 r600_store_value(cb
, 0);
2855 r600_store_value(cb
, 0);
2856 r600_store_value(cb
, 0);
2857 r600_store_value(cb
, 0);
2858 r600_store_value(cb
, 0);
2859 r600_store_value(cb
, 0);
2860 r600_store_value(cb
, 0);
2861 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2862 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2863 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2865 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2867 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2868 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2869 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2871 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2872 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2874 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2875 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
2876 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2878 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2879 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2880 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2881 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2883 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2884 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2885 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2886 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2887 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2889 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2890 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2891 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2893 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2894 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2895 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2897 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2899 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2900 if (rctx
->screen
->has_streamout
) {
2901 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2904 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2905 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2908 void evergreen_polygon_offset_update(struct r600_context
*rctx
)
2910 struct r600_pipe_state state
;
2912 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
2914 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
2915 float offset_units
= rctx
->rasterizer
->offset_units
;
2916 unsigned offset_db_fmt_cntl
= 0, depth
;
2918 switch (rctx
->framebuffer
.zsbuf
->format
) {
2919 case PIPE_FORMAT_Z24X8_UNORM
:
2920 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2922 offset_units
*= 2.0f
;
2924 case PIPE_FORMAT_Z32_FLOAT
:
2925 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2927 offset_units
*= 1.0f
;
2928 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2930 case PIPE_FORMAT_Z16_UNORM
:
2932 offset_units
*= 4.0f
;
2937 /* XXX some of those reg can be computed with cso */
2938 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
2939 r600_pipe_state_add_reg(&state
,
2940 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
2941 fui(rctx
->rasterizer
->offset_scale
));
2942 r600_pipe_state_add_reg(&state
,
2943 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
2945 r600_pipe_state_add_reg(&state
,
2946 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
2947 fui(rctx
->rasterizer
->offset_scale
));
2948 r600_pipe_state_add_reg(&state
,
2949 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
2951 r600_pipe_state_add_reg(&state
,
2952 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2953 offset_db_fmt_cntl
);
2954 r600_context_pipe_state_set(rctx
, &state
);
2958 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2960 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2961 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2962 struct r600_shader
*rshader
= &shader
->shader
;
2963 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2964 int pos_index
= -1, face_index
= -1;
2966 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
2967 unsigned spi_baryc_cntl
, sid
, tmp
, idx
= 0;
2968 unsigned z_export
= 0, stencil_export
= 0;
2972 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2973 for (i
= 0; i
< rshader
->ninput
; i
++) {
2974 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2975 POSITION goes via GPRs from the SC so isn't counted */
2976 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2978 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2982 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
2984 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
2985 have_perspective
= TRUE
;
2986 if (rshader
->input
[i
].centroid
)
2987 have_centroid
= TRUE
;
2990 sid
= rshader
->input
[i
].spi_sid
;
2994 tmp
= S_028644_SEMANTIC(sid
);
2996 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2997 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2998 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2999 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
3000 tmp
|= S_028644_FLAT_SHADE(1);
3003 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
3004 (rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
3005 tmp
|= S_028644_PT_SPRITE_TEX(1);
3008 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ idx
* 4,
3015 for (i
= 0; i
< rshader
->noutput
; i
++) {
3016 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3018 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3021 if (rshader
->uses_kill
)
3022 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3024 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3025 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3028 for (i
= 0; i
< rshader
->noutput
; i
++) {
3029 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3030 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3034 num_cout
= rshader
->nr_ps_color_exports
;
3036 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3038 /* always at least export 1 component per pixel */
3041 shader
->nr_ps_color_outputs
= num_cout
;
3044 have_perspective
= TRUE
;
3047 if (!have_perspective
&& !have_linear
)
3048 have_perspective
= TRUE
;
3050 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3051 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3052 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3054 if (pos_index
!= -1) {
3055 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3056 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
3057 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3061 spi_ps_in_control_1
= 0;
3062 if (face_index
!= -1) {
3063 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3064 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3068 if (have_perspective
)
3069 spi_baryc_cntl
|= S_0286E0_PERSP_CENTER_ENA(1) |
3070 S_0286E0_PERSP_CENTROID_ENA(have_centroid
);
3072 spi_baryc_cntl
|= S_0286E0_LINEAR_CENTER_ENA(1) |
3073 S_0286E0_LINEAR_CENTROID_ENA(have_centroid
);
3075 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
,
3076 spi_ps_in_control_0
);
3077 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
,
3078 spi_ps_in_control_1
);
3079 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_PS_IN_CONTROL_2
,
3081 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3082 r600_pipe_state_add_reg(rstate
,
3083 R_0286E0_SPI_BARYC_CNTL
,
3086 r600_pipe_state_add_reg_bo(rstate
,
3087 R_028840_SQ_PGM_START_PS
,
3088 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
3089 shader
->bo
, RADEON_USAGE_READ
);
3090 r600_pipe_state_add_reg(rstate
,
3091 R_028844_SQ_PGM_RESOURCES_PS
,
3092 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3093 S_028844_PRIME_CACHE_ON_DRAW(1) |
3094 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3095 r600_pipe_state_add_reg(rstate
,
3096 R_02884C_SQ_PGM_EXPORTS_PS
,
3099 shader
->db_shader_control
= db_shader_control
;
3100 shader
->ps_depth_export
= z_export
| stencil_export
;
3102 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
3103 if (rctx
->rasterizer
)
3104 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3107 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3109 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3110 struct r600_pipe_state
*rstate
= &shader
->rstate
;
3111 struct r600_shader
*rshader
= &shader
->shader
;
3112 unsigned spi_vs_out_id
[10] = {};
3113 unsigned i
, tmp
, nparams
= 0;
3115 /* clear previous register */
3118 for (i
= 0; i
< rshader
->noutput
; i
++) {
3119 if (rshader
->output
[i
].spi_sid
) {
3120 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3121 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3126 for (i
= 0; i
< 10; i
++) {
3127 r600_pipe_state_add_reg(rstate
,
3128 R_02861C_SPI_VS_OUT_ID_0
+ i
* 4,
3132 /* Certain attributes (position, psize, etc.) don't count as params.
3133 * VS is required to export at least one param and r600_shader_from_tgsi()
3134 * takes care of adding a dummy export.
3139 r600_pipe_state_add_reg(rstate
,
3140 R_0286C4_SPI_VS_OUT_CONFIG
,
3141 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3142 r600_pipe_state_add_reg(rstate
,
3143 R_028860_SQ_PGM_RESOURCES_VS
,
3144 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3145 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3146 r600_pipe_state_add_reg_bo(rstate
,
3147 R_02885C_SQ_PGM_START_VS
,
3148 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8,
3149 shader
->bo
, RADEON_USAGE_READ
);
3151 shader
->pa_cl_vs_out_cntl
=
3152 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3153 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3154 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3155 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
3158 void evergreen_fetch_shader(struct pipe_context
*ctx
,
3159 struct r600_vertex_element
*ve
)
3161 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3162 struct r600_pipe_state
*rstate
= &ve
->rstate
;
3163 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
3165 r600_pipe_state_add_reg_bo(rstate
, R_0288A4_SQ_PGM_START_FS
,
3166 r600_resource_va(ctx
->screen
, (void *)ve
->fetch_shader
) >> 8,
3167 ve
->fetch_shader
, RADEON_USAGE_READ
);
3170 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3172 struct pipe_blend_state blend
;
3173 struct r600_pipe_state
*rstate
;
3175 memset(&blend
, 0, sizeof(blend
));
3176 blend
.independent_blend_enable
= true;
3177 blend
.rt
[0].colormask
= 0xf;
3178 rstate
= evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_RESOLVE
);
3182 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3184 struct pipe_blend_state blend
;
3185 struct r600_pipe_state
*rstate
;
3187 memset(&blend
, 0, sizeof(blend
));
3188 blend
.independent_blend_enable
= true;
3189 blend
.rt
[0].colormask
= 0xf;
3190 rstate
= evergreen_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_CB_DECOMPRESS
);
3194 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3196 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3198 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
3201 void evergreen_update_dual_export_state(struct r600_context
* rctx
)
3203 unsigned dual_export
= rctx
->export_16bpc
&& rctx
->nr_cbufs
&&
3204 !rctx
->ps_shader
->current
->ps_depth_export
;
3206 unsigned db_source_format
= dual_export
? V_02880C_EXPORT_DB_TWO
:
3207 V_02880C_EXPORT_DB_FULL
;
3209 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3210 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3211 S_02880C_DB_SOURCE_FORMAT(db_source_format
) |
3212 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->cb0_is_integer
);
3214 if (db_shader_control
!= rctx
->db_shader_control
) {
3215 struct r600_pipe_state rstate
;
3217 rctx
->db_shader_control
= db_shader_control
;
3220 r600_pipe_state_add_reg(&rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
3221 r600_context_pipe_state_set(rctx
, &rstate
);