2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "evergreend.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32 #include "evergreen_compute.h"
33 #include "util/u_math.h"
35 static inline unsigned evergreen_array_mode(unsigned mode
)
39 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_028C70_ARRAY_LINEAR_ALIGNED
;
41 case RADEON_SURF_MODE_1D
: return V_028C70_ARRAY_1D_TILED_THIN1
;
43 case RADEON_SURF_MODE_2D
: return V_028C70_ARRAY_2D_TILED_THIN1
;
47 static uint32_t eg_num_banks(uint32_t nbanks
)
63 static unsigned eg_tile_split(unsigned tile_split
)
66 case 64: tile_split
= 0; break;
67 case 128: tile_split
= 1; break;
68 case 256: tile_split
= 2; break;
69 case 512: tile_split
= 3; break;
71 case 1024: tile_split
= 4; break;
72 case 2048: tile_split
= 5; break;
73 case 4096: tile_split
= 6; break;
78 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect
)
80 switch (macro_tile_aspect
) {
82 case 1: macro_tile_aspect
= 0; break;
83 case 2: macro_tile_aspect
= 1; break;
84 case 4: macro_tile_aspect
= 2; break;
85 case 8: macro_tile_aspect
= 3; break;
87 return macro_tile_aspect
;
90 static unsigned eg_bank_wh(unsigned bankwh
)
94 case 1: bankwh
= 0; break;
95 case 2: bankwh
= 1; break;
96 case 4: bankwh
= 2; break;
97 case 8: bankwh
= 3; break;
102 static uint32_t r600_translate_blend_function(int blend_func
)
104 switch (blend_func
) {
106 return V_028780_COMB_DST_PLUS_SRC
;
107 case PIPE_BLEND_SUBTRACT
:
108 return V_028780_COMB_SRC_MINUS_DST
;
109 case PIPE_BLEND_REVERSE_SUBTRACT
:
110 return V_028780_COMB_DST_MINUS_SRC
;
112 return V_028780_COMB_MIN_DST_SRC
;
114 return V_028780_COMB_MAX_DST_SRC
;
116 R600_ERR("Unknown blend function %d\n", blend_func
);
123 static uint32_t r600_translate_blend_factor(int blend_fact
)
125 switch (blend_fact
) {
126 case PIPE_BLENDFACTOR_ONE
:
127 return V_028780_BLEND_ONE
;
128 case PIPE_BLENDFACTOR_SRC_COLOR
:
129 return V_028780_BLEND_SRC_COLOR
;
130 case PIPE_BLENDFACTOR_SRC_ALPHA
:
131 return V_028780_BLEND_SRC_ALPHA
;
132 case PIPE_BLENDFACTOR_DST_ALPHA
:
133 return V_028780_BLEND_DST_ALPHA
;
134 case PIPE_BLENDFACTOR_DST_COLOR
:
135 return V_028780_BLEND_DST_COLOR
;
136 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
137 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
138 case PIPE_BLENDFACTOR_CONST_COLOR
:
139 return V_028780_BLEND_CONST_COLOR
;
140 case PIPE_BLENDFACTOR_CONST_ALPHA
:
141 return V_028780_BLEND_CONST_ALPHA
;
142 case PIPE_BLENDFACTOR_ZERO
:
143 return V_028780_BLEND_ZERO
;
144 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
145 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
146 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
147 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
148 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
149 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
150 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
151 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
152 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
153 return V_028780_BLEND_ONE_MINUS_CONST_COLOR
;
154 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
155 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA
;
156 case PIPE_BLENDFACTOR_SRC1_COLOR
:
157 return V_028780_BLEND_SRC1_COLOR
;
158 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
159 return V_028780_BLEND_SRC1_ALPHA
;
160 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
161 return V_028780_BLEND_INV_SRC1_COLOR
;
162 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
163 return V_028780_BLEND_INV_SRC1_ALPHA
;
165 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
172 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
176 case PIPE_TEXTURE_1D
:
177 return V_030000_SQ_TEX_DIM_1D
;
178 case PIPE_TEXTURE_1D_ARRAY
:
179 return V_030000_SQ_TEX_DIM_1D_ARRAY
;
180 case PIPE_TEXTURE_2D
:
181 case PIPE_TEXTURE_RECT
:
182 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_MSAA
:
183 V_030000_SQ_TEX_DIM_2D
;
184 case PIPE_TEXTURE_2D_ARRAY
:
185 return nr_samples
> 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
186 V_030000_SQ_TEX_DIM_2D_ARRAY
;
187 case PIPE_TEXTURE_3D
:
188 return V_030000_SQ_TEX_DIM_3D
;
189 case PIPE_TEXTURE_CUBE
:
190 case PIPE_TEXTURE_CUBE_ARRAY
:
191 return V_030000_SQ_TEX_DIM_CUBEMAP
;
195 static uint32_t r600_translate_dbformat(enum pipe_format format
)
198 case PIPE_FORMAT_Z16_UNORM
:
199 return V_028040_Z_16
;
200 case PIPE_FORMAT_Z24X8_UNORM
:
201 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
202 case PIPE_FORMAT_X8Z24_UNORM
:
203 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
204 return V_028040_Z_24
;
205 case PIPE_FORMAT_Z32_FLOAT
:
206 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
207 return V_028040_Z_32_FLOAT
;
213 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
215 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
,
219 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
221 return r600_translate_colorformat(chip
, format
, FALSE
) != ~0U &&
222 r600_translate_colorswap(format
, FALSE
) != ~0U;
225 static bool r600_is_zs_format_supported(enum pipe_format format
)
227 return r600_translate_dbformat(format
) != ~0U;
230 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
231 enum pipe_format format
,
232 enum pipe_texture_target target
,
233 unsigned sample_count
,
236 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
239 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
240 R600_ERR("r600: unsupported texture type %d\n", target
);
244 if (!util_format_is_supported(format
, usage
))
247 if (sample_count
> 1) {
248 if (!rscreen
->has_msaa
)
251 switch (sample_count
) {
261 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
262 if (target
== PIPE_BUFFER
) {
263 if (r600_is_vertex_format_supported(format
))
264 retval
|= PIPE_BIND_SAMPLER_VIEW
;
266 if (r600_is_sampler_format_supported(screen
, format
))
267 retval
|= PIPE_BIND_SAMPLER_VIEW
;
271 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
272 PIPE_BIND_DISPLAY_TARGET
|
275 PIPE_BIND_BLENDABLE
)) &&
276 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
278 (PIPE_BIND_RENDER_TARGET
|
279 PIPE_BIND_DISPLAY_TARGET
|
282 if (!util_format_is_pure_integer(format
) &&
283 !util_format_is_depth_or_stencil(format
))
284 retval
|= usage
& PIPE_BIND_BLENDABLE
;
287 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
288 r600_is_zs_format_supported(format
)) {
289 retval
|= PIPE_BIND_DEPTH_STENCIL
;
292 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
293 r600_is_vertex_format_supported(format
)) {
294 retval
|= PIPE_BIND_VERTEX_BUFFER
;
297 if (usage
& PIPE_BIND_TRANSFER_READ
)
298 retval
|= PIPE_BIND_TRANSFER_READ
;
299 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
300 retval
|= PIPE_BIND_TRANSFER_WRITE
;
302 if ((usage
& PIPE_BIND_LINEAR
) &&
303 !util_format_is_compressed(format
) &&
304 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
305 retval
|= PIPE_BIND_LINEAR
;
307 return retval
== usage
;
310 static void *evergreen_create_blend_state_mode(struct pipe_context
*ctx
,
311 const struct pipe_blend_state
*state
, int mode
)
313 uint32_t color_control
= 0, target_mask
= 0;
314 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
320 r600_init_command_buffer(&blend
->buffer
, 20);
321 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
323 if (state
->logicop_enable
) {
324 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
326 color_control
|= (0xcc << 16);
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state
->independent_blend_enable
) {
330 for (int i
= 0; i
< 8; i
++) {
331 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
334 for (int i
= 0; i
< 8; i
++) {
335 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
339 /* only have dual source on MRT0 */
340 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
341 blend
->cb_target_mask
= target_mask
;
342 blend
->alpha_to_one
= state
->alpha_to_one
;
345 color_control
|= S_028808_MODE(mode
);
347 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
350 r600_store_context_reg(&blend
->buffer
, R_028808_CB_COLOR_CONTROL
, color_control
);
351 r600_store_context_reg(&blend
->buffer
, R_028B70_DB_ALPHA_TO_MASK
,
352 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
353 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
354 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
355 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
357 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
359 /* Copy over the dwords set so far into buffer_no_blend.
360 * Only the CB_BLENDi_CONTROL registers must be set after this. */
361 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
362 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
364 for (int i
= 0; i
< 8; i
++) {
365 /* state->rt entries > 0 only written if independent blending */
366 const int j
= state
->independent_blend_enable
? i
: 0;
368 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
369 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
370 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
371 unsigned eqA
= state
->rt
[j
].alpha_func
;
372 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
373 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
376 r600_store_value(&blend
->buffer_no_blend
, 0);
378 if (!state
->rt
[j
].blend_enable
) {
379 r600_store_value(&blend
->buffer
, 0);
383 bc
|= S_028780_BLEND_CONTROL_ENABLE(1);
384 bc
|= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
385 bc
|= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
386 bc
|= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
388 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
389 bc
|= S_028780_SEPARATE_ALPHA_BLEND(1);
390 bc
|= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
391 bc
|= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
392 bc
|= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
394 r600_store_value(&blend
->buffer
, bc
);
399 static void *evergreen_create_blend_state(struct pipe_context
*ctx
,
400 const struct pipe_blend_state
*state
)
403 return evergreen_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
406 static void *evergreen_create_dsa_state(struct pipe_context
*ctx
,
407 const struct pipe_depth_stencil_alpha_state
*state
)
409 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
410 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
416 r600_init_command_buffer(&dsa
->buffer
, 3);
418 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
419 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
420 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
421 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
422 dsa
->zwritemask
= state
->depth
.writemask
;
424 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
425 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
426 S_028800_ZFUNC(state
->depth
.func
);
429 if (state
->stencil
[0].enabled
) {
430 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
431 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
432 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
433 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
434 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
436 if (state
->stencil
[1].enabled
) {
437 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
439 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
440 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
441 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
446 alpha_test_control
= 0;
448 if (state
->alpha
.enabled
) {
449 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
450 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref
= fui(state
->alpha
.ref_value
);
453 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
454 dsa
->alpha_ref
= alpha_ref
;
457 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
461 static void *evergreen_create_rs_state(struct pipe_context
*ctx
,
462 const struct pipe_rasterizer_state
*state
)
464 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
465 unsigned tmp
, spi_interp
;
466 float psize_min
, psize_max
;
467 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
473 r600_init_command_buffer(&rs
->buffer
, 30);
475 rs
->scissor_enable
= state
->scissor
;
476 rs
->flatshade
= state
->flatshade
;
477 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
478 rs
->two_side
= state
->light_twoside
;
479 rs
->clip_plane_enable
= state
->clip_plane_enable
;
480 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
481 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
482 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
483 rs
->pa_cl_clip_cntl
=
484 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
485 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
486 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
487 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
488 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
489 rs
->multisample_enable
= state
->multisample
;
492 rs
->offset_units
= state
->offset_units
;
493 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
494 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
495 rs
->offset_units_unscaled
= state
->offset_units_unscaled
;
497 if (state
->point_size_per_vertex
) {
498 psize_min
= util_get_min_point_size(state
);
501 /* Force the point size to be as if the vertex output was disabled. */
502 psize_min
= state
->point_size
;
503 psize_max
= state
->point_size
;
506 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
507 if (state
->sprite_coord_enable
) {
508 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
509 S_0286D4_PNT_SPRITE_OVRD_X(2) |
510 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
511 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
512 S_0286D4_PNT_SPRITE_OVRD_W(1);
513 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
514 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
518 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
519 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
520 tmp
= r600_pack_float_12p4(state
->point_size
/2);
521 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
522 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
523 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
524 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
525 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
526 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
527 S_028A08_WIDTH((unsigned)(state
->line_width
* 8)));
529 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
530 r600_store_context_reg(&rs
->buffer
, R_028A48_PA_SC_MODE_CNTL_0
,
531 S_028A48_MSAA_ENABLE(state
->multisample
) |
532 S_028A48_VPORT_SCISSOR_ENABLE(1) |
533 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
535 if (rctx
->b
.chip_class
== CAYMAN
) {
536 r600_store_context_reg(&rs
->buffer
, CM_R_028BE4_PA_SU_VTX_CNTL
,
537 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
538 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
540 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
541 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
542 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
545 r600_store_context_reg(&rs
->buffer
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
546 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
547 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
548 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
549 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
550 S_028814_FACE(!state
->front_ccw
) |
551 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
552 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
553 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
554 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
555 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
556 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
557 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
561 static void *evergreen_create_sampler_state(struct pipe_context
*ctx
,
562 const struct pipe_sampler_state
*state
)
564 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)ctx
->screen
;
565 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
566 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
567 : state
->max_anisotropy
;
568 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
574 ss
->border_color_use
= sampler_state_needs_border_color(state
);
576 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
577 ss
->tex_sampler_words
[0] =
578 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
579 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
580 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
581 S_03C000_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
582 S_03C000_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
583 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
584 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio
) |
585 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
586 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
587 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
588 ss
->tex_sampler_words
[1] =
589 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
590 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8));
591 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
592 ss
->tex_sampler_words
[2] =
593 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
594 (state
->seamless_cube_map
? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
597 if (ss
->border_color_use
) {
598 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
603 static struct pipe_sampler_view
*
604 texture_buffer_sampler_view(struct r600_context
*rctx
,
605 struct r600_pipe_sampler_view
*view
,
606 unsigned width0
, unsigned height0
)
609 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
611 int stride
= util_format_get_blocksize(view
->base
.format
);
612 unsigned format
, num_format
, format_comp
, endian
;
613 unsigned swizzle_res
;
614 unsigned char swizzle
[4];
615 const struct util_format_description
*desc
;
616 unsigned offset
= view
->base
.u
.buf
.first_element
* stride
;
617 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
619 swizzle
[0] = view
->base
.swizzle_r
;
620 swizzle
[1] = view
->base
.swizzle_g
;
621 swizzle
[2] = view
->base
.swizzle_b
;
622 swizzle
[3] = view
->base
.swizzle_a
;
624 r600_vertex_data_type(view
->base
.format
,
625 &format
, &num_format
, &format_comp
,
628 desc
= util_format_description(view
->base
.format
);
630 swizzle_res
= r600_get_swizzle_combined(desc
->swizzle
, swizzle
, TRUE
);
632 va
= tmp
->resource
.gpu_address
+ offset
;
633 view
->tex_resource
= &tmp
->resource
;
635 view
->skip_mip_address_reloc
= true;
636 view
->tex_resource_words
[0] = va
;
637 view
->tex_resource_words
[1] = size
- 1;
638 view
->tex_resource_words
[2] = S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
639 S_030008_STRIDE(stride
) |
640 S_030008_DATA_FORMAT(format
) |
641 S_030008_NUM_FORMAT_ALL(num_format
) |
642 S_030008_FORMAT_COMP_ALL(format_comp
) |
643 S_030008_ENDIAN_SWAP(endian
);
644 view
->tex_resource_words
[3] = swizzle_res
;
646 * in theory dword 4 is for number of elements, for use with resinfo,
647 * but it seems to utterly fail to work, the amd gpu shader analyser
648 * uses a const buffer to store the element sizes for buffer txq
650 view
->tex_resource_words
[4] = 0;
651 view
->tex_resource_words
[5] = view
->tex_resource_words
[6] = 0;
652 view
->tex_resource_words
[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
);
654 if (tmp
->resource
.gpu_address
)
655 LIST_ADDTAIL(&view
->list
, &rctx
->b
.texture_buffers
);
659 struct pipe_sampler_view
*
660 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
661 struct pipe_resource
*texture
,
662 const struct pipe_sampler_view
*state
,
663 unsigned width0
, unsigned height0
,
664 unsigned force_level
)
666 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
667 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
668 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
669 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
670 unsigned format
, endian
;
671 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
672 unsigned char swizzle
[4], array_mode
= 0, non_disp_tiling
= 0;
673 unsigned height
, depth
, width
;
674 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
, fmask_bankh
;
675 enum pipe_format pipe_format
= state
->format
;
676 struct radeon_surf_level
*surflevel
;
677 unsigned base_level
, first_level
, last_level
;
678 unsigned dim
, last_layer
;
680 bool do_endian_swap
= FALSE
;
685 /* initialize base object */
687 view
->base
.texture
= NULL
;
688 pipe_reference(NULL
, &texture
->reference
);
689 view
->base
.texture
= texture
;
690 view
->base
.reference
.count
= 1;
691 view
->base
.context
= ctx
;
693 if (state
->target
== PIPE_BUFFER
)
694 return texture_buffer_sampler_view(rctx
, view
, width0
, height0
);
696 swizzle
[0] = state
->swizzle_r
;
697 swizzle
[1] = state
->swizzle_g
;
698 swizzle
[2] = state
->swizzle_b
;
699 swizzle
[3] = state
->swizzle_a
;
701 tile_split
= tmp
->surface
.tile_split
;
702 surflevel
= tmp
->surface
.level
;
704 /* Texturing with separate depth and stencil. */
705 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
706 switch (pipe_format
) {
707 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
708 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
710 case PIPE_FORMAT_X8Z24_UNORM
:
711 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
712 /* Z24 is always stored like this. */
713 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
715 case PIPE_FORMAT_X24S8_UINT
:
716 case PIPE_FORMAT_S8X24_UINT
:
717 case PIPE_FORMAT_X32_S8X24_UINT
:
718 pipe_format
= PIPE_FORMAT_S8_UINT
;
719 tile_split
= tmp
->surface
.stencil_tile_split
;
720 surflevel
= tmp
->surface
.stencil_level
;
727 do_endian_swap
= !(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
729 format
= r600_translate_texformat(ctx
->screen
, pipe_format
,
731 &word4
, &yuv_format
, do_endian_swap
);
732 assert(format
!= ~0);
738 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
741 first_level
= state
->u
.tex
.first_level
;
742 last_level
= state
->u
.tex
.last_level
;
745 depth
= texture
->depth0
;
748 base_level
= force_level
;
751 width
= u_minify(width
, force_level
);
752 height
= u_minify(height
, force_level
);
753 depth
= u_minify(depth
, force_level
);
756 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(pipe_format
);
757 non_disp_tiling
= tmp
->non_disp_tiling
;
759 switch (surflevel
[base_level
].mode
) {
761 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
762 array_mode
= V_028C70_ARRAY_LINEAR_ALIGNED
;
764 case RADEON_SURF_MODE_2D
:
765 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
767 case RADEON_SURF_MODE_1D
:
768 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
771 macro_aspect
= tmp
->surface
.mtilea
;
772 bankw
= tmp
->surface
.bankw
;
773 bankh
= tmp
->surface
.bankh
;
774 tile_split
= eg_tile_split(tile_split
);
775 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
776 bankw
= eg_bank_wh(bankw
);
777 bankh
= eg_bank_wh(bankh
);
778 fmask_bankh
= eg_bank_wh(tmp
->fmask
.bank_height
);
780 /* 128 bit formats require tile type = 1 */
781 if (rscreen
->b
.chip_class
== CAYMAN
) {
782 if (util_format_get_blocksize(pipe_format
) >= 16)
785 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
787 if (state
->target
== PIPE_TEXTURE_1D_ARRAY
) {
789 depth
= texture
->array_size
;
790 } else if (state
->target
== PIPE_TEXTURE_2D_ARRAY
) {
791 depth
= texture
->array_size
;
792 } else if (state
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
793 depth
= texture
->array_size
/ 6;
795 va
= tmp
->resource
.gpu_address
;
797 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
798 state
->format
== PIPE_FORMAT_S8X24_UINT
||
799 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
800 state
->format
== PIPE_FORMAT_S8_UINT
)
801 view
->is_stencil_sampler
= true;
803 view
->tex_resource
= &tmp
->resource
;
805 /* array type views and views into array types need to use layer offset */
807 if (state
->target
!= PIPE_TEXTURE_CUBE
)
808 dim
= MAX2(state
->target
, texture
->target
);
810 view
->tex_resource_words
[0] = (S_030000_DIM(r600_tex_dim(dim
, texture
->nr_samples
)) |
811 S_030000_PITCH((pitch
/ 8) - 1) |
812 S_030000_TEX_WIDTH(width
- 1));
813 if (rscreen
->b
.chip_class
== CAYMAN
)
814 view
->tex_resource_words
[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
816 view
->tex_resource_words
[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling
);
817 view
->tex_resource_words
[1] = (S_030004_TEX_HEIGHT(height
- 1) |
818 S_030004_TEX_DEPTH(depth
- 1) |
819 S_030004_ARRAY_MODE(array_mode
));
820 view
->tex_resource_words
[2] = (surflevel
[base_level
].offset
+ va
) >> 8;
822 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
823 if (texture
->nr_samples
> 1 && rscreen
->has_compressed_msaa_texturing
) {
825 /* disable FMASK (0 = disabled) */
826 view
->tex_resource_words
[3] = 0;
827 view
->skip_mip_address_reloc
= true;
829 /* FMASK should be in MIP_ADDRESS for multisample textures */
830 view
->tex_resource_words
[3] = (tmp
->fmask
.offset
+ va
) >> 8;
832 } else if (last_level
&& texture
->nr_samples
<= 1) {
833 view
->tex_resource_words
[3] = (surflevel
[1].offset
+ va
) >> 8;
835 view
->tex_resource_words
[3] = (surflevel
[base_level
].offset
+ va
) >> 8;
838 last_layer
= state
->u
.tex
.last_layer
;
839 if (state
->target
!= texture
->target
&& depth
== 1) {
840 last_layer
= state
->u
.tex
.first_layer
;
842 view
->tex_resource_words
[4] = (word4
|
843 S_030010_ENDIAN_SWAP(endian
));
844 view
->tex_resource_words
[5] = S_030014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
845 S_030014_LAST_ARRAY(last_layer
);
846 view
->tex_resource_words
[6] = S_030018_TILE_SPLIT(tile_split
);
848 if (texture
->nr_samples
> 1) {
849 unsigned log_samples
= util_logbase2(texture
->nr_samples
);
850 if (rscreen
->b
.chip_class
== CAYMAN
) {
851 view
->tex_resource_words
[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples
);
853 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
854 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(log_samples
);
855 view
->tex_resource_words
[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh
);
857 bool no_mip
= first_level
== last_level
;
859 view
->tex_resource_words
[4] |= S_030010_BASE_LEVEL(first_level
);
860 view
->tex_resource_words
[5] |= S_030014_LAST_LEVEL(last_level
);
861 /* aniso max 16 samples */
862 view
->tex_resource_words
[6] |= S_030018_MAX_ANISO_RATIO(no_mip
? 0 : 4);
865 view
->tex_resource_words
[7] = S_03001C_DATA_FORMAT(format
) |
866 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE
) |
867 S_03001C_BANK_WIDTH(bankw
) |
868 S_03001C_BANK_HEIGHT(bankh
) |
869 S_03001C_MACRO_TILE_ASPECT(macro_aspect
) |
870 S_03001C_NUM_BANKS(nbanks
) |
871 S_03001C_DEPTH_SAMPLE_ORDER(tmp
->is_depth
&& !tmp
->is_flushing_texture
);
875 static struct pipe_sampler_view
*
876 evergreen_create_sampler_view(struct pipe_context
*ctx
,
877 struct pipe_resource
*tex
,
878 const struct pipe_sampler_view
*state
)
880 return evergreen_create_sampler_view_custom(ctx
, tex
, state
,
881 tex
->width0
, tex
->height0
, 0);
884 static void evergreen_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
886 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
887 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
889 radeon_set_config_reg_seq(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, 3);
890 if (a
->dyn_gpr_enabled
) {
891 radeon_emit(cs
, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
));
895 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_1
);
896 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_2
);
897 radeon_emit(cs
, a
->sq_gpr_resource_mgmt_3
);
899 radeon_set_config_reg(cs
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (a
->dyn_gpr_enabled
<< 8));
900 if (a
->dyn_gpr_enabled
) {
901 radeon_set_context_reg(cs
, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
,
902 S_028838_PS_GPRS(0x1e) |
903 S_028838_VS_GPRS(0x1e) |
904 S_028838_GS_GPRS(0x1e) |
905 S_028838_ES_GPRS(0x1e) |
906 S_028838_HS_GPRS(0x1e) |
907 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
911 static void evergreen_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
913 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
914 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
916 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP0_X
, 6*4);
917 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
920 static void evergreen_set_polygon_stipple(struct pipe_context
*ctx
,
921 const struct pipe_poly_stipple
*state
)
925 static void evergreen_get_scissor_rect(struct r600_context
*rctx
,
926 unsigned tl_x
, unsigned tl_y
, unsigned br_x
, unsigned br_y
,
927 uint32_t *tl
, uint32_t *br
)
929 struct pipe_scissor_state scissor
= {tl_x
, tl_y
, br_x
, br_y
};
931 evergreen_apply_scissor_bug_workaround(&rctx
->b
, &scissor
);
933 *tl
= S_028240_TL_X(scissor
.minx
) | S_028240_TL_Y(scissor
.miny
);
934 *br
= S_028244_BR_X(scissor
.maxx
) | S_028244_BR_Y(scissor
.maxy
);
938 * This function intializes the CB* register values for RATs. It is meant
939 * to be used for 1D aligned buffers that do not have an associated
942 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
943 struct r600_surface
*surf
)
945 struct pipe_resource
*pipe_buffer
= surf
->base
.texture
;
946 unsigned format
= r600_translate_colorformat(rctx
->b
.chip_class
,
947 surf
->base
.format
, FALSE
);
948 unsigned endian
= r600_colorformat_endian_swap(format
, FALSE
);
949 unsigned swap
= r600_translate_colorswap(surf
->base
.format
, FALSE
);
950 unsigned block_size
=
951 align(util_format_get_blocksize(pipe_buffer
->format
), 4);
952 unsigned pitch_alignment
=
953 MAX2(64, rctx
->screen
->b
.info
.pipe_interleave_bytes
/ block_size
);
954 unsigned pitch
= align(pipe_buffer
->width0
, pitch_alignment
);
956 surf
->cb_color_base
= r600_resource(pipe_buffer
)->gpu_address
>> 8;
958 surf
->cb_color_pitch
= (pitch
/ 8) - 1;
960 surf
->cb_color_slice
= 0;
962 surf
->cb_color_view
= 0;
964 surf
->cb_color_info
=
965 S_028C70_ENDIAN(endian
)
966 | S_028C70_FORMAT(format
)
967 | S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
)
968 | S_028C70_NUMBER_TYPE(V_028C70_NUMBER_UINT
)
969 | S_028C70_COMP_SWAP(swap
)
970 | S_028C70_BLEND_BYPASS(1) /* We must set this bit because we
971 * are using NUMBER_UINT */
975 surf
->cb_color_attrib
= S_028C74_NON_DISP_TILING_ORDER(1);
977 /* For buffers, CB_COLOR0_DIM needs to be set to the number of
979 surf
->cb_color_dim
= pipe_buffer
->width0
;
981 /* Set the buffer range the GPU will have access to: */
982 util_range_add(&r600_resource(pipe_buffer
)->valid_buffer_range
,
983 0, pipe_buffer
->width0
);
985 surf
->cb_color_fmask
= surf
->cb_color_base
;
986 surf
->cb_color_fmask_slice
= 0;
989 void evergreen_init_color_surface(struct r600_context
*rctx
,
990 struct r600_surface
*surf
)
992 struct r600_screen
*rscreen
= rctx
->screen
;
993 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
994 unsigned level
= surf
->base
.u
.tex
.level
;
995 unsigned pitch
, slice
;
996 unsigned color_info
, color_attrib
, color_dim
= 0, color_view
;
997 unsigned format
, swap
, ntype
, endian
;
998 uint64_t offset
, base_offset
;
999 unsigned non_disp_tiling
, macro_aspect
, tile_split
, bankh
, bankw
, fmask_bankh
, nbanks
;
1000 const struct util_format_description
*desc
;
1002 bool blend_clamp
= 0, blend_bypass
= 0, do_endian_swap
= FALSE
;
1004 offset
= rtex
->surface
.level
[level
].offset
;
1005 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1006 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1008 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1009 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1014 switch (rtex
->surface
.level
[level
].mode
) {
1016 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1017 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED
);
1018 non_disp_tiling
= 1;
1020 case RADEON_SURF_MODE_1D
:
1021 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1
);
1022 non_disp_tiling
= rtex
->non_disp_tiling
;
1024 case RADEON_SURF_MODE_2D
:
1025 color_info
= S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1
);
1026 non_disp_tiling
= rtex
->non_disp_tiling
;
1029 tile_split
= rtex
->surface
.tile_split
;
1030 macro_aspect
= rtex
->surface
.mtilea
;
1031 bankw
= rtex
->surface
.bankw
;
1032 bankh
= rtex
->surface
.bankh
;
1033 if (rtex
->fmask
.size
)
1034 fmask_bankh
= rtex
->fmask
.bank_height
;
1036 fmask_bankh
= rtex
->surface
.bankh
;
1037 tile_split
= eg_tile_split(tile_split
);
1038 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1039 bankw
= eg_bank_wh(bankw
);
1040 bankh
= eg_bank_wh(bankh
);
1041 fmask_bankh
= eg_bank_wh(fmask_bankh
);
1043 /* 128 bit formats require tile type = 1 */
1044 if (rscreen
->b
.chip_class
== CAYMAN
) {
1045 if (util_format_get_blocksize(surf
->base
.format
) >= 16)
1046 non_disp_tiling
= 1;
1048 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1049 desc
= util_format_description(surf
->base
.format
);
1050 for (i
= 0; i
< 4; i
++) {
1051 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1056 color_attrib
= S_028C74_TILE_SPLIT(tile_split
)|
1057 S_028C74_NUM_BANKS(nbanks
) |
1058 S_028C74_BANK_WIDTH(bankw
) |
1059 S_028C74_BANK_HEIGHT(bankh
) |
1060 S_028C74_MACRO_TILE_ASPECT(macro_aspect
) |
1061 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling
) |
1062 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1064 if (rctx
->b
.chip_class
== CAYMAN
) {
1065 color_attrib
|= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] ==
1068 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1069 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1070 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1071 S_028C74_NUM_FRAGMENTS(log_samples
);
1075 ntype
= V_028C70_NUMBER_UNORM
;
1076 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1077 ntype
= V_028C70_NUMBER_SRGB
;
1078 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1079 if (desc
->channel
[i
].normalized
)
1080 ntype
= V_028C70_NUMBER_SNORM
;
1081 else if (desc
->channel
[i
].pure_integer
)
1082 ntype
= V_028C70_NUMBER_SINT
;
1083 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1084 if (desc
->channel
[i
].normalized
)
1085 ntype
= V_028C70_NUMBER_UNORM
;
1086 else if (desc
->channel
[i
].pure_integer
)
1087 ntype
= V_028C70_NUMBER_UINT
;
1090 if (R600_BIG_ENDIAN
)
1091 do_endian_swap
= !(rtex
->is_depth
&& !rtex
->is_flushing_texture
);
1093 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
,
1095 assert(format
!= ~0);
1097 swap
= r600_translate_colorswap(surf
->base
.format
, do_endian_swap
);
1100 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
1102 /* blend clamp should be set for all NORM/SRGB types */
1103 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
1104 ntype
== V_028C70_NUMBER_SRGB
)
1107 /* set blend bypass according to docs if SINT/UINT or
1108 8/24 COLOR variants */
1109 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1110 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1111 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1116 surf
->alphatest_bypass
= ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
;
1118 color_info
|= S_028C70_FORMAT(format
) |
1119 S_028C70_COMP_SWAP(swap
) |
1120 S_028C70_BLEND_CLAMP(blend_clamp
) |
1121 S_028C70_BLEND_BYPASS(blend_bypass
) |
1122 S_028C70_NUMBER_TYPE(ntype
) |
1123 S_028C70_ENDIAN(endian
);
1125 /* EXPORT_NORM is an optimzation that can be enabled for better
1126 * performance in certain cases.
1127 * EXPORT_NORM can be enabled if:
1128 * - 11-bit or smaller UNORM/SNORM/SRGB
1129 * - 16-bit or smaller FLOAT
1131 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1132 ((desc
->channel
[i
].size
< 12 &&
1133 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1134 ntype
!= V_028C70_NUMBER_UINT
&& ntype
!= V_028C70_NUMBER_SINT
) ||
1135 (desc
->channel
[i
].size
< 17 &&
1136 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1137 color_info
|= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC
);
1138 surf
->export_16bpc
= true;
1141 if (rtex
->fmask
.size
) {
1142 color_info
|= S_028C70_COMPRESSION(1);
1145 base_offset
= rtex
->resource
.gpu_address
;
1147 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1148 surf
->cb_color_base
= (base_offset
+ offset
) >> 8;
1149 surf
->cb_color_dim
= color_dim
;
1150 surf
->cb_color_info
= color_info
;
1151 surf
->cb_color_pitch
= S_028C64_PITCH_TILE_MAX(pitch
);
1152 surf
->cb_color_slice
= S_028C68_SLICE_TILE_MAX(slice
);
1153 surf
->cb_color_view
= color_view
;
1154 surf
->cb_color_attrib
= color_attrib
;
1155 if (rtex
->fmask
.size
) {
1156 surf
->cb_color_fmask
= (base_offset
+ rtex
->fmask
.offset
) >> 8;
1157 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1159 surf
->cb_color_fmask
= surf
->cb_color_base
;
1160 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice
);
1163 surf
->color_initialized
= true;
1166 static void evergreen_init_depth_surface(struct r600_context
*rctx
,
1167 struct r600_surface
*surf
)
1169 struct r600_screen
*rscreen
= rctx
->screen
;
1170 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1171 unsigned level
= surf
->base
.u
.tex
.level
;
1172 struct radeon_surf_level
*levelinfo
= &rtex
->surface
.level
[level
];
1174 unsigned format
, array_mode
;
1175 unsigned macro_aspect
, tile_split
, bankh
, bankw
, nbanks
;
1178 format
= r600_translate_dbformat(surf
->base
.format
);
1179 assert(format
!= ~0);
1181 offset
= rtex
->resource
.gpu_address
;
1182 offset
+= rtex
->surface
.level
[level
].offset
;
1184 switch (rtex
->surface
.level
[level
].mode
) {
1185 case RADEON_SURF_MODE_2D
:
1186 array_mode
= V_028C70_ARRAY_2D_TILED_THIN1
;
1188 case RADEON_SURF_MODE_1D
:
1189 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1191 array_mode
= V_028C70_ARRAY_1D_TILED_THIN1
;
1194 tile_split
= rtex
->surface
.tile_split
;
1195 macro_aspect
= rtex
->surface
.mtilea
;
1196 bankw
= rtex
->surface
.bankw
;
1197 bankh
= rtex
->surface
.bankh
;
1198 tile_split
= eg_tile_split(tile_split
);
1199 macro_aspect
= eg_macro_tile_aspect(macro_aspect
);
1200 bankw
= eg_bank_wh(bankw
);
1201 bankh
= eg_bank_wh(bankh
);
1202 nbanks
= eg_num_banks(rscreen
->b
.info
.r600_num_banks
);
1205 surf
->db_z_info
= S_028040_ARRAY_MODE(array_mode
) |
1206 S_028040_FORMAT(format
) |
1207 S_028040_TILE_SPLIT(tile_split
)|
1208 S_028040_NUM_BANKS(nbanks
) |
1209 S_028040_BANK_WIDTH(bankw
) |
1210 S_028040_BANK_HEIGHT(bankh
) |
1211 S_028040_MACRO_TILE_ASPECT(macro_aspect
);
1212 if (rscreen
->b
.chip_class
== CAYMAN
&& rtex
->resource
.b
.b
.nr_samples
> 1) {
1213 surf
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1216 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
1218 surf
->db_depth_base
= offset
;
1219 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1220 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1221 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX(levelinfo
->nblk_x
/ 8 - 1) |
1222 S_028058_HEIGHT_TILE_MAX(levelinfo
->nblk_y
/ 8 - 1);
1223 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX(levelinfo
->nblk_x
*
1224 levelinfo
->nblk_y
/ 64 - 1);
1226 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1227 uint64_t stencil_offset
;
1228 unsigned stile_split
= rtex
->surface
.stencil_tile_split
;
1230 stile_split
= eg_tile_split(stile_split
);
1232 stencil_offset
= rtex
->surface
.stencil_level
[level
].offset
;
1233 stencil_offset
+= rtex
->resource
.gpu_address
;
1235 surf
->db_stencil_base
= stencil_offset
>> 8;
1236 surf
->db_stencil_info
= S_028044_FORMAT(V_028044_STENCIL_8
) |
1237 S_028044_TILE_SPLIT(stile_split
);
1239 surf
->db_stencil_base
= offset
;
1240 /* DRM 2.6.18 allows the INVALID format to disable stencil.
1241 * Older kernels are out of luck. */
1242 surf
->db_stencil_info
= rctx
->screen
->b
.info
.drm_minor
>= 18 ?
1243 S_028044_FORMAT(V_028044_STENCIL_INVALID
) :
1244 S_028044_FORMAT(V_028044_STENCIL_8
);
1247 /* use htile only for first level */
1248 if (rtex
->htile_buffer
&& !level
) {
1249 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
1250 surf
->db_htile_data_base
= va
>> 8;
1251 surf
->db_htile_surface
= S_028ABC_HTILE_WIDTH(1) |
1252 S_028ABC_HTILE_HEIGHT(1) |
1253 S_028ABC_FULL_CACHE(1);
1254 surf
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1255 surf
->db_preload_control
= 0;
1258 surf
->depth_initialized
= true;
1261 static void evergreen_set_framebuffer_state(struct pipe_context
*ctx
,
1262 const struct pipe_framebuffer_state
*state
)
1264 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1265 struct r600_surface
*surf
;
1266 struct r600_texture
*rtex
;
1267 uint32_t i
, log_samples
;
1269 /* Flush TC when changing the framebuffer state, because the only
1270 * client not using TC that can change textures is the framebuffer.
1271 * Other places don't typically have to flush TC.
1273 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
|
1274 R600_CONTEXT_FLUSH_AND_INV
|
1275 R600_CONTEXT_FLUSH_AND_INV_CB
|
1276 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
1277 R600_CONTEXT_FLUSH_AND_INV_DB
|
1278 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
1279 R600_CONTEXT_INV_TEX_CACHE
;
1281 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1284 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1285 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1286 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1287 rctx
->framebuffer
.compressed_cb_mask
= 0;
1288 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1290 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1291 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1295 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1297 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1299 if (!surf
->color_initialized
) {
1300 evergreen_init_color_surface(rctx
, surf
);
1303 if (!surf
->export_16bpc
) {
1304 rctx
->framebuffer
.export_16bpc
= false;
1307 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1308 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1312 /* Update alpha-test state dependencies.
1313 * Alpha-test is done on the first colorbuffer only. */
1314 if (state
->nr_cbufs
) {
1315 bool alphatest_bypass
= false;
1316 bool export_16bpc
= true;
1318 surf
= (struct r600_surface
*)state
->cbufs
[0];
1320 alphatest_bypass
= surf
->alphatest_bypass
;
1321 export_16bpc
= surf
->export_16bpc
;
1324 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1325 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1326 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1328 if (rctx
->alphatest_state
.cb0_export_16bpc
!= export_16bpc
) {
1329 rctx
->alphatest_state
.cb0_export_16bpc
= export_16bpc
;
1330 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1336 surf
= (struct r600_surface
*)state
->zsbuf
;
1338 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1340 if (!surf
->depth_initialized
) {
1341 evergreen_init_depth_surface(rctx
, surf
);
1344 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1345 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1346 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
1349 if (rctx
->db_state
.rsurf
!= surf
) {
1350 rctx
->db_state
.rsurf
= surf
;
1351 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1352 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1354 } else if (rctx
->db_state
.rsurf
) {
1355 rctx
->db_state
.rsurf
= NULL
;
1356 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1357 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1360 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1361 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1362 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1365 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1366 rctx
->alphatest_state
.bypass
= false;
1367 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1370 log_samples
= util_logbase2(rctx
->framebuffer
.nr_samples
);
1371 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1372 if ((rctx
->b
.chip_class
== CAYMAN
||
1373 rctx
->b
.family
== CHIP_RV770
) &&
1374 rctx
->db_misc_state
.log_samples
!= log_samples
) {
1375 rctx
->db_misc_state
.log_samples
= log_samples
;
1376 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1380 /* Calculate the CS size. */
1381 rctx
->framebuffer
.atom
.num_dw
= 4; /* SCISSOR */
1384 if (rctx
->b
.chip_class
== EVERGREEN
)
1385 rctx
->framebuffer
.atom
.num_dw
+= 17; /* Evergreen */
1387 rctx
->framebuffer
.atom
.num_dw
+= 28; /* Cayman */
1390 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 23;
1391 rctx
->framebuffer
.atom
.num_dw
+= state
->nr_cbufs
* 2;
1392 rctx
->framebuffer
.atom
.num_dw
+= (12 - state
->nr_cbufs
) * 3;
1396 rctx
->framebuffer
.atom
.num_dw
+= 24;
1397 rctx
->framebuffer
.atom
.num_dw
+= 2;
1398 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1399 rctx
->framebuffer
.atom
.num_dw
+= 4;
1402 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1404 r600_set_sample_locations_constant_buffer(rctx
);
1407 static void evergreen_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
1409 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1411 if (rctx
->ps_iter_samples
== min_samples
)
1414 rctx
->ps_iter_samples
= min_samples
;
1415 if (rctx
->framebuffer
.nr_samples
> 1) {
1416 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1421 static uint32_t sample_locs_8x
[] = {
1422 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1423 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1424 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1425 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1426 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1427 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1428 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1429 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1431 static unsigned max_dist_8x
= 7;
1433 static void evergreen_get_sample_position(struct pipe_context
*ctx
,
1434 unsigned sample_count
,
1435 unsigned sample_index
,
1442 switch (sample_count
) {
1445 out_value
[0] = out_value
[1] = 0.5;
1448 offset
= 4 * (sample_index
* 2);
1449 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1450 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1451 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1452 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1455 offset
= 4 * (sample_index
* 2);
1456 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1457 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1458 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1459 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1462 offset
= 4 * (sample_index
% 4 * 2);
1463 index
= (sample_index
/ 4);
1464 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1465 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1466 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1467 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1472 static void evergreen_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
, int ps_iter_samples
)
1475 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1476 unsigned max_dist
= 0;
1478 switch (nr_samples
) {
1483 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_2x
));
1484 radeon_emit_array(cs
, eg_sample_locs_2x
, ARRAY_SIZE(eg_sample_locs_2x
));
1485 max_dist
= eg_max_dist_2x
;
1488 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(eg_sample_locs_4x
));
1489 radeon_emit_array(cs
, eg_sample_locs_4x
, ARRAY_SIZE(eg_sample_locs_4x
));
1490 max_dist
= eg_max_dist_4x
;
1493 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0
, ARRAY_SIZE(sample_locs_8x
));
1494 radeon_emit_array(cs
, sample_locs_8x
, ARRAY_SIZE(sample_locs_8x
));
1495 max_dist
= max_dist_8x
;
1499 if (nr_samples
> 1) {
1500 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1501 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1502 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1503 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1504 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1505 radeon_set_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
,
1506 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1) |
1507 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1508 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1510 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1511 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1512 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1513 radeon_set_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
,
1514 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1515 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1519 static void evergreen_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1521 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1522 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1523 unsigned nr_cbufs
= state
->nr_cbufs
;
1525 struct r600_texture
*tex
= NULL
;
1526 struct r600_surface
*cb
= NULL
;
1528 /* XXX support more colorbuffers once we need them */
1529 assert(nr_cbufs
<= 8);
1534 for (i
= 0; i
< nr_cbufs
; i
++) {
1535 unsigned reloc
, cmask_reloc
;
1537 cb
= (struct r600_surface
*)state
->cbufs
[i
];
1539 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1540 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1544 tex
= (struct r600_texture
*)cb
->base
.texture
;
1545 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1547 (struct r600_resource
*)cb
->base
.texture
,
1548 RADEON_USAGE_READWRITE
,
1549 tex
->surface
.nsamples
> 1 ?
1550 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1551 RADEON_PRIO_COLOR_BUFFER
);
1553 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
1554 cmask_reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1555 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
1558 cmask_reloc
= reloc
;
1561 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 13);
1562 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
1563 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
1564 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
1565 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
1566 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
1567 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
1568 radeon_emit(cs
, cb
->cb_color_dim
); /* R_028C78_CB_COLOR0_DIM */
1569 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
1570 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1571 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
1572 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1573 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1574 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1576 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1577 radeon_emit(cs
, reloc
);
1579 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1580 radeon_emit(cs
, reloc
);
1582 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1583 radeon_emit(cs
, cmask_reloc
);
1585 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1586 radeon_emit(cs
, reloc
);
1588 /* set CB_COLOR1_INFO for possible dual-src blending */
1589 if (i
== 1 && state
->cbufs
[0]) {
1590 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
1591 cb
->cb_color_info
| tex
->cb_color_info
);
1595 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
1597 radeon_set_context_reg(cs
, R_028E50_CB_COLOR8_INFO
+ (i
- 8) * 0x1C, 0);
1601 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
1602 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1604 (struct r600_resource
*)state
->zsbuf
->texture
,
1605 RADEON_USAGE_READWRITE
,
1606 zb
->base
.texture
->nr_samples
> 1 ?
1607 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1608 RADEON_PRIO_DEPTH_BUFFER
);
1610 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
1612 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 8);
1613 radeon_emit(cs
, zb
->db_z_info
); /* R_028040_DB_Z_INFO */
1614 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1615 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
1616 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1617 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
1618 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1619 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1620 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1622 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1623 radeon_emit(cs
, reloc
);
1625 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1626 radeon_emit(cs
, reloc
);
1628 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1629 radeon_emit(cs
, reloc
);
1631 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1632 radeon_emit(cs
, reloc
);
1633 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1634 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1635 * Older kernels are out of luck. */
1636 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
1637 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
1638 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
1641 /* Framebuffer dimensions. */
1642 evergreen_get_scissor_rect(rctx
, 0, 0, state
->width
, state
->height
, &tl
, &br
);
1644 radeon_set_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1645 radeon_emit(cs
, tl
); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1646 radeon_emit(cs
, br
); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1648 if (rctx
->b
.chip_class
== EVERGREEN
) {
1649 evergreen_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
, rctx
->ps_iter_samples
);
1651 unsigned sc_mode_cntl_1
=
1652 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1653 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1655 cayman_emit_msaa_sample_locs(cs
, rctx
->framebuffer
.nr_samples
);
1656 cayman_emit_msaa_config(cs
, rctx
->framebuffer
.nr_samples
,
1657 rctx
->ps_iter_samples
, 0, sc_mode_cntl_1
);
1661 static void evergreen_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
1663 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1664 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
1665 float offset_units
= state
->offset_units
;
1666 float offset_scale
= state
->offset_scale
;
1667 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
1669 if (!state
->offset_units_unscaled
) {
1670 switch (state
->zs_format
) {
1671 case PIPE_FORMAT_Z24X8_UNORM
:
1672 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1673 case PIPE_FORMAT_X8Z24_UNORM
:
1674 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1675 offset_units
*= 2.0f
;
1676 pa_su_poly_offset_db_fmt_cntl
=
1677 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1679 case PIPE_FORMAT_Z16_UNORM
:
1680 offset_units
*= 4.0f
;
1681 pa_su_poly_offset_db_fmt_cntl
=
1682 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1685 pa_su_poly_offset_db_fmt_cntl
=
1686 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1687 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1691 radeon_set_context_reg_seq(cs
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
1692 radeon_emit(cs
, fui(offset_scale
));
1693 radeon_emit(cs
, fui(offset_units
));
1694 radeon_emit(cs
, fui(offset_scale
));
1695 radeon_emit(cs
, fui(offset_units
));
1697 radeon_set_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1698 pa_su_poly_offset_db_fmt_cntl
);
1701 static void evergreen_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1703 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1704 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1705 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1706 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1708 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1709 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1710 /* This must match the used export instructions exactly.
1711 * Other values may lead to undefined behavior and hangs.
1713 radeon_emit(cs
, ps_colormask
); /* R_02823C_CB_SHADER_MASK */
1716 static void evergreen_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1718 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1719 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1721 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1722 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1725 radeon_set_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1726 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1727 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, a
->rsurf
->db_preload_control
);
1728 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1729 reloc_idx
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rtex
->htile_buffer
,
1730 RADEON_USAGE_READWRITE
, RADEON_PRIO_HTILE
);
1731 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1732 radeon_emit(cs
, reloc_idx
);
1734 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, 0);
1735 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0);
1739 static void evergreen_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1741 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1742 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1743 unsigned db_render_control
= 0;
1744 unsigned db_count_control
= 0;
1745 unsigned db_render_override
=
1746 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1747 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1749 if (rctx
->b
.num_occlusion_queries
> 0 &&
1750 !a
->occlusion_queries_disabled
) {
1751 db_count_control
|= S_028004_PERFECT_ZPASS_COUNTS(1);
1752 if (rctx
->b
.chip_class
== CAYMAN
) {
1753 db_count_control
|= S_028004_SAMPLE_RATE(a
->log_samples
);
1755 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1757 db_count_control
|= S_028004_ZPASS_INCREMENT_DISABLE(1);
1760 /* This is to fix a lockup when hyperz and alpha test are enabled at
1761 * the same time somehow GPU get confuse on which order to pick for
1764 if (rctx
->alphatest_state
.sx_alpha_test_control
)
1765 db_render_override
|= S_02800C_FORCE_SHADER_Z_ORDER(1);
1767 if (a
->flush_depthstencil_through_cb
) {
1768 assert(a
->copy_depth
|| a
->copy_stencil
);
1770 db_render_control
|= S_028000_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1771 S_028000_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1772 S_028000_COPY_CENTROID(1) |
1773 S_028000_COPY_SAMPLE(a
->copy_sample
);
1774 } else if (a
->flush_depth_inplace
|| a
->flush_stencil_inplace
) {
1775 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(a
->flush_depth_inplace
) |
1776 S_028000_STENCIL_COMPRESS_DISABLE(a
->flush_stencil_inplace
);
1777 db_render_override
|= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
1779 if (a
->htile_clear
) {
1780 /* FIXME we might want to disable cliprect here */
1781 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(1);
1784 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1785 radeon_emit(cs
, db_render_control
); /* R_028000_DB_RENDER_CONTROL */
1786 radeon_emit(cs
, db_count_control
); /* R_028004_DB_COUNT_CONTROL */
1787 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1788 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1791 static void evergreen_emit_vertex_buffers(struct r600_context
*rctx
,
1792 struct r600_vertexbuf_state
*state
,
1793 unsigned resource_offset
,
1796 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1797 uint32_t dirty_mask
= state
->dirty_mask
;
1799 while (dirty_mask
) {
1800 struct pipe_vertex_buffer
*vb
;
1801 struct r600_resource
*rbuffer
;
1803 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1805 vb
= &state
->vb
[buffer_index
];
1806 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1809 va
= rbuffer
->gpu_address
+ vb
->buffer_offset
;
1811 /* fetch resources start at index 992 */
1812 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1813 radeon_emit(cs
, (resource_offset
+ buffer_index
) * 8);
1814 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1815 radeon_emit(cs
, rbuffer
->b
.b
.width0
- vb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1816 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1817 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1818 S_030008_STRIDE(vb
->stride
) |
1819 S_030008_BASE_ADDRESS_HI(va
>> 32UL));
1820 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1821 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1822 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1823 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1824 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1825 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1826 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1827 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1828 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD7 */
1830 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1831 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1832 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
));
1834 state
->dirty_mask
= 0;
1837 static void evergreen_fs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1839 evergreen_emit_vertex_buffers(rctx
, &rctx
->vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_FS
, 0);
1842 static void evergreen_cs_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
* atom
)
1844 evergreen_emit_vertex_buffers(rctx
, &rctx
->cs_vertex_buffer_state
, EG_FETCH_CONSTANTS_OFFSET_CS
,
1845 RADEON_CP_PACKET3_COMPUTE_MODE
);
1848 static void evergreen_emit_constant_buffers(struct r600_context
*rctx
,
1849 struct r600_constbuf_state
*state
,
1850 unsigned buffer_id_base
,
1851 unsigned reg_alu_constbuf_size
,
1852 unsigned reg_alu_const_cache
,
1855 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1856 uint32_t dirty_mask
= state
->dirty_mask
;
1858 while (dirty_mask
) {
1859 struct pipe_constant_buffer
*cb
;
1860 struct r600_resource
*rbuffer
;
1862 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1863 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1865 cb
= &state
->cb
[buffer_index
];
1866 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1869 va
= rbuffer
->gpu_address
+ cb
->buffer_offset
;
1871 if (!gs_ring_buffer
) {
1872 radeon_set_context_reg_flag(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1873 DIV_ROUND_UP(cb
->buffer_size
, 256), pkt_flags
);
1874 radeon_set_context_reg_flag(cs
, reg_alu_const_cache
+ buffer_index
* 4, va
>> 8,
1878 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1879 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1880 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
1882 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1883 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 8);
1884 radeon_emit(cs
, va
); /* RESOURCEi_WORD0 */
1885 radeon_emit(cs
, rbuffer
->b
.b
.width0
- cb
->buffer_offset
- 1); /* RESOURCEi_WORD1 */
1886 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1887 S_030008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1888 S_030008_STRIDE(gs_ring_buffer
? 4 : 16) |
1889 S_030008_BASE_ADDRESS_HI(va
>> 32UL) |
1890 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT
));
1891 radeon_emit(cs
, /* RESOURCEi_WORD3 */
1892 S_03000C_UNCACHED(gs_ring_buffer
? 1 : 0) |
1893 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X
) |
1894 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y
) |
1895 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z
) |
1896 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W
));
1897 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1898 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1899 radeon_emit(cs
, 0); /* RESOURCEi_WORD6 */
1900 radeon_emit(cs
, /* RESOURCEi_WORD7 */
1901 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER
));
1903 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
1904 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1905 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
1907 dirty_mask
&= ~(1 << buffer_index
);
1909 state
->dirty_mask
= 0;
1912 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
1913 static void evergreen_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1915 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
1916 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
1917 EG_FETCH_CONSTANTS_OFFSET_LS
,
1918 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
1919 R_028F40_ALU_CONST_CACHE_LS_0
,
1920 0 /* PKT3 flags */);
1922 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
1923 EG_FETCH_CONSTANTS_OFFSET_VS
,
1924 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1925 R_028980_ALU_CONST_CACHE_VS_0
,
1926 0 /* PKT3 flags */);
1930 static void evergreen_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1932 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
],
1933 EG_FETCH_CONSTANTS_OFFSET_GS
,
1934 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1935 R_0289C0_ALU_CONST_CACHE_GS_0
,
1936 0 /* PKT3 flags */);
1939 static void evergreen_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1941 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
],
1942 EG_FETCH_CONSTANTS_OFFSET_PS
,
1943 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1944 R_028940_ALU_CONST_CACHE_PS_0
,
1945 0 /* PKT3 flags */);
1948 static void evergreen_emit_cs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1950 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
],
1951 EG_FETCH_CONSTANTS_OFFSET_CS
,
1952 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
,
1953 R_028F40_ALU_CONST_CACHE_LS_0
,
1954 RADEON_CP_PACKET3_COMPUTE_MODE
);
1957 /* tes constants can be emitted to VS or ES - which are common */
1958 static void evergreen_emit_tes_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1960 if (!rctx
->tes_shader
)
1962 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
],
1963 EG_FETCH_CONSTANTS_OFFSET_VS
,
1964 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1965 R_028980_ALU_CONST_CACHE_VS_0
,
1969 static void evergreen_emit_tcs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1971 if (!rctx
->tes_shader
)
1973 evergreen_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
],
1974 EG_FETCH_CONSTANTS_OFFSET_HS
,
1975 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
,
1976 R_028F00_ALU_CONST_CACHE_HS_0
,
1980 static void evergreen_emit_sampler_views(struct r600_context
*rctx
,
1981 struct r600_samplerview_state
*state
,
1982 unsigned resource_id_base
, unsigned pkt_flags
)
1984 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1985 uint32_t dirty_mask
= state
->dirty_mask
;
1987 while (dirty_mask
) {
1988 struct r600_pipe_sampler_view
*rview
;
1989 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1992 rview
= state
->views
[resource_index
];
1995 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 8, 0) | pkt_flags
);
1996 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 8);
1997 radeon_emit_array(cs
, rview
->tex_resource_words
, 8);
1999 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rview
->tex_resource
,
2001 r600_get_sampler_view_priority(rview
->tex_resource
));
2002 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2003 radeon_emit(cs
, reloc
);
2005 if (!rview
->skip_mip_address_reloc
) {
2006 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0) | pkt_flags
);
2007 radeon_emit(cs
, reloc
);
2010 state
->dirty_mask
= 0;
2013 static void evergreen_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2015 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2016 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2017 EG_FETCH_CONSTANTS_OFFSET_LS
+ R600_MAX_CONST_BUFFERS
, 0);
2019 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
,
2020 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2024 static void evergreen_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2026 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
,
2027 EG_FETCH_CONSTANTS_OFFSET_GS
+ R600_MAX_CONST_BUFFERS
, 0);
2030 static void evergreen_emit_tcs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2032 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
,
2033 EG_FETCH_CONSTANTS_OFFSET_HS
+ R600_MAX_CONST_BUFFERS
, 0);
2036 static void evergreen_emit_tes_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2038 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
,
2039 EG_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
, 0);
2042 static void evergreen_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2044 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
,
2045 EG_FETCH_CONSTANTS_OFFSET_PS
+ R600_MAX_CONST_BUFFERS
, 0);
2048 static void evergreen_emit_cs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2050 evergreen_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
,
2051 EG_FETCH_CONSTANTS_OFFSET_CS
+ 2, RADEON_CP_PACKET3_COMPUTE_MODE
);
2054 static void evergreen_emit_sampler_states(struct r600_context
*rctx
,
2055 struct r600_textures_info
*texinfo
,
2056 unsigned resource_id_base
,
2057 unsigned border_index_reg
,
2060 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2061 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2063 while (dirty_mask
) {
2064 struct r600_pipe_sampler_state
*rstate
;
2065 unsigned i
= u_bit_scan(&dirty_mask
);
2067 rstate
= texinfo
->states
.states
[i
];
2070 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0) | pkt_flags
);
2071 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
2072 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
2074 if (rstate
->border_color_use
) {
2075 radeon_set_config_reg_seq(cs
, border_index_reg
, 5);
2077 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
2080 texinfo
->states
.dirty_mask
= 0;
2083 static void evergreen_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2085 if (rctx
->vs_shader
->current
->shader
.vs_as_ls
) {
2086 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 72,
2087 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2089 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18,
2090 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2094 static void evergreen_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2096 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36,
2097 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX
, 0);
2100 static void evergreen_emit_tcs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2102 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
], 54,
2103 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX
, 0);
2106 static void evergreen_emit_tes_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2108 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
], 18,
2109 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, 0);
2112 static void evergreen_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2114 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0,
2115 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, 0);
2118 static void evergreen_emit_cs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2120 evergreen_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
], 90,
2121 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX
,
2122 RADEON_CP_PACKET3_COMPUTE_MODE
);
2125 static void evergreen_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2127 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2128 uint8_t mask
= s
->sample_mask
;
2130 radeon_set_context_reg(rctx
->b
.gfx
.cs
, R_028C3C_PA_SC_AA_MASK
,
2131 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2134 static void cayman_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2136 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2137 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2138 uint16_t mask
= s
->sample_mask
;
2140 radeon_set_context_reg_seq(cs
, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2141 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y0_X1Y0 */
2142 radeon_emit(cs
, mask
| (mask
<< 16)); /* X0Y1_X1Y1 */
2145 static void evergreen_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2147 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2148 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2149 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2151 radeon_set_context_reg(cs
, R_0288A4_SQ_PGM_START_FS
,
2152 (shader
->buffer
->gpu_address
+ shader
->offset
) >> 8);
2153 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2154 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->buffer
,
2156 RADEON_PRIO_INTERNAL_SHADER
));
2159 static void evergreen_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
2161 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2162 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
2164 uint32_t v
= 0, v2
= 0, primid
= 0, tf_param
= 0;
2166 if (rctx
->vs_shader
->current
->shader
.vs_as_gs_a
) {
2167 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2171 if (state
->geom_enable
) {
2174 if (rctx
->gs_shader
->gs_max_out_vertices
<= 128)
2175 cut_val
= V_028A40_GS_CUT_128
;
2176 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 256)
2177 cut_val
= V_028A40_GS_CUT_256
;
2178 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 512)
2179 cut_val
= V_028A40_GS_CUT_512
;
2181 cut_val
= V_028A40_GS_CUT_1024
;
2183 v
= S_028B54_GS_EN(1) |
2184 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2185 if (!rctx
->tes_shader
)
2186 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
2188 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
2189 S_028A40_CUT_MODE(cut_val
);
2191 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2195 if (rctx
->tes_shader
) {
2196 uint32_t type
, partitioning
, topology
;
2197 struct tgsi_shader_info
*info
= &rctx
->tes_shader
->current
->selector
->info
;
2198 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
2199 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
2200 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
2201 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
2202 switch (tes_prim_mode
) {
2203 case PIPE_PRIM_LINES
:
2204 type
= V_028B6C_TESS_ISOLINE
;
2206 case PIPE_PRIM_TRIANGLES
:
2207 type
= V_028B6C_TESS_TRIANGLE
;
2209 case PIPE_PRIM_QUADS
:
2210 type
= V_028B6C_TESS_QUAD
;
2217 switch (tes_spacing
) {
2218 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
2219 partitioning
= V_028B6C_PART_FRAC_ODD
;
2221 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
2222 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2224 case PIPE_TESS_SPACING_EQUAL
:
2225 partitioning
= V_028B6C_PART_INTEGER
;
2233 topology
= V_028B6C_OUTPUT_POINT
;
2234 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
2235 topology
= V_028B6C_OUTPUT_LINE
;
2236 else if (tes_vertex_order_cw
)
2237 /* XXX follow radeonsi and invert */
2238 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2240 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2242 tf_param
= S_028B6C_TYPE(type
) |
2243 S_028B6C_PARTITIONING(partitioning
) |
2244 S_028B6C_TOPOLOGY(topology
);
2247 if (rctx
->tes_shader
) {
2248 v
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2250 if (!state
->geom_enable
)
2251 v
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2253 v
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
2256 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, v
? 1 : 0 );
2257 radeon_set_context_reg(cs
, R_028B54_VGT_SHADER_STAGES_EN
, v
);
2258 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2259 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2260 radeon_set_context_reg(cs
, R_028B6C_VGT_TF_PARAM
, tf_param
);
2263 static void evergreen_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2265 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2266 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2267 struct r600_resource
*rbuffer
;
2269 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2270 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2271 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2273 if (state
->enable
) {
2274 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2275 radeon_set_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
2276 rbuffer
->gpu_address
>> 8);
2277 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2278 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2279 RADEON_USAGE_READWRITE
,
2280 RADEON_PRIO_RINGS_STREAMOUT
));
2281 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2282 state
->esgs_ring
.buffer_size
>> 8);
2284 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2285 radeon_set_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
2286 rbuffer
->gpu_address
>> 8);
2287 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2288 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2289 RADEON_USAGE_READWRITE
,
2290 RADEON_PRIO_RINGS_STREAMOUT
));
2291 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2292 state
->gsvs_ring
.buffer_size
>> 8);
2294 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2295 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2298 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2299 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2300 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2303 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
2304 enum chip_class ctx_chip_class
,
2305 enum radeon_family ctx_family
,
2308 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 2);
2309 r600_store_value(cb
, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2310 /* always set the temp clauses */
2311 r600_store_value(cb
, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2313 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2314 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2315 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2317 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, (1 << 8));
2319 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2320 r600_store_value(cb
, 0);
2321 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2323 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2326 static void cayman_init_atom_start_cs(struct r600_context
*rctx
)
2328 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2331 r600_init_command_buffer(cb
, 338);
2333 /* This must be first. */
2334 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2335 r600_store_value(cb
, 0x80000000);
2336 r600_store_value(cb
, 0x80000000);
2338 /* We're setting config registers here. */
2339 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2340 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2342 /* This enables pipeline stat & streamout queries.
2343 * They are only disabled by blits.
2345 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2346 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2348 cayman_init_common_regs(cb
, rctx
->b
.chip_class
,
2349 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2351 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2352 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2354 /* remove LS/HS from one SIMD for hw workaround */
2355 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
2356 r600_store_value(cb
, 0xffffffff);
2357 r600_store_value(cb
, 0xffffffff);
2358 r600_store_value(cb
, 0xfffffffe);
2360 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2361 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2362 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2363 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2364 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2365 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2366 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2368 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2369 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2370 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2371 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2372 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2374 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2375 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2376 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2377 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2378 r600_store_value(cb
, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2379 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2380 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2381 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2382 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2383 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2384 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2385 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2386 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2387 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2389 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2391 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2393 r600_store_context_reg_seq(cb
, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
2394 r600_store_value(cb
, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2395 r600_store_value(cb
, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2397 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
2398 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
2399 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2401 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2403 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2404 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2405 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2407 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2409 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2411 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2413 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2414 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2415 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2416 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2418 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2419 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2421 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * R600_MAX_VIEWPORTS
);
2422 for (tmp
= 0; tmp
< R600_MAX_VIEWPORTS
; tmp
++) {
2423 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2424 r600_store_value(cb
, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2427 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2428 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2430 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2431 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2432 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2434 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2435 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2436 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2438 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2439 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2440 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2441 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2442 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2443 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2445 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2447 /* to avoid GPU doing any preloading of constant from random address */
2448 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2449 for (i
= 0; i
< 16; i
++)
2450 r600_store_value(cb
, 0);
2452 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2453 for (i
= 0; i
< 16; i
++)
2454 r600_store_value(cb
, 0);
2456 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2457 for (i
= 0; i
< 16; i
++)
2458 r600_store_value(cb
, 0);
2460 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
2461 for (i
= 0; i
< 16; i
++)
2462 r600_store_value(cb
, 0);
2464 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
2465 for (i
= 0; i
< 16; i
++)
2466 r600_store_value(cb
, 0);
2468 if (rctx
->screen
->b
.has_streamout
) {
2469 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2472 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2473 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2474 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2475 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2476 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2477 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2479 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
2480 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2481 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
2482 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
2483 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2484 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2485 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2486 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
2487 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
2490 void evergreen_init_common_regs(struct r600_context
*rctx
, struct r600_command_buffer
*cb
,
2491 enum chip_class ctx_chip_class
,
2492 enum radeon_family ctx_family
,
2514 rctx
->default_gprs
[R600_HW_STAGE_PS
] = 93;
2515 rctx
->default_gprs
[R600_HW_STAGE_VS
] = 46;
2516 rctx
->r6xx_num_clause_temp_gprs
= 4;
2517 rctx
->default_gprs
[R600_HW_STAGE_GS
] = 31;
2518 rctx
->default_gprs
[R600_HW_STAGE_ES
] = 31;
2519 rctx
->default_gprs
[EG_HW_STAGE_HS
] = 23;
2520 rctx
->default_gprs
[EG_HW_STAGE_LS
] = 23;
2523 switch (ctx_family
) {
2531 tmp
|= S_008C00_VC_ENABLE(1);
2534 tmp
|= S_008C00_EXPORT_SRC_C(1);
2535 tmp
|= S_008C00_CS_PRIO(cs_prio
);
2536 tmp
|= S_008C00_LS_PRIO(ls_prio
);
2537 tmp
|= S_008C00_HS_PRIO(hs_prio
);
2538 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2539 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2540 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2541 tmp
|= S_008C00_ES_PRIO(es_prio
);
2543 r600_store_config_reg_seq(cb
, R_008C00_SQ_CONFIG
, 1);
2544 r600_store_value(cb
, tmp
); /* R_008C00_SQ_CONFIG */
2546 r600_store_config_reg_seq(cb
, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1
, 2);
2547 r600_store_value(cb
, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2548 r600_store_value(cb
, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2550 /* The cs checker requires this register to be set. */
2551 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2553 r600_store_context_reg_seq(cb
, R_028350_SX_MISC
, 2);
2554 r600_store_value(cb
, 0);
2555 r600_store_value(cb
, S_028354_SURFACE_SYNC_MASK(0xf));
2560 void evergreen_init_atom_start_cs(struct r600_context
*rctx
)
2562 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2570 int num_ps_stack_entries
;
2571 int num_vs_stack_entries
;
2572 int num_gs_stack_entries
;
2573 int num_es_stack_entries
;
2574 int num_hs_stack_entries
;
2575 int num_ls_stack_entries
;
2576 enum radeon_family family
;
2579 if (rctx
->b
.chip_class
== CAYMAN
) {
2580 cayman_init_atom_start_cs(rctx
);
2584 r600_init_command_buffer(cb
, 338);
2586 /* This must be first. */
2587 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2588 r600_store_value(cb
, 0x80000000);
2589 r600_store_value(cb
, 0x80000000);
2591 /* We're setting config registers here. */
2592 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2593 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2595 /* This enables pipeline stat & streamout queries.
2596 * They are only disabled by blits.
2598 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2599 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2601 evergreen_init_common_regs(rctx
, cb
, rctx
->b
.chip_class
,
2602 rctx
->b
.family
, rctx
->screen
->b
.info
.drm_minor
);
2604 family
= rctx
->b
.family
;
2608 num_ps_threads
= 96;
2609 num_vs_threads
= 16;
2610 num_gs_threads
= 16;
2611 num_es_threads
= 16;
2612 num_hs_threads
= 16;
2613 num_ls_threads
= 16;
2614 num_ps_stack_entries
= 42;
2615 num_vs_stack_entries
= 42;
2616 num_gs_stack_entries
= 42;
2617 num_es_stack_entries
= 42;
2618 num_hs_stack_entries
= 42;
2619 num_ls_stack_entries
= 42;
2622 num_ps_threads
= 128;
2623 num_vs_threads
= 20;
2624 num_gs_threads
= 20;
2625 num_es_threads
= 20;
2626 num_hs_threads
= 20;
2627 num_ls_threads
= 20;
2628 num_ps_stack_entries
= 42;
2629 num_vs_stack_entries
= 42;
2630 num_gs_stack_entries
= 42;
2631 num_es_stack_entries
= 42;
2632 num_hs_stack_entries
= 42;
2633 num_ls_stack_entries
= 42;
2636 num_ps_threads
= 128;
2637 num_vs_threads
= 20;
2638 num_gs_threads
= 20;
2639 num_es_threads
= 20;
2640 num_hs_threads
= 20;
2641 num_ls_threads
= 20;
2642 num_ps_stack_entries
= 85;
2643 num_vs_stack_entries
= 85;
2644 num_gs_stack_entries
= 85;
2645 num_es_stack_entries
= 85;
2646 num_hs_stack_entries
= 85;
2647 num_ls_stack_entries
= 85;
2651 num_ps_threads
= 128;
2652 num_vs_threads
= 20;
2653 num_gs_threads
= 20;
2654 num_es_threads
= 20;
2655 num_hs_threads
= 20;
2656 num_ls_threads
= 20;
2657 num_ps_stack_entries
= 85;
2658 num_vs_stack_entries
= 85;
2659 num_gs_stack_entries
= 85;
2660 num_es_stack_entries
= 85;
2661 num_hs_stack_entries
= 85;
2662 num_ls_stack_entries
= 85;
2665 num_ps_threads
= 96;
2666 num_vs_threads
= 16;
2667 num_gs_threads
= 16;
2668 num_es_threads
= 16;
2669 num_hs_threads
= 16;
2670 num_ls_threads
= 16;
2671 num_ps_stack_entries
= 42;
2672 num_vs_stack_entries
= 42;
2673 num_gs_stack_entries
= 42;
2674 num_es_stack_entries
= 42;
2675 num_hs_stack_entries
= 42;
2676 num_ls_stack_entries
= 42;
2679 num_ps_threads
= 96;
2680 num_vs_threads
= 25;
2681 num_gs_threads
= 25;
2682 num_es_threads
= 25;
2683 num_hs_threads
= 16;
2684 num_ls_threads
= 16;
2685 num_ps_stack_entries
= 42;
2686 num_vs_stack_entries
= 42;
2687 num_gs_stack_entries
= 42;
2688 num_es_stack_entries
= 42;
2689 num_hs_stack_entries
= 42;
2690 num_ls_stack_entries
= 42;
2693 num_ps_threads
= 96;
2694 num_vs_threads
= 25;
2695 num_gs_threads
= 25;
2696 num_es_threads
= 25;
2697 num_hs_threads
= 16;
2698 num_ls_threads
= 16;
2699 num_ps_stack_entries
= 85;
2700 num_vs_stack_entries
= 85;
2701 num_gs_stack_entries
= 85;
2702 num_es_stack_entries
= 85;
2703 num_hs_stack_entries
= 85;
2704 num_ls_stack_entries
= 85;
2707 num_ps_threads
= 128;
2708 num_vs_threads
= 20;
2709 num_gs_threads
= 20;
2710 num_es_threads
= 20;
2711 num_hs_threads
= 20;
2712 num_ls_threads
= 20;
2713 num_ps_stack_entries
= 85;
2714 num_vs_stack_entries
= 85;
2715 num_gs_stack_entries
= 85;
2716 num_es_stack_entries
= 85;
2717 num_hs_stack_entries
= 85;
2718 num_ls_stack_entries
= 85;
2721 num_ps_threads
= 128;
2722 num_vs_threads
= 20;
2723 num_gs_threads
= 20;
2724 num_es_threads
= 20;
2725 num_hs_threads
= 20;
2726 num_ls_threads
= 20;
2727 num_ps_stack_entries
= 42;
2728 num_vs_stack_entries
= 42;
2729 num_gs_stack_entries
= 42;
2730 num_es_stack_entries
= 42;
2731 num_hs_stack_entries
= 42;
2732 num_ls_stack_entries
= 42;
2735 num_ps_threads
= 96;
2736 num_vs_threads
= 10;
2737 num_gs_threads
= 10;
2738 num_es_threads
= 10;
2739 num_hs_threads
= 10;
2740 num_ls_threads
= 10;
2741 num_ps_stack_entries
= 42;
2742 num_vs_stack_entries
= 42;
2743 num_gs_stack_entries
= 42;
2744 num_es_stack_entries
= 42;
2745 num_hs_stack_entries
= 42;
2746 num_ls_stack_entries
= 42;
2750 tmp
= S_008C18_NUM_PS_THREADS(num_ps_threads
);
2751 tmp
|= S_008C18_NUM_VS_THREADS(num_vs_threads
);
2752 tmp
|= S_008C18_NUM_GS_THREADS(num_gs_threads
);
2753 tmp
|= S_008C18_NUM_ES_THREADS(num_es_threads
);
2755 r600_store_config_reg_seq(cb
, R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 5);
2756 r600_store_value(cb
, tmp
); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2758 tmp
= S_008C1C_NUM_HS_THREADS(num_hs_threads
);
2759 tmp
|= S_008C1C_NUM_LS_THREADS(num_ls_threads
);
2760 r600_store_value(cb
, tmp
); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2762 tmp
= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2763 tmp
|= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2764 r600_store_value(cb
, tmp
); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2766 tmp
= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2767 tmp
|= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2768 r600_store_value(cb
, tmp
); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2770 tmp
= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries
);
2771 tmp
|= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries
);
2772 r600_store_value(cb
, tmp
); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2774 r600_store_config_reg(cb
, R_008E2C_SQ_LDS_RESOURCE_MGMT
,
2775 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2777 /* remove LS/HS from one SIMD for hw workaround */
2778 r600_store_config_reg_seq(cb
, R_008E20_SQ_STATIC_THREAD_MGMT1
, 3);
2779 r600_store_value(cb
, 0xffffffff);
2780 r600_store_value(cb
, 0xffffffff);
2781 r600_store_value(cb
, 0xfffffffe);
2783 r600_store_config_reg(cb
, R_009100_SPI_CONFIG_CNTL
, 0);
2784 r600_store_config_reg(cb
, R_00913C_SPI_CONFIG_CNTL_1
, S_00913C_VTX_DONE_DELAY(4));
2786 r600_store_context_reg_seq(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
, 6);
2787 r600_store_value(cb
, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2788 r600_store_value(cb
, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2789 r600_store_value(cb
, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2790 r600_store_value(cb
, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2791 r600_store_value(cb
, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2792 r600_store_value(cb
, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2794 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
2795 r600_store_value(cb
, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2796 r600_store_value(cb
, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2797 r600_store_value(cb
, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2798 r600_store_value(cb
, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2800 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2801 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2802 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2803 r600_store_value(cb
, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2804 r600_store_value(cb
, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2805 r600_store_value(cb
, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2806 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2807 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2808 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2809 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2810 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2811 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2812 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2813 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE */
2815 r600_store_config_reg(cb
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2817 r600_store_context_reg(cb
, R_0288F0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2819 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2820 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2821 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2823 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2825 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2827 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2828 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2829 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2831 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * R600_MAX_VIEWPORTS
);
2832 for (tmp
= 0; tmp
< R600_MAX_VIEWPORTS
; tmp
++) {
2833 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2834 r600_store_value(cb
, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2837 r600_store_context_reg(cb
, R_0286DC_SPI_FOG_CNTL
, 0);
2838 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2840 r600_store_context_reg_seq(cb
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 3);
2841 r600_store_value(cb
, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2842 r600_store_value(cb
, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2843 r600_store_value(cb
, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2845 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2846 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2847 r600_store_value(cb
, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2849 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2850 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2851 r600_store_value(cb
, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2853 r600_store_context_reg(cb
, R_028848_SQ_PGM_RESOURCES_2_PS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2854 r600_store_context_reg(cb
, R_028864_SQ_PGM_RESOURCES_2_VS
, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2855 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_2_GS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2856 r600_store_context_reg(cb
, R_028894_SQ_PGM_RESOURCES_2_ES
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2857 r600_store_context_reg(cb
, R_0288A8_SQ_PGM_RESOURCES_FS
, 0);
2858 r600_store_context_reg(cb
, R_0288C0_SQ_PGM_RESOURCES_2_HS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2859 r600_store_context_reg(cb
, R_0288D8_SQ_PGM_RESOURCES_2_LS
, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN
));
2861 /* to avoid GPU doing any preloading of constant from random address */
2862 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2863 for (i
= 0; i
< 16; i
++)
2864 r600_store_value(cb
, 0);
2866 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2867 for (i
= 0; i
< 16; i
++)
2868 r600_store_value(cb
, 0);
2870 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2871 for (i
= 0; i
< 16; i
++)
2872 r600_store_value(cb
, 0);
2874 r600_store_context_reg_seq(cb
, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0
, 16);
2875 for (i
= 0; i
< 16; i
++)
2876 r600_store_value(cb
, 0);
2878 r600_store_context_reg_seq(cb
, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0
, 16);
2879 for (i
= 0; i
< 16; i
++)
2880 r600_store_value(cb
, 0);
2882 r600_store_context_reg(cb
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0);
2884 if (rctx
->screen
->b
.has_streamout
) {
2885 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2888 r600_store_context_reg(cb
, R_028010_DB_RENDER_OVERRIDE2
, 0);
2889 r600_store_context_reg(cb
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
2890 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2891 r600_store_context_reg_seq(cb
, R_0286E4_SPI_PS_IN_CONTROL_2
, 2);
2892 r600_store_value(cb
, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2893 r600_store_value(cb
, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2895 r600_store_context_reg_seq(cb
, R_0288E8_SQ_LDS_ALLOC
, 2);
2896 r600_store_value(cb
, 0); /* R_0288E8_SQ_LDS_ALLOC */
2897 r600_store_value(cb
, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2899 if (rctx
->b
.family
== CHIP_CAICOS
) {
2900 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 2);
2901 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2902 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
2903 r600_store_context_reg(cb
, R_028B6C_VGT_TF_PARAM
, 0);
2905 r600_store_context_reg_seq(cb
, R_028B54_VGT_SHADER_STAGES_EN
, 7);
2906 r600_store_value(cb
, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2907 r600_store_value(cb
, 0); /* R028B58_VGT_LS_HS_CONFIG */
2908 r600_store_value(cb
, 0); /* R028B5C_VGT_LS_SIZE */
2909 r600_store_value(cb
, 0); /* R028B60_VGT_HS_SIZE */
2910 r600_store_value(cb
, 0); /* R028B64_VGT_LS_HS_ALLOC */
2911 r600_store_value(cb
, 0); /* R028B68_VGT_HS_PATCH_CONST */
2912 r600_store_value(cb
, 0); /* R028B68_VGT_TF_PARAM */
2915 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
, 0x01000FFF);
2916 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF);
2917 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (64 * 4), 0x01000FFF);
2918 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (96 * 4), 0x01000FFF);
2919 eg_store_loop_const(cb
, R_03A200_SQ_LOOP_CONST_0
+ (128 * 4), 0x01000FFF);
2922 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2924 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2925 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2926 struct r600_shader
*rshader
= &shader
->shader
;
2927 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
= 0;
2928 int pos_index
= -1, face_index
= -1, fixed_pt_position_index
= -1;
2930 boolean have_perspective
= FALSE
, have_linear
= FALSE
;
2931 static const unsigned spi_baryc_enable_bit
[6] = {
2932 S_0286E0_PERSP_SAMPLE_ENA(1),
2933 S_0286E0_PERSP_CENTER_ENA(1),
2934 S_0286E0_PERSP_CENTROID_ENA(1),
2935 S_0286E0_LINEAR_SAMPLE_ENA(1),
2936 S_0286E0_LINEAR_CENTER_ENA(1),
2937 S_0286E0_LINEAR_CENTROID_ENA(1)
2939 unsigned spi_baryc_cntl
= 0, sid
, tmp
, num
= 0;
2940 unsigned z_export
= 0, stencil_export
= 0, mask_export
= 0;
2941 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2942 uint32_t spi_ps_input_cntl
[32];
2945 r600_init_command_buffer(cb
, 64);
2950 for (i
= 0; i
< rshader
->ninput
; i
++) {
2951 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2952 POSITION goes via GPRs from the SC so isn't counted */
2953 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2955 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
) {
2956 if (face_index
== -1)
2959 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
2960 if (face_index
== -1)
2961 face_index
= i
; /* lives in same register, same enable bit */
2963 else if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEID
) {
2964 fixed_pt_position_index
= i
;
2968 int k
= eg_get_interpolator_index(
2969 rshader
->input
[i
].interpolate
,
2970 rshader
->input
[i
].interpolate_location
);
2972 spi_baryc_cntl
|= spi_baryc_enable_bit
[k
];
2973 have_perspective
|= k
< 3;
2974 have_linear
|= !(k
< 3);
2978 sid
= rshader
->input
[i
].spi_sid
;
2981 tmp
= S_028644_SEMANTIC(sid
);
2983 /* D3D 9 behaviour. GL is undefined */
2984 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
&& rshader
->input
[i
].sid
== 0)
2985 tmp
|= S_028644_DEFAULT_VAL(3);
2987 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2988 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2989 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2990 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
2991 tmp
|= S_028644_FLAT_SHADE(1);
2994 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2995 (sprite_coord_enable
& (1 << rshader
->input
[i
].sid
))) {
2996 tmp
|= S_028644_PT_SPRITE_TEX(1);
2999 spi_ps_input_cntl
[num
++] = tmp
;
3003 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, num
);
3004 r600_store_array(cb
, num
, spi_ps_input_cntl
);
3006 for (i
= 0; i
< rshader
->noutput
; i
++) {
3007 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
3009 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
3011 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
&&
3012 rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0)
3015 if (rshader
->uses_kill
)
3016 db_shader_control
|= S_02880C_KILL_ENABLE(1);
3018 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
3019 db_shader_control
|= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export
);
3020 db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(mask_export
);
3022 switch (rshader
->ps_conservative_z
) {
3023 default: /* fall through */
3024 case TGSI_FS_DEPTH_LAYOUT_ANY
:
3025 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z
);
3027 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
3028 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
3030 case TGSI_FS_DEPTH_LAYOUT_LESS
:
3031 db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
3036 for (i
= 0; i
< rshader
->noutput
; i
++) {
3037 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
3038 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
||
3039 rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
)
3043 num_cout
= rshader
->nr_ps_color_exports
;
3045 exports_ps
|= S_02884C_EXPORT_COLORS(num_cout
);
3047 /* always at least export 1 component per pixel */
3050 shader
->nr_ps_color_outputs
= num_cout
;
3053 have_perspective
= TRUE
;
3055 if (!spi_baryc_cntl
)
3056 spi_baryc_cntl
|= spi_baryc_enable_bit
[0];
3058 if (!have_perspective
&& !have_linear
)
3059 have_perspective
= TRUE
;
3061 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(ninterp
) |
3062 S_0286CC_PERSP_GRADIENT_ENA(have_perspective
) |
3063 S_0286CC_LINEAR_GRADIENT_ENA(have_linear
);
3065 if (pos_index
!= -1) {
3066 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
3067 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
) |
3068 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
);
3069 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
3072 spi_ps_in_control_1
= 0;
3073 if (face_index
!= -1) {
3074 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
3075 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
3077 if (fixed_pt_position_index
!= -1) {
3078 spi_ps_in_control_1
|= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3079 S_0286D0_FIXED_PT_POSITION_ADDR(rshader
->input
[fixed_pt_position_index
].gpr
);
3082 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
3083 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3084 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3086 r600_store_context_reg(cb
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
3087 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
3088 r600_store_context_reg(cb
, R_02884C_SQ_PGM_EXPORTS_PS
, exports_ps
);
3090 r600_store_context_reg_seq(cb
, R_028840_SQ_PGM_START_PS
, 2);
3091 r600_store_value(cb
, shader
->bo
->gpu_address
>> 8);
3092 r600_store_value(cb
, /* R_028844_SQ_PGM_RESOURCES_PS */
3093 S_028844_NUM_GPRS(rshader
->bc
.ngpr
) |
3094 S_028844_PRIME_CACHE_ON_DRAW(1) |
3095 S_028844_STACK_SIZE(rshader
->bc
.nstack
));
3096 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3098 shader
->db_shader_control
= db_shader_control
;
3099 shader
->ps_depth_export
= z_export
| stencil_export
| mask_export
;
3101 shader
->sprite_coord_enable
= sprite_coord_enable
;
3102 if (rctx
->rasterizer
)
3103 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
3106 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3108 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3109 struct r600_shader
*rshader
= &shader
->shader
;
3111 r600_init_command_buffer(cb
, 32);
3113 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
3114 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
3115 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
3116 r600_store_context_reg(cb
, R_02888C_SQ_PGM_START_ES
,
3117 shader
->bo
->gpu_address
>> 8);
3118 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3121 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3123 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3124 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3125 struct r600_shader
*rshader
= &shader
->shader
;
3126 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
3127 unsigned gsvs_itemsizes
[4] = {
3128 (cp_shader
->ring_item_sizes
[0] * shader
->selector
->gs_max_out_vertices
) >> 2,
3129 (cp_shader
->ring_item_sizes
[1] * shader
->selector
->gs_max_out_vertices
) >> 2,
3130 (cp_shader
->ring_item_sizes
[2] * shader
->selector
->gs_max_out_vertices
) >> 2,
3131 (cp_shader
->ring_item_sizes
[3] * shader
->selector
->gs_max_out_vertices
) >> 2
3134 r600_init_command_buffer(cb
, 64);
3136 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3139 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
3140 S_028B38_MAX_VERT_OUT(shader
->selector
->gs_max_out_vertices
));
3141 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
3142 r600_conv_prim_to_gs_out(shader
->selector
->gs_output_prim
));
3144 if (rctx
->screen
->b
.info
.drm_minor
>= 35) {
3145 r600_store_context_reg(cb
, R_028B90_VGT_GS_INSTANCE_CNT
,
3146 S_028B90_CNT(MIN2(shader
->selector
->gs_num_invocations
, 127)) |
3147 S_028B90_ENABLE(shader
->selector
->gs_num_invocations
> 0));
3149 r600_store_context_reg_seq(cb
, R_02891C_SQ_GS_VERT_ITEMSIZE
, 4);
3150 r600_store_value(cb
, cp_shader
->ring_item_sizes
[0] >> 2);
3151 r600_store_value(cb
, cp_shader
->ring_item_sizes
[1] >> 2);
3152 r600_store_value(cb
, cp_shader
->ring_item_sizes
[2] >> 2);
3153 r600_store_value(cb
, cp_shader
->ring_item_sizes
[3] >> 2);
3155 r600_store_context_reg(cb
, R_028900_SQ_ESGS_RING_ITEMSIZE
,
3156 (rshader
->ring_item_sizes
[0]) >> 2);
3158 r600_store_context_reg(cb
, R_028904_SQ_GSVS_RING_ITEMSIZE
,
3164 r600_store_context_reg_seq(cb
, R_02892C_SQ_GSVS_RING_OFFSET_1
, 3);
3165 r600_store_value(cb
, gsvs_itemsizes
[0]);
3166 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1]);
3167 r600_store_value(cb
, gsvs_itemsizes
[0] + gsvs_itemsizes
[1] + gsvs_itemsizes
[2]);
3169 /* FIXME calculate these values somehow ??? */
3170 r600_store_context_reg_seq(cb
, R_028A54_GS_PER_ES
, 3);
3171 r600_store_value(cb
, 0x80); /* GS_PER_ES */
3172 r600_store_value(cb
, 0x100); /* ES_PER_GS */
3173 r600_store_value(cb
, 0x2); /* GS_PER_VS */
3175 r600_store_context_reg(cb
, R_028878_SQ_PGM_RESOURCES_GS
,
3176 S_028878_NUM_GPRS(rshader
->bc
.ngpr
) |
3177 S_028878_STACK_SIZE(rshader
->bc
.nstack
));
3178 r600_store_context_reg(cb
, R_028874_SQ_PGM_START_GS
,
3179 shader
->bo
->gpu_address
>> 8);
3180 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3184 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3186 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3187 struct r600_shader
*rshader
= &shader
->shader
;
3188 unsigned spi_vs_out_id
[10] = {};
3189 unsigned i
, tmp
, nparams
= 0;
3191 for (i
= 0; i
< rshader
->noutput
; i
++) {
3192 if (rshader
->output
[i
].spi_sid
) {
3193 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
3194 spi_vs_out_id
[nparams
/ 4] |= tmp
;
3199 r600_init_command_buffer(cb
, 32);
3201 r600_store_context_reg_seq(cb
, R_02861C_SPI_VS_OUT_ID_0
, 10);
3202 for (i
= 0; i
< 10; i
++) {
3203 r600_store_value(cb
, spi_vs_out_id
[i
]);
3206 /* Certain attributes (position, psize, etc.) don't count as params.
3207 * VS is required to export at least one param and r600_shader_from_tgsi()
3208 * takes care of adding a dummy export.
3213 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
3214 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
3215 r600_store_context_reg(cb
, R_028860_SQ_PGM_RESOURCES_VS
,
3216 S_028860_NUM_GPRS(rshader
->bc
.ngpr
) |
3217 S_028860_STACK_SIZE(rshader
->bc
.nstack
));
3218 if (rshader
->vs_position_window_space
) {
3219 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3220 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3222 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
3223 S_028818_VTX_W0_FMT(1) |
3224 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3225 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3226 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3229 r600_store_context_reg(cb
, R_02885C_SQ_PGM_START_VS
,
3230 shader
->bo
->gpu_address
>> 8);
3231 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3233 shader
->pa_cl_vs_out_cntl
=
3234 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
3235 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
3236 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
3237 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
3238 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
3239 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
) |
3240 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
);
3243 void evergreen_update_hs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3245 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3246 struct r600_shader
*rshader
= &shader
->shader
;
3248 r600_init_command_buffer(cb
, 32);
3249 r600_store_context_reg(cb
, R_0288BC_SQ_PGM_RESOURCES_HS
,
3250 S_0288BC_NUM_GPRS(rshader
->bc
.ngpr
) |
3251 S_0288BC_STACK_SIZE(rshader
->bc
.nstack
));
3252 r600_store_context_reg(cb
, R_0288B8_SQ_PGM_START_HS
,
3253 shader
->bo
->gpu_address
>> 8);
3256 void evergreen_update_ls_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
3258 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
3259 struct r600_shader
*rshader
= &shader
->shader
;
3261 r600_init_command_buffer(cb
, 32);
3262 r600_store_context_reg(cb
, R_0288D4_SQ_PGM_RESOURCES_LS
,
3263 S_0288D4_NUM_GPRS(rshader
->bc
.ngpr
) |
3264 S_0288D4_STACK_SIZE(rshader
->bc
.nstack
));
3265 r600_store_context_reg(cb
, R_0288D0_SQ_PGM_START_LS
,
3266 shader
->bo
->gpu_address
>> 8);
3268 void *evergreen_create_resolve_blend(struct r600_context
*rctx
)
3270 struct pipe_blend_state blend
;
3272 memset(&blend
, 0, sizeof(blend
));
3273 blend
.independent_blend_enable
= true;
3274 blend
.rt
[0].colormask
= 0xf;
3275 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_CB_RESOLVE
);
3278 void *evergreen_create_decompress_blend(struct r600_context
*rctx
)
3280 struct pipe_blend_state blend
;
3281 unsigned mode
= rctx
->screen
->has_compressed_msaa_texturing
?
3282 V_028808_CB_FMASK_DECOMPRESS
: V_028808_CB_DECOMPRESS
;
3284 memset(&blend
, 0, sizeof(blend
));
3285 blend
.independent_blend_enable
= true;
3286 blend
.rt
[0].colormask
= 0xf;
3287 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3290 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
)
3292 struct pipe_blend_state blend
;
3293 unsigned mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
;
3295 memset(&blend
, 0, sizeof(blend
));
3296 blend
.independent_blend_enable
= true;
3297 blend
.rt
[0].colormask
= 0xf;
3298 return evergreen_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3301 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
)
3303 struct pipe_depth_stencil_alpha_state dsa
= {{0}};
3305 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
3308 void evergreen_update_db_shader_control(struct r600_context
* rctx
)
3311 unsigned db_shader_control
;
3313 if (!rctx
->ps_shader
) {
3317 dual_export
= rctx
->framebuffer
.export_16bpc
&&
3318 !rctx
->ps_shader
->current
->ps_depth_export
;
3320 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
3321 S_02880C_DUAL_EXPORT_ENABLE(dual_export
) |
3322 S_02880C_DB_SOURCE_FORMAT(dual_export
? V_02880C_EXPORT_DB_TWO
:
3323 V_02880C_EXPORT_DB_FULL
) |
3324 S_02880C_ALPHA_TO_MASK_DISABLE(rctx
->framebuffer
.cb0_is_integer
);
3326 /* When alpha test is enabled we can't trust the hw to make the proper
3327 * decision on the order in which ztest should be run related to fragment
3330 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3331 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3332 * execution and thus after alpha test so if discarded by the alpha test
3333 * the z value is not written.
3334 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3335 * get a hang unless you flush the DB in between. For now just use
3338 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3339 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3341 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3344 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3345 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3346 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3350 static void evergreen_dma_copy_tile(struct r600_context
*rctx
,
3351 struct pipe_resource
*dst
,
3356 struct pipe_resource
*src
,
3361 unsigned copy_height
,
3365 struct radeon_winsys_cs
*cs
= rctx
->b
.dma
.cs
;
3366 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3367 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3368 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3369 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3370 unsigned sub_cmd
, bank_h
, bank_w
, mt_aspect
, nbanks
, tile_split
, non_disp_tiling
= 0;
3371 uint64_t base
, addr
;
3373 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3374 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3375 assert(dst_mode
!= src_mode
);
3377 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3378 if (util_format_has_depth(util_format_description(src
->format
)))
3379 non_disp_tiling
= 1;
3382 sub_cmd
= EG_DMA_COPY_TILED
;
3383 lbpp
= util_logbase2(bpp
);
3384 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
3385 nbanks
= eg_num_banks(rctx
->screen
->b
.info
.r600_num_banks
);
3387 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
) {
3389 array_mode
= evergreen_array_mode(src_mode
);
3390 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
3391 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3392 /* linear height must be the same as the slice tile max height, it's ok even
3393 * if the linear destination/source have smaller heigh as the size of the
3394 * dma packet will be using the copy_height which is always smaller or equal
3395 * to the linear height
3397 height
= rsrc
->surface
.level
[src_level
].npix_y
;
3402 base
= rsrc
->surface
.level
[src_level
].offset
;
3403 addr
= rdst
->surface
.level
[dst_level
].offset
;
3404 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3405 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3406 bank_h
= eg_bank_wh(rsrc
->surface
.bankh
);
3407 bank_w
= eg_bank_wh(rsrc
->surface
.bankw
);
3408 mt_aspect
= eg_macro_tile_aspect(rsrc
->surface
.mtilea
);
3409 tile_split
= eg_tile_split(rsrc
->surface
.tile_split
);
3410 base
+= rsrc
->resource
.gpu_address
;
3411 addr
+= rdst
->resource
.gpu_address
;
3414 array_mode
= evergreen_array_mode(dst_mode
);
3415 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
3416 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3417 /* linear height must be the same as the slice tile max height, it's ok even
3418 * if the linear destination/source have smaller heigh as the size of the
3419 * dma packet will be using the copy_height which is always smaller or equal
3420 * to the linear height
3422 height
= rdst
->surface
.level
[dst_level
].npix_y
;
3427 base
= rdst
->surface
.level
[dst_level
].offset
;
3428 addr
= rsrc
->surface
.level
[src_level
].offset
;
3429 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
3430 addr
+= src_y
* pitch
+ src_x
* bpp
;
3431 bank_h
= eg_bank_wh(rdst
->surface
.bankh
);
3432 bank_w
= eg_bank_wh(rdst
->surface
.bankw
);
3433 mt_aspect
= eg_macro_tile_aspect(rdst
->surface
.mtilea
);
3434 tile_split
= eg_tile_split(rdst
->surface
.tile_split
);
3435 base
+= rdst
->resource
.gpu_address
;
3436 addr
+= rsrc
->resource
.gpu_address
;
3439 size
= (copy_height
* pitch
) / 4;
3440 ncopy
= (size
/ EG_DMA_COPY_MAX_SIZE
) + !!(size
% EG_DMA_COPY_MAX_SIZE
);
3441 r600_need_dma_space(&rctx
->b
, ncopy
* 9, &rdst
->resource
, &rsrc
->resource
);
3443 for (i
= 0; i
< ncopy
; i
++) {
3444 cheight
= copy_height
;
3445 if (((cheight
* pitch
) / 4) > EG_DMA_COPY_MAX_SIZE
) {
3446 cheight
= (EG_DMA_COPY_MAX_SIZE
* 4) / pitch
;
3448 size
= (cheight
* pitch
) / 4;
3449 /* emit reloc before writing cs so that cs is always in consistent state */
3450 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rsrc
->resource
,
3451 RADEON_USAGE_READ
, RADEON_PRIO_SDMA_TEXTURE
);
3452 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rdst
->resource
,
3453 RADEON_USAGE_WRITE
, RADEON_PRIO_SDMA_TEXTURE
);
3454 radeon_emit(cs
, DMA_PACKET(DMA_PACKET_COPY
, sub_cmd
, size
));
3455 radeon_emit(cs
, base
>> 8);
3456 radeon_emit(cs
, (detile
<< 31) | (array_mode
<< 27) |
3457 (lbpp
<< 24) | (bank_h
<< 21) |
3458 (bank_w
<< 18) | (mt_aspect
<< 16));
3459 radeon_emit(cs
, (pitch_tile_max
<< 0) | ((height
- 1) << 16));
3460 radeon_emit(cs
, (slice_tile_max
<< 0));
3461 radeon_emit(cs
, (x
<< 0) | (z
<< 18));
3462 radeon_emit(cs
, (y
<< 0) | (tile_split
<< 21) | (nbanks
<< 25) | (non_disp_tiling
<< 28));
3463 radeon_emit(cs
, addr
& 0xfffffffc);
3464 radeon_emit(cs
, (addr
>> 32UL) & 0xff);
3465 copy_height
-= cheight
;
3466 addr
+= cheight
* pitch
;
3469 r600_dma_emit_wait_idle(&rctx
->b
);
3472 static void evergreen_dma_copy(struct pipe_context
*ctx
,
3473 struct pipe_resource
*dst
,
3475 unsigned dstx
, unsigned dsty
, unsigned dstz
,
3476 struct pipe_resource
*src
,
3478 const struct pipe_box
*src_box
)
3480 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3481 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3482 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3483 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3484 unsigned src_w
, dst_w
;
3485 unsigned src_x
, src_y
;
3486 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3488 if (rctx
->b
.dma
.cs
== NULL
) {
3492 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3493 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3497 if (src_box
->depth
> 1 ||
3498 !r600_prepare_for_dma_blit(&rctx
->b
, rdst
, dst_level
, dstx
, dsty
,
3499 dstz
, rsrc
, src_level
, src_box
))
3502 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3503 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3504 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3505 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3507 bpp
= rdst
->surface
.bpe
;
3508 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3509 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3510 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3511 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3512 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3514 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3515 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3517 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3518 /* FIXME evergreen can do partial blit */
3521 /* the x test here are currently useless (because we don't support partial blit)
3522 * but keep them around so we don't forget about those
3524 if (src_pitch
% 8 || src_box
->x
% 8 || dst_x
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3528 /* 128 bpp surfaces require non_disp_tiling for both
3529 * tiled and linear buffers on cayman. However, async
3530 * DMA only supports it on the tiled side. As such
3531 * the tile order is backwards after a L2T/T2L packet.
3533 if ((rctx
->b
.chip_class
== CAYMAN
) &&
3534 (src_mode
!= dst_mode
) &&
3535 (util_format_get_blocksize(src
->format
) >= 16)) {
3539 if (src_mode
== dst_mode
) {
3540 uint64_t dst_offset
, src_offset
;
3541 /* simple dma blit would do NOTE code here assume :
3544 * dst_pitch == src_pitch
3546 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3547 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3548 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3549 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3550 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3551 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3552 evergreen_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
,
3553 src_box
->height
* src_pitch
);
3555 evergreen_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3556 src
, src_level
, src_x
, src_y
, src_box
->z
,
3557 copy_height
, dst_pitch
, bpp
);
3562 r600_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3563 src
, src_level
, src_box
);
3566 static void evergreen_set_tess_state(struct pipe_context
*ctx
,
3567 const float default_outer_level
[4],
3568 const float default_inner_level
[2])
3570 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3572 memcpy(rctx
->tess_state
, default_outer_level
, sizeof(float) * 4);
3573 memcpy(rctx
->tess_state
+4, default_inner_level
, sizeof(float) * 2);
3574 rctx
->tess_state_dirty
= true;
3577 void evergreen_init_state_functions(struct r600_context
*rctx
)
3582 * To avoid GPU lockup registers must be emitted in a specific order
3583 * (no kidding ...). The order below is important and have been
3584 * partially inferred from analyzing fglrx command stream.
3586 * Don't reorder atom without carefully checking the effect (GPU lockup
3587 * or piglit regression).
3590 if (rctx
->b
.chip_class
== EVERGREEN
) {
3591 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, evergreen_emit_config_state
, 11);
3592 rctx
->config_state
.dyn_gpr_enabled
= true;
3594 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, evergreen_emit_framebuffer_state
, 0);
3596 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, evergreen_emit_vs_constant_buffers
, 0);
3597 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, evergreen_emit_gs_constant_buffers
, 0);
3598 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, evergreen_emit_ps_constant_buffers
, 0);
3599 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_CTRL
].atom
, id
++, evergreen_emit_tcs_constant_buffers
, 0);
3600 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_TESS_EVAL
].atom
, id
++, evergreen_emit_tes_constant_buffers
, 0);
3601 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_COMPUTE
].atom
, id
++, evergreen_emit_cs_constant_buffers
, 0);
3602 /* shader program */
3603 r600_init_atom(rctx
, &rctx
->cs_shader_state
.atom
, id
++, evergreen_emit_cs_shader
, 0);
3605 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, evergreen_emit_vs_sampler_states
, 0);
3606 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, evergreen_emit_gs_sampler_states
, 0);
3607 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].states
.atom
, id
++, evergreen_emit_tcs_sampler_states
, 0);
3608 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].states
.atom
, id
++, evergreen_emit_tes_sampler_states
, 0);
3609 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, evergreen_emit_ps_sampler_states
, 0);
3610 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].states
.atom
, id
++, evergreen_emit_cs_sampler_states
, 0);
3612 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, evergreen_fs_emit_vertex_buffers
, 0);
3613 r600_init_atom(rctx
, &rctx
->cs_vertex_buffer_state
.atom
, id
++, evergreen_cs_emit_vertex_buffers
, 0);
3614 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, evergreen_emit_vs_sampler_views
, 0);
3615 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, evergreen_emit_gs_sampler_views
, 0);
3616 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_CTRL
].views
.atom
, id
++, evergreen_emit_tcs_sampler_views
, 0);
3617 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_TESS_EVAL
].views
.atom
, id
++, evergreen_emit_tes_sampler_views
, 0);
3618 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, evergreen_emit_ps_sampler_views
, 0);
3619 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
.atom
, id
++, evergreen_emit_cs_sampler_views
, 0);
3621 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 10);
3623 if (rctx
->b
.chip_class
== EVERGREEN
) {
3624 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, evergreen_emit_sample_mask
, 3);
3626 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, cayman_emit_sample_mask
, 4);
3628 rctx
->sample_mask
.sample_mask
= ~0;
3630 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3631 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3632 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3633 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, evergreen_emit_cb_misc_state
, 4);
3634 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 9);
3635 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, evergreen_emit_clip_state
, 26);
3636 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, evergreen_emit_db_misc_state
, 10);
3637 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, evergreen_emit_db_state
, 14);
3638 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3639 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, evergreen_emit_polygon_offset
, 9);
3640 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3641 r600_add_atom(rctx
, &rctx
->b
.scissors
.atom
, id
++);
3642 r600_add_atom(rctx
, &rctx
->b
.viewports
.atom
, id
++);
3643 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3644 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, evergreen_emit_vertex_fetch_shader
, 5);
3645 r600_add_atom(rctx
, &rctx
->b
.render_cond_atom
, id
++);
3646 r600_add_atom(rctx
, &rctx
->b
.streamout
.begin_atom
, id
++);
3647 r600_add_atom(rctx
, &rctx
->b
.streamout
.enable_atom
, id
++);
3648 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++)
3649 r600_init_atom(rctx
, &rctx
->hw_shader_stages
[i
].atom
, id
++, r600_emit_shader
, 0);
3650 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, evergreen_emit_shader_stages
, 15);
3651 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, evergreen_emit_gs_rings
, 26);
3653 rctx
->b
.b
.create_blend_state
= evergreen_create_blend_state
;
3654 rctx
->b
.b
.create_depth_stencil_alpha_state
= evergreen_create_dsa_state
;
3655 rctx
->b
.b
.create_rasterizer_state
= evergreen_create_rs_state
;
3656 rctx
->b
.b
.create_sampler_state
= evergreen_create_sampler_state
;
3657 rctx
->b
.b
.create_sampler_view
= evergreen_create_sampler_view
;
3658 rctx
->b
.b
.set_framebuffer_state
= evergreen_set_framebuffer_state
;
3659 rctx
->b
.b
.set_polygon_stipple
= evergreen_set_polygon_stipple
;
3660 rctx
->b
.b
.set_min_samples
= evergreen_set_min_samples
;
3661 rctx
->b
.b
.set_tess_state
= evergreen_set_tess_state
;
3662 if (rctx
->b
.chip_class
== EVERGREEN
)
3663 rctx
->b
.b
.get_sample_position
= evergreen_get_sample_position
;
3665 rctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3666 rctx
->b
.dma_copy
= evergreen_dma_copy
;
3668 evergreen_init_compute_state_functions(rctx
);
3672 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
3674 * The information about LDS and other non-compile-time parameters is then
3675 * written to the const buffer.
3677 * const buffer contains -
3678 * uint32_t input_patch_size
3679 * uint32_t input_vertex_size
3680 * uint32_t num_tcs_input_cp
3681 * uint32_t num_tcs_output_cp;
3682 * uint32_t output_patch_size
3683 * uint32_t output_vertex_size
3684 * uint32_t output_patch0_offset
3685 * uint32_t perpatch_output_offset
3686 * and the same constbuf is bound to LS/HS/VS(ES).
3688 void evergreen_setup_tess_constants(struct r600_context
*rctx
, const struct pipe_draw_info
*info
, unsigned *num_patches
)
3690 struct pipe_constant_buffer constbuf
= {0};
3691 struct r600_pipe_shader_selector
*tcs
= rctx
->tcs_shader
? rctx
->tcs_shader
: rctx
->tes_shader
;
3692 struct r600_pipe_shader_selector
*ls
= rctx
->vs_shader
;
3693 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
3694 unsigned num_tcs_outputs
;
3695 unsigned num_tcs_output_cp
;
3696 unsigned num_tcs_patch_outputs
;
3697 unsigned num_tcs_inputs
;
3698 unsigned input_vertex_size
, output_vertex_size
;
3699 unsigned input_patch_size
, pervertex_output_patch_size
, output_patch_size
;
3700 unsigned output_patch0_offset
, perpatch_output_offset
, lds_size
;
3701 uint32_t values
[16];
3703 unsigned num_pipes
= rctx
->screen
->b
.info
.r600_max_quad_pipes
;
3704 unsigned wave_divisor
= (16 * num_pipes
);
3708 if (!rctx
->tes_shader
) {
3709 rctx
->lds_alloc
= 0;
3710 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
3711 R600_LDS_INFO_CONST_BUFFER
, NULL
);
3712 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
3713 R600_LDS_INFO_CONST_BUFFER
, NULL
);
3714 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
3715 R600_LDS_INFO_CONST_BUFFER
, NULL
);
3719 if (rctx
->lds_alloc
!= 0 &&
3720 rctx
->last_ls
== ls
&&
3721 !rctx
->tess_state_dirty
&&
3722 rctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
3723 rctx
->last_tcs
== tcs
)
3726 num_tcs_inputs
= util_last_bit64(ls
->lds_outputs_written_mask
);
3728 if (rctx
->tcs_shader
) {
3729 num_tcs_outputs
= util_last_bit64(tcs
->lds_outputs_written_mask
);
3730 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
3731 num_tcs_patch_outputs
= util_last_bit64(tcs
->lds_patch_outputs_written_mask
);
3733 num_tcs_outputs
= num_tcs_inputs
;
3734 num_tcs_output_cp
= num_tcs_input_cp
;
3735 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
3739 input_vertex_size
= num_tcs_inputs
* 16;
3740 output_vertex_size
= num_tcs_outputs
* 16;
3742 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
3744 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
3745 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3747 output_patch0_offset
= rctx
->tcs_shader
? input_patch_size
* *num_patches
: 0;
3748 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
3750 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
3752 values
[0] = input_patch_size
;
3753 values
[1] = input_vertex_size
;
3754 values
[2] = num_tcs_input_cp
;
3755 values
[3] = num_tcs_output_cp
;
3757 values
[4] = output_patch_size
;
3758 values
[5] = output_vertex_size
;
3759 values
[6] = output_patch0_offset
;
3760 values
[7] = perpatch_output_offset
;
3762 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
3763 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
3764 num_waves
= ceilf((float)(*num_patches
* num_tcs_output_cp
) / (float)wave_divisor
);
3766 rctx
->lds_alloc
= (lds_size
| (num_waves
<< 14));
3768 memcpy(&values
[8], rctx
->tess_state
, 6 * sizeof(float));
3772 rctx
->tess_state_dirty
= false;
3774 rctx
->last_tcs
= tcs
;
3775 rctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
3777 constbuf
.user_buffer
= values
;
3778 constbuf
.buffer_size
= 16 * 4;
3780 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
3781 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
3782 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_CTRL
,
3783 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
3784 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
3785 R600_LDS_INFO_CONST_BUFFER
, &constbuf
);
3786 pipe_resource_reference(&constbuf
.buffer
, NULL
);
3789 uint32_t evergreen_get_ls_hs_config(struct r600_context
*rctx
,
3790 const struct pipe_draw_info
*info
,
3791 unsigned num_patches
)
3793 unsigned num_output_cp
;
3795 if (!rctx
->tes_shader
)
3798 num_output_cp
= rctx
->tcs_shader
?
3799 rctx
->tcs_shader
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] :
3800 info
->vertices_per_patch
;
3802 return S_028B58_NUM_PATCHES(num_patches
) |
3803 S_028B58_HS_NUM_INPUT_CP(info
->vertices_per_patch
) |
3804 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp
);
3807 void evergreen_set_ls_hs_config(struct r600_context
*rctx
,
3808 struct radeon_winsys_cs
*cs
,
3809 uint32_t ls_hs_config
)
3811 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
, ls_hs_config
);
3814 void evergreen_set_lds_alloc(struct r600_context
*rctx
,
3815 struct radeon_winsys_cs
*cs
,
3818 radeon_set_context_reg(cs
, R_0288E8_SQ_LDS_ALLOC
, lds_alloc
);
3821 /* on evergreen if you are running tessellation you need to disable dynamic
3822 GPRs to workaround a hardware bug.*/
3823 bool evergreen_adjust_gprs(struct r600_context
*rctx
)
3825 unsigned num_gprs
[EG_NUM_HW_STAGES
];
3826 unsigned def_gprs
[EG_NUM_HW_STAGES
];
3827 unsigned cur_gprs
[EG_NUM_HW_STAGES
];
3828 unsigned new_gprs
[EG_NUM_HW_STAGES
];
3829 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
3832 unsigned total_gprs
;
3834 bool rework
= false, set_default
= false, set_dirty
= false;
3836 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3837 def_gprs
[i
] = rctx
->default_gprs
[i
];
3838 max_gprs
+= def_gprs
[i
];
3840 max_gprs
+= def_num_clause_temp_gprs
* 2;
3842 /* if we have no TESS and dyn gpr is enabled then do nothing. */
3843 if (!rctx
->hw_shader_stages
[EG_HW_STAGE_HS
].shader
) {
3844 if (rctx
->config_state
.dyn_gpr_enabled
)
3847 /* transition back to dyn gpr enabled state */
3848 rctx
->config_state
.dyn_gpr_enabled
= true;
3849 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
3850 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
3855 /* gather required shader gprs */
3856 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3857 if (rctx
->hw_shader_stages
[i
].shader
)
3858 num_gprs
[i
] = rctx
->hw_shader_stages
[i
].shader
->shader
.bc
.ngpr
;
3863 cur_gprs
[R600_HW_STAGE_PS
] = G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
3864 cur_gprs
[R600_HW_STAGE_VS
] = G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
3865 cur_gprs
[R600_HW_STAGE_GS
] = G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
3866 cur_gprs
[R600_HW_STAGE_ES
] = G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
3867 cur_gprs
[EG_HW_STAGE_LS
] = G_008C0C_NUM_LS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
3868 cur_gprs
[EG_HW_STAGE_HS
] = G_008C0C_NUM_HS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_3
);
3871 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3872 new_gprs
[i
] = num_gprs
[i
];
3873 total_gprs
+= num_gprs
[i
];
3876 if (total_gprs
> (max_gprs
- (2 * def_num_clause_temp_gprs
)))
3879 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3880 if (new_gprs
[i
] > cur_gprs
[i
]) {
3886 if (rctx
->config_state
.dyn_gpr_enabled
) {
3888 rctx
->config_state
.dyn_gpr_enabled
= false;
3893 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3894 if (new_gprs
[i
] > def_gprs
[i
])
3895 set_default
= false;
3899 for (i
= 0; i
< EG_NUM_HW_STAGES
; i
++) {
3900 new_gprs
[i
] = def_gprs
[i
];
3903 unsigned ps_value
= max_gprs
;
3905 ps_value
-= (def_num_clause_temp_gprs
* 2);
3906 for (i
= R600_HW_STAGE_VS
; i
< EG_NUM_HW_STAGES
; i
++)
3907 ps_value
-= new_gprs
[i
];
3909 new_gprs
[R600_HW_STAGE_PS
] = ps_value
;
3912 tmp
[0] = S_008C04_NUM_PS_GPRS(new_gprs
[R600_HW_STAGE_PS
]) |
3913 S_008C04_NUM_VS_GPRS(new_gprs
[R600_HW_STAGE_VS
]) |
3914 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
3916 tmp
[1] = S_008C08_NUM_ES_GPRS(new_gprs
[R600_HW_STAGE_ES
]) |
3917 S_008C08_NUM_GS_GPRS(new_gprs
[R600_HW_STAGE_GS
]);
3919 tmp
[2] = S_008C0C_NUM_HS_GPRS(new_gprs
[EG_HW_STAGE_HS
]) |
3920 S_008C0C_NUM_LS_GPRS(new_gprs
[EG_HW_STAGE_LS
]);
3922 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
[0] ||
3923 rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp
[1] ||
3924 rctx
->config_state
.sq_gpr_resource_mgmt_3
!= tmp
[2]) {
3925 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
[0];
3926 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp
[1];
3927 rctx
->config_state
.sq_gpr_resource_mgmt_3
= tmp
[2];
3934 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
3935 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;