src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include <assert.h>
  30 #include <stdint.h>
  31 #include <stdio.h>
  32 #include <util/u_double_list.h>
  33 #include <util/u_inlines.h>
  34 #include <pipe/p_compiler.h>
  35
  36 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  37
  38 #define R600_ERR(fmt, args...) \
  39         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  40
  41 typedef uint64_t                u64;
  42 typedef uint32_t                u32;
  43 typedef uint16_t                u16;
  44 typedef uint8_t                 u8;
  45
  46 struct radeon;
  47 struct winsys_handle;
  48
  49 enum radeon_family {
  50         CHIP_UNKNOWN,
  51         CHIP_R600,
  52         CHIP_RV610,
  53         CHIP_RV630,
  54         CHIP_RV670,
  55         CHIP_RV620,
  56         CHIP_RV635,
  57         CHIP_RS780,
  58         CHIP_RS880,
  59         CHIP_RV770,
  60         CHIP_RV730,
  61         CHIP_RV710,
  62         CHIP_RV740,
  63         CHIP_CEDAR,
  64         CHIP_REDWOOD,
  65         CHIP_JUNIPER,
  66         CHIP_CYPRESS,
  67         CHIP_HEMLOCK,
  68         CHIP_PALM,
  69         CHIP_SUMO,
  70         CHIP_SUMO2,
  71         CHIP_BARTS,
  72         CHIP_TURKS,
  73         CHIP_CAICOS,
  74         CHIP_CAYMAN,
  75         CHIP_LAST,
  76 };
  77
  78 enum chip_class {
  79         R600,
  80         R700,
  81         EVERGREEN,
  82         CAYMAN,
  83 };
  84
  85 struct r600_tiling_info {
  86         unsigned num_channels;
  87         unsigned num_banks;
  88         unsigned group_bytes;
  89 };
  90
  91 enum radeon_family r600_get_family(struct radeon *rw);
  92 enum chip_class r600_get_family_class(struct radeon *radeon);
  93 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
  94 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
  95 unsigned r600_get_minor_version(struct radeon *radeon);
  96 unsigned r600_get_num_backends(struct radeon *radeon);
  97
  98 /* r600_bo.c */
  99 struct r600_bo;
 100 struct r600_bo *r600_bo(struct radeon *radeon,
 101                         unsigned size, unsigned alignment,
 102                         unsigned binding, unsigned usage);
 103 struct r600_bo *r600_bo_handle(struct radeon *radeon,
 104                                 unsigned handle, unsigned *array_mode);
 105 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 106 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 107 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
 108                                 unsigned stride, struct winsys_handle *whandle);
 109 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
 110 {
 111         return 0;
 112 }
 113 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
 114
 115 /* this relies on the pipe_reference being the first member of r600_bo */
 116 static INLINE void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src)
 117 {
 118         struct r600_bo *old = *dst;
 119
 120         if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) {
 121                 r600_bo_destroy(radeon, old);
 122         }
 123         *dst = src;
 124 }
 125
 126
 127 /* R600/R700 STATES */
 128 #define R600_GROUP_MAX                  16
 129 #define R600_BLOCK_MAX_BO               32
 130 #define R600_BLOCK_MAX_REG              128
 131
 132 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
 133 /* there is a block entry for each register so 512 blocks */
 134 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
 135 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
 136 #define RANGE_OFFSET_START 0x8000
 137 #define HASH_SHIFT 9
 138 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
 139
 140 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
 141 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 142
 143 struct r600_pipe_reg {
 144         u32                             value;
 145         u32                             mask;
 146         struct r600_block               *block;
 147         struct r600_bo                  *bo;
 148         u32                             id;
 149 };
 150
 151 struct r600_pipe_state {
 152         unsigned                        id;
 153         unsigned                        nregs;
 154         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 155 };
 156
 157 struct r600_pipe_resource_state {
 158         unsigned                        id;
 159         u32                             val[8];
 160         struct r600_bo *bo[2];
 161 };
 162
 163 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 164 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 165
 166 struct r600_block_reloc {
 167         struct r600_bo          *bo;
 168         unsigned                flush_flags;
 169         unsigned                flush_mask;
 170         unsigned                bo_pm4_index;
 171 };
 172
 173 struct r600_block {
 174         struct list_head        list;
 175         struct list_head        enable_list;
 176         unsigned                status;
 177         unsigned                flags;
 178         unsigned                start_offset;
 179         unsigned                pm4_ndwords;
 180         unsigned                pm4_flush_ndwords;
 181         unsigned                nbo;
 182         u16                     nreg;
 183         u16                     nreg_dirty;
 184         u32                     *reg;
 185         u32                     pm4[R600_BLOCK_MAX_REG];
 186         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 187         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 188 };
 189
 190 struct r600_range {
 191         struct r600_block       **blocks;
 192 };
 193
 194 /*
 195  * relocation
 196  */
 197 #pragma pack(1)
 198 struct r600_reloc {
 199         uint32_t        handle;
 200         uint32_t        read_domain;
 201         uint32_t        write_domain;
 202         uint32_t        flags;
 203 };
 204 #pragma pack()
 205
 206 /*
 207  * query
 208  */
 209 struct r600_query {
 210         u64                                     result;
 211         /* The kind of query. Currently only OQ is supported. */
 212         unsigned                                type;
 213         /* How many results have been written, in dwords. It's incremented
 214          * after end_query and flush. */
 215         unsigned                                num_results;
 216         /* if we've flushed the query */
 217         unsigned                                state;
 218         /* The buffer where query results are stored. */
 219         struct r600_bo                  *buffer;
 220         unsigned                                buffer_size;
 221         /* linked list of queries */
 222         struct list_head                        list;
 223 };
 224
 225 #define R600_QUERY_STATE_STARTED        (1 << 0)
 226 #define R600_QUERY_STATE_ENDED          (1 << 1)
 227 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 228
 229 #define R600_CONTEXT_DRAW_PENDING       (1 << 0)
 230 #define R600_CONTEXT_DST_CACHES_DIRTY   (1 << 1)
 231 #define R600_CONTEXT_CHECK_EVENT_FLUSH  (1 << 2)
 232
 233 struct r600_context {
 234         struct radeon           *radeon;
 235         struct r600_range       *range;
 236         unsigned                nblocks;
 237         struct r600_block       **blocks;
 238         struct list_head        dirty;
 239         struct list_head        enable_list;
 240         unsigned                pm4_ndwords;
 241         unsigned                pm4_cdwords;
 242         unsigned                pm4_dirty_cdwords;
 243         unsigned                ctx_pm4_ndwords;
 244         unsigned                nreloc;
 245         unsigned                creloc;
 246         struct r600_reloc       *reloc;
 247         struct radeon_bo        **bo;
 248         u32                     *pm4;
 249         struct list_head        query_list;
 250         unsigned                num_query_running;
 251         struct list_head        fenced_bo;
 252         unsigned                max_db; /* for OQ */
 253         unsigned                num_dest_buffers;
 254         unsigned                flags;
 255         boolean                 predicate_drawing;
 256         struct r600_range ps_resources;
 257         struct r600_range vs_resources;
 258         struct r600_range fs_resources;
 259         int num_ps_resources, num_vs_resources, num_fs_resources;
 260 };
 261
 262 struct r600_draw {
 263         u32                     vgt_num_indices;
 264         u32                     vgt_num_instances;
 265         u32                     vgt_index_type;
 266         u32                     vgt_draw_initiator;
 267         u32                     indices_bo_offset;
 268         struct r600_bo          *indices;
 269 };
 270
 271 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 272 void r600_context_fini(struct r600_context *ctx);
 273 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 274 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 275 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 276 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 277 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 278 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 279 void r600_context_flush(struct r600_context *ctx);
 280 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 281 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 282
 283 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 284 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 285 boolean r600_context_query_result(struct r600_context *ctx,
 286                                 struct r600_query *query,
 287                                 boolean wait, void *vresult);
 288 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 289 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 290 void r600_context_queries_suspend(struct r600_context *ctx);
 291 void r600_context_queries_resume(struct r600_context *ctx);
 292 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
 293                             int flag_wait);
 294 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
 295                              unsigned offset, unsigned value);
 296 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
 297 void r600_context_flush_dest_caches(struct r600_context *ctx);
 298
 299 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 300 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 301 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
 302 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 303 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 304 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 305 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 306 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 307
 308 struct radeon *radeon_decref(struct radeon *radeon);
 309
 310 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 311                               struct r600_pipe_state *state,
 312                               u32 offset, u32 value, u32 mask,
 313                               u32 range_id, u32 block_id,
 314                               struct r600_bo *bo);
 315
 316 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 317                                      u32 offset, u32 value, u32 mask,
 318                                      struct r600_bo *bo);
 319 #define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
 320
 321 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
 322                                            u32 value)
 323 {
 324         state->regs[state->nregs].value = value;
 325         state->nregs++;
 326 }
 327
 328 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
 329                                            u32 value, struct r600_bo *bo)
 330 {
 331         state->regs[state->nregs].value = value;
 332         state->regs[state->nregs].bo = bo;
 333         state->nregs++;
 334 }
 335
 336 #endif