src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include <stdint.h>
  30 #include <stdio.h>
  31 #include <util/u_double_list.h>
  32 #include <pipe/p_compiler.h>
  33
  34 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  35
  36 #define R600_ERR(fmt, args...) \
  37         fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
  38
  39 typedef uint64_t                u64;
  40 typedef uint32_t                u32;
  41 typedef uint16_t                u16;
  42 typedef uint8_t                 u8;
  43
  44 struct radeon;
  45
  46 enum radeon_family {
  47         CHIP_UNKNOWN,
  48         CHIP_R100,
  49         CHIP_RV100,
  50         CHIP_RS100,
  51         CHIP_RV200,
  52         CHIP_RS200,
  53         CHIP_R200,
  54         CHIP_RV250,
  55         CHIP_RS300,
  56         CHIP_RV280,
  57         CHIP_R300,
  58         CHIP_R350,
  59         CHIP_RV350,
  60         CHIP_RV380,
  61         CHIP_R420,
  62         CHIP_R423,
  63         CHIP_RV410,
  64         CHIP_RS400,
  65         CHIP_RS480,
  66         CHIP_RS600,
  67         CHIP_RS690,
  68         CHIP_RS740,
  69         CHIP_RV515,
  70         CHIP_R520,
  71         CHIP_RV530,
  72         CHIP_RV560,
  73         CHIP_RV570,
  74         CHIP_R580,
  75         CHIP_R600,
  76         CHIP_RV610,
  77         CHIP_RV630,
  78         CHIP_RV670,
  79         CHIP_RV620,
  80         CHIP_RV635,
  81         CHIP_RS780,
  82         CHIP_RS880,
  83         CHIP_RV770,
  84         CHIP_RV730,
  85         CHIP_RV710,
  86         CHIP_RV740,
  87         CHIP_CEDAR,
  88         CHIP_REDWOOD,
  89         CHIP_JUNIPER,
  90         CHIP_CYPRESS,
  91         CHIP_HEMLOCK,
  92         CHIP_LAST,
  93 };
  94
  95 enum chip_class {
  96         R600,
  97         R700,
  98         EVERGREEN,
  99 };
 100
 101 enum radeon_family r600_get_family(struct radeon *rw);
 102 enum chip_class r600_get_family_class(struct radeon *radeon);
 103
 104 /* lowlevel WS bo */
 105 struct radeon_ws_bo;
 106 struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
 107                                   unsigned size, unsigned alignment, unsigned usage);
 108 struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
 109                                          unsigned handle);
 110 void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
 111 void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
 112 void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
 113                             struct radeon_ws_bo *src);
 114
 115 /* R600/R700 STATES */
 116 #define R600_GROUP_MAX                  16
 117 #define R600_BLOCK_MAX_BO               32
 118 #define R600_BLOCK_MAX_REG              128
 119
 120 struct r600_pipe_reg {
 121         u32                             offset;
 122         u32                             mask;
 123         u32                             value;
 124         struct radeon_ws_bo             *bo;
 125 };
 126
 127 struct r600_pipe_state {
 128         unsigned                        id;
 129         unsigned                        nregs;
 130         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 131 };
 132
 133 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 134                                         u32 offset, u32 value, u32 mask,
 135                                         struct radeon_ws_bo *bo)
 136 {
 137         state->regs[state->nregs].offset = offset;
 138         state->regs[state->nregs].value = value;
 139         state->regs[state->nregs].mask = mask;
 140         state->regs[state->nregs].bo = bo;
 141         state->nregs++;
 142         assert(state->nregs < R600_BLOCK_MAX_REG);
 143 }
 144
 145 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 146 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 147
 148 struct r600_block_reloc {
 149         struct radeon_ws_bo     *bo;
 150         unsigned                nreloc;
 151         unsigned                bo_pm4_index[R600_BLOCK_MAX_BO];
 152 };
 153
 154 struct r600_block {
 155         unsigned                status;
 156         unsigned                start_offset;
 157         unsigned                pm4_ndwords;
 158         unsigned                nbo;
 159         unsigned                nreg;
 160         u32                     *reg;
 161         u32                     pm4[R600_BLOCK_MAX_REG];
 162         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 163         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 164 };
 165
 166 struct r600_range {
 167         unsigned                start_offset;
 168         unsigned                end_offset;
 169         struct r600_block       **blocks;
 170 };
 171
 172 /*
 173  * relocation
 174  */
 175 #pragma pack(1)
 176 struct r600_reloc {
 177         uint32_t        handle;
 178         uint32_t        read_domain;
 179         uint32_t        write_domain;
 180         uint32_t        flags;
 181 };
 182 #pragma pack()
 183
 184 /*
 185  * query
 186  */
 187 struct r600_query {
 188         u64                                     result;
 189         /* The kind of query. Currently only OQ is supported. */
 190         unsigned                                type;
 191         /* How many results have been written, in dwords. It's incremented
 192          * after end_query and flush. */
 193         unsigned                                num_results;
 194         /* if we've flushed the query */
 195         unsigned                                state;
 196         /* The buffer where query results are stored. */
 197         struct radeon_ws_bo                     *buffer;
 198         unsigned                                buffer_size;
 199         /* linked list of queries */
 200         struct list_head                        list;
 201 };
 202
 203 #define R600_QUERY_STATE_STARTED        (1 << 0)
 204 #define R600_QUERY_STATE_ENDED          (1 << 1)
 205 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 206
 207
 208 struct r600_context {
 209         struct radeon           *radeon;
 210         unsigned                hash_size;
 211         unsigned                hash_shift;
 212         struct r600_range       range[256];
 213         unsigned                nblocks;
 214         struct r600_block       **blocks;
 215         unsigned                pm4_ndwords;
 216         unsigned                pm4_cdwords;
 217         unsigned                pm4_dirty_cdwords;
 218         unsigned                ctx_pm4_ndwords;
 219         unsigned                nreloc;
 220         unsigned                creloc;
 221         struct r600_reloc       *reloc;
 222         struct radeon_bo        **bo;
 223         u32                     *pm4;
 224         struct list_head        query_list;
 225         unsigned                num_query_running;
 226 };
 227
 228 struct r600_draw {
 229         u32                     vgt_num_indices;
 230         u32                     vgt_num_instances;
 231         u32                     vgt_index_type;
 232         u32                     vgt_draw_initiator;
 233         u32                     indices_bo_offset;
 234         struct radeon_ws_bo     *indices;
 235 };
 236
 237 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 238 void r600_context_fini(struct r600_context *ctx);
 239 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 240 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 241 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 242 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 243 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 244 void r600_context_flush(struct r600_context *ctx);
 245 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 246 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 247
 248 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 249 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 250 boolean r600_context_query_result(struct r600_context *ctx,
 251                                 struct r600_query *query,
 252                                 boolean wait, void *vresult);
 253 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 254 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 255 void r600_context_queries_suspend(struct r600_context *ctx);
 256 void r600_context_queries_resume(struct r600_context *ctx);
 257
 258 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 259 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 260 void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 261 void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 262
 263 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 264 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 265 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 266 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 267
 268 #endif