src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include <assert.h>
  30 #include <stdint.h>
  31 #include <stdio.h>
  32 #include <util/u_double_list.h>
  33 #include <pipe/p_compiler.h>
  34
  35 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  36
  37 #define R600_ERR(fmt, args...) \
  38         fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
  39
  40 typedef uint64_t                u64;
  41 typedef uint32_t                u32;
  42 typedef uint16_t                u16;
  43 typedef uint8_t                 u8;
  44
  45 struct radeon;
  46
  47 enum radeon_family {
  48         CHIP_UNKNOWN,
  49         CHIP_R100,
  50         CHIP_RV100,
  51         CHIP_RS100,
  52         CHIP_RV200,
  53         CHIP_RS200,
  54         CHIP_R200,
  55         CHIP_RV250,
  56         CHIP_RS300,
  57         CHIP_RV280,
  58         CHIP_R300,
  59         CHIP_R350,
  60         CHIP_RV350,
  61         CHIP_RV380,
  62         CHIP_R420,
  63         CHIP_R423,
  64         CHIP_RV410,
  65         CHIP_RS400,
  66         CHIP_RS480,
  67         CHIP_RS600,
  68         CHIP_RS690,
  69         CHIP_RS740,
  70         CHIP_RV515,
  71         CHIP_R520,
  72         CHIP_RV530,
  73         CHIP_RV560,
  74         CHIP_RV570,
  75         CHIP_R580,
  76         CHIP_R600,
  77         CHIP_RV610,
  78         CHIP_RV630,
  79         CHIP_RV670,
  80         CHIP_RV620,
  81         CHIP_RV635,
  82         CHIP_RS780,
  83         CHIP_RS880,
  84         CHIP_RV770,
  85         CHIP_RV730,
  86         CHIP_RV710,
  87         CHIP_RV740,
  88         CHIP_CEDAR,
  89         CHIP_REDWOOD,
  90         CHIP_JUNIPER,
  91         CHIP_CYPRESS,
  92         CHIP_HEMLOCK,
  93         CHIP_LAST,
  94 };
  95
  96 enum chip_class {
  97         R600,
  98         R700,
  99         EVERGREEN,
 100 };
 101
 102 struct r600_tiling_info {
 103         unsigned num_channels;
 104         unsigned num_banks;
 105         unsigned group_bytes;
 106 };
 107
 108 enum radeon_family r600_get_family(struct radeon *rw);
 109 enum chip_class r600_get_family_class(struct radeon *radeon);
 110 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
 111
 112 /* r600_bo.c */
 113 struct r600_bo;
 114 struct r600_bo *r600_bo(struct radeon *radeon,
 115                         unsigned size, unsigned alignment,
 116                         unsigned binding, unsigned usage);
 117 struct r600_bo *r600_bo_handle(struct radeon *radeon,
 118                                unsigned handle, unsigned *array_mode);
 119 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 120 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 121 void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
 122                             struct r600_bo *src);
 123 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
 124 {
 125         return 0;
 126 }
 127
 128
 129 /* R600/R700 STATES */
 130 #define R600_GROUP_MAX                  16
 131 #define R600_BLOCK_MAX_BO               32
 132 #define R600_BLOCK_MAX_REG              128
 133
 134 struct r600_pipe_reg {
 135         u32                             offset;
 136         u32                             mask;
 137         u32                             value;
 138         struct r600_bo          *bo;
 139 };
 140
 141 struct r600_pipe_state {
 142         unsigned                        id;
 143         unsigned                        nregs;
 144         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 145 };
 146
 147 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 148                                         u32 offset, u32 value, u32 mask,
 149                                         struct r600_bo *bo)
 150 {
 151         state->regs[state->nregs].offset = offset;
 152         state->regs[state->nregs].value = value;
 153         state->regs[state->nregs].mask = mask;
 154         state->regs[state->nregs].bo = bo;
 155         state->nregs++;
 156         assert(state->nregs < R600_BLOCK_MAX_REG);
 157 }
 158
 159 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 160 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 161
 162 struct r600_block_reloc {
 163         struct r600_bo          *bo;
 164         unsigned                flush_flags;
 165         unsigned                flush_mask;
 166         unsigned                bo_pm4_index;
 167 };
 168
 169 struct r600_block {
 170         struct list_head        list;
 171         unsigned                status;
 172         unsigned                start_offset;
 173         unsigned                pm4_ndwords;
 174         unsigned                pm4_flush_ndwords;
 175         unsigned                nbo;
 176         unsigned                nreg;
 177         u32                     *reg;
 178         u32                     pm4[R600_BLOCK_MAX_REG];
 179         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 180         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 181 };
 182
 183 struct r600_range {
 184         unsigned                start_offset;
 185         unsigned                end_offset;
 186         struct r600_block       **blocks;
 187 };
 188
 189 /*
 190  * relocation
 191  */
 192 #pragma pack(1)
 193 struct r600_reloc {
 194         uint32_t        handle;
 195         uint32_t        read_domain;
 196         uint32_t        write_domain;
 197         uint32_t        flags;
 198 };
 199 #pragma pack()
 200
 201 /*
 202  * query
 203  */
 204 struct r600_query {
 205         u64                                     result;
 206         /* The kind of query. Currently only OQ is supported. */
 207         unsigned                                type;
 208         /* How many results have been written, in dwords. It's incremented
 209          * after end_query and flush. */
 210         unsigned                                num_results;
 211         /* if we've flushed the query */
 212         unsigned                                state;
 213         /* The buffer where query results are stored. */
 214         struct r600_bo                  *buffer;
 215         unsigned                                buffer_size;
 216         /* linked list of queries */
 217         struct list_head                        list;
 218 };
 219
 220 #define R600_QUERY_STATE_STARTED        (1 << 0)
 221 #define R600_QUERY_STATE_ENDED          (1 << 1)
 222 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 223
 224
 225 struct r600_context {
 226         struct radeon           *radeon;
 227         unsigned                hash_size;
 228         unsigned                hash_shift;
 229         struct r600_range       range[256];
 230         unsigned                nblocks;
 231         struct r600_block       **blocks;
 232         struct list_head        dirty;
 233         unsigned                pm4_ndwords;
 234         unsigned                pm4_cdwords;
 235         unsigned                pm4_dirty_cdwords;
 236         unsigned                ctx_pm4_ndwords;
 237         unsigned                nreloc;
 238         unsigned                creloc;
 239         struct r600_reloc       *reloc;
 240         struct radeon_bo        **bo;
 241         u32                     *pm4;
 242         struct list_head        query_list;
 243         unsigned                num_query_running;
 244         unsigned                fence;
 245         struct list_head        fenced_bo;
 246         unsigned                *cfence;
 247         struct r600_bo          *fence_bo;
 248 };
 249
 250 struct r600_draw {
 251         u32                     vgt_num_indices;
 252         u32                     vgt_num_instances;
 253         u32                     vgt_index_type;
 254         u32                     vgt_draw_initiator;
 255         u32                     indices_bo_offset;
 256         struct r600_bo          *indices;
 257 };
 258
 259 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 260 void r600_context_fini(struct r600_context *ctx);
 261 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 262 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 263 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 264 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 265 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 266 void r600_context_flush(struct r600_context *ctx);
 267 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 268 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 269
 270 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 271 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 272 boolean r600_context_query_result(struct r600_context *ctx,
 273                                 struct r600_query *query,
 274                                 boolean wait, void *vresult);
 275 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 276 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 277 void r600_context_queries_suspend(struct r600_context *ctx);
 278 void r600_context_queries_resume(struct r600_context *ctx);
 279
 280 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 281 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 282 void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 283 void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 284
 285 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 286 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 287 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 288 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 289
 290 #endif