src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include <assert.h>
  30 #include <stdint.h>
  31 #include <stdio.h>
  32 #include <util/u_double_list.h>
  33 #include <pipe/p_compiler.h>
  34
  35 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  36
  37 #define R600_ERR(fmt, args...) \
  38         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  39
  40 typedef uint64_t                u64;
  41 typedef uint32_t                u32;
  42 typedef uint16_t                u16;
  43 typedef uint8_t                 u8;
  44
  45 struct radeon;
  46 struct winsys_handle;
  47
  48 enum radeon_family {
  49         CHIP_UNKNOWN,
  50         CHIP_R100,
  51         CHIP_RV100,
  52         CHIP_RS100,
  53         CHIP_RV200,
  54         CHIP_RS200,
  55         CHIP_R200,
  56         CHIP_RV250,
  57         CHIP_RS300,
  58         CHIP_RV280,
  59         CHIP_R300,
  60         CHIP_R350,
  61         CHIP_RV350,
  62         CHIP_RV380,
  63         CHIP_R420,
  64         CHIP_R423,
  65         CHIP_RV410,
  66         CHIP_RS400,
  67         CHIP_RS480,
  68         CHIP_RS600,
  69         CHIP_RS690,
  70         CHIP_RS740,
  71         CHIP_RV515,
  72         CHIP_R520,
  73         CHIP_RV530,
  74         CHIP_RV560,
  75         CHIP_RV570,
  76         CHIP_R580,
  77         CHIP_R600,
  78         CHIP_RV610,
  79         CHIP_RV630,
  80         CHIP_RV670,
  81         CHIP_RV620,
  82         CHIP_RV635,
  83         CHIP_RS780,
  84         CHIP_RS880,
  85         CHIP_RV770,
  86         CHIP_RV730,
  87         CHIP_RV710,
  88         CHIP_RV740,
  89         CHIP_CEDAR,
  90         CHIP_REDWOOD,
  91         CHIP_JUNIPER,
  92         CHIP_CYPRESS,
  93         CHIP_HEMLOCK,
  94         CHIP_PALM,
  95         CHIP_BARTS,
  96         CHIP_TURKS,
  97         CHIP_CAICOS,
  98         CHIP_LAST,
  99 };
 100
 101 enum chip_class {
 102         R600,
 103         R700,
 104         EVERGREEN,
 105 };
 106
 107 struct r600_tiling_info {
 108         unsigned num_channels;
 109         unsigned num_banks;
 110         unsigned group_bytes;
 111 };
 112
 113 enum radeon_family r600_get_family(struct radeon *rw);
 114 enum chip_class r600_get_family_class(struct radeon *radeon);
 115 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
 116 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
 117
 118 /* r600_bo.c */
 119 struct r600_bo;
 120 struct r600_bo *r600_bo(struct radeon *radeon,
 121                         unsigned size, unsigned alignment,
 122                         unsigned binding, unsigned usage);
 123 struct r600_bo *r600_bo_handle(struct radeon *radeon,
 124                                unsigned handle, unsigned *array_mode);
 125 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 126 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 127 void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
 128                             struct r600_bo *src);
 129 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
 130                                 unsigned stride, struct winsys_handle *whandle);
 131 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
 132 {
 133         return 0;
 134 }
 135
 136
 137 /* R600/R700 STATES */
 138 #define R600_GROUP_MAX                  16
 139 #define R600_BLOCK_MAX_BO               32
 140 #define R600_BLOCK_MAX_REG              128
 141
 142 struct r600_pipe_reg {
 143         u32                             offset;
 144         u32                             mask;
 145         u32                             value;
 146         struct r600_bo          *bo;
 147 };
 148
 149 struct r600_pipe_state {
 150         unsigned                        id;
 151         unsigned                        nregs;
 152         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 153 };
 154
 155 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 156                                         u32 offset, u32 value, u32 mask,
 157                                         struct r600_bo *bo)
 158 {
 159         state->regs[state->nregs].offset = offset;
 160         state->regs[state->nregs].value = value;
 161         state->regs[state->nregs].mask = mask;
 162         state->regs[state->nregs].bo = bo;
 163         state->nregs++;
 164         assert(state->nregs < R600_BLOCK_MAX_REG);
 165 }
 166
 167 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 168 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 169
 170 struct r600_block_reloc {
 171         struct r600_bo          *bo;
 172         unsigned                flush_flags;
 173         unsigned                flush_mask;
 174         unsigned                bo_pm4_index;
 175 };
 176
 177 struct r600_block {
 178         struct list_head        list;
 179         unsigned                status;
 180         unsigned                start_offset;
 181         unsigned                pm4_ndwords;
 182         unsigned                pm4_flush_ndwords;
 183         unsigned                nbo;
 184         unsigned                nreg;
 185         u32                     *reg;
 186         u32                     pm4[R600_BLOCK_MAX_REG];
 187         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 188         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 189 };
 190
 191 struct r600_range {
 192         unsigned                start_offset;
 193         unsigned                end_offset;
 194         struct r600_block       **blocks;
 195 };
 196
 197 /*
 198  * relocation
 199  */
 200 #pragma pack(1)
 201 struct r600_reloc {
 202         uint32_t        handle;
 203         uint32_t        read_domain;
 204         uint32_t        write_domain;
 205         uint32_t        flags;
 206 };
 207 #pragma pack()
 208
 209 /*
 210  * query
 211  */
 212 struct r600_query {
 213         u64                                     result;
 214         /* The kind of query. Currently only OQ is supported. */
 215         unsigned                                type;
 216         /* How many results have been written, in dwords. It's incremented
 217          * after end_query and flush. */
 218         unsigned                                num_results;
 219         /* if we've flushed the query */
 220         unsigned                                state;
 221         /* The buffer where query results are stored. */
 222         struct r600_bo                  *buffer;
 223         unsigned                                buffer_size;
 224         /* linked list of queries */
 225         struct list_head                        list;
 226 };
 227
 228 #define R600_QUERY_STATE_STARTED        (1 << 0)
 229 #define R600_QUERY_STATE_ENDED          (1 << 1)
 230 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 231
 232
 233 struct r600_context {
 234         struct radeon           *radeon;
 235         unsigned                hash_size;
 236         unsigned                hash_shift;
 237         struct r600_range       range[256];
 238         unsigned                nblocks;
 239         struct r600_block       **blocks;
 240         struct list_head        dirty;
 241         unsigned                pm4_ndwords;
 242         unsigned                pm4_cdwords;
 243         unsigned                pm4_dirty_cdwords;
 244         unsigned                ctx_pm4_ndwords;
 245         unsigned                nreloc;
 246         unsigned                creloc;
 247         struct r600_reloc       *reloc;
 248         struct radeon_bo        **bo;
 249         u32                     *pm4;
 250         struct list_head        query_list;
 251         unsigned                num_query_running;
 252         struct list_head        fenced_bo;
 253         unsigned                max_db; /* for OQ */
 254 };
 255
 256 struct r600_draw {
 257         u32                     vgt_num_indices;
 258         u32                     vgt_num_instances;
 259         u32                     vgt_index_type;
 260         u32                     vgt_draw_initiator;
 261         u32                     indices_bo_offset;
 262         struct r600_bo          *indices;
 263 };
 264
 265 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 266 void r600_context_fini(struct r600_context *ctx);
 267 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 268 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 269 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 270 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 271 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 272 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 273 void r600_context_flush(struct r600_context *ctx);
 274 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 275 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 276
 277 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 278 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 279 boolean r600_context_query_result(struct r600_context *ctx,
 280                                 struct r600_query *query,
 281                                 boolean wait, void *vresult);
 282 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 283 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 284 void r600_context_queries_suspend(struct r600_context *ctx);
 285 void r600_context_queries_resume(struct r600_context *ctx);
 286
 287 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 288 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 289 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 290 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 291 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 292 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 293 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 294
 295 struct radeon *radeon_decref(struct radeon *radeon);
 296
 297 #endif