src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include "util/u_double_list.h"
  30 #include "util/u_inlines.h"
  31
  32 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  33
  34 #define R600_ERR(fmt, args...) \
  35         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  36
  37 typedef uint64_t                u64;
  38 typedef uint32_t                u32;
  39 typedef uint16_t                u16;
  40 typedef uint8_t                 u8;
  41
  42 struct radeon;
  43 struct winsys_handle;
  44
  45 enum radeon_family {
  46         CHIP_UNKNOWN,
  47         CHIP_R600,
  48         CHIP_RV610,
  49         CHIP_RV630,
  50         CHIP_RV670,
  51         CHIP_RV620,
  52         CHIP_RV635,
  53         CHIP_RS780,
  54         CHIP_RS880,
  55         CHIP_RV770,
  56         CHIP_RV730,
  57         CHIP_RV710,
  58         CHIP_RV740,
  59         CHIP_CEDAR,
  60         CHIP_REDWOOD,
  61         CHIP_JUNIPER,
  62         CHIP_CYPRESS,
  63         CHIP_HEMLOCK,
  64         CHIP_PALM,
  65         CHIP_SUMO,
  66         CHIP_SUMO2,
  67         CHIP_BARTS,
  68         CHIP_TURKS,
  69         CHIP_CAICOS,
  70         CHIP_CAYMAN,
  71         CHIP_LAST,
  72 };
  73
  74 enum chip_class {
  75         R600,
  76         R700,
  77         EVERGREEN,
  78         CAYMAN,
  79 };
  80
  81 struct r600_tiling_info {
  82         unsigned num_channels;
  83         unsigned num_banks;
  84         unsigned group_bytes;
  85 };
  86
  87 enum radeon_family r600_get_family(struct radeon *rw);
  88 enum chip_class r600_get_family_class(struct radeon *radeon);
  89 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
  90 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
  91 unsigned r600_get_minor_version(struct radeon *radeon);
  92 unsigned r600_get_num_backends(struct radeon *radeon);
  93 unsigned r600_get_num_tile_pipes(struct radeon *radeon);
  94 unsigned r600_get_backend_map(struct radeon *radeon);
  95
  96 /* r600_bo.c */
  97 struct r600_bo;
  98 struct r600_bo *r600_bo(struct radeon *radeon,
  99                         unsigned size, unsigned alignment,
 100                         unsigned binding, unsigned usage);
 101 struct r600_bo *r600_bo_handle(struct radeon *radeon,
 102                                 unsigned handle, unsigned *array_mode);
 103 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 104 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 105 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
 106                                   unsigned stride, struct winsys_handle *whandle);
 107
 108 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
 109
 110 /* this relies on the pipe_reference being the first member of r600_bo */
 111 static INLINE void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src)
 112 {
 113         struct r600_bo *old = *dst;
 114
 115         if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) {
 116                 r600_bo_destroy(radeon, old);
 117         }
 118         *dst = src;
 119 }
 120
 121
 122 /* R600/R700 STATES */
 123 #define R600_GROUP_MAX                  16
 124 #define R600_BLOCK_MAX_BO               32
 125 #define R600_BLOCK_MAX_REG              128
 126
 127 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
 128 /* there is a block entry for each register so 512 blocks */
 129 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
 130 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
 131 #define RANGE_OFFSET_START 0x8000
 132 #define HASH_SHIFT 9
 133 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
 134
 135 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
 136 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 137
 138 struct r600_pipe_reg {
 139         u32                             value;
 140         u32                             mask;
 141         struct r600_block               *block;
 142         struct r600_bo                  *bo;
 143         u32                             id;
 144 };
 145
 146 struct r600_pipe_state {
 147         unsigned                        id;
 148         unsigned                        nregs;
 149         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 150 };
 151
 152 struct r600_pipe_resource_state {
 153         unsigned                        id;
 154         u32                             val[8];
 155         struct r600_bo *bo[2];
 156 };
 157
 158 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 159 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 160 #define R600_BLOCK_STATUS_RESOURCE_DIRTY        (1 << 2)
 161
 162 #define R600_BLOCK_STATUS_RESOURCE_VERTEX       (1 << 3)
 163
 164 struct r600_block_reloc {
 165         struct r600_bo          *bo;
 166         unsigned                flush_flags;
 167         unsigned                flush_mask;
 168         unsigned                bo_pm4_index;
 169 };
 170
 171 struct r600_block {
 172         struct list_head        list;
 173         struct list_head        enable_list;
 174         unsigned                status;
 175         unsigned                flags;
 176         unsigned                start_offset;
 177         unsigned                pm4_ndwords;
 178         unsigned                pm4_flush_ndwords;
 179         unsigned                nbo;
 180         u16                     nreg;
 181         u16                     nreg_dirty;
 182         u32                     *reg;
 183         u32                     pm4[R600_BLOCK_MAX_REG];
 184         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 185         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 186 };
 187
 188 struct r600_range {
 189         struct r600_block       **blocks;
 190 };
 191
 192 /*
 193  * relocation
 194  */
 195 #pragma pack(1)
 196 struct r600_reloc {
 197         uint32_t        handle;
 198         uint32_t        read_domain;
 199         uint32_t        write_domain;
 200         uint32_t        flags;
 201 };
 202 #pragma pack()
 203
 204 /*
 205  * query
 206  */
 207 struct r600_query {
 208         u64                                     result;
 209         /* The kind of query */
 210         unsigned                                type;
 211         /* Offset of the first result for current query */
 212         unsigned                                results_start;
 213         /* Offset of the next free result after current query data */
 214         unsigned                                results_end;
 215         /* Size of the result */
 216         unsigned                                result_size;
 217         /* Count of new queries started in one stream without flushing */
 218         unsigned                                queries_emitted;
 219         /* State flags */
 220         unsigned                                state;
 221         /* The buffer where query results are stored. It's used as a ring,
 222          * data blocks for current query are stored sequentially from
 223          * results_start to results_end, with wrapping on the buffer end */
 224         struct r600_bo                  *buffer;
 225         unsigned                                buffer_size;
 226         /* linked list of queries */
 227         struct list_head                        list;
 228 };
 229
 230 #define R600_QUERY_STATE_STARTED        (1 << 0)
 231 #define R600_QUERY_STATE_ENDED          (1 << 1)
 232 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 233 #define R600_QUERY_STATE_FLUSHED        (1 << 3)
 234
 235 #define R600_CONTEXT_DRAW_PENDING       (1 << 0)
 236 #define R600_CONTEXT_DST_CACHES_DIRTY   (1 << 1)
 237 #define R600_CONTEXT_CHECK_EVENT_FLUSH  (1 << 2)
 238
 239 struct r600_context {
 240         struct radeon           *radeon;
 241         struct r600_range       *range;
 242         unsigned                nblocks;
 243         struct r600_block       **blocks;
 244         struct list_head        dirty;
 245         struct list_head        resource_dirty;
 246         struct list_head        enable_list;
 247         unsigned                pm4_ndwords;
 248         unsigned                pm4_cdwords;
 249         unsigned                pm4_dirty_cdwords;
 250         unsigned                ctx_pm4_ndwords;
 251         unsigned                init_dwords;
 252         unsigned                nreloc;
 253         unsigned                creloc;
 254         struct r600_reloc       *reloc;
 255         struct radeon_bo        **bo;
 256         u32                     *pm4;
 257         struct list_head        query_list;
 258         unsigned                num_query_running;
 259         unsigned                backend_mask;
 260         struct list_head        fenced_bo;
 261         unsigned                max_db; /* for OQ */
 262         unsigned                num_dest_buffers;
 263         unsigned                flags;
 264         boolean                 predicate_drawing;
 265         struct r600_range ps_resources;
 266         struct r600_range vs_resources;
 267         struct r600_range fs_resources;
 268         int num_ps_resources, num_vs_resources, num_fs_resources;
 269         boolean                 have_depth_texture, have_depth_fb;
 270 };
 271
 272 struct r600_draw {
 273         u32                     vgt_num_indices;
 274         u32                     vgt_num_instances;
 275         u32                     vgt_index_type;
 276         u32                     vgt_draw_initiator;
 277         u32                     indices_bo_offset;
 278         struct r600_bo          *indices;
 279 };
 280
 281 void r600_get_backend_mask(struct r600_context *ctx);
 282 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 283 void r600_context_fini(struct r600_context *ctx);
 284 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 285 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 286 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 287 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 288 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 289 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 290 void r600_context_flush(struct r600_context *ctx);
 291 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 292
 293 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 294 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 295 boolean r600_context_query_result(struct r600_context *ctx,
 296                                 struct r600_query *query,
 297                                 boolean wait, void *vresult);
 298 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 299 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 300 void r600_context_queries_suspend(struct r600_context *ctx);
 301 void r600_context_queries_resume(struct r600_context *ctx, boolean flushed);
 302 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
 303                             int flag_wait);
 304 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
 305                              unsigned offset, unsigned value);
 306 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
 307 void r600_context_flush_dest_caches(struct r600_context *ctx);
 308
 309 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 310 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 311 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
 312 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 313 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 314 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 315 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 316 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 317
 318 struct radeon *radeon_decref(struct radeon *radeon);
 319
 320 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 321                               struct r600_pipe_state *state,
 322                               u32 offset, u32 value, u32 mask,
 323                               u32 range_id, u32 block_id,
 324                               struct r600_bo *bo);
 325
 326 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 327                                      u32 offset, u32 value, u32 mask,
 328                                      struct r600_bo *bo);
 329 #define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
 330
 331 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
 332                                            u32 value)
 333 {
 334         state->regs[state->nregs].value = value;
 335         state->nregs++;
 336 }
 337
 338 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
 339                                            u32 value, struct r600_bo *bo)
 340 {
 341         state->regs[state->nregs].value = value;
 342         state->regs[state->nregs].bo = bo;
 343         state->nregs++;
 344 }
 345
 346 #endif