2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
30 #include "util/u_double_list.h"
31 #include "util/u_vbuf_mgr.h"
33 #define R600_ERR(fmt, args...) \
34 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
79 struct r600_tiling_info
{
80 unsigned num_channels
;
85 struct r600_resource
{
86 struct u_vbuf_resource b
;
89 struct pb_buffer
*buf
;
90 struct radeon_winsys_cs_handle
*cs_buf
;
93 /* R600/R700 STATES */
94 #define R600_GROUP_MAX 16
95 #define R600_BLOCK_MAX_BO 32
96 #define R600_BLOCK_MAX_REG 128
98 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
99 /* there is a block entry for each register so 512 blocks */
100 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
101 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
102 #define RANGE_OFFSET_START 0x8000
104 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
106 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
107 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
109 struct r600_pipe_reg
{
112 struct r600_block
*block
;
113 struct r600_resource
*bo
;
114 enum radeon_bo_usage bo_usage
;
118 struct r600_pipe_state
{
121 struct r600_pipe_reg regs
[R600_BLOCK_MAX_REG
];
124 struct r600_pipe_resource_state
{
127 struct r600_resource
*bo
[2];
128 enum radeon_bo_usage bo_usage
[2];
131 #define R600_BLOCK_STATUS_ENABLED (1 << 0)
132 #define R600_BLOCK_STATUS_DIRTY (1 << 1)
133 #define R600_BLOCK_STATUS_RESOURCE_DIRTY (1 << 2)
135 #define R600_BLOCK_STATUS_RESOURCE_VERTEX (1 << 3)
137 struct r600_block_reloc
{
138 struct r600_resource
*bo
;
139 enum radeon_bo_usage bo_usage
;
140 unsigned flush_flags
;
142 unsigned bo_pm4_index
;
146 struct list_head list
;
147 struct list_head enable_list
;
150 unsigned start_offset
;
151 unsigned pm4_ndwords
;
152 unsigned pm4_flush_ndwords
;
157 u32 pm4
[R600_BLOCK_MAX_REG
];
158 unsigned pm4_bo_index
[R600_BLOCK_MAX_REG
];
159 struct r600_block_reloc reloc
[R600_BLOCK_MAX_BO
];
163 struct r600_block
**blocks
;
168 /* The kind of query */
170 /* Offset of the first result for current query */
171 unsigned results_start
;
172 /* Offset of the next free result after current query data */
173 unsigned results_end
;
174 /* Size of the result in memory for both begin_query and end_query,
175 * this can be one or two numbers, or it could even be a size of a structure. */
176 unsigned result_size
;
177 /* The buffer where query results are stored. It's used as a ring,
178 * data blocks for current query are stored sequentially from
179 * results_start to results_end, with wrapping on the buffer end */
180 struct r600_resource
*buffer
;
181 /* linked list of queries */
182 struct list_head list
;
185 #define R600_CONTEXT_DRAW_PENDING (1 << 0)
186 #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
187 #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2)
189 struct r600_context
{
190 struct r600_screen
*screen
;
191 struct radeon_winsys
*ws
;
192 struct radeon_winsys_cs
*cs
;
194 struct r600_range
*range
;
196 struct r600_block
**blocks
;
197 struct list_head dirty
;
198 struct list_head resource_dirty
;
199 struct list_head enable_list
;
200 unsigned pm4_ndwords
;
201 unsigned pm4_dirty_cdwords
;
202 unsigned ctx_pm4_ndwords
;
203 unsigned init_dwords
;
206 struct r600_resource
**bo
;
209 unsigned pm4_cdwords
;
211 /* The list of active queries. Only one query of each type can be active. */
212 struct list_head active_query_list
;
214 unsigned num_query_running
;
215 unsigned backend_mask
;
216 unsigned max_db
; /* for OQ */
217 unsigned num_dest_buffers
;
219 boolean predicate_drawing
;
220 struct r600_range ps_resources
;
221 struct r600_range vs_resources
;
222 struct r600_range fs_resources
;
223 int num_ps_resources
, num_vs_resources
, num_fs_resources
;
224 boolean have_depth_texture
, have_depth_fb
;
229 u32 vgt_num_instances
;
231 u32 vgt_draw_initiator
;
232 u32 indices_bo_offset
;
233 struct r600_resource
*indices
;
236 void r600_get_backend_mask(struct r600_context
*ctx
);
237 int r600_context_init(struct r600_context
*ctx
, struct r600_screen
*screen
);
238 void r600_context_fini(struct r600_context
*ctx
);
239 void r600_context_pipe_state_set(struct r600_context
*ctx
, struct r600_pipe_state
*state
);
240 void r600_context_pipe_state_set_ps_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
241 void r600_context_pipe_state_set_vs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
242 void r600_context_pipe_state_set_fs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
243 void r600_context_pipe_state_set_ps_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
244 void r600_context_pipe_state_set_vs_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
245 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
);
246 void r600_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
);
248 struct r600_query
*r600_context_query_create(struct r600_context
*ctx
, unsigned query_type
);
249 void r600_context_query_destroy(struct r600_context
*ctx
, struct r600_query
*query
);
250 boolean
r600_context_query_result(struct r600_context
*ctx
,
251 struct r600_query
*query
,
252 boolean wait
, void *vresult
);
253 void r600_query_begin(struct r600_context
*ctx
, struct r600_query
*query
);
254 void r600_query_end(struct r600_context
*ctx
, struct r600_query
*query
);
255 void r600_context_queries_suspend(struct r600_context
*ctx
);
256 void r600_context_queries_resume(struct r600_context
*ctx
);
257 void r600_query_predication(struct r600_context
*ctx
, struct r600_query
*query
, int operation
,
259 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_resource
*fence
,
260 unsigned offset
, unsigned value
);
261 void r600_context_flush_all(struct r600_context
*ctx
, unsigned flush_flags
);
262 void r600_context_flush_dest_caches(struct r600_context
*ctx
);
264 int evergreen_context_init(struct r600_context
*ctx
, struct r600_screen
*screen
);
265 void evergreen_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
);
266 void evergreen_context_flush_dest_caches(struct r600_context
*ctx
);
267 void evergreen_context_pipe_state_set_ps_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
268 void evergreen_context_pipe_state_set_vs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
269 void evergreen_context_pipe_state_set_fs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
270 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
271 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
273 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
274 struct r600_pipe_state
*state
,
275 u32 offset
, u32 value
, u32 mask
,
276 u32 range_id
, u32 block_id
,
277 struct r600_resource
*bo
,
278 enum radeon_bo_usage usage
);
280 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
281 u32 offset
, u32 value
, u32 mask
,
282 struct r600_resource
*bo
,
283 enum radeon_bo_usage usage
);
285 #define r600_pipe_state_add_reg(state, offset, value, mask, bo, usage) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
287 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state
*state
,
290 state
->regs
[state
->nregs
].value
= value
;
294 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state
*state
,
295 u32 value
, struct r600_resource
*bo
,
296 enum radeon_bo_usage usage
)
298 state
->regs
[state
->nregs
].value
= value
;
299 state
->regs
[state
->nregs
].bo
= bo
;
300 state
->regs
[state
->nregs
].bo_usage
= usage
;