2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
32 #include <util/u_double_list.h>
33 #include <pipe/p_compiler.h>
35 #define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
37 #define R600_ERR(fmt, args...) \
38 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
84 struct r600_tiling_info
{
85 unsigned num_channels
;
90 enum radeon_family
r600_get_family(struct radeon
*rw
);
91 enum chip_class
r600_get_family_class(struct radeon
*radeon
);
92 struct r600_tiling_info
*r600_get_tiling_info(struct radeon
*radeon
);
93 unsigned r600_get_clock_crystal_freq(struct radeon
*radeon
);
94 unsigned r600_get_minor_version(struct radeon
*radeon
);
95 unsigned r600_get_num_backends(struct radeon
*radeon
);
99 struct r600_bo
*r600_bo(struct radeon
*radeon
,
100 unsigned size
, unsigned alignment
,
101 unsigned binding
, unsigned usage
);
102 struct r600_bo
*r600_bo_handle(struct radeon
*radeon
,
103 unsigned handle
, unsigned *array_mode
);
104 void *r600_bo_map(struct radeon
*radeon
, struct r600_bo
*bo
, unsigned usage
, void *ctx
);
105 void r600_bo_unmap(struct radeon
*radeon
, struct r600_bo
*bo
);
106 void r600_bo_reference(struct radeon
*radeon
, struct r600_bo
**dst
,
107 struct r600_bo
*src
);
108 boolean
r600_bo_get_winsys_handle(struct radeon
*radeon
, struct r600_bo
*pb_bo
,
109 unsigned stride
, struct winsys_handle
*whandle
);
110 static INLINE
unsigned r600_bo_offset(struct r600_bo
*bo
)
116 /* R600/R700 STATES */
117 #define R600_GROUP_MAX 16
118 #define R600_BLOCK_MAX_BO 32
119 #define R600_BLOCK_MAX_REG 128
121 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
122 /* there is a block entry for each register so 512 blocks */
123 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
124 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
125 #define RANGE_OFFSET_START 0x8000
127 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
129 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
130 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
132 struct r600_pipe_reg
{
135 struct r600_block
*block
;
140 struct r600_pipe_state
{
143 struct r600_pipe_reg regs
[R600_BLOCK_MAX_REG
];
146 struct r600_pipe_resource_state
{
149 struct r600_bo
*bo
[2];
152 #define R600_BLOCK_STATUS_ENABLED (1 << 0)
153 #define R600_BLOCK_STATUS_DIRTY (1 << 1)
155 struct r600_block_reloc
{
157 unsigned flush_flags
;
159 unsigned bo_pm4_index
;
163 struct list_head list
;
164 struct list_head enable_list
;
167 unsigned start_offset
;
168 unsigned pm4_ndwords
;
169 unsigned pm4_flush_ndwords
;
174 u32 pm4
[R600_BLOCK_MAX_REG
];
175 unsigned pm4_bo_index
[R600_BLOCK_MAX_REG
];
176 struct r600_block_reloc reloc
[R600_BLOCK_MAX_BO
];
180 struct r600_block
**blocks
;
189 uint32_t read_domain
;
190 uint32_t write_domain
;
200 /* The kind of query. Currently only OQ is supported. */
202 /* How many results have been written, in dwords. It's incremented
203 * after end_query and flush. */
204 unsigned num_results
;
205 /* if we've flushed the query */
207 /* The buffer where query results are stored. */
208 struct r600_bo
*buffer
;
209 unsigned buffer_size
;
210 /* linked list of queries */
211 struct list_head list
;
214 #define R600_QUERY_STATE_STARTED (1 << 0)
215 #define R600_QUERY_STATE_ENDED (1 << 1)
216 #define R600_QUERY_STATE_SUSPENDED (1 << 2)
218 #define R600_CONTEXT_DRAW_PENDING (1 << 0)
219 #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
220 #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2)
222 struct r600_context
{
223 struct radeon
*radeon
;
224 struct r600_range
*range
;
226 struct r600_block
**blocks
;
227 struct list_head dirty
;
228 struct list_head enable_list
;
229 unsigned pm4_ndwords
;
230 unsigned pm4_cdwords
;
231 unsigned pm4_dirty_cdwords
;
232 unsigned ctx_pm4_ndwords
;
235 struct r600_reloc
*reloc
;
236 struct radeon_bo
**bo
;
238 struct list_head query_list
;
239 unsigned num_query_running
;
240 struct list_head fenced_bo
;
241 unsigned max_db
; /* for OQ */
242 unsigned num_dest_buffers
;
244 boolean predicate_drawing
;
245 struct r600_range ps_resources
;
246 struct r600_range vs_resources
;
247 struct r600_range fs_resources
;
248 int num_ps_resources
, num_vs_resources
, num_fs_resources
;
253 u32 vgt_num_instances
;
255 u32 vgt_draw_initiator
;
256 u32 indices_bo_offset
;
257 struct r600_bo
*indices
;
260 int r600_context_init(struct r600_context
*ctx
, struct radeon
*radeon
);
261 void r600_context_fini(struct r600_context
*ctx
);
262 void r600_context_pipe_state_set(struct r600_context
*ctx
, struct r600_pipe_state
*state
);
263 void r600_context_pipe_state_set_ps_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
264 void r600_context_pipe_state_set_vs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
265 void r600_context_pipe_state_set_fs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
266 void r600_context_pipe_state_set_ps_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
267 void r600_context_pipe_state_set_vs_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
268 void r600_context_flush(struct r600_context
*ctx
);
269 void r600_context_dump_bof(struct r600_context
*ctx
, const char *file
);
270 void r600_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
);
272 struct r600_query
*r600_context_query_create(struct r600_context
*ctx
, unsigned query_type
);
273 void r600_context_query_destroy(struct r600_context
*ctx
, struct r600_query
*query
);
274 boolean
r600_context_query_result(struct r600_context
*ctx
,
275 struct r600_query
*query
,
276 boolean wait
, void *vresult
);
277 void r600_query_begin(struct r600_context
*ctx
, struct r600_query
*query
);
278 void r600_query_end(struct r600_context
*ctx
, struct r600_query
*query
);
279 void r600_context_queries_suspend(struct r600_context
*ctx
);
280 void r600_context_queries_resume(struct r600_context
*ctx
);
281 void r600_query_predication(struct r600_context
*ctx
, struct r600_query
*query
, int operation
,
283 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_bo
*fence
,
284 unsigned offset
, unsigned value
);
285 void r600_context_flush_all(struct r600_context
*ctx
, unsigned flush_flags
);
286 void r600_context_flush_dest_caches(struct r600_context
*ctx
);
288 int evergreen_context_init(struct r600_context
*ctx
, struct radeon
*radeon
);
289 void evergreen_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
);
290 void evergreen_context_flush_dest_caches(struct r600_context
*ctx
);
291 void evergreen_context_pipe_state_set_ps_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
292 void evergreen_context_pipe_state_set_vs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
293 void evergreen_context_pipe_state_set_fs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
);
294 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
295 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
);
297 struct radeon
*radeon_decref(struct radeon
*radeon
);
299 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
300 struct r600_pipe_state
*state
,
301 u32 offset
, u32 value
, u32 mask
,
302 u32 range_id
, u32 block_id
,
305 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
306 u32 offset
, u32 value
, u32 mask
,
308 #define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
310 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state
*state
,
313 state
->regs
[state
->nregs
].value
= value
;
317 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state
*state
,
318 u32 value
, struct r600_bo
*bo
)
320 state
->regs
[state
->nregs
].value
= value
;
321 state
->regs
[state
->nregs
].bo
= bo
;