src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include <stdint.h>
  30 #include <stdio.h>
  31
  32 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  33
  34 #define R600_ERR(fmt, args...) \
  35         fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
  36
  37 typedef uint64_t                u64;
  38 typedef uint32_t                u32;
  39 typedef uint16_t                u16;
  40 typedef uint8_t                 u8;
  41
  42 struct radeon;
  43
  44 enum radeon_family {
  45         CHIP_UNKNOWN,
  46         CHIP_R100,
  47         CHIP_RV100,
  48         CHIP_RS100,
  49         CHIP_RV200,
  50         CHIP_RS200,
  51         CHIP_R200,
  52         CHIP_RV250,
  53         CHIP_RS300,
  54         CHIP_RV280,
  55         CHIP_R300,
  56         CHIP_R350,
  57         CHIP_RV350,
  58         CHIP_RV380,
  59         CHIP_R420,
  60         CHIP_R423,
  61         CHIP_RV410,
  62         CHIP_RS400,
  63         CHIP_RS480,
  64         CHIP_RS600,
  65         CHIP_RS690,
  66         CHIP_RS740,
  67         CHIP_RV515,
  68         CHIP_R520,
  69         CHIP_RV530,
  70         CHIP_RV560,
  71         CHIP_RV570,
  72         CHIP_R580,
  73         CHIP_R600,
  74         CHIP_RV610,
  75         CHIP_RV630,
  76         CHIP_RV670,
  77         CHIP_RV620,
  78         CHIP_RV635,
  79         CHIP_RS780,
  80         CHIP_RS880,
  81         CHIP_RV770,
  82         CHIP_RV730,
  83         CHIP_RV710,
  84         CHIP_RV740,
  85         CHIP_CEDAR,
  86         CHIP_REDWOOD,
  87         CHIP_JUNIPER,
  88         CHIP_CYPRESS,
  89         CHIP_HEMLOCK,
  90         CHIP_LAST,
  91 };
  92
  93 enum chip_class {
  94         R600,
  95         R700,
  96         EVERGREEN,
  97 };
  98
  99 enum radeon_family r600_get_family(struct radeon *rw);
 100 enum chip_class r600_get_family_class(struct radeon *radeon);
 101
 102 /* lowlevel WS bo */
 103 struct radeon_ws_bo;
 104 struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
 105                                   unsigned size, unsigned alignment, unsigned usage);
 106 struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
 107                                          unsigned handle);
 108 void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
 109 void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
 110 void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
 111                             struct radeon_ws_bo *src);
 112
 113 /* R600/R700 STATES */
 114 #define R600_GROUP_MAX                  16
 115 #define R600_BLOCK_MAX_BO               32
 116 #define R600_BLOCK_MAX_REG              128
 117
 118 enum r600_group_id {
 119         R600_GROUP_CONFIG = 0,
 120         R600_GROUP_CONTEXT,
 121         R600_GROUP_ALU_CONST,
 122         R600_GROUP_RESOURCE,
 123         R600_GROUP_SAMPLER,
 124         R600_GROUP_CTL_CONST,
 125         R600_GROUP_LOOP_CONST,
 126         R600_GROUP_BOOL_CONST,
 127         R600_NGROUPS
 128 };
 129
 130 struct r600_pipe_reg {
 131         unsigned                        group_id;
 132         u32                             offset;
 133         u32                             mask;
 134         u32                             value;
 135         struct radeon_ws_bo             *bo;
 136 };
 137
 138 struct r600_pipe_state {
 139         unsigned                        id;
 140         unsigned                        nregs;
 141         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 142 };
 143
 144 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 145                                         unsigned group_id, u32 offset,
 146                                         u32 value, u32 mask,
 147                                         struct radeon_ws_bo *bo)
 148 {
 149         state->regs[state->nregs].group_id = group_id;
 150         state->regs[state->nregs].offset = offset;
 151         state->regs[state->nregs].value = value;
 152         state->regs[state->nregs].mask = mask;
 153         state->regs[state->nregs].bo = bo;
 154         state->nregs++;
 155         assert(state->nregs < R600_BLOCK_MAX_REG);
 156 }
 157
 158 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 159 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 160
 161 struct r600_block_reloc {
 162         struct radeon_ws_bo     *bo;
 163         unsigned                nreloc;
 164         unsigned                bo_pm4_index[R600_BLOCK_MAX_BO];
 165 };
 166
 167 struct r600_group_block {
 168         unsigned                status;
 169         unsigned                start_offset;
 170         unsigned                pm4_ndwords;
 171         unsigned                nbo;
 172         unsigned                nreg;
 173         u32                     pm4[R600_BLOCK_MAX_REG];
 174         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 175         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 176 };
 177
 178 struct r600_group {
 179         unsigned                start_offset;
 180         unsigned                end_offset;
 181         unsigned                nblocks;
 182         struct r600_group_block *blocks;
 183         unsigned                *offset_block_id;
 184 };
 185
 186 #pragma pack(1)
 187 struct r600_reloc {
 188         uint32_t        handle;
 189         uint32_t        read_domain;
 190         uint32_t        write_domain;
 191         uint32_t        flags;
 192 };
 193 #pragma pack()
 194
 195 struct r600_context {
 196         struct radeon           *radeon;
 197         unsigned                ngroups;
 198         struct r600_group       groups[R600_GROUP_MAX];
 199         unsigned                pm4_ndwords;
 200         unsigned                pm4_cdwords;
 201         unsigned                pm4_dirty_cdwords;
 202         unsigned                ctx_pm4_ndwords;
 203         unsigned                nreloc;
 204         unsigned                creloc;
 205         struct r600_reloc       *reloc;
 206         struct radeon_ws_bo     **bo;
 207         u32                     *pm4;
 208 };
 209
 210 struct r600_draw {
 211         u32                     vgt_num_indices;
 212         u32                     vgt_num_instances;
 213         u32                     vgt_index_type;
 214         u32                     vgt_draw_initiator;
 215         u32                     indices_bo_offset;
 216         struct radeon_ws_bo     *indices;
 217 };
 218
 219 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 220 void r600_context_fini(struct r600_context *ctx);
 221 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 222 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 223 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 224 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 225 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 226 void r600_context_flush(struct r600_context *ctx);
 227 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 228 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 229
 230 #endif