src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30 #include "util/u_double_list.h"
  31 #include "util/u_vbuf.h"
  32
  33 #define R600_ERR(fmt, args...) \
  34         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  35
  36 struct winsys_handle;
  37
  38 enum radeon_family {
  39         CHIP_UNKNOWN,
  40         CHIP_R600,
  41         CHIP_RV610,
  42         CHIP_RV630,
  43         CHIP_RV670,
  44         CHIP_RV620,
  45         CHIP_RV635,
  46         CHIP_RS780,
  47         CHIP_RS880,
  48         CHIP_RV770,
  49         CHIP_RV730,
  50         CHIP_RV710,
  51         CHIP_RV740,
  52         CHIP_CEDAR,
  53         CHIP_REDWOOD,
  54         CHIP_JUNIPER,
  55         CHIP_CYPRESS,
  56         CHIP_HEMLOCK,
  57         CHIP_PALM,
  58         CHIP_SUMO,
  59         CHIP_SUMO2,
  60         CHIP_BARTS,
  61         CHIP_TURKS,
  62         CHIP_CAICOS,
  63         CHIP_CAYMAN,
  64         CHIP_LAST,
  65 };
  66
  67 enum chip_class {
  68         R600,
  69         R700,
  70         EVERGREEN,
  71         CAYMAN,
  72 };
  73
  74 struct r600_tiling_info {
  75         unsigned num_channels;
  76         unsigned num_banks;
  77         unsigned group_bytes;
  78 };
  79
  80 struct r600_resource {
  81         struct u_vbuf_resource          b;
  82
  83         /* Winsys objects. */
  84         struct pb_buffer                *buf;
  85         struct radeon_winsys_cs_handle  *cs_buf;
  86
  87         /* Resource state. */
  88         unsigned                        domains;
  89 };
  90
  91 /* R600/R700 STATES */
  92 #define R600_GROUP_MAX                  16
  93 #define R600_BLOCK_MAX_BO               32
  94 #define R600_BLOCK_MAX_REG              128
  95
  96 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
  97 /* there is a block entry for each register so 512 blocks */
  98 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
  99 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
 100 #define RANGE_OFFSET_START 0x8000
 101 #define HASH_SHIFT 9
 102 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
 103
 104 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
 105 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 106
 107 struct r600_pipe_reg {
 108         uint32_t                        value;
 109         struct r600_block               *block;
 110         struct r600_resource            *bo;
 111         enum radeon_bo_usage            bo_usage;
 112         uint32_t                        id;
 113 };
 114
 115 struct r600_pipe_state {
 116         unsigned                        id;
 117         unsigned                        nregs;
 118         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 119 };
 120
 121 struct r600_pipe_resource_state {
 122         unsigned                        id;
 123         uint32_t                        val[8];
 124         struct r600_resource            *bo[2];
 125         enum radeon_bo_usage            bo_usage[2];
 126 };
 127
 128 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 129 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 130 #define R600_BLOCK_STATUS_RESOURCE_DIRTY        (1 << 2)
 131
 132 #define R600_BLOCK_STATUS_RESOURCE_VERTEX       (1 << 3)
 133
 134 struct r600_block_reloc {
 135         struct r600_resource    *bo;
 136         enum radeon_bo_usage    bo_usage;
 137         unsigned                bo_pm4_index;
 138 };
 139
 140 struct r600_block {
 141         struct list_head        list;
 142         struct list_head        enable_list;
 143         unsigned                status;
 144         unsigned                flags;
 145         unsigned                start_offset;
 146         unsigned                pm4_ndwords;
 147         unsigned                nbo;
 148         uint16_t                nreg;
 149         uint16_t                nreg_dirty;
 150         uint32_t                *reg;
 151         uint32_t                pm4[R600_BLOCK_MAX_REG];
 152         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 153         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 154 };
 155
 156 struct r600_range {
 157         struct r600_block       **blocks;
 158 };
 159
 160 struct r600_query_buffer {
 161         /* The buffer where query results are stored. */
 162         struct r600_resource                    *buf;
 163         /* Offset of the next free result after current query data */
 164         unsigned                                results_end;
 165         /* If a query buffer is full, a new buffer is created and the old one
 166          * is put in here. When we calculate the result, we sum up the samples
 167          * from all buffers. */
 168         struct r600_query_buffer                *previous;
 169 };
 170
 171 union r600_query_result {
 172         uint64_t                        u64;
 173         boolean                         b;
 174         struct pipe_query_data_so_statistics so;
 175 };
 176
 177 struct r600_query {
 178         /* The query buffer and how many results are in it. */
 179         struct r600_query_buffer                buffer;
 180         /* The type of query */
 181         unsigned                                type;
 182         /* Size of the result in memory for both begin_query and end_query,
 183          * this can be one or two numbers, or it could even be a size of a structure. */
 184         unsigned                                result_size;
 185         /* The number of dwords for begin_query or end_query. */
 186         unsigned                                num_cs_dw;
 187         /* linked list of queries */
 188         struct list_head                        list;
 189 };
 190
 191 struct r600_so_target {
 192         struct pipe_stream_output_target b;
 193
 194         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 195         struct r600_resource    *filled_size;
 196         unsigned                stride_in_dw;
 197         unsigned                so_index;
 198 };
 199
 200 #define R600_CONTEXT_DRAW_PENDING       (1 << 0)
 201 #define R600_CONTEXT_DST_CACHES_DIRTY   (1 << 1)
 202 #define R600_CONTEXT_CHECK_EVENT_FLUSH  (1 << 2)
 203
 204 struct r600_context;
 205 struct r600_screen;
 206
 207 void r600_get_backend_mask(struct r600_context *ctx);
 208 int r600_context_init(struct r600_context *ctx);
 209 void r600_context_fini(struct r600_context *ctx);
 210 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 211 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 212 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 213 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 214 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 215 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 216 void r600_context_flush(struct r600_context *ctx, unsigned flags);
 217
 218 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
 219                              unsigned offset, unsigned value);
 220 void r600_inval_shader_cache(struct r600_context *ctx);
 221 void r600_inval_texture_cache(struct r600_context *ctx);
 222 void r600_inval_vertex_cache(struct r600_context *ctx);
 223 void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now);
 224
 225 void r600_context_streamout_begin(struct r600_context *ctx);
 226 void r600_context_streamout_end(struct r600_context *ctx);
 227 void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
 228 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
 229 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
 230 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
 231
 232 int evergreen_context_init(struct r600_context *ctx);
 233 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 234 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 235
 236 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 237                               struct r600_pipe_state *state,
 238                               uint32_t offset, uint32_t value,
 239                               uint32_t range_id, uint32_t block_id,
 240                               struct r600_resource *bo,
 241                               enum radeon_bo_usage usage);
 242
 243 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 244                                      uint32_t offset, uint32_t value,
 245                                      struct r600_resource *bo,
 246                                      enum radeon_bo_usage usage);
 247
 248 #define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
 249
 250 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
 251                                            uint32_t value)
 252 {
 253         state->regs[state->nregs].value = value;
 254         state->nregs++;
 255 }
 256
 257 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
 258                                               uint32_t value, struct r600_resource *bo,
 259                                               enum radeon_bo_usage usage)
 260 {
 261         state->regs[state->nregs].value = value;
 262         state->regs[state->nregs].bo = bo;
 263         state->regs[state->nregs].bo_usage = usage;
 264         state->nregs++;
 265 }
 266
 267 #endif