src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include "util/u_double_list.h"
  30 #include "util/u_inlines.h"
  31
  32 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  33
  34 #define R600_ERR(fmt, args...) \
  35         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  36
  37 typedef uint64_t                u64;
  38 typedef uint32_t                u32;
  39 typedef uint16_t                u16;
  40 typedef uint8_t                 u8;
  41
  42 struct radeon;
  43 struct winsys_handle;
  44
  45 enum radeon_family {
  46         CHIP_UNKNOWN,
  47         CHIP_R600,
  48         CHIP_RV610,
  49         CHIP_RV630,
  50         CHIP_RV670,
  51         CHIP_RV620,
  52         CHIP_RV635,
  53         CHIP_RS780,
  54         CHIP_RS880,
  55         CHIP_RV770,
  56         CHIP_RV730,
  57         CHIP_RV710,
  58         CHIP_RV740,
  59         CHIP_CEDAR,
  60         CHIP_REDWOOD,
  61         CHIP_JUNIPER,
  62         CHIP_CYPRESS,
  63         CHIP_HEMLOCK,
  64         CHIP_PALM,
  65         CHIP_SUMO,
  66         CHIP_SUMO2,
  67         CHIP_BARTS,
  68         CHIP_TURKS,
  69         CHIP_CAICOS,
  70         CHIP_CAYMAN,
  71         CHIP_LAST,
  72 };
  73
  74 enum chip_class {
  75         R600,
  76         R700,
  77         EVERGREEN,
  78         CAYMAN,
  79 };
  80
  81 struct r600_tiling_info {
  82         unsigned num_channels;
  83         unsigned num_banks;
  84         unsigned group_bytes;
  85 };
  86
  87 enum radeon_family r600_get_family(struct radeon *rw);
  88 enum chip_class r600_get_family_class(struct radeon *radeon);
  89 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
  90 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
  91 unsigned r600_get_minor_version(struct radeon *radeon);
  92 unsigned r600_get_num_backends(struct radeon *radeon);
  93 unsigned r600_get_num_tile_pipes(struct radeon *radeon);
  94 unsigned r600_get_backend_map(struct radeon *radeon);
  95
  96 /* r600_bo.c */
  97 struct r600_bo;
  98 struct radeon_winsys_cs;
  99
 100 struct r600_bo *r600_bo(struct radeon *radeon,
 101                         unsigned size, unsigned alignment,
 102                         unsigned binding, unsigned usage);
 103 struct r600_bo *r600_bo_handle(struct radeon *radeon, struct winsys_handle *whandle,
 104                                 unsigned *stride, unsigned *array_mode);
 105 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, struct radeon_winsys_cs *cs, unsigned usage);
 106 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 107 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
 108                                   unsigned stride, struct winsys_handle *whandle);
 109
 110 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
 111
 112 /* this relies on the pipe_reference being the first member of r600_bo */
 113 static INLINE void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src)
 114 {
 115         struct r600_bo *old = *dst;
 116
 117         if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) {
 118                 r600_bo_destroy(radeon, old);
 119         }
 120         *dst = src;
 121 }
 122
 123
 124 /* R600/R700 STATES */
 125 #define R600_GROUP_MAX                  16
 126 #define R600_BLOCK_MAX_BO               32
 127 #define R600_BLOCK_MAX_REG              128
 128
 129 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
 130 /* there is a block entry for each register so 512 blocks */
 131 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
 132 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
 133 #define RANGE_OFFSET_START 0x8000
 134 #define HASH_SHIFT 9
 135 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
 136
 137 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
 138 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 139
 140 struct r600_pipe_reg {
 141         u32                             value;
 142         u32                             mask;
 143         struct r600_block               *block;
 144         struct r600_bo                  *bo;
 145         u32                             id;
 146 };
 147
 148 struct r600_pipe_state {
 149         unsigned                        id;
 150         unsigned                        nregs;
 151         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 152 };
 153
 154 struct r600_pipe_resource_state {
 155         unsigned                        id;
 156         u32                             val[8];
 157         struct r600_bo *bo[2];
 158 };
 159
 160 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 161 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 162 #define R600_BLOCK_STATUS_RESOURCE_DIRTY        (1 << 2)
 163
 164 #define R600_BLOCK_STATUS_RESOURCE_VERTEX       (1 << 3)
 165
 166 struct r600_block_reloc {
 167         struct r600_bo          *bo;
 168         unsigned                flush_flags;
 169         unsigned                flush_mask;
 170         unsigned                bo_pm4_index;
 171 };
 172
 173 struct r600_block {
 174         struct list_head        list;
 175         struct list_head        enable_list;
 176         unsigned                status;
 177         unsigned                flags;
 178         unsigned                start_offset;
 179         unsigned                pm4_ndwords;
 180         unsigned                pm4_flush_ndwords;
 181         unsigned                nbo;
 182         u16                     nreg;
 183         u16                     nreg_dirty;
 184         u32                     *reg;
 185         u32                     pm4[R600_BLOCK_MAX_REG];
 186         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 187         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 188 };
 189
 190 struct r600_range {
 191         struct r600_block       **blocks;
 192 };
 193
 194 /*
 195  * query
 196  */
 197 struct r600_query {
 198         u64                                     result;
 199         /* The kind of query */
 200         unsigned                                type;
 201         /* Offset of the first result for current query */
 202         unsigned                                results_start;
 203         /* Offset of the next free result after current query data */
 204         unsigned                                results_end;
 205         /* Size of the result */
 206         unsigned                                result_size;
 207         /* Count of new queries started in one stream without flushing */
 208         unsigned                                queries_emitted;
 209         /* State flags */
 210         unsigned                                state;
 211         /* The buffer where query results are stored. It's used as a ring,
 212          * data blocks for current query are stored sequentially from
 213          * results_start to results_end, with wrapping on the buffer end */
 214         struct r600_bo                  *buffer;
 215         unsigned                                buffer_size;
 216         /* linked list of queries */
 217         struct list_head                        list;
 218 };
 219
 220 #define R600_QUERY_STATE_STARTED        (1 << 0)
 221 #define R600_QUERY_STATE_ENDED          (1 << 1)
 222 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 223 #define R600_QUERY_STATE_FLUSHED        (1 << 3)
 224
 225 #define R600_CONTEXT_DRAW_PENDING       (1 << 0)
 226 #define R600_CONTEXT_DST_CACHES_DIRTY   (1 << 1)
 227 #define R600_CONTEXT_CHECK_EVENT_FLUSH  (1 << 2)
 228
 229 struct r600_context {
 230         struct radeon           *radeon;
 231         struct radeon_winsys_cs *cs;
 232
 233         struct r600_range       *range;
 234         unsigned                nblocks;
 235         struct r600_block       **blocks;
 236         struct list_head        dirty;
 237         struct list_head        resource_dirty;
 238         struct list_head        enable_list;
 239         unsigned                pm4_ndwords;
 240         unsigned                pm4_dirty_cdwords;
 241         unsigned                ctx_pm4_ndwords;
 242         unsigned                init_dwords;
 243
 244         unsigned                creloc;
 245         struct radeon_bo        **bo;
 246
 247         u32                     *pm4;
 248         unsigned                pm4_cdwords;
 249
 250         struct list_head        query_list;
 251         unsigned                num_query_running;
 252         unsigned                backend_mask;
 253         unsigned                max_db; /* for OQ */
 254         unsigned                num_dest_buffers;
 255         unsigned                flags;
 256         boolean                 predicate_drawing;
 257         struct r600_range ps_resources;
 258         struct r600_range vs_resources;
 259         struct r600_range fs_resources;
 260         int num_ps_resources, num_vs_resources, num_fs_resources;
 261         boolean                 have_depth_texture, have_depth_fb;
 262 };
 263
 264 struct r600_draw {
 265         u32                     vgt_num_indices;
 266         u32                     vgt_num_instances;
 267         u32                     vgt_index_type;
 268         u32                     vgt_draw_initiator;
 269         u32                     indices_bo_offset;
 270         struct r600_bo          *indices;
 271 };
 272
 273 void r600_get_backend_mask(struct r600_context *ctx);
 274 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 275 void r600_context_fini(struct r600_context *ctx);
 276 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 277 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 278 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 279 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 280 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 281 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 282 void r600_context_flush(struct r600_context *ctx, unsigned flags);
 283 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 284
 285 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 286 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 287 boolean r600_context_query_result(struct r600_context *ctx,
 288                                 struct r600_query *query,
 289                                 boolean wait, void *vresult);
 290 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 291 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 292 void r600_context_queries_suspend(struct r600_context *ctx);
 293 void r600_context_queries_resume(struct r600_context *ctx, boolean flushed);
 294 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
 295                             int flag_wait);
 296 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
 297                              unsigned offset, unsigned value);
 298 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
 299 void r600_context_flush_dest_caches(struct r600_context *ctx);
 300
 301 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 302 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 303 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
 304 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 305 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 306 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 307 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 308 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 309
 310 struct radeon *radeon_destroy(struct radeon *radeon);
 311
 312 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 313                               struct r600_pipe_state *state,
 314                               u32 offset, u32 value, u32 mask,
 315                               u32 range_id, u32 block_id,
 316                               struct r600_bo *bo);
 317
 318 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 319                                      u32 offset, u32 value, u32 mask,
 320                                      struct r600_bo *bo);
 321 #define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
 322
 323 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
 324                                            u32 value)
 325 {
 326         state->regs[state->nregs].value = value;
 327         state->nregs++;
 328 }
 329
 330 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
 331                                            u32 value, struct r600_bo *bo)
 332 {
 333         state->regs[state->nregs].value = value;
 334         state->regs[state->nregs].bo = bo;
 335         state->nregs++;
 336 }
 337
 338 #endif