src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30 #include "util/u_double_list.h"
  31
  32 #define R600_ERR(fmt, args...) \
  33         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  34
  35 typedef uint64_t                u64;
  36 typedef uint32_t                u32;
  37 typedef uint16_t                u16;
  38 typedef uint8_t                 u8;
  39
  40 struct radeon;
  41 struct winsys_handle;
  42
  43 enum radeon_family {
  44         CHIP_UNKNOWN,
  45         CHIP_R600,
  46         CHIP_RV610,
  47         CHIP_RV630,
  48         CHIP_RV670,
  49         CHIP_RV620,
  50         CHIP_RV635,
  51         CHIP_RS780,
  52         CHIP_RS880,
  53         CHIP_RV770,
  54         CHIP_RV730,
  55         CHIP_RV710,
  56         CHIP_RV740,
  57         CHIP_CEDAR,
  58         CHIP_REDWOOD,
  59         CHIP_JUNIPER,
  60         CHIP_CYPRESS,
  61         CHIP_HEMLOCK,
  62         CHIP_PALM,
  63         CHIP_SUMO,
  64         CHIP_SUMO2,
  65         CHIP_BARTS,
  66         CHIP_TURKS,
  67         CHIP_CAICOS,
  68         CHIP_CAYMAN,
  69         CHIP_LAST,
  70 };
  71
  72 enum chip_class {
  73         R600,
  74         R700,
  75         EVERGREEN,
  76         CAYMAN,
  77 };
  78
  79 struct r600_tiling_info {
  80         unsigned num_channels;
  81         unsigned num_banks;
  82         unsigned group_bytes;
  83 };
  84
  85 enum radeon_family r600_get_family(struct radeon *rw);
  86 enum chip_class r600_get_family_class(struct radeon *radeon);
  87
  88 /* r600_bo.c */
  89 struct r600_bo;
  90 struct radeon_winsys_cs;
  91
  92 struct r600_bo *r600_bo(struct radeon *radeon,
  93                         unsigned size, unsigned alignment,
  94                         unsigned binding, unsigned usage);
  95 struct r600_bo *r600_bo_handle(struct radeon *radeon, struct winsys_handle *whandle,
  96                                 unsigned *stride, unsigned *array_mode);
  97 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, struct radeon_winsys_cs *cs, unsigned usage);
  98 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
  99 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
 100                                   unsigned stride, struct winsys_handle *whandle);
 101
 102 void r600_bo_destroy(struct r600_bo *bo);
 103
 104 /* this relies on the pipe_reference being the first member of r600_bo */
 105 static INLINE void r600_bo_reference(struct r600_bo **dst, struct r600_bo *src)
 106 {
 107         struct r600_bo *old = *dst;
 108
 109         if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) {
 110                 r600_bo_destroy(old);
 111         }
 112         *dst = src;
 113 }
 114
 115
 116 /* R600/R700 STATES */
 117 #define R600_GROUP_MAX                  16
 118 #define R600_BLOCK_MAX_BO               32
 119 #define R600_BLOCK_MAX_REG              128
 120
 121 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
 122 /* there is a block entry for each register so 512 blocks */
 123 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
 124 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
 125 #define RANGE_OFFSET_START 0x8000
 126 #define HASH_SHIFT 9
 127 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
 128
 129 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
 130 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 131
 132 struct r600_pipe_reg {
 133         u32                             value;
 134         u32                             mask;
 135         struct r600_block               *block;
 136         struct r600_bo                  *bo;
 137         enum radeon_bo_usage            bo_usage;
 138         u32                             id;
 139 };
 140
 141 struct r600_pipe_state {
 142         unsigned                        id;
 143         unsigned                        nregs;
 144         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 145 };
 146
 147 struct r600_pipe_resource_state {
 148         unsigned                        id;
 149         u32                             val[8];
 150         struct r600_bo                  *bo[2];
 151         enum radeon_bo_usage            bo_usage[2]; /* XXX set these */
 152 };
 153
 154 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 155 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 156 #define R600_BLOCK_STATUS_RESOURCE_DIRTY        (1 << 2)
 157
 158 #define R600_BLOCK_STATUS_RESOURCE_VERTEX       (1 << 3)
 159
 160 struct r600_block_reloc {
 161         struct r600_bo          *bo;
 162         enum radeon_bo_usage    bo_usage;
 163         unsigned                flush_flags;
 164         unsigned                flush_mask;
 165         unsigned                bo_pm4_index;
 166 };
 167
 168 struct r600_block {
 169         struct list_head        list;
 170         struct list_head        enable_list;
 171         unsigned                status;
 172         unsigned                flags;
 173         unsigned                start_offset;
 174         unsigned                pm4_ndwords;
 175         unsigned                pm4_flush_ndwords;
 176         unsigned                nbo;
 177         u16                     nreg;
 178         u16                     nreg_dirty;
 179         u32                     *reg;
 180         u32                     pm4[R600_BLOCK_MAX_REG];
 181         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 182         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 183 };
 184
 185 struct r600_range {
 186         struct r600_block       **blocks;
 187 };
 188
 189 /*
 190  * query
 191  */
 192 struct r600_query {
 193         u64                                     result;
 194         /* The kind of query */
 195         unsigned                                type;
 196         /* Offset of the first result for current query */
 197         unsigned                                results_start;
 198         /* Offset of the next free result after current query data */
 199         unsigned                                results_end;
 200         /* Size of the result */
 201         unsigned                                result_size;
 202         /* Count of new queries started in one stream without flushing */
 203         unsigned                                queries_emitted;
 204         /* State flags */
 205         unsigned                                state;
 206         /* The buffer where query results are stored. It's used as a ring,
 207          * data blocks for current query are stored sequentially from
 208          * results_start to results_end, with wrapping on the buffer end */
 209         struct r600_bo                  *buffer;
 210         unsigned                                buffer_size;
 211         /* linked list of queries */
 212         struct list_head                        list;
 213 };
 214
 215 #define R600_QUERY_STATE_STARTED        (1 << 0)
 216 #define R600_QUERY_STATE_ENDED          (1 << 1)
 217 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 218 #define R600_QUERY_STATE_FLUSHED        (1 << 3)
 219
 220 #define R600_CONTEXT_DRAW_PENDING       (1 << 0)
 221 #define R600_CONTEXT_DST_CACHES_DIRTY   (1 << 1)
 222 #define R600_CONTEXT_CHECK_EVENT_FLUSH  (1 << 2)
 223
 224 struct r600_context {
 225         struct radeon           *radeon;
 226         struct radeon_winsys_cs *cs;
 227
 228         struct r600_range       *range;
 229         unsigned                nblocks;
 230         struct r600_block       **blocks;
 231         struct list_head        dirty;
 232         struct list_head        resource_dirty;
 233         struct list_head        enable_list;
 234         unsigned                pm4_ndwords;
 235         unsigned                pm4_dirty_cdwords;
 236         unsigned                ctx_pm4_ndwords;
 237         unsigned                init_dwords;
 238
 239         unsigned                creloc;
 240         struct r600_bo          **bo;
 241
 242         u32                     *pm4;
 243         unsigned                pm4_cdwords;
 244
 245         struct list_head        query_list;
 246         unsigned                num_query_running;
 247         unsigned                backend_mask;
 248         unsigned                max_db; /* for OQ */
 249         unsigned                num_dest_buffers;
 250         unsigned                flags;
 251         boolean                 predicate_drawing;
 252         struct r600_range ps_resources;
 253         struct r600_range vs_resources;
 254         struct r600_range fs_resources;
 255         int num_ps_resources, num_vs_resources, num_fs_resources;
 256         boolean                 have_depth_texture, have_depth_fb;
 257 };
 258
 259 struct r600_draw {
 260         u32                     vgt_num_indices;
 261         u32                     vgt_num_instances;
 262         u32                     vgt_index_type;
 263         u32                     vgt_draw_initiator;
 264         u32                     indices_bo_offset;
 265         struct r600_bo          *indices;
 266 };
 267
 268 void r600_get_backend_mask(struct r600_context *ctx);
 269 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 270 void r600_context_fini(struct r600_context *ctx);
 271 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 272 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 273 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 274 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 275 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 276 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 277 void r600_context_flush(struct r600_context *ctx, unsigned flags);
 278 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 279
 280 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 281 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 282 boolean r600_context_query_result(struct r600_context *ctx,
 283                                 struct r600_query *query,
 284                                 boolean wait, void *vresult);
 285 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 286 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 287 void r600_context_queries_suspend(struct r600_context *ctx);
 288 void r600_context_queries_resume(struct r600_context *ctx, boolean flushed);
 289 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
 290                             int flag_wait);
 291 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
 292                              unsigned offset, unsigned value);
 293 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
 294 void r600_context_flush_dest_caches(struct r600_context *ctx);
 295
 296 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 297 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 298 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
 299 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 300 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 301 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 302 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 303 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 304
 305 struct radeon *radeon_create(struct radeon_winsys *ws);
 306 struct radeon *radeon_destroy(struct radeon *radeon);
 307
 308 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 309                               struct r600_pipe_state *state,
 310                               u32 offset, u32 value, u32 mask,
 311                               u32 range_id, u32 block_id,
 312                               struct r600_bo *bo,
 313                               enum radeon_bo_usage usage);
 314
 315 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 316                                      u32 offset, u32 value, u32 mask,
 317                                      struct r600_bo *bo,
 318                                      enum radeon_bo_usage usage);
 319
 320 #define r600_pipe_state_add_reg(state, offset, value, mask, bo, usage) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
 321
 322 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
 323                                            u32 value)
 324 {
 325         state->regs[state->nregs].value = value;
 326         state->nregs++;
 327 }
 328
 329 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
 330                                               u32 value, struct r600_bo *bo,
 331                                               enum radeon_bo_usage usage)
 332 {
 333         state->regs[state->nregs].value = value;
 334         state->regs[state->nregs].bo = bo;
 335         state->regs[state->nregs].bo_usage = usage;
 336         state->nregs++;
 337 }
 338
 339 #endif