r600g: occlusion query for new design
[mesa.git] / src / gallium / drivers / r600 / r600.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_H
27 #define R600_H
28
29 #include <stdint.h>
30 #include <stdio.h>
31 #include <util/u_double_list.h>
32 #include <pipe/p_compiler.h>
33
34 #define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
35
36 #define R600_ERR(fmt, args...) \
37 fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
38
39 typedef uint64_t u64;
40 typedef uint32_t u32;
41 typedef uint16_t u16;
42 typedef uint8_t u8;
43
44 struct radeon;
45
46 enum radeon_family {
47 CHIP_UNKNOWN,
48 CHIP_R100,
49 CHIP_RV100,
50 CHIP_RS100,
51 CHIP_RV200,
52 CHIP_RS200,
53 CHIP_R200,
54 CHIP_RV250,
55 CHIP_RS300,
56 CHIP_RV280,
57 CHIP_R300,
58 CHIP_R350,
59 CHIP_RV350,
60 CHIP_RV380,
61 CHIP_R420,
62 CHIP_R423,
63 CHIP_RV410,
64 CHIP_RS400,
65 CHIP_RS480,
66 CHIP_RS600,
67 CHIP_RS690,
68 CHIP_RS740,
69 CHIP_RV515,
70 CHIP_R520,
71 CHIP_RV530,
72 CHIP_RV560,
73 CHIP_RV570,
74 CHIP_R580,
75 CHIP_R600,
76 CHIP_RV610,
77 CHIP_RV630,
78 CHIP_RV670,
79 CHIP_RV620,
80 CHIP_RV635,
81 CHIP_RS780,
82 CHIP_RS880,
83 CHIP_RV770,
84 CHIP_RV730,
85 CHIP_RV710,
86 CHIP_RV740,
87 CHIP_CEDAR,
88 CHIP_REDWOOD,
89 CHIP_JUNIPER,
90 CHIP_CYPRESS,
91 CHIP_HEMLOCK,
92 CHIP_LAST,
93 };
94
95 enum chip_class {
96 R600,
97 R700,
98 EVERGREEN,
99 };
100
101 enum radeon_family r600_get_family(struct radeon *rw);
102 enum chip_class r600_get_family_class(struct radeon *radeon);
103
104 /* lowlevel WS bo */
105 struct radeon_ws_bo;
106 struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
107 unsigned size, unsigned alignment, unsigned usage);
108 struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
109 unsigned handle);
110 void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
111 void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
112 void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
113 struct radeon_ws_bo *src);
114
115 /* R600/R700 STATES */
116 #define R600_GROUP_MAX 16
117 #define R600_BLOCK_MAX_BO 32
118 #define R600_BLOCK_MAX_REG 128
119
120 enum r600_group_id {
121 R600_GROUP_CONFIG = 0,
122 R600_GROUP_CONTEXT,
123 R600_GROUP_ALU_CONST,
124 R600_GROUP_RESOURCE,
125 R600_GROUP_SAMPLER,
126 R600_GROUP_CTL_CONST,
127 R600_GROUP_LOOP_CONST,
128 R600_GROUP_BOOL_CONST,
129 R600_NGROUPS
130 };
131
132 struct r600_pipe_reg {
133 unsigned group_id;
134 u32 offset;
135 u32 mask;
136 u32 value;
137 struct radeon_ws_bo *bo;
138 };
139
140 struct r600_pipe_state {
141 unsigned id;
142 unsigned nregs;
143 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG];
144 };
145
146 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
147 unsigned group_id, u32 offset,
148 u32 value, u32 mask,
149 struct radeon_ws_bo *bo)
150 {
151 state->regs[state->nregs].group_id = group_id;
152 state->regs[state->nregs].offset = offset;
153 state->regs[state->nregs].value = value;
154 state->regs[state->nregs].mask = mask;
155 state->regs[state->nregs].bo = bo;
156 state->nregs++;
157 assert(state->nregs < R600_BLOCK_MAX_REG);
158 }
159
160 #define R600_BLOCK_STATUS_ENABLED (1 << 0)
161 #define R600_BLOCK_STATUS_DIRTY (1 << 1)
162
163 struct r600_block_reloc {
164 struct radeon_ws_bo *bo;
165 unsigned nreloc;
166 unsigned bo_pm4_index[R600_BLOCK_MAX_BO];
167 };
168
169 struct r600_group_block {
170 unsigned status;
171 unsigned start_offset;
172 unsigned pm4_ndwords;
173 unsigned nbo;
174 unsigned nreg;
175 u32 pm4[R600_BLOCK_MAX_REG];
176 unsigned pm4_bo_index[R600_BLOCK_MAX_REG];
177 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
178 };
179
180 struct r600_group {
181 unsigned start_offset;
182 unsigned end_offset;
183 unsigned nblocks;
184 struct r600_group_block *blocks;
185 unsigned *offset_block_id;
186 };
187
188 /*
189 * relocation
190 */
191 #pragma pack(1)
192 struct r600_reloc {
193 uint32_t handle;
194 uint32_t read_domain;
195 uint32_t write_domain;
196 uint32_t flags;
197 };
198 #pragma pack()
199
200 /*
201 * query
202 */
203 struct r600_query {
204 u64 result;
205 /* The kind of query. Currently only OQ is supported. */
206 unsigned type;
207 /* How many results have been written, in dwords. It's incremented
208 * after end_query and flush. */
209 unsigned num_results;
210 /* if we've flushed the query */
211 unsigned state;
212 /* The buffer where query results are stored. */
213 struct radeon_ws_bo *buffer;
214 unsigned buffer_size;
215 /* linked list of queries */
216 struct list_head list;
217 };
218
219 #define R600_QUERY_STATE_STARTED (1 << 0)
220 #define R600_QUERY_STATE_ENDED (1 << 1)
221 #define R600_QUERY_STATE_SUSPENDED (1 << 2)
222
223
224 struct r600_context {
225 struct radeon *radeon;
226 unsigned ngroups;
227 struct r600_group groups[R600_GROUP_MAX];
228 unsigned pm4_ndwords;
229 unsigned pm4_cdwords;
230 unsigned pm4_dirty_cdwords;
231 unsigned ctx_pm4_ndwords;
232 unsigned nreloc;
233 unsigned creloc;
234 struct r600_reloc *reloc;
235 struct radeon_bo **bo;
236 u32 *pm4;
237 struct list_head query_list;
238 };
239
240 struct r600_draw {
241 u32 vgt_num_indices;
242 u32 vgt_num_instances;
243 u32 vgt_index_type;
244 u32 vgt_draw_initiator;
245 u32 indices_bo_offset;
246 struct radeon_ws_bo *indices;
247 };
248
249 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
250 void r600_context_fini(struct r600_context *ctx);
251 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
252 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
253 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
254 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
255 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
256 void r600_context_flush(struct r600_context *ctx);
257 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
258 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
259
260 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
261 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
262 boolean r600_context_query_result(struct r600_context *ctx,
263 struct r600_query *query,
264 boolean wait, void *vresult);
265 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
266 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
267
268 #endif