src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include <assert.h>
  30 #include <stdint.h>
  31 #include <stdio.h>
  32 #include <util/u_double_list.h>
  33 #include <pipe/p_compiler.h>
  34
  35 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  36
  37 #define R600_ERR(fmt, args...) \
  38         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  39
  40 typedef uint64_t                u64;
  41 typedef uint32_t                u32;
  42 typedef uint16_t                u16;
  43 typedef uint8_t                 u8;
  44
  45 struct radeon;
  46 struct winsys_handle;
  47
  48 enum radeon_family {
  49         CHIP_UNKNOWN,
  50         CHIP_R100,
  51         CHIP_RV100,
  52         CHIP_RS100,
  53         CHIP_RV200,
  54         CHIP_RS200,
  55         CHIP_R200,
  56         CHIP_RV250,
  57         CHIP_RS300,
  58         CHIP_RV280,
  59         CHIP_R300,
  60         CHIP_R350,
  61         CHIP_RV350,
  62         CHIP_RV380,
  63         CHIP_R420,
  64         CHIP_R423,
  65         CHIP_RV410,
  66         CHIP_RS400,
  67         CHIP_RS480,
  68         CHIP_RS600,
  69         CHIP_RS690,
  70         CHIP_RS740,
  71         CHIP_RV515,
  72         CHIP_R520,
  73         CHIP_RV530,
  74         CHIP_RV560,
  75         CHIP_RV570,
  76         CHIP_R580,
  77         CHIP_R600,
  78         CHIP_RV610,
  79         CHIP_RV630,
  80         CHIP_RV670,
  81         CHIP_RV620,
  82         CHIP_RV635,
  83         CHIP_RS780,
  84         CHIP_RS880,
  85         CHIP_RV770,
  86         CHIP_RV730,
  87         CHIP_RV710,
  88         CHIP_RV740,
  89         CHIP_CEDAR,
  90         CHIP_REDWOOD,
  91         CHIP_JUNIPER,
  92         CHIP_CYPRESS,
  93         CHIP_HEMLOCK,
  94         CHIP_PALM,
  95         CHIP_SUMO,
  96         CHIP_SUMO2,
  97         CHIP_BARTS,
  98         CHIP_TURKS,
  99         CHIP_CAICOS,
 100         CHIP_CAYMAN,
 101         CHIP_LAST,
 102 };
 103
 104 enum chip_class {
 105         R600,
 106         R700,
 107         EVERGREEN,
 108         CAYMAN,
 109 };
 110
 111 struct r600_tiling_info {
 112         unsigned num_channels;
 113         unsigned num_banks;
 114         unsigned group_bytes;
 115 };
 116
 117 enum radeon_family r600_get_family(struct radeon *rw);
 118 enum chip_class r600_get_family_class(struct radeon *radeon);
 119 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
 120 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
 121 unsigned r600_get_minor_version(struct radeon *radeon);
 122 unsigned r600_get_num_backends(struct radeon *radeon);
 123
 124 /* r600_bo.c */
 125 struct r600_bo;
 126 struct r600_bo *r600_bo(struct radeon *radeon,
 127                         unsigned size, unsigned alignment,
 128                         unsigned binding, unsigned usage);
 129 struct r600_bo *r600_bo_handle(struct radeon *radeon,
 130                                 unsigned handle, unsigned *array_mode);
 131 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 132 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 133 void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
 134                             struct r600_bo *src);
 135 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
 136                                 unsigned stride, struct winsys_handle *whandle);
 137 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
 138 {
 139         return 0;
 140 }
 141
 142
 143 /* R600/R700 STATES */
 144 #define R600_GROUP_MAX                  16
 145 #define R600_BLOCK_MAX_BO               32
 146 #define R600_BLOCK_MAX_REG              128
 147
 148 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
 149 /* there is a block entry for each register so 512 blocks */
 150 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
 151 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
 152 #define RANGE_OFFSET_START 0x8000
 153 #define HASH_SHIFT 9
 154 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
 155
 156 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
 157 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 158
 159 struct r600_pipe_reg {
 160         u32                             value;
 161         u32                             mask;
 162         struct r600_block               *block;
 163         struct r600_bo                  *bo;
 164         u32                             id;
 165 };
 166
 167 struct r600_pipe_state {
 168         unsigned                        id;
 169         unsigned                        nregs;
 170         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 171 };
 172
 173 struct r600_pipe_resource_state {
 174         unsigned                        id;
 175         u32                             val[8];
 176         struct r600_bo *bo[2];
 177 };
 178
 179 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 180 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 181
 182 struct r600_block_reloc {
 183         struct r600_bo          *bo;
 184         unsigned                flush_flags;
 185         unsigned                flush_mask;
 186         unsigned                bo_pm4_index;
 187 };
 188
 189 struct r600_block {
 190         struct list_head        list;
 191         unsigned                status;
 192         unsigned                flags;
 193         unsigned                start_offset;
 194         unsigned                pm4_ndwords;
 195         unsigned                pm4_flush_ndwords;
 196         unsigned                nbo;
 197         u16                     nreg;
 198         u16                     nreg_dirty;
 199         u32                     *reg;
 200         u32                     pm4[R600_BLOCK_MAX_REG];
 201         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 202         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 203 };
 204
 205 struct r600_range {
 206         struct r600_block       **blocks;
 207 };
 208
 209 /*
 210  * relocation
 211  */
 212 #pragma pack(1)
 213 struct r600_reloc {
 214         uint32_t        handle;
 215         uint32_t        read_domain;
 216         uint32_t        write_domain;
 217         uint32_t        flags;
 218 };
 219 #pragma pack()
 220
 221 /*
 222  * query
 223  */
 224 struct r600_query {
 225         u64                                     result;
 226         /* The kind of query. Currently only OQ is supported. */
 227         unsigned                                type;
 228         /* How many results have been written, in dwords. It's incremented
 229          * after end_query and flush. */
 230         unsigned                                num_results;
 231         /* if we've flushed the query */
 232         unsigned                                state;
 233         /* The buffer where query results are stored. */
 234         struct r600_bo                  *buffer;
 235         unsigned                                buffer_size;
 236         /* linked list of queries */
 237         struct list_head                        list;
 238 };
 239
 240 #define R600_QUERY_STATE_STARTED        (1 << 0)
 241 #define R600_QUERY_STATE_ENDED          (1 << 1)
 242 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 243
 244 #define R600_CONTEXT_DRAW_PENDING       (1 << 0)
 245 #define R600_CONTEXT_DST_CACHES_DIRTY   (1 << 1)
 246 #define R600_CONTEXT_CHECK_EVENT_FLUSH  (1 << 2)
 247
 248 struct r600_context {
 249         struct radeon           *radeon;
 250         struct r600_range       *range;
 251         unsigned                nblocks;
 252         struct r600_block       **blocks;
 253         struct list_head        dirty;
 254         unsigned                pm4_ndwords;
 255         unsigned                pm4_cdwords;
 256         unsigned                pm4_dirty_cdwords;
 257         unsigned                ctx_pm4_ndwords;
 258         unsigned                nreloc;
 259         unsigned                creloc;
 260         struct r600_reloc       *reloc;
 261         struct radeon_bo        **bo;
 262         u32                     *pm4;
 263         struct list_head        query_list;
 264         unsigned                num_query_running;
 265         struct list_head        fenced_bo;
 266         unsigned                max_db; /* for OQ */
 267         unsigned                num_dest_buffers;
 268         unsigned                flags;
 269         boolean                 predicate_drawing;
 270         struct r600_range ps_resources;
 271         struct r600_range vs_resources;
 272         struct r600_range fs_resources;
 273         int num_ps_resources, num_vs_resources, num_fs_resources;
 274 };
 275
 276 struct r600_draw {
 277         u32                     vgt_num_indices;
 278         u32                     vgt_num_instances;
 279         u32                     vgt_index_type;
 280         u32                     vgt_draw_initiator;
 281         u32                     indices_bo_offset;
 282         struct r600_bo          *indices;
 283 };
 284
 285 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 286 void r600_context_fini(struct r600_context *ctx);
 287 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 288 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 289 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 290 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 291 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 292 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 293 void r600_context_flush(struct r600_context *ctx);
 294 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 295 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 296
 297 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 298 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 299 boolean r600_context_query_result(struct r600_context *ctx,
 300                                 struct r600_query *query,
 301                                 boolean wait, void *vresult);
 302 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 303 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 304 void r600_context_queries_suspend(struct r600_context *ctx);
 305 void r600_context_queries_resume(struct r600_context *ctx);
 306 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
 307                             int flag_wait);
 308 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
 309                              unsigned offset, unsigned value);
 310 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
 311 void r600_context_flush_dest_caches(struct r600_context *ctx);
 312
 313 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 314 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 315 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
 316 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 317 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 318 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
 319 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 320 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 321
 322 struct radeon *radeon_decref(struct radeon *radeon);
 323
 324 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 325                               struct r600_pipe_state *state,
 326                               u32 offset, u32 value, u32 mask,
 327                               u32 range_id, u32 block_id,
 328                               struct r600_bo *bo);
 329
 330 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 331                                      u32 offset, u32 value, u32 mask,
 332                                      struct r600_bo *bo);
 333 #define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
 334
 335 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
 336                                            u32 value)
 337 {
 338         state->regs[state->nregs].value = value;
 339         state->nregs++;
 340 }
 341
 342 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
 343                                            u32 value, struct r600_bo *bo)
 344 {
 345         state->regs[state->nregs].value = value;
 346         state->regs[state->nregs].bo = bo;
 347         state->nregs++;
 348 }
 349
 350 #endif