2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
30 #include "util/u_memory.h"
31 #include "pipe/p_shader_tokens.h"
33 #define NUM_OF_CYCLES 3
34 #define NUM_OF_COMPONENTS 4
36 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
41 switch (bc
->chip_class
) {
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT
:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
:
93 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
:
117 "Need instruction operand number for 0x%x.\n", alu
->inst
);
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT
:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY
:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW
:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0
:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT
:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
:
197 "Need instruction operand number for 0x%x.\n", alu
->inst
);
205 int r700_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
);
207 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
209 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
213 LIST_INITHEAD(&cf
->list
);
214 LIST_INITHEAD(&cf
->alu
);
215 LIST_INITHEAD(&cf
->vtx
);
216 LIST_INITHEAD(&cf
->tex
);
220 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
222 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
226 LIST_INITHEAD(&alu
->list
);
230 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
232 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
236 LIST_INITHEAD(&vtx
->list
);
240 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
242 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
246 LIST_INITHEAD(&tex
->list
);
250 void r600_bytecode_init(struct r600_bytecode
*bc
, enum chip_class chip_class
, enum radeon_family family
)
252 if ((chip_class
== R600
) && (family
!= CHIP_RV670
))
253 bc
->ar_handling
= AR_HANDLE_RV6XX
;
255 bc
->ar_handling
= AR_HANDLE_NORMAL
;
257 if ((chip_class
== R600
) && (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&&
258 family
!= CHIP_RS880
))
259 bc
->r6xx_nop_after_rel_dst
= 1;
261 bc
->r6xx_nop_after_rel_dst
= 0;
262 LIST_INITHEAD(&bc
->cf
);
263 bc
->chip_class
= chip_class
;
266 static int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
268 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
272 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
274 cf
->id
= bc
->cf_last
->id
+ 2;
275 if (bc
->cf_last
->eg_alu_extended
) {
276 /* take into account extended alu size */
284 bc
->force_add_cf
= 0;
289 int r600_bytecode_add_output(struct r600_bytecode
*bc
, const struct r600_bytecode_output
*output
)
293 if (output
->gpr
>= bc
->ngpr
)
294 bc
->ngpr
= output
->gpr
+ 1;
296 if (bc
->cf_last
&& (bc
->cf_last
->inst
== output
->inst
||
297 (bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
) &&
298 output
->inst
== BC_INST(bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
))) &&
299 output
->type
== bc
->cf_last
->output
.type
&&
300 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
301 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
302 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
303 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
304 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
305 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
307 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
308 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
310 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
311 bc
->cf_last
->output
.inst
= output
->inst
;
312 bc
->cf_last
->output
.gpr
= output
->gpr
;
313 bc
->cf_last
->output
.array_base
= output
->array_base
;
314 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
317 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
318 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
320 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
321 bc
->cf_last
->output
.inst
= output
->inst
;
322 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
327 r
= r600_bytecode_add_cf(bc
);
330 bc
->cf_last
->inst
= output
->inst
;
331 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
335 /* alu instructions that can ony exits once per group */
336 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
338 switch (bc
->chip_class
) {
341 return !alu
->is_op3
&& (
342 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
||
343 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
||
344 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
||
345 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
||
346 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT
||
347 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT
||
348 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT
||
349 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT
||
350 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT
||
351 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT
||
352 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT
||
353 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT
||
354 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
||
355 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
||
356 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
||
357 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
||
358 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV
||
359 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP
||
360 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR
||
361 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE
||
362 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH
||
363 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH
||
364 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH
||
365 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH
||
366 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
||
367 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT
||
368 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT
||
369 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
||
370 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT
||
371 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT
||
372 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT
||
373 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT
||
374 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT
||
375 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT
);
379 return !alu
->is_op3
&& (
380 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
||
381 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
||
382 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
||
383 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
||
384 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT
||
385 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT
||
386 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT
||
387 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT
||
388 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT
||
389 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT
||
390 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT
||
391 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT
||
392 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
||
393 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
||
394 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
||
395 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
||
396 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV
||
397 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP
||
398 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR
||
399 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE
||
400 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH
||
401 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH
||
402 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH
||
403 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH
||
404 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
||
405 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT
||
406 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT
||
407 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
||
408 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT
||
409 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT
||
410 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT
||
411 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT
||
412 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT
||
413 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT
);
417 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
419 switch (bc
->chip_class
) {
422 return !alu
->is_op3
&& (
423 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
||
424 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
||
425 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
||
426 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
);
430 return !alu
->is_op3
&& (
431 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
||
432 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
||
433 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
||
434 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
);
438 static int is_alu_cube_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
440 switch (bc
->chip_class
) {
443 return !alu
->is_op3
&&
444 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
;
448 return !alu
->is_op3
&&
449 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
;
453 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
455 switch (bc
->chip_class
) {
458 return !alu
->is_op3
&& (
459 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
||
460 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
||
461 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
||
462 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
);
466 return !alu
->is_op3
&& (
467 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
);
471 static int is_opcode_in_range(unsigned opcode
, unsigned min
, unsigned max
)
473 return min
<= opcode
&& opcode
<= max
;
476 /* ALU instructions that can only execute on the vector unit:
480 * op3 : [0x08 - 0x0B]
481 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
487 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
489 switch (bc
->chip_class
) {
493 return is_opcode_in_range(alu
->inst
,
494 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64
,
495 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2
);
497 return (alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64
) ||
498 is_opcode_in_range(alu
->inst
,
499 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
,
500 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
) ||
501 is_opcode_in_range(alu
->inst
,
502 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64
,
503 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64
) ||
504 is_opcode_in_range(alu
->inst
,
505 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
,
506 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
) ||
507 is_opcode_in_range(alu
->inst
,
508 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64
,
509 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64
);
513 return is_opcode_in_range(alu
->inst
,
514 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT
,
515 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP
);
517 return is_opcode_in_range(alu
->inst
,
518 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT
,
519 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20
);
527 /* ALU instructions that can only execute on the trans unit:
536 * op2: [0x60 - 0x6F], [0x73 - 0x79]
542 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
545 switch (bc
->chip_class
) {
548 return alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
550 return is_opcode_in_range(alu
->inst
,
551 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
,
552 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
555 return alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
557 return is_opcode_in_range(alu
->inst
,
558 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
,
559 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
) ||
560 is_opcode_in_range(alu
->inst
,
561 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
,
562 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
565 return alu
->inst
== EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
567 return is_opcode_in_range(alu
->inst
,
568 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
,
569 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
);
577 /* alu instructions that can execute on any unit */
578 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
580 return !is_alu_vec_unit_inst(bc
, alu
) &&
581 !is_alu_trans_unit_inst(bc
, alu
);
584 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
586 switch (bc
->chip_class
) {
589 return (!alu
->is_op3
&& alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
593 return (!alu
->is_op3
&& alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
597 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
598 struct r600_bytecode_alu
*assignment
[5])
600 struct r600_bytecode_alu
*alu
;
601 unsigned i
, chan
, trans
;
602 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
604 for (i
= 0; i
< max_slots
; i
++)
605 assignment
[i
] = NULL
;
607 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
608 chan
= alu
->dst
.chan
;
611 else if (is_alu_trans_unit_inst(bc
, alu
))
613 else if (is_alu_vec_unit_inst(bc
, alu
))
615 else if (assignment
[chan
])
616 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
622 assert(0); /* ALU.Trans has already been allocated. */
627 if (assignment
[chan
]) {
628 assert(0); /* ALU.chan has already been allocated. */
631 assignment
[chan
] = alu
;
640 struct alu_bank_swizzle
{
641 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
642 int hw_cfile_addr
[4];
643 int hw_cfile_elem
[4];
646 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
647 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
648 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
649 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
650 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
651 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
652 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
655 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
656 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
657 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
658 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
659 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
662 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
664 int i
, cycle
, component
;
666 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
667 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
668 bs
->hw_gpr
[cycle
][component
] = -1;
669 for (i
= 0; i
< 4; i
++)
670 bs
->hw_cfile_addr
[i
] = -1;
671 for (i
= 0; i
< 4; i
++)
672 bs
->hw_cfile_elem
[i
] = -1;
675 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
677 if (bs
->hw_gpr
[cycle
][chan
] == -1)
678 bs
->hw_gpr
[cycle
][chan
] = sel
;
679 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
680 /* Another scalar operation has already used the GPR read port for the channel. */
686 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
688 int res
, num_res
= 4;
689 if (bc
->chip_class
>= R700
) {
693 for (res
= 0; res
< num_res
; ++res
) {
694 if (bs
->hw_cfile_addr
[res
] == -1) {
695 bs
->hw_cfile_addr
[res
] = sel
;
696 bs
->hw_cfile_elem
[res
] = chan
;
698 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
699 bs
->hw_cfile_elem
[res
] == chan
)
700 return 0; /* Read for this scalar element already reserved, nothing to do here. */
702 /* All cfile read ports are used, cannot reference vector element. */
706 static int is_gpr(unsigned sel
)
708 return (sel
>= 0 && sel
<= 127);
711 /* CB constants start at 512, and get translated to a kcache index when ALU
712 * clauses are constructed. Note that we handle kcache constants the same way
713 * as (the now gone) cfile constants, is that really required? */
714 static int is_cfile(unsigned sel
)
716 return (sel
> 255 && sel
< 512) ||
717 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
718 (sel
> 127 && sel
< 192); /* Kcache after translation. */
721 static int is_const(int sel
)
723 return is_cfile(sel
) ||
724 (sel
>= V_SQ_ALU_SRC_0
&&
725 sel
<= V_SQ_ALU_SRC_LITERAL
);
728 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
729 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
731 int r
, src
, num_src
, sel
, elem
, cycle
;
733 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
734 for (src
= 0; src
< num_src
; src
++) {
735 sel
= alu
->src
[src
].sel
;
736 elem
= alu
->src
[src
].chan
;
738 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
739 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
740 /* Nothing to do; special-case optimization,
741 * second source uses first source’s reservation. */
744 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
748 } else if (is_cfile(sel
)) {
749 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
753 /* No restrictions on PV, PS, literal or special constants. */
758 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
759 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
761 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
763 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
764 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
765 sel
= alu
->src
[src
].sel
;
766 elem
= alu
->src
[src
].chan
;
767 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
768 if (const_count
>= 2)
769 /* More than two references to a constant in
770 * transcendental operation. */
776 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
781 for (src
= 0; src
< num_src
; ++src
) {
782 sel
= alu
->src
[src
].sel
;
783 elem
= alu
->src
[src
].chan
;
785 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
786 if (cycle
< const_count
)
787 /* Cycle for GPR load conflicts with
788 * constant load in transcendental operation. */
790 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
794 /* PV PS restrictions */
795 if (const_count
&& (sel
== 254 || sel
== 255)) {
796 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
797 if (cycle
< const_count
)
804 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
805 struct r600_bytecode_alu
*slots
[5])
807 struct alu_bank_swizzle bs
;
809 int i
, r
= 0, forced
= 1;
810 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
811 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
813 for (i
= 0; i
< max_slots
; i
++) {
815 if (slots
[i
]->bank_swizzle_force
) {
816 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
822 if (i
< 4 && slots
[i
])
828 /* Just check every possible combination of bank swizzle.
829 * Not very efficent, but works on the first try in most of the cases. */
830 for (i
= 0; i
< 4; i
++)
831 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
832 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
834 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
836 bank_swizzle
[4] = SQ_ALU_SCL_210
;
837 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
839 if (max_slots
== 4) {
840 for (i
= 0; i
< max_slots
; i
++) {
841 if (bank_swizzle
[i
] == SQ_ALU_VEC_210
)
845 init_bank_swizzle(&bs
);
846 if (scalar_only
== false) {
847 for (i
= 0; i
< 4; i
++) {
849 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
857 if (!r
&& slots
[4] && max_slots
== 5) {
858 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
861 for (i
= 0; i
< max_slots
; i
++) {
863 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
871 for (i
= 0; i
< max_slots
; i
++) {
872 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
874 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
877 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
883 /* Couldn't find a working swizzle. */
887 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
888 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
890 struct r600_bytecode_alu
*prev
[5];
892 int i
, j
, r
, src
, num_src
;
893 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
895 r
= assign_alu_units(bc
, alu_prev
, prev
);
899 for (i
= 0; i
< max_slots
; ++i
) {
900 if (prev
[i
] && (prev
[i
]->dst
.write
|| prev
[i
]->is_op3
) && !prev
[i
]->dst
.rel
) {
901 gpr
[i
] = prev
[i
]->dst
.sel
;
902 /* cube writes more than PV.X */
903 if (!is_alu_cube_inst(bc
, prev
[i
]) && is_alu_reduction_inst(bc
, prev
[i
]))
906 chan
[i
] = prev
[i
]->dst
.chan
;
911 for (i
= 0; i
< max_slots
; ++i
) {
912 struct r600_bytecode_alu
*alu
= slots
[i
];
916 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
917 for (src
= 0; src
< num_src
; ++src
) {
918 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
921 if (bc
->chip_class
< CAYMAN
) {
922 if (alu
->src
[src
].sel
== gpr
[4] &&
923 alu
->src
[src
].chan
== chan
[4]) {
924 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
925 alu
->src
[src
].chan
= 0;
930 for (j
= 0; j
< 4; ++j
) {
931 if (alu
->src
[src
].sel
== gpr
[j
] &&
932 alu
->src
[src
].chan
== j
) {
933 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
934 alu
->src
[src
].chan
= chan
[j
];
944 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
)
948 *sel
= V_SQ_ALU_SRC_0
;
951 *sel
= V_SQ_ALU_SRC_1_INT
;
954 *sel
= V_SQ_ALU_SRC_M_1_INT
;
956 case 0x3F800000: /* 1.0f */
957 *sel
= V_SQ_ALU_SRC_1
;
959 case 0x3F000000: /* 0.5f */
960 *sel
= V_SQ_ALU_SRC_0_5
;
962 case 0xBF800000: /* -1.0f */
963 *sel
= V_SQ_ALU_SRC_1
;
966 case 0xBF000000: /* -0.5f */
967 *sel
= V_SQ_ALU_SRC_0_5
;
971 *sel
= V_SQ_ALU_SRC_LITERAL
;
976 /* compute how many literal are needed */
977 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
978 uint32_t literal
[4], unsigned *nliteral
)
980 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
983 for (i
= 0; i
< num_src
; ++i
) {
984 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
985 uint32_t value
= alu
->src
[i
].value
;
987 for (j
= 0; j
< *nliteral
; ++j
) {
988 if (literal
[j
] == value
) {
996 literal
[(*nliteral
)++] = value
;
1003 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
1004 struct r600_bytecode_alu
*alu
,
1005 uint32_t literal
[4], unsigned nliteral
)
1007 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
1010 for (i
= 0; i
< num_src
; ++i
) {
1011 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1012 uint32_t value
= alu
->src
[i
].value
;
1013 for (j
= 0; j
< nliteral
; ++j
) {
1014 if (literal
[j
] == value
) {
1015 alu
->src
[i
].chan
= j
;
1023 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
1024 struct r600_bytecode_alu
*alu_prev
)
1026 struct r600_bytecode_alu
*prev
[5];
1027 struct r600_bytecode_alu
*result
[5] = { NULL
};
1029 uint32_t literal
[4], prev_literal
[4];
1030 unsigned nliteral
= 0, prev_nliteral
= 0;
1032 int i
, j
, r
, src
, num_src
;
1033 int num_once_inst
= 0;
1034 int have_mova
= 0, have_rel
= 0;
1035 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1037 r
= assign_alu_units(bc
, alu_prev
, prev
);
1041 for (i
= 0; i
< max_slots
; ++i
) {
1042 struct r600_bytecode_alu
*alu
;
1044 /* check number of literals */
1046 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
1048 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
1050 if (is_alu_mova_inst(bc
, prev
[i
])) {
1055 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
1057 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
1060 /* Let's check used slots. */
1061 if (prev
[i
] && !slots
[i
]) {
1062 result
[i
] = prev
[i
];
1064 } else if (prev
[i
] && slots
[i
]) {
1065 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
1066 /* Trans unit is still free try to use it. */
1067 if (is_alu_any_unit_inst(bc
, slots
[i
])) {
1068 result
[i
] = prev
[i
];
1069 result
[4] = slots
[i
];
1070 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
1071 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
1072 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
1073 (prev
[i
]->dst
.write
== 1 || prev
[i
]->is_op3
))
1076 result
[i
] = slots
[i
];
1077 result
[4] = prev
[i
];
1082 } else if(!slots
[i
]) {
1085 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
1086 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
1087 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
1088 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
1089 (prev
[4]->dst
.write
== 1 || prev
[4]->is_op3
))
1092 result
[i
] = slots
[i
];
1096 num_once_inst
+= is_alu_once_inst(bc
, alu
);
1098 /* don't reschedule NOPs */
1099 if (is_nop_inst(bc
, alu
))
1102 /* Let's check dst gpr. */
1109 /* Let's check source gprs */
1110 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
1111 for (src
= 0; src
< num_src
; ++src
) {
1112 if (alu
->src
[src
].rel
) {
1118 /* Constants don't matter. */
1119 if (!is_gpr(alu
->src
[src
].sel
))
1122 for (j
= 0; j
< max_slots
; ++j
) {
1123 if (!prev
[j
] || !(prev
[j
]->dst
.write
|| prev
[j
]->is_op3
))
1126 /* If it's relative then we can't determin which gpr is really used. */
1127 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
1128 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
1129 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
1135 /* more than one PRED_ or KILL_ ? */
1136 if (num_once_inst
> 1)
1139 /* check if the result can still be swizzlet */
1140 r
= check_and_set_bank_swizzle(bc
, result
);
1144 /* looks like everything worked out right, apply the changes */
1146 /* undo adding previus literals */
1147 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
1149 /* sort instructions */
1150 for (i
= 0; i
< max_slots
; ++i
) {
1151 slots
[i
] = result
[i
];
1153 LIST_DEL(&result
[i
]->list
);
1154 result
[i
]->last
= 0;
1155 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
1159 /* determine new last instruction */
1160 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
1162 /* determine new first instruction */
1163 for (i
= 0; i
< max_slots
; ++i
) {
1165 bc
->cf_last
->curr_bs_head
= result
[i
];
1170 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
1171 bc
->cf_last
->prev2_bs_head
= NULL
;
1176 /* we'll keep kcache sets sorted by bank & addr */
1177 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
1178 struct r600_bytecode_kcache
*kcache
,
1179 unsigned bank
, unsigned line
)
1181 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
1183 for (i
= 0; i
< kcache_banks
; i
++) {
1184 if (kcache
[i
].mode
) {
1187 if (kcache
[i
].bank
< bank
)
1190 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
1191 kcache
[i
].bank
> bank
) {
1192 /* try to insert new line */
1193 if (kcache
[kcache_banks
-1].mode
) {
1194 /* all sets are in use */
1198 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
1199 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
1200 kcache
[i
].bank
= bank
;
1201 kcache
[i
].addr
= line
;
1205 d
= line
- kcache
[i
].addr
;
1209 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
1210 /* we are prepending the line to the current set,
1211 * discarding the existing second line,
1212 * so we'll have to insert line+2 after it */
1215 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
1216 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
1219 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1222 } else if (d
== 1) {
1223 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
1227 } else { /* free kcache set - use it */
1228 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
1229 kcache
[i
].bank
= bank
;
1230 kcache
[i
].addr
= line
;
1237 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
1238 struct r600_bytecode_kcache
*kcache
,
1239 struct r600_bytecode_alu
*alu
)
1243 for (i
= 0; i
< 3; i
++) {
1244 unsigned bank
, line
, sel
= alu
->src
[i
].sel
;
1249 bank
= alu
->src
[i
].kc_bank
;
1250 line
= (sel
-512)>>4;
1252 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
)))
1258 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
1259 struct r600_bytecode_alu
*alu
,
1260 struct r600_bytecode_kcache
* kcache
)
1264 /* Alter the src operands to refer to the kcache. */
1265 for (i
= 0; i
< 3; ++i
) {
1266 static const unsigned int base
[] = {128, 160, 256, 288};
1267 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
1275 for (j
= 0; j
< 4 && !found
; ++j
) {
1276 switch (kcache
[j
].mode
) {
1277 case V_SQ_CF_KCACHE_NOP
:
1278 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
1279 R600_ERR("unexpected kcache line mode\n");
1282 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
1283 kcache
[j
].addr
<= line
&&
1284 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1285 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1286 alu
->src
[i
].sel
+= base
[j
];
1295 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, int type
)
1297 struct r600_bytecode_kcache kcache_sets
[4];
1298 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1301 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1303 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1304 /* can't alloc, need to start new clause */
1305 if ((r
= r600_bytecode_add_cf(bc
))) {
1308 bc
->cf_last
->inst
= type
;
1310 /* retry with the new clause */
1311 kcache
= bc
->cf_last
->kcache
;
1312 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1313 /* can't alloc again- should never happen */
1317 /* update kcache sets */
1318 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1321 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1322 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
) {
1323 if (bc
->chip_class
< EVERGREEN
)
1325 bc
->cf_last
->eg_alu_extended
= 1;
1331 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1333 struct r600_bytecode_alu alu
;
1336 for (i
= 0; i
< 4; i
++) {
1337 memset(&alu
, 0, sizeof(alu
));
1338 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
1339 alu
.src
[0].chan
= i
;
1341 alu
.last
= (i
== 3);
1342 r
= r600_bytecode_add_alu(bc
, &alu
);
1349 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1350 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1352 struct r600_bytecode_alu alu
;
1358 /* hack to avoid making MOVA the last instruction in the clause */
1359 if ((bc
->cf_last
->ndw
>>1) >= 110)
1360 bc
->force_add_cf
= 1;
1362 memset(&alu
, 0, sizeof(alu
));
1363 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
;
1364 alu
.src
[0].sel
= bc
->ar_reg
;
1366 alu
.index_mode
= INDEX_MODE_LOOP
;
1367 r
= r600_bytecode_add_alu(bc
, &alu
);
1371 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1376 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1377 static int load_ar(struct r600_bytecode
*bc
)
1379 struct r600_bytecode_alu alu
;
1382 if (bc
->ar_handling
)
1383 return load_ar_r6xx(bc
);
1388 /* hack to avoid making MOVA the last instruction in the clause */
1389 if ((bc
->cf_last
->ndw
>>1) >= 110)
1390 bc
->force_add_cf
= 1;
1392 memset(&alu
, 0, sizeof(alu
));
1393 alu
.inst
= BC_INST(bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
);
1394 alu
.src
[0].sel
= bc
->ar_reg
;
1396 r
= r600_bytecode_add_alu(bc
, &alu
);
1400 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1405 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
, int type
)
1407 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1408 struct r600_bytecode_alu
*lalu
;
1413 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1415 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->inst
!= type
) {
1416 /* check if we could add it anyway */
1417 if (bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
) &&
1418 type
== BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
)) {
1419 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1420 if (lalu
->predicate
) {
1421 bc
->force_add_cf
= 1;
1426 bc
->force_add_cf
= 1;
1429 /* cf can contains only alu or only vtx or only tex */
1430 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1431 r
= r600_bytecode_add_cf(bc
);
1437 bc
->cf_last
->inst
= type
;
1439 /* Check AR usage and load it if required */
1440 for (i
= 0; i
< 3; i
++)
1441 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1444 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1447 /* Setup the kcache for this ALU instruction. This will start a new
1448 * ALU clause if needed. */
1449 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1454 if (!bc
->cf_last
->curr_bs_head
) {
1455 bc
->cf_last
->curr_bs_head
= nalu
;
1457 /* number of gpr == the last gpr used in any alu */
1458 for (i
= 0; i
< 3; i
++) {
1459 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1460 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1462 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1463 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1464 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
);
1466 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1467 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1469 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1470 /* each alu use 2 dwords */
1471 bc
->cf_last
->ndw
+= 2;
1474 /* process cur ALU instructions for bank swizzle */
1476 uint32_t literal
[4];
1478 struct r600_bytecode_alu
*slots
[5];
1479 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1480 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1484 if (bc
->cf_last
->prev_bs_head
) {
1485 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1490 if (bc
->cf_last
->prev_bs_head
) {
1491 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1496 r
= check_and_set_bank_swizzle(bc
, slots
);
1500 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1502 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1507 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1509 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1511 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1512 bc
->force_add_cf
= 1;
1515 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1516 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1517 bc
->cf_last
->curr_bs_head
= NULL
;
1520 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1521 insert_nop_r6xx(bc
);
1526 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1528 return r600_bytecode_add_alu_type(bc
, alu
, BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
1531 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1533 switch (bc
->chip_class
) {
1543 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1548 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1550 switch (bc
->chip_class
) {
1553 return bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX
&&
1554 bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
;
1556 return bc
->cf_last
->inst
!= EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1558 return bc
->cf_last
->inst
!= CM_V_SQ_CF_WORD1_SQ_CF_INST_TC
;
1560 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1565 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1567 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1572 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1574 /* cf can contains only alu or only vtx or only tex */
1575 if (bc
->cf_last
== NULL
||
1576 last_inst_was_not_vtx_fetch(bc
) ||
1578 r
= r600_bytecode_add_cf(bc
);
1583 switch (bc
->chip_class
) {
1586 bc
->cf_last
->inst
= V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1589 bc
->cf_last
->inst
= EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1592 bc
->cf_last
->inst
= CM_V_SQ_CF_WORD1_SQ_CF_INST_TC
;
1595 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1599 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1600 /* each fetch use 4 dwords */
1601 bc
->cf_last
->ndw
+= 4;
1603 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1604 bc
->force_add_cf
= 1;
1608 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1610 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1615 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1617 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1618 if (bc
->cf_last
!= NULL
&&
1619 bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
)) {
1620 struct r600_bytecode_tex
*ttex
;
1621 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1622 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1623 bc
->force_add_cf
= 1;
1627 /* slight hack to make gradients always go into same cf */
1628 if (ntex
->inst
== SQ_TEX_INST_SET_GRADIENTS_H
)
1629 bc
->force_add_cf
= 1;
1632 /* cf can contains only alu or only vtx or only tex */
1633 if (bc
->cf_last
== NULL
||
1634 bc
->cf_last
->inst
!= BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
) ||
1636 r
= r600_bytecode_add_cf(bc
);
1641 bc
->cf_last
->inst
= BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
);
1643 if (ntex
->src_gpr
>= bc
->ngpr
) {
1644 bc
->ngpr
= ntex
->src_gpr
+ 1;
1646 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1647 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1649 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1650 /* each texture fetch use 4 dwords */
1651 bc
->cf_last
->ndw
+= 4;
1653 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1654 bc
->force_add_cf
= 1;
1658 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, int inst
)
1661 r
= r600_bytecode_add_cf(bc
);
1665 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1666 bc
->cf_last
->inst
= inst
;
1670 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1672 return r600_bytecode_add_cfinst(bc
, CM_V_SQ_CF_WORD1_SQ_CF_INST_END
);
1675 /* common to all 3 families */
1676 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1678 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1679 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1680 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1681 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1682 if (bc
->chip_class
< CAYMAN
)
1683 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1685 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1686 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1687 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1688 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1689 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1690 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1691 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1692 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1693 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1694 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1695 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1696 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1697 if (bc
->chip_class
< CAYMAN
)
1698 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1700 bc
->bytecode
[id
++] = 0;
1704 /* common to all 3 families */
1705 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1707 bc
->bytecode
[id
++] = S_SQ_TEX_WORD0_TEX_INST(tex
->inst
) |
1708 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1709 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1710 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1711 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1712 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1713 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1714 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1715 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1716 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1717 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1718 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1719 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1720 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1721 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1722 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1723 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1724 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1725 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1726 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1727 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1728 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1729 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1730 bc
->bytecode
[id
++] = 0;
1734 /* r600 only, r700/eg bits in r700_asm.c */
1735 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1737 /* don't replace gpr by pv or ps for destination register */
1738 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1739 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1740 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1741 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1742 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1743 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1744 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1745 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1746 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1747 S_SQ_ALU_WORD0_LAST(alu
->last
);
1750 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1751 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1752 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1753 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1754 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1755 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1756 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1757 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1758 S_SQ_ALU_WORD1_OP3_ALU_INST(alu
->inst
) |
1759 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1761 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1762 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1763 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1764 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1765 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1766 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1767 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1768 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1769 S_SQ_ALU_WORD1_OP2_ALU_INST(alu
->inst
) |
1770 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1771 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->predicate
) |
1772 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->predicate
);
1777 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1779 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1780 *bytecode
++ = cf
->inst
|
1781 S_SQ_CF_WORD1_BARRIER(1) |
1782 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1785 /* common for r600/r700 - eg in eg_asm.c */
1786 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1788 unsigned id
= cf
->id
;
1791 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1792 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1793 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1794 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1795 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1796 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1797 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1798 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1800 bc
->bytecode
[id
++] = cf
->inst
|
1801 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1802 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1803 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1804 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1805 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1806 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1808 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1809 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1810 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1811 if (bc
->chip_class
== R700
)
1812 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1814 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1816 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1817 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1818 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1819 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1820 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1821 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1822 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1823 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1824 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1825 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1826 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1827 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1829 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
);
1831 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
1832 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
1833 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
1834 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
1835 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1836 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1837 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1838 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1839 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1840 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1842 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
) |
1843 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1844 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1846 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1847 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1848 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1849 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1850 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1851 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1852 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1853 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1854 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1855 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1856 bc
->bytecode
[id
++] = cf
->inst
|
1857 S_SQ_CF_WORD1_BARRIER(1) |
1858 S_SQ_CF_WORD1_COND(cf
->cond
) |
1859 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
);
1863 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1869 int r600_bytecode_build(struct r600_bytecode
*bc
)
1871 struct r600_bytecode_cf
*cf
;
1872 struct r600_bytecode_alu
*alu
;
1873 struct r600_bytecode_vtx
*vtx
;
1874 struct r600_bytecode_tex
*tex
;
1875 uint32_t literal
[4];
1880 if (bc
->callstack
[0].max
> 0)
1881 bc
->nstack
= ((bc
->callstack
[0].max
+ 3) >> 2) + 2;
1882 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1886 /* first path compute addr of each CF block */
1887 /* addr start after all the CF instructions */
1888 addr
= bc
->cf_last
->id
+ 2;
1889 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1890 if (bc
->chip_class
>= EVERGREEN
) {
1892 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1893 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1894 /* fetch node need to be 16 bytes aligned*/
1896 addr
&= 0xFFFFFFFCUL
;
1898 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1899 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1900 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1901 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1902 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1903 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1904 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
1905 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
1906 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
1907 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
1908 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
1909 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
1910 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
1911 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
1912 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
1913 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
1914 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
1915 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
1916 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
1917 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
1918 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
1919 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
1920 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1921 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1922 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1923 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1924 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1925 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1926 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1927 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1928 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1929 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
1932 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1937 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1938 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1939 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1940 /* fetch node need to be 16 bytes aligned*/
1942 addr
&= 0xFFFFFFFCUL
;
1944 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1945 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1946 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1947 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1948 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1949 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1950 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
1951 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
1952 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
1953 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
1954 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1955 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1956 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1957 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1958 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1959 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1960 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1961 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1962 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1965 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1971 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1974 bc
->bytecode
= calloc(1, bc
->ndw
* 4);
1975 if (bc
->bytecode
== NULL
)
1977 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1979 if (bc
->chip_class
>= EVERGREEN
) {
1980 r
= eg_bytecode_cf_build(bc
, cf
);
1985 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1986 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1987 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1988 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1990 memset(literal
, 0, sizeof(literal
));
1991 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1992 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
1995 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
1996 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
1998 switch(bc
->chip_class
) {
1999 case EVERGREEN
: /* eg alu is same encoding as r700 */
2001 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
2004 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
2011 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
2012 bc
->bytecode
[addr
++] = literal
[i
];
2015 memset(literal
, 0, sizeof(literal
));
2019 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2020 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2021 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2027 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2028 if (bc
->chip_class
== CAYMAN
) {
2029 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2030 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2036 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2037 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
2043 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2044 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2045 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
2046 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
2047 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
2048 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
2049 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
2050 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
2051 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
2052 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
2053 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
2054 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
2055 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
2056 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
2057 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
2058 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
2059 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
2060 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
2061 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2062 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2063 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2064 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2065 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2066 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2067 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2068 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2069 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2070 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
2073 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2077 r
= r600_bytecode_cf_build(bc
, cf
);
2082 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2083 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2084 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2085 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2087 memset(literal
, 0, sizeof(literal
));
2088 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2089 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2092 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
2093 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
2095 switch(bc
->chip_class
) {
2097 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
2100 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
2103 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
2110 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
2111 bc
->bytecode
[addr
++] = literal
[i
];
2114 memset(literal
, 0, sizeof(literal
));
2118 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2119 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
2120 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2121 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2127 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2128 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2129 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
2135 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2136 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2137 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
2138 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
2139 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
2140 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
2141 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2142 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2143 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2144 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2145 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2146 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2147 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2148 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2149 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2152 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2160 void r600_bytecode_clear(struct r600_bytecode
*bc
)
2162 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
2165 bc
->bytecode
= NULL
;
2167 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
2168 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
2169 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
2170 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
2172 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
2176 LIST_INITHEAD(&cf
->alu
);
2178 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
2182 LIST_INITHEAD(&cf
->tex
);
2184 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
2188 LIST_INITHEAD(&cf
->vtx
);
2193 LIST_INITHEAD(&cf
->list
);
2196 void r600_bytecode_dump(struct r600_bytecode
*bc
)
2198 struct r600_bytecode_cf
*cf
= NULL
;
2199 struct r600_bytecode_alu
*alu
= NULL
;
2200 struct r600_bytecode_vtx
*vtx
= NULL
;
2201 struct r600_bytecode_tex
*tex
= NULL
;
2204 uint32_t literal
[4];
2208 switch (bc
->chip_class
) {
2223 fprintf(stderr
, "bytecode %d dw -- %d gprs ---------------------\n", bc
->ndw
, bc
->ngpr
);
2224 fprintf(stderr
, " %c\n", chip
);
2226 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2229 if (bc
->chip_class
>= EVERGREEN
) {
2231 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2232 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2233 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2234 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2235 if (cf
->eg_alu_extended
) {
2236 fprintf(stderr
, "%04d %08X ALU_EXT0 ", id
, bc
->bytecode
[id
]);
2237 fprintf(stderr
, "KCACHE_BANK2:%X ", cf
->kcache
[2].bank
);
2238 fprintf(stderr
, "KCACHE_BANK3:%X ", cf
->kcache
[3].bank
);
2239 fprintf(stderr
, "KCACHE_MODE2:%X\n", cf
->kcache
[2].mode
);
2241 fprintf(stderr
, "%04d %08X ALU_EXT1 ", id
, bc
->bytecode
[id
]);
2242 fprintf(stderr
, "KCACHE_MODE3:%X ", cf
->kcache
[3].mode
);
2243 fprintf(stderr
, "KCACHE_ADDR2:%X ", cf
->kcache
[2].addr
);
2244 fprintf(stderr
, "KCACHE_ADDR3:%X\n", cf
->kcache
[3].addr
);
2248 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2249 fprintf(stderr
, "ADDR:%d ", cf
->addr
);
2250 fprintf(stderr
, "KCACHE_MODE0:%X ", cf
->kcache
[0].mode
);
2251 fprintf(stderr
, "KCACHE_BANK0:%X ", cf
->kcache
[0].bank
);
2252 fprintf(stderr
, "KCACHE_BANK1:%X\n", cf
->kcache
[1].bank
);
2254 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2255 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
));
2256 fprintf(stderr
, "KCACHE_MODE1:%X ", cf
->kcache
[1].mode
);
2257 fprintf(stderr
, "KCACHE_ADDR0:%X ", cf
->kcache
[0].addr
);
2258 fprintf(stderr
, "KCACHE_ADDR1:%X ", cf
->kcache
[1].addr
);
2259 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 2);
2261 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2262 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2263 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2264 fprintf(stderr
, "ADDR:%d\n", cf
->addr
);
2266 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2267 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2268 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 4);
2270 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2271 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2272 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2273 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2274 fprintf(stderr
, "ELEM_SIZE:%X ", cf
->output
.elem_size
);
2275 fprintf(stderr
, "ARRAY_BASE:%X ", cf
->output
.array_base
);
2276 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2278 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2279 fprintf(stderr
, "SWIZ_X:%X ", cf
->output
.swizzle_x
);
2280 fprintf(stderr
, "SWIZ_Y:%X ", cf
->output
.swizzle_y
);
2281 fprintf(stderr
, "SWIZ_Z:%X ", cf
->output
.swizzle_z
);
2282 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
2283 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2284 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
));
2285 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2286 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2288 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
2289 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
2290 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
2291 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
2292 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
2293 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
2294 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
2295 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
2296 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
2297 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
2298 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
2299 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
2300 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
2301 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
2302 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
2303 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
2304 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id
, bc
->bytecode
[id
],
2305 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2306 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) / 4,
2307 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2308 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) % 4);
2309 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2310 fprintf(stderr
, "ELEM_SIZE:%i ", cf
->output
.elem_size
);
2311 fprintf(stderr
, "ARRAY_BASE:%i ", cf
->output
.array_base
);
2312 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2314 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id
, bc
->bytecode
[id
],
2315 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2316 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) / 4,
2317 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2318 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) % 4);
2319 fprintf(stderr
, "ARRAY_SIZE:%i ", cf
->output
.array_size
);
2320 fprintf(stderr
, "COMP_MASK:%X ", cf
->output
.comp_mask
);
2321 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2322 fprintf(stderr
, "INST:%d ", cf
->output
.inst
);
2323 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2324 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2326 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2327 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2328 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2329 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2330 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2331 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2332 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2333 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2334 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2335 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
2336 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2337 fprintf(stderr
, "ADDR:%d\n", cf
->cf_addr
);
2339 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2340 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2341 fprintf(stderr
, "COND:%X ", cf
->cond
);
2342 fprintf(stderr
, "POP_COUNT:%X\n", cf
->pop_count
);
2345 R600_ERR("Unknown instruction %0x\n", cf
->inst
);
2349 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2350 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2351 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2352 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2353 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2354 fprintf(stderr
, "ADDR:%d ", cf
->addr
);
2355 fprintf(stderr
, "KCACHE_MODE0:%X ", cf
->kcache
[0].mode
);
2356 fprintf(stderr
, "KCACHE_BANK0:%X ", cf
->kcache
[0].bank
);
2357 fprintf(stderr
, "KCACHE_BANK1:%X\n", cf
->kcache
[1].bank
);
2359 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2360 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
));
2361 fprintf(stderr
, "KCACHE_MODE1:%X ", cf
->kcache
[1].mode
);
2362 fprintf(stderr
, "KCACHE_ADDR0:%X ", cf
->kcache
[0].addr
);
2363 fprintf(stderr
, "KCACHE_ADDR1:%X ", cf
->kcache
[1].addr
);
2364 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 2);
2366 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2367 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2368 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
2369 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2370 fprintf(stderr
, "ADDR:%d\n", cf
->addr
);
2372 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2373 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2374 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 4);
2376 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2377 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2378 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2379 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2380 fprintf(stderr
, "ELEM_SIZE:%X ", cf
->output
.elem_size
);
2381 fprintf(stderr
, "ARRAY_BASE:%X ", cf
->output
.array_base
);
2382 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2384 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2385 fprintf(stderr
, "SWIZ_X:%X ", cf
->output
.swizzle_x
);
2386 fprintf(stderr
, "SWIZ_Y:%X ", cf
->output
.swizzle_y
);
2387 fprintf(stderr
, "SWIZ_Z:%X ", cf
->output
.swizzle_z
);
2388 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
2389 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2390 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
));
2391 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2392 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2394 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
2395 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
2396 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
2397 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
2398 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i ", id
, bc
->bytecode
[id
],
2399 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2400 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
));
2401 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2402 fprintf(stderr
, "ELEM_SIZE:%i ", cf
->output
.elem_size
);
2403 fprintf(stderr
, "ARRAY_BASE:%i ", cf
->output
.array_base
);
2404 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2406 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i ", id
, bc
->bytecode
[id
],
2407 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2408 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
));
2409 fprintf(stderr
, "ARRAY_SIZE:%i ", cf
->output
.array_size
);
2410 fprintf(stderr
, "COMP_MASK:%X ", cf
->output
.comp_mask
);
2411 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2412 fprintf(stderr
, "INST:%d ", cf
->output
.inst
);
2413 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2414 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2416 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2417 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2418 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2419 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2420 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2421 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2422 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2423 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2424 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2425 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2426 fprintf(stderr
, "ADDR:%d\n", cf
->cf_addr
);
2428 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2429 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2430 fprintf(stderr
, "COND:%X ", cf
->cond
);
2431 fprintf(stderr
, "POP_COUNT:%X\n", cf
->pop_count
);
2434 R600_ERR("Unknown instruction %0x\n", cf
->inst
);
2440 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2441 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2443 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2444 fprintf(stderr
, "SRC0(SEL:%d ", alu
->src
[0].sel
);
2445 fprintf(stderr
, "REL:%d ", alu
->src
[0].rel
);
2446 fprintf(stderr
, "CHAN:%d ", alu
->src
[0].chan
);
2447 fprintf(stderr
, "NEG:%d) ", alu
->src
[0].neg
);
2448 fprintf(stderr
, "SRC1(SEL:%d ", alu
->src
[1].sel
);
2449 fprintf(stderr
, "REL:%d ", alu
->src
[1].rel
);
2450 fprintf(stderr
, "CHAN:%d ", alu
->src
[1].chan
);
2451 fprintf(stderr
, "NEG:%d ", alu
->src
[1].neg
);
2452 fprintf(stderr
, "IM:%d) ", alu
->index_mode
);
2453 fprintf(stderr
, "LAST:%d)\n", alu
->last
);
2455 fprintf(stderr
, "%04d %08X %c ", id
, bc
->bytecode
[id
], alu
->last
? '*' : ' ');
2456 fprintf(stderr
, "INST:0x%x ", alu
->inst
);
2457 fprintf(stderr
, "DST(SEL:%d ", alu
->dst
.sel
);
2458 fprintf(stderr
, "CHAN:%d ", alu
->dst
.chan
);
2459 fprintf(stderr
, "REL:%d ", alu
->dst
.rel
);
2460 fprintf(stderr
, "CLAMP:%d) ", alu
->dst
.clamp
);
2461 fprintf(stderr
, "BANK_SWIZZLE:%d ", alu
->bank_swizzle
);
2463 fprintf(stderr
, "SRC2(SEL:%d ", alu
->src
[2].sel
);
2464 fprintf(stderr
, "REL:%d ", alu
->src
[2].rel
);
2465 fprintf(stderr
, "CHAN:%d ", alu
->src
[2].chan
);
2466 fprintf(stderr
, "NEG:%d)\n", alu
->src
[2].neg
);
2468 fprintf(stderr
, "SRC0_ABS:%d ", alu
->src
[0].abs
);
2469 fprintf(stderr
, "SRC1_ABS:%d ", alu
->src
[1].abs
);
2470 fprintf(stderr
, "WRITE_MASK:%d ", alu
->dst
.write
);
2471 fprintf(stderr
, "OMOD:%d ", alu
->omod
);
2472 fprintf(stderr
, "EXECUTE_MASK:%d ", alu
->predicate
);
2473 fprintf(stderr
, "UPDATE_PRED:%d\n", alu
->predicate
);
2478 for (i
= 0; i
< nliteral
; i
++, id
++) {
2479 float *f
= (float*)(bc
->bytecode
+ id
);
2480 fprintf(stderr
, "%04d %08X\t%f\n", id
, bc
->bytecode
[id
], *f
);
2487 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2488 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2489 fprintf(stderr
, "INST:0x%x ", tex
->inst
);
2490 fprintf(stderr
, "RESOURCE_ID:%d ", tex
->resource_id
);
2491 fprintf(stderr
, "SRC(GPR:%d ", tex
->src_gpr
);
2492 fprintf(stderr
, "REL:%d)\n", tex
->src_rel
);
2494 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2495 fprintf(stderr
, "DST(GPR:%d ", tex
->dst_gpr
);
2496 fprintf(stderr
, "REL:%d ", tex
->dst_rel
);
2497 fprintf(stderr
, "SEL_X:%d ", tex
->dst_sel_x
);
2498 fprintf(stderr
, "SEL_Y:%d ", tex
->dst_sel_y
);
2499 fprintf(stderr
, "SEL_Z:%d ", tex
->dst_sel_z
);
2500 fprintf(stderr
, "SEL_W:%d) ", tex
->dst_sel_w
);
2501 fprintf(stderr
, "LOD_BIAS:%d ", tex
->lod_bias
);
2502 fprintf(stderr
, "COORD_TYPE_X:%d ", tex
->coord_type_x
);
2503 fprintf(stderr
, "COORD_TYPE_Y:%d ", tex
->coord_type_y
);
2504 fprintf(stderr
, "COORD_TYPE_Z:%d ", tex
->coord_type_z
);
2505 fprintf(stderr
, "COORD_TYPE_W:%d\n", tex
->coord_type_w
);
2507 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2508 fprintf(stderr
, "OFFSET_X:%d ", tex
->offset_x
);
2509 fprintf(stderr
, "OFFSET_Y:%d ", tex
->offset_y
);
2510 fprintf(stderr
, "OFFSET_Z:%d ", tex
->offset_z
);
2511 fprintf(stderr
, "SAMPLER_ID:%d ", tex
->sampler_id
);
2512 fprintf(stderr
, "SRC(SEL_X:%d ", tex
->src_sel_x
);
2513 fprintf(stderr
, "SEL_Y:%d ", tex
->src_sel_y
);
2514 fprintf(stderr
, "SEL_Z:%d ", tex
->src_sel_z
);
2515 fprintf(stderr
, "SEL_W:%d)\n", tex
->src_sel_w
);
2517 fprintf(stderr
, "%04d %08X \n", id
, bc
->bytecode
[id
]);
2521 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2522 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2523 fprintf(stderr
, "INST:%d ", vtx
->inst
);
2524 fprintf(stderr
, "FETCH_TYPE:%d ", vtx
->fetch_type
);
2525 fprintf(stderr
, "BUFFER_ID:%d\n", vtx
->buffer_id
);
2527 /* This assumes that no semantic fetches exist */
2528 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2529 fprintf(stderr
, "SRC(GPR:%d ", vtx
->src_gpr
);
2530 fprintf(stderr
, "SEL_X:%d) ", vtx
->src_sel_x
);
2531 if (bc
->chip_class
< CAYMAN
)
2532 fprintf(stderr
, "MEGA_FETCH_COUNT:%d ", vtx
->mega_fetch_count
);
2534 fprintf(stderr
, "SEL_Y:%d) ", 0);
2535 fprintf(stderr
, "DST(GPR:%d ", vtx
->dst_gpr
);
2536 fprintf(stderr
, "SEL_X:%d ", vtx
->dst_sel_x
);
2537 fprintf(stderr
, "SEL_Y:%d ", vtx
->dst_sel_y
);
2538 fprintf(stderr
, "SEL_Z:%d ", vtx
->dst_sel_z
);
2539 fprintf(stderr
, "SEL_W:%d) ", vtx
->dst_sel_w
);
2540 fprintf(stderr
, "USE_CONST_FIELDS:%d ", vtx
->use_const_fields
);
2541 fprintf(stderr
, "FORMAT(DATA:%d ", vtx
->data_format
);
2542 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2543 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2544 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2546 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2547 fprintf(stderr
, "ENDIAN:%d ", vtx
->endian
);
2548 fprintf(stderr
, "OFFSET:%d\n", vtx
->offset
);
2551 fprintf(stderr
, "%04d %08X \n", id
, bc
->bytecode
[id
]);
2556 fprintf(stderr
, "--------------------------------------\n");
2559 static void r600_vertex_data_type(enum pipe_format pformat
,
2561 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2563 const struct util_format_description
*desc
;
2569 *endian
= ENDIAN_NONE
;
2571 desc
= util_format_description(pformat
);
2572 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2576 /* Find the first non-VOID channel. */
2577 for (i
= 0; i
< 4; i
++) {
2578 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2583 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2585 switch (desc
->channel
[i
].type
) {
2586 /* Half-floats, floats, ints */
2587 case UTIL_FORMAT_TYPE_FLOAT
:
2588 switch (desc
->channel
[i
].size
) {
2590 switch (desc
->nr_channels
) {
2592 *format
= FMT_16_FLOAT
;
2595 *format
= FMT_16_16_FLOAT
;
2599 *format
= FMT_16_16_16_16_FLOAT
;
2604 switch (desc
->nr_channels
) {
2606 *format
= FMT_32_FLOAT
;
2609 *format
= FMT_32_32_FLOAT
;
2612 *format
= FMT_32_32_32_FLOAT
;
2615 *format
= FMT_32_32_32_32_FLOAT
;
2624 case UTIL_FORMAT_TYPE_UNSIGNED
:
2626 case UTIL_FORMAT_TYPE_SIGNED
:
2627 switch (desc
->channel
[i
].size
) {
2629 switch (desc
->nr_channels
) {
2638 *format
= FMT_8_8_8_8
;
2643 if (desc
->nr_channels
!= 4)
2646 *format
= FMT_2_10_10_10
;
2649 switch (desc
->nr_channels
) {
2654 *format
= FMT_16_16
;
2658 *format
= FMT_16_16_16_16
;
2663 switch (desc
->nr_channels
) {
2668 *format
= FMT_32_32
;
2671 *format
= FMT_32_32_32
;
2674 *format
= FMT_32_32_32_32
;
2686 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2691 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2692 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2693 if (!desc
->channel
[i
].normalized
) {
2694 if (desc
->channel
[i
].pure_integer
)
2702 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2705 int r600_vertex_elements_build_fetch_shader(struct r600_context
*rctx
, struct r600_vertex_element
*ve
)
2707 static int dump_shaders
= -1;
2709 struct r600_bytecode bc
;
2710 struct r600_bytecode_vtx vtx
;
2711 struct pipe_vertex_element
*elements
= ve
->elements
;
2712 const struct util_format_description
*desc
;
2713 unsigned fetch_resource_start
= rctx
->chip_class
>= EVERGREEN
? 0 : 160;
2714 unsigned format
, num_format
, format_comp
, endian
;
2718 memset(&bc
, 0, sizeof(bc
));
2719 r600_bytecode_init(&bc
, rctx
->chip_class
, rctx
->family
);
2721 for (i
= 0; i
< ve
->count
; i
++) {
2722 if (elements
[i
].instance_divisor
> 1) {
2723 struct r600_bytecode_alu alu
;
2725 memset(&alu
, 0, sizeof(alu
));
2726 alu
.inst
= BC_INST(&bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2728 alu
.src
[0].chan
= 3;
2730 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2731 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2733 alu
.dst
.sel
= i
+ 1;
2738 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2739 r600_bytecode_clear(&bc
);
2745 for (i
= 0; i
< ve
->count
; i
++) {
2746 r600_vertex_data_type(ve
->elements
[i
].src_format
,
2747 &format
, &num_format
, &format_comp
, &endian
);
2749 desc
= util_format_description(ve
->elements
[i
].src_format
);
2751 r600_bytecode_clear(&bc
);
2752 R600_ERR("unknown format %d\n", ve
->elements
[i
].src_format
);
2756 if (elements
[i
].src_offset
> 65535) {
2757 r600_bytecode_clear(&bc
);
2758 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2762 memset(&vtx
, 0, sizeof(vtx
));
2763 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2764 vtx
.fetch_type
= elements
[i
].instance_divisor
? 1 : 0;
2765 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2766 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2767 vtx
.mega_fetch_count
= 0x1F;
2768 vtx
.dst_gpr
= i
+ 1;
2769 vtx
.dst_sel_x
= desc
->swizzle
[0];
2770 vtx
.dst_sel_y
= desc
->swizzle
[1];
2771 vtx
.dst_sel_z
= desc
->swizzle
[2];
2772 vtx
.dst_sel_w
= desc
->swizzle
[3];
2773 vtx
.data_format
= format
;
2774 vtx
.num_format_all
= num_format
;
2775 vtx
.format_comp_all
= format_comp
;
2776 vtx
.srf_mode_all
= 1;
2777 vtx
.offset
= elements
[i
].src_offset
;
2778 vtx
.endian
= endian
;
2780 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2781 r600_bytecode_clear(&bc
);
2786 r600_bytecode_add_cfinst(&bc
, BC_INST(&bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
));
2788 if ((r
= r600_bytecode_build(&bc
))) {
2789 r600_bytecode_clear(&bc
);
2793 if (dump_shaders
== -1)
2794 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
2797 fprintf(stderr
, "--------------------------------------------------------------\n");
2798 r600_bytecode_dump(&bc
);
2799 fprintf(stderr
, "______________________________________________________________\n");
2802 ve
->fs_size
= bc
.ndw
*4;
2804 ve
->fetch_shader
= (struct r600_resource
*)
2805 pipe_buffer_create(rctx
->context
.screen
,
2807 PIPE_USAGE_IMMUTABLE
, ve
->fs_size
);
2808 if (ve
->fetch_shader
== NULL
) {
2809 r600_bytecode_clear(&bc
);
2813 bytecode
= rctx
->ws
->buffer_map(ve
->fetch_shader
->buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
2814 if (bytecode
== NULL
) {
2815 r600_bytecode_clear(&bc
);
2816 pipe_resource_reference((struct pipe_resource
**)&ve
->fetch_shader
, NULL
);
2820 if (R600_BIG_ENDIAN
) {
2821 for (i
= 0; i
< ve
->fs_size
/ 4; ++i
) {
2822 bytecode
[i
] = bswap_32(bc
.bytecode
[i
]);
2825 memcpy(bytecode
, bc
.bytecode
, ve
->fs_size
);
2828 rctx
->ws
->buffer_unmap(ve
->fetch_shader
->buf
);
2829 r600_bytecode_clear(&bc
);
2831 if (rctx
->chip_class
>= EVERGREEN
)
2832 evergreen_fetch_shader(&rctx
->context
, ve
);
2834 r600_fetch_shader(&rctx
->context
, ve
);