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1a501f62cbaca656511aa5b739f96108e4339ce5
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include <byteswap.h>
31 #include "util/u_memory.h"
32 #include "pipe/p_shader_tokens.h"
33
34 #define NUM_OF_CYCLES 3
35 #define NUM_OF_COMPONENTS 4
36
37 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
38 {
39 if(alu->is_op3)
40 return 3;
41
42 switch (bc->chip_class) {
43 default:
44 case R600:
45 case R700:
46 switch (alu->inst) {
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
48 return 0;
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
93 return 2;
94
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
118 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
119 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
120 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
121 return 1;
122 default: R600_ERR(
123 "Need instruction operand number for 0x%x.\n", alu->inst);
124 }
125 break;
126 case EVERGREEN:
127 case CAYMAN:
128 switch (alu->inst) {
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
130 return 0;
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
177 return 2;
178
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
198 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
199 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
200 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
201 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
202 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
203 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
204 return 1;
205 default:
206 R600_ERR("Need instruction operand number for 0x%x.\n", alu->inst);
207 }
208 break;
209 }
210
211 return 3;
212 }
213
214 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
215
216 static struct r600_bytecode_cf *r600_bytecode_cf(void)
217 {
218 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
219
220 if (cf == NULL)
221 return NULL;
222 LIST_INITHEAD(&cf->list);
223 LIST_INITHEAD(&cf->alu);
224 LIST_INITHEAD(&cf->vtx);
225 LIST_INITHEAD(&cf->tex);
226 return cf;
227 }
228
229 static struct r600_bytecode_alu *r600_bytecode_alu(void)
230 {
231 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
232
233 if (alu == NULL)
234 return NULL;
235 LIST_INITHEAD(&alu->list);
236 return alu;
237 }
238
239 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
240 {
241 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
242
243 if (vtx == NULL)
244 return NULL;
245 LIST_INITHEAD(&vtx->list);
246 return vtx;
247 }
248
249 static struct r600_bytecode_tex *r600_bytecode_tex(void)
250 {
251 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
252
253 if (tex == NULL)
254 return NULL;
255 LIST_INITHEAD(&tex->list);
256 return tex;
257 }
258
259 void r600_bytecode_init(struct r600_bytecode *bc,
260 enum chip_class chip_class,
261 enum radeon_family family,
262 enum r600_msaa_texture_mode msaa_texture_mode)
263 {
264 if ((chip_class == R600) &&
265 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
266 bc->ar_handling = AR_HANDLE_RV6XX;
267 bc->r6xx_nop_after_rel_dst = 1;
268 } else {
269 bc->ar_handling = AR_HANDLE_NORMAL;
270 bc->r6xx_nop_after_rel_dst = 0;
271 }
272
273 LIST_INITHEAD(&bc->cf);
274 bc->chip_class = chip_class;
275 bc->msaa_texture_mode = msaa_texture_mode;
276 }
277
278 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
279 {
280 struct r600_bytecode_cf *cf = r600_bytecode_cf();
281
282 if (cf == NULL)
283 return -ENOMEM;
284 LIST_ADDTAIL(&cf->list, &bc->cf);
285 if (bc->cf_last) {
286 cf->id = bc->cf_last->id + 2;
287 if (bc->cf_last->eg_alu_extended) {
288 /* take into account extended alu size */
289 cf->id += 2;
290 bc->ndw += 2;
291 }
292 }
293 bc->cf_last = cf;
294 bc->ncf++;
295 bc->ndw += 2;
296 bc->force_add_cf = 0;
297 bc->ar_loaded = 0;
298 return 0;
299 }
300
301 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
302 {
303 int r;
304
305 if (output->gpr >= bc->ngpr)
306 bc->ngpr = output->gpr + 1;
307
308 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
309 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
310 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
311 output->type == bc->cf_last->output.type &&
312 output->elem_size == bc->cf_last->output.elem_size &&
313 output->swizzle_x == bc->cf_last->output.swizzle_x &&
314 output->swizzle_y == bc->cf_last->output.swizzle_y &&
315 output->swizzle_z == bc->cf_last->output.swizzle_z &&
316 output->swizzle_w == bc->cf_last->output.swizzle_w &&
317 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
318
319 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
320 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
321
322 bc->cf_last->output.end_of_program |= output->end_of_program;
323 bc->cf_last->output.inst = output->inst;
324 bc->cf_last->output.gpr = output->gpr;
325 bc->cf_last->output.array_base = output->array_base;
326 bc->cf_last->output.burst_count += output->burst_count;
327 return 0;
328
329 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
330 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
331
332 bc->cf_last->output.end_of_program |= output->end_of_program;
333 bc->cf_last->output.inst = output->inst;
334 bc->cf_last->output.burst_count += output->burst_count;
335 return 0;
336 }
337 }
338
339 r = r600_bytecode_add_cf(bc);
340 if (r)
341 return r;
342 bc->cf_last->inst = output->inst;
343 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
344 return 0;
345 }
346
347 /* alu instructions that can ony exits once per group */
348 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
349 {
350 switch (bc->chip_class) {
351 case R600:
352 case R700:
353 return !alu->is_op3 && (
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
377 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
378 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
379 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
380 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
381 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
382 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
383 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
384 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
385 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
386 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
387 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
388 case EVERGREEN:
389 case CAYMAN:
390 default:
391 return !alu->is_op3 && (
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
415 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
416 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
417 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
418 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
419 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
420 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
421 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
422 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
423 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
424 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
425 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
426 }
427 }
428
429 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
430 {
431 switch (bc->chip_class) {
432 case R600:
433 case R700:
434 return !alu->is_op3 && (
435 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
436 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
437 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
438 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
439 case EVERGREEN:
440 case CAYMAN:
441 default:
442 return !alu->is_op3 && (
443 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
444 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
445 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
446 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
447 }
448 }
449
450 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
451 {
452 switch (bc->chip_class) {
453 case R600:
454 case R700:
455 return !alu->is_op3 &&
456 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
457 case EVERGREEN:
458 case CAYMAN:
459 default:
460 return !alu->is_op3 &&
461 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
462 }
463 }
464
465 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
466 {
467 switch (bc->chip_class) {
468 case R600:
469 case R700:
470 return !alu->is_op3 && (
471 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
472 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
473 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
474 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
475 case EVERGREEN:
476 case CAYMAN:
477 default:
478 return !alu->is_op3 && (
479 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
480 }
481 }
482
483 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
484 {
485 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
486 unsigned src;
487
488 if (alu->dst.rel) {
489 return 1;
490 }
491
492 for (src = 0; src < num_src; ++src) {
493 if (alu->src[src].rel) {
494 return 1;
495 }
496 }
497 return 0;
498 }
499
500 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
501 {
502 return min <= opcode && opcode <= max;
503 }
504
505 /* ALU instructions that can only execute on the vector unit:
506 *
507 * opcode ranges:
508 * R6xx/R7xx:
509 * op3 : [0x08 - 0x0B]
510 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
511 *
512 * EVERGREEN:
513 * op3: [0x04 - 0x11]
514 * op2: [0xA0 - 0xE2]
515 */
516 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
517 {
518 switch (bc->chip_class) {
519 case R600:
520 case R700:
521 if (alu->is_op3)
522 return is_opcode_in_range(alu->inst,
523 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
524 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
525 else
526 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
527 is_opcode_in_range(alu->inst,
528 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
529 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
530 is_opcode_in_range(alu->inst,
531 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
532 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
533 is_opcode_in_range(alu->inst,
534 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
535 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
536 is_opcode_in_range(alu->inst,
537 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
538 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
539
540 case EVERGREEN:
541 if (alu->is_op3)
542 return is_opcode_in_range(alu->inst,
543 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
544 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
545 else
546 return is_opcode_in_range(alu->inst,
547 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
548 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
549 case CAYMAN:
550 default:
551 assert(0);
552 return 0;
553 }
554 }
555
556 /* ALU instructions that can only execute on the trans unit:
557 *
558 * opcode ranges:
559 * R600:
560 * op3: 0x0C
561 * op2: [0x60 - 0x79]
562 *
563 * R700:
564 * op3: 0x0C
565 * op2: [0x60 - 0x6F], [0x73 - 0x79]
566 *
567 * EVERGREEN:
568 * op3: 0x1F
569 * op2: [0x81 - 0x9C]
570 */
571 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
572 {
573
574 switch (bc->chip_class) {
575 case R600:
576 if (alu->is_op3)
577 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
578 else
579 return is_opcode_in_range(alu->inst,
580 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
581 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
582 case R700:
583 if (alu->is_op3)
584 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
585 else
586 return is_opcode_in_range(alu->inst,
587 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
588 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
589 is_opcode_in_range(alu->inst,
590 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
591 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
592 case EVERGREEN:
593 if (alu->is_op3)
594 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
595 else
596 return is_opcode_in_range(alu->inst,
597 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
598 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
599 case CAYMAN:
600 default:
601 assert(0);
602 return 0;
603 }
604 }
605
606 /* alu instructions that can execute on any unit */
607 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
608 {
609 return !is_alu_vec_unit_inst(bc, alu) &&
610 !is_alu_trans_unit_inst(bc, alu);
611 }
612
613 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
614 {
615 switch (bc->chip_class) {
616 case R600:
617 case R700:
618 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
619 case EVERGREEN:
620 case CAYMAN:
621 default:
622 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
623 }
624 }
625
626 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
627 struct r600_bytecode_alu *assignment[5])
628 {
629 struct r600_bytecode_alu *alu;
630 unsigned i, chan, trans;
631 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
632
633 for (i = 0; i < max_slots; i++)
634 assignment[i] = NULL;
635
636 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
637 chan = alu->dst.chan;
638 if (max_slots == 4)
639 trans = 0;
640 else if (is_alu_trans_unit_inst(bc, alu))
641 trans = 1;
642 else if (is_alu_vec_unit_inst(bc, alu))
643 trans = 0;
644 else if (assignment[chan])
645 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
646 else
647 trans = 0;
648
649 if (trans) {
650 if (assignment[4]) {
651 assert(0); /* ALU.Trans has already been allocated. */
652 return -1;
653 }
654 assignment[4] = alu;
655 } else {
656 if (assignment[chan]) {
657 assert(0); /* ALU.chan has already been allocated. */
658 return -1;
659 }
660 assignment[chan] = alu;
661 }
662
663 if (alu->last)
664 break;
665 }
666 return 0;
667 }
668
669 struct alu_bank_swizzle {
670 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
671 int hw_cfile_addr[4];
672 int hw_cfile_elem[4];
673 };
674
675 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
676 [SQ_ALU_VEC_012] = { 0, 1, 2 },
677 [SQ_ALU_VEC_021] = { 0, 2, 1 },
678 [SQ_ALU_VEC_120] = { 1, 2, 0 },
679 [SQ_ALU_VEC_102] = { 1, 0, 2 },
680 [SQ_ALU_VEC_201] = { 2, 0, 1 },
681 [SQ_ALU_VEC_210] = { 2, 1, 0 }
682 };
683
684 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
685 [SQ_ALU_SCL_210] = { 2, 1, 0 },
686 [SQ_ALU_SCL_122] = { 1, 2, 2 },
687 [SQ_ALU_SCL_212] = { 2, 1, 2 },
688 [SQ_ALU_SCL_221] = { 2, 2, 1 }
689 };
690
691 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
692 {
693 int i, cycle, component;
694 /* set up gpr use */
695 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
696 for (component = 0; component < NUM_OF_COMPONENTS; component++)
697 bs->hw_gpr[cycle][component] = -1;
698 for (i = 0; i < 4; i++)
699 bs->hw_cfile_addr[i] = -1;
700 for (i = 0; i < 4; i++)
701 bs->hw_cfile_elem[i] = -1;
702 }
703
704 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
705 {
706 if (bs->hw_gpr[cycle][chan] == -1)
707 bs->hw_gpr[cycle][chan] = sel;
708 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
709 /* Another scalar operation has already used the GPR read port for the channel. */
710 return -1;
711 }
712 return 0;
713 }
714
715 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
716 {
717 int res, num_res = 4;
718 if (bc->chip_class >= R700) {
719 num_res = 2;
720 chan /= 2;
721 }
722 for (res = 0; res < num_res; ++res) {
723 if (bs->hw_cfile_addr[res] == -1) {
724 bs->hw_cfile_addr[res] = sel;
725 bs->hw_cfile_elem[res] = chan;
726 return 0;
727 } else if (bs->hw_cfile_addr[res] == sel &&
728 bs->hw_cfile_elem[res] == chan)
729 return 0; /* Read for this scalar element already reserved, nothing to do here. */
730 }
731 /* All cfile read ports are used, cannot reference vector element. */
732 return -1;
733 }
734
735 static int is_gpr(unsigned sel)
736 {
737 return (sel >= 0 && sel <= 127);
738 }
739
740 /* CB constants start at 512, and get translated to a kcache index when ALU
741 * clauses are constructed. Note that we handle kcache constants the same way
742 * as (the now gone) cfile constants, is that really required? */
743 static int is_cfile(unsigned sel)
744 {
745 return (sel > 255 && sel < 512) ||
746 (sel > 511 && sel < 4607) || /* Kcache before translation. */
747 (sel > 127 && sel < 192); /* Kcache after translation. */
748 }
749
750 static int is_const(int sel)
751 {
752 return is_cfile(sel) ||
753 (sel >= V_SQ_ALU_SRC_0 &&
754 sel <= V_SQ_ALU_SRC_LITERAL);
755 }
756
757 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
758 struct alu_bank_swizzle *bs, int bank_swizzle)
759 {
760 int r, src, num_src, sel, elem, cycle;
761
762 num_src = r600_bytecode_get_num_operands(bc, alu);
763 for (src = 0; src < num_src; src++) {
764 sel = alu->src[src].sel;
765 elem = alu->src[src].chan;
766 if (is_gpr(sel)) {
767 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
768 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
769 /* Nothing to do; special-case optimization,
770 * second source uses first source’s reservation. */
771 continue;
772 else {
773 r = reserve_gpr(bs, sel, elem, cycle);
774 if (r)
775 return r;
776 }
777 } else if (is_cfile(sel)) {
778 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
779 if (r)
780 return r;
781 }
782 /* No restrictions on PV, PS, literal or special constants. */
783 }
784 return 0;
785 }
786
787 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
788 struct alu_bank_swizzle *bs, int bank_swizzle)
789 {
790 int r, src, num_src, const_count, sel, elem, cycle;
791
792 num_src = r600_bytecode_get_num_operands(bc, alu);
793 for (const_count = 0, src = 0; src < num_src; ++src) {
794 sel = alu->src[src].sel;
795 elem = alu->src[src].chan;
796 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
797 if (const_count >= 2)
798 /* More than two references to a constant in
799 * transcendental operation. */
800 return -1;
801 else
802 const_count++;
803 }
804 if (is_cfile(sel)) {
805 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
806 if (r)
807 return r;
808 }
809 }
810 for (src = 0; src < num_src; ++src) {
811 sel = alu->src[src].sel;
812 elem = alu->src[src].chan;
813 if (is_gpr(sel)) {
814 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
815 if (cycle < const_count)
816 /* Cycle for GPR load conflicts with
817 * constant load in transcendental operation. */
818 return -1;
819 r = reserve_gpr(bs, sel, elem, cycle);
820 if (r)
821 return r;
822 }
823 /* PV PS restrictions */
824 if (const_count && (sel == 254 || sel == 255)) {
825 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
826 if (cycle < const_count)
827 return -1;
828 }
829 }
830 return 0;
831 }
832
833 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
834 struct r600_bytecode_alu *slots[5])
835 {
836 struct alu_bank_swizzle bs;
837 int bank_swizzle[5];
838 int i, r = 0, forced = 1;
839 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
840 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
841
842 for (i = 0; i < max_slots; i++) {
843 if (slots[i]) {
844 if (slots[i]->bank_swizzle_force) {
845 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
846 } else {
847 forced = 0;
848 }
849 }
850
851 if (i < 4 && slots[i])
852 scalar_only = false;
853 }
854 if (forced)
855 return 0;
856
857 /* Just check every possible combination of bank swizzle.
858 * Not very efficent, but works on the first try in most of the cases. */
859 for (i = 0; i < 4; i++)
860 if (!slots[i] || !slots[i]->bank_swizzle_force)
861 bank_swizzle[i] = SQ_ALU_VEC_012;
862 else
863 bank_swizzle[i] = slots[i]->bank_swizzle;
864
865 bank_swizzle[4] = SQ_ALU_SCL_210;
866 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
867
868 if (max_slots == 4) {
869 for (i = 0; i < max_slots; i++) {
870 if (bank_swizzle[i] == SQ_ALU_VEC_210)
871 return -1;
872 }
873 }
874 init_bank_swizzle(&bs);
875 if (scalar_only == false) {
876 for (i = 0; i < 4; i++) {
877 if (slots[i]) {
878 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
879 if (r)
880 break;
881 }
882 }
883 } else
884 r = 0;
885
886 if (!r && slots[4] && max_slots == 5) {
887 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
888 }
889 if (!r) {
890 for (i = 0; i < max_slots; i++) {
891 if (slots[i])
892 slots[i]->bank_swizzle = bank_swizzle[i];
893 }
894 return 0;
895 }
896
897 if (scalar_only) {
898 bank_swizzle[4]++;
899 } else {
900 for (i = 0; i < max_slots; i++) {
901 if (!slots[i] || !slots[i]->bank_swizzle_force) {
902 bank_swizzle[i]++;
903 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
904 break;
905 else
906 bank_swizzle[i] = SQ_ALU_VEC_012;
907 }
908 }
909 }
910 }
911
912 /* Couldn't find a working swizzle. */
913 return -1;
914 }
915
916 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
917 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
918 {
919 struct r600_bytecode_alu *prev[5];
920 int gpr[5], chan[5];
921 int i, j, r, src, num_src;
922 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
923
924 r = assign_alu_units(bc, alu_prev, prev);
925 if (r)
926 return r;
927
928 for (i = 0; i < max_slots; ++i) {
929 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
930 gpr[i] = prev[i]->dst.sel;
931 /* cube writes more than PV.X */
932 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
933 chan[i] = 0;
934 else
935 chan[i] = prev[i]->dst.chan;
936 } else
937 gpr[i] = -1;
938 }
939
940 for (i = 0; i < max_slots; ++i) {
941 struct r600_bytecode_alu *alu = slots[i];
942 if(!alu)
943 continue;
944
945 num_src = r600_bytecode_get_num_operands(bc, alu);
946 for (src = 0; src < num_src; ++src) {
947 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
948 continue;
949
950 if (bc->chip_class < CAYMAN) {
951 if (alu->src[src].sel == gpr[4] &&
952 alu->src[src].chan == chan[4] &&
953 alu_prev->pred_sel == alu->pred_sel) {
954 alu->src[src].sel = V_SQ_ALU_SRC_PS;
955 alu->src[src].chan = 0;
956 continue;
957 }
958 }
959
960 for (j = 0; j < 4; ++j) {
961 if (alu->src[src].sel == gpr[j] &&
962 alu->src[src].chan == j &&
963 alu_prev->pred_sel == alu->pred_sel) {
964 alu->src[src].sel = V_SQ_ALU_SRC_PV;
965 alu->src[src].chan = chan[j];
966 break;
967 }
968 }
969 }
970 }
971
972 return 0;
973 }
974
975 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
976 {
977 switch(value) {
978 case 0:
979 *sel = V_SQ_ALU_SRC_0;
980 break;
981 case 1:
982 *sel = V_SQ_ALU_SRC_1_INT;
983 break;
984 case -1:
985 *sel = V_SQ_ALU_SRC_M_1_INT;
986 break;
987 case 0x3F800000: /* 1.0f */
988 *sel = V_SQ_ALU_SRC_1;
989 break;
990 case 0x3F000000: /* 0.5f */
991 *sel = V_SQ_ALU_SRC_0_5;
992 break;
993 case 0xBF800000: /* -1.0f */
994 *sel = V_SQ_ALU_SRC_1;
995 *neg ^= 1;
996 break;
997 case 0xBF000000: /* -0.5f */
998 *sel = V_SQ_ALU_SRC_0_5;
999 *neg ^= 1;
1000 break;
1001 default:
1002 *sel = V_SQ_ALU_SRC_LITERAL;
1003 break;
1004 }
1005 }
1006
1007 /* compute how many literal are needed */
1008 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
1009 uint32_t literal[4], unsigned *nliteral)
1010 {
1011 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1012 unsigned i, j;
1013
1014 for (i = 0; i < num_src; ++i) {
1015 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1016 uint32_t value = alu->src[i].value;
1017 unsigned found = 0;
1018 for (j = 0; j < *nliteral; ++j) {
1019 if (literal[j] == value) {
1020 found = 1;
1021 break;
1022 }
1023 }
1024 if (!found) {
1025 if (*nliteral >= 4)
1026 return -EINVAL;
1027 literal[(*nliteral)++] = value;
1028 }
1029 }
1030 }
1031 return 0;
1032 }
1033
1034 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1035 struct r600_bytecode_alu *alu,
1036 uint32_t literal[4], unsigned nliteral)
1037 {
1038 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1039 unsigned i, j;
1040
1041 for (i = 0; i < num_src; ++i) {
1042 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1043 uint32_t value = alu->src[i].value;
1044 for (j = 0; j < nliteral; ++j) {
1045 if (literal[j] == value) {
1046 alu->src[i].chan = j;
1047 break;
1048 }
1049 }
1050 }
1051 }
1052 }
1053
1054 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1055 struct r600_bytecode_alu *alu_prev)
1056 {
1057 struct r600_bytecode_alu *prev[5];
1058 struct r600_bytecode_alu *result[5] = { NULL };
1059
1060 uint32_t literal[4], prev_literal[4];
1061 unsigned nliteral = 0, prev_nliteral = 0;
1062
1063 int i, j, r, src, num_src;
1064 int num_once_inst = 0;
1065 int have_mova = 0, have_rel = 0;
1066 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1067
1068 r = assign_alu_units(bc, alu_prev, prev);
1069 if (r)
1070 return r;
1071
1072 for (i = 0; i < max_slots; ++i) {
1073 if (prev[i]) {
1074 if (prev[i]->pred_sel)
1075 return 0;
1076 if (is_alu_once_inst(bc, prev[i]))
1077 return 0;
1078 }
1079 if (slots[i]) {
1080 if (slots[i]->pred_sel)
1081 return 0;
1082 if (is_alu_once_inst(bc, slots[i]))
1083 return 0;
1084 }
1085 }
1086
1087 for (i = 0; i < max_slots; ++i) {
1088 struct r600_bytecode_alu *alu;
1089
1090 if (num_once_inst > 0)
1091 return 0;
1092
1093 /* check number of literals */
1094 if (prev[i]) {
1095 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1096 return 0;
1097 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1098 return 0;
1099 if (is_alu_mova_inst(bc, prev[i])) {
1100 if (have_rel)
1101 return 0;
1102 have_mova = 1;
1103 }
1104
1105 if (alu_uses_rel(bc, prev[i])) {
1106 if (have_mova) {
1107 return 0;
1108 }
1109 have_rel = 1;
1110 }
1111
1112 num_once_inst += is_alu_once_inst(bc, prev[i]);
1113 }
1114 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1115 return 0;
1116
1117 /* Let's check used slots. */
1118 if (prev[i] && !slots[i]) {
1119 result[i] = prev[i];
1120 continue;
1121 } else if (prev[i] && slots[i]) {
1122 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1123 /* Trans unit is still free try to use it. */
1124 if (is_alu_any_unit_inst(bc, slots[i])) {
1125 result[i] = prev[i];
1126 result[4] = slots[i];
1127 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1128 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1129 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1130 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1131 return 0;
1132
1133 result[i] = slots[i];
1134 result[4] = prev[i];
1135 } else
1136 return 0;
1137 } else
1138 return 0;
1139 } else if(!slots[i]) {
1140 continue;
1141 } else {
1142 if (max_slots == 5 && slots[i] && prev[4] &&
1143 slots[i]->dst.sel == prev[4]->dst.sel &&
1144 slots[i]->dst.chan == prev[4]->dst.chan &&
1145 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1146 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1147 return 0;
1148
1149 result[i] = slots[i];
1150 }
1151
1152 alu = slots[i];
1153 num_once_inst += is_alu_once_inst(bc, alu);
1154
1155 /* don't reschedule NOPs */
1156 if (is_nop_inst(bc, alu))
1157 return 0;
1158
1159 if (is_alu_mova_inst(bc, alu)) {
1160 if (have_rel) {
1161 return 0;
1162 }
1163 have_mova = 1;
1164 }
1165
1166 if (alu_uses_rel(bc, alu)) {
1167 if (have_mova) {
1168 return 0;
1169 }
1170 have_rel = 1;
1171 }
1172
1173 /* Let's check source gprs */
1174 num_src = r600_bytecode_get_num_operands(bc, alu);
1175 for (src = 0; src < num_src; ++src) {
1176
1177 /* Constants don't matter. */
1178 if (!is_gpr(alu->src[src].sel))
1179 continue;
1180
1181 for (j = 0; j < max_slots; ++j) {
1182 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1183 continue;
1184
1185 /* If it's relative then we can't determin which gpr is really used. */
1186 if (prev[j]->dst.chan == alu->src[src].chan &&
1187 (prev[j]->dst.sel == alu->src[src].sel ||
1188 prev[j]->dst.rel || alu->src[src].rel))
1189 return 0;
1190 }
1191 }
1192 }
1193
1194 /* more than one PRED_ or KILL_ ? */
1195 if (num_once_inst > 1)
1196 return 0;
1197
1198 /* check if the result can still be swizzlet */
1199 r = check_and_set_bank_swizzle(bc, result);
1200 if (r)
1201 return 0;
1202
1203 /* looks like everything worked out right, apply the changes */
1204
1205 /* undo adding previus literals */
1206 bc->cf_last->ndw -= align(prev_nliteral, 2);
1207
1208 /* sort instructions */
1209 for (i = 0; i < max_slots; ++i) {
1210 slots[i] = result[i];
1211 if (result[i]) {
1212 LIST_DEL(&result[i]->list);
1213 result[i]->last = 0;
1214 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1215 }
1216 }
1217
1218 /* determine new last instruction */
1219 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1220
1221 /* determine new first instruction */
1222 for (i = 0; i < max_slots; ++i) {
1223 if (result[i]) {
1224 bc->cf_last->curr_bs_head = result[i];
1225 break;
1226 }
1227 }
1228
1229 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1230 bc->cf_last->prev2_bs_head = NULL;
1231
1232 return 0;
1233 }
1234
1235 /* we'll keep kcache sets sorted by bank & addr */
1236 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1237 struct r600_bytecode_kcache *kcache,
1238 unsigned bank, unsigned line)
1239 {
1240 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1241
1242 for (i = 0; i < kcache_banks; i++) {
1243 if (kcache[i].mode) {
1244 int d;
1245
1246 if (kcache[i].bank < bank)
1247 continue;
1248
1249 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1250 kcache[i].bank > bank) {
1251 /* try to insert new line */
1252 if (kcache[kcache_banks-1].mode) {
1253 /* all sets are in use */
1254 return -ENOMEM;
1255 }
1256
1257 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1258 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1259 kcache[i].bank = bank;
1260 kcache[i].addr = line;
1261 return 0;
1262 }
1263
1264 d = line - kcache[i].addr;
1265
1266 if (d == -1) {
1267 kcache[i].addr--;
1268 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1269 /* we are prepending the line to the current set,
1270 * discarding the existing second line,
1271 * so we'll have to insert line+2 after it */
1272 line += 2;
1273 continue;
1274 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1275 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1276 return 0;
1277 } else {
1278 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1279 return -ENOMEM;
1280 }
1281 } else if (d == 1) {
1282 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1283 return 0;
1284 } else if (d == 0)
1285 return 0;
1286 } else { /* free kcache set - use it */
1287 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1288 kcache[i].bank = bank;
1289 kcache[i].addr = line;
1290 return 0;
1291 }
1292 }
1293 return -ENOMEM;
1294 }
1295
1296 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1297 struct r600_bytecode_kcache *kcache,
1298 struct r600_bytecode_alu *alu)
1299 {
1300 int i, r;
1301
1302 for (i = 0; i < 3; i++) {
1303 unsigned bank, line, sel = alu->src[i].sel;
1304
1305 if (sel < 512)
1306 continue;
1307
1308 bank = alu->src[i].kc_bank;
1309 line = (sel-512)>>4;
1310
1311 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1312 return r;
1313 }
1314 return 0;
1315 }
1316
1317 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1318 struct r600_bytecode_alu *alu,
1319 struct r600_bytecode_kcache * kcache)
1320 {
1321 int i, j;
1322
1323 /* Alter the src operands to refer to the kcache. */
1324 for (i = 0; i < 3; ++i) {
1325 static const unsigned int base[] = {128, 160, 256, 288};
1326 unsigned int line, sel = alu->src[i].sel, found = 0;
1327
1328 if (sel < 512)
1329 continue;
1330
1331 sel -= 512;
1332 line = sel>>4;
1333
1334 for (j = 0; j < 4 && !found; ++j) {
1335 switch (kcache[j].mode) {
1336 case V_SQ_CF_KCACHE_NOP:
1337 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1338 R600_ERR("unexpected kcache line mode\n");
1339 return -ENOMEM;
1340 default:
1341 if (kcache[j].bank == alu->src[i].kc_bank &&
1342 kcache[j].addr <= line &&
1343 line < kcache[j].addr + kcache[j].mode) {
1344 alu->src[i].sel = sel - (kcache[j].addr<<4);
1345 alu->src[i].sel += base[j];
1346 found=1;
1347 }
1348 }
1349 }
1350 }
1351 return 0;
1352 }
1353
1354 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1355 {
1356 struct r600_bytecode_kcache kcache_sets[4];
1357 struct r600_bytecode_kcache *kcache = kcache_sets;
1358 int r;
1359
1360 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1361
1362 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1363 /* can't alloc, need to start new clause */
1364 if ((r = r600_bytecode_add_cf(bc))) {
1365 return r;
1366 }
1367 bc->cf_last->inst = type;
1368
1369 /* retry with the new clause */
1370 kcache = bc->cf_last->kcache;
1371 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1372 /* can't alloc again- should never happen */
1373 return r;
1374 }
1375 } else {
1376 /* update kcache sets */
1377 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1378 }
1379
1380 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1381 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1382 if (bc->chip_class < EVERGREEN)
1383 return -ENOMEM;
1384 bc->cf_last->eg_alu_extended = 1;
1385 }
1386
1387 return 0;
1388 }
1389
1390 static int insert_nop_r6xx(struct r600_bytecode *bc)
1391 {
1392 struct r600_bytecode_alu alu;
1393 int r, i;
1394
1395 for (i = 0; i < 4; i++) {
1396 memset(&alu, 0, sizeof(alu));
1397 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1398 alu.src[0].chan = i;
1399 alu.dst.chan = i;
1400 alu.last = (i == 3);
1401 r = r600_bytecode_add_alu(bc, &alu);
1402 if (r)
1403 return r;
1404 }
1405 return 0;
1406 }
1407
1408 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1409 static int load_ar_r6xx(struct r600_bytecode *bc)
1410 {
1411 struct r600_bytecode_alu alu;
1412 int r;
1413
1414 if (bc->ar_loaded)
1415 return 0;
1416
1417 /* hack to avoid making MOVA the last instruction in the clause */
1418 if ((bc->cf_last->ndw>>1) >= 110)
1419 bc->force_add_cf = 1;
1420
1421 memset(&alu, 0, sizeof(alu));
1422 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1423 alu.src[0].sel = bc->ar_reg;
1424 alu.src[0].chan = bc->ar_chan;
1425 alu.last = 1;
1426 alu.index_mode = INDEX_MODE_LOOP;
1427 r = r600_bytecode_add_alu(bc, &alu);
1428 if (r)
1429 return r;
1430
1431 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1432 bc->ar_loaded = 1;
1433 return 0;
1434 }
1435
1436 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1437 static int load_ar(struct r600_bytecode *bc)
1438 {
1439 struct r600_bytecode_alu alu;
1440 int r;
1441
1442 if (bc->ar_handling)
1443 return load_ar_r6xx(bc);
1444
1445 if (bc->ar_loaded)
1446 return 0;
1447
1448 /* hack to avoid making MOVA the last instruction in the clause */
1449 if ((bc->cf_last->ndw>>1) >= 110)
1450 bc->force_add_cf = 1;
1451
1452 memset(&alu, 0, sizeof(alu));
1453 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1454 alu.src[0].sel = bc->ar_reg;
1455 alu.src[0].chan = bc->ar_chan;
1456 alu.last = 1;
1457 r = r600_bytecode_add_alu(bc, &alu);
1458 if (r)
1459 return r;
1460
1461 bc->cf_last->r6xx_uses_waterfall = 1;
1462 bc->ar_loaded = 1;
1463 return 0;
1464 }
1465
1466 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1467 {
1468 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1469 struct r600_bytecode_alu *lalu;
1470 int i, r;
1471
1472 if (nalu == NULL)
1473 return -ENOMEM;
1474 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1475
1476 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1477 /* check if we could add it anyway */
1478 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1479 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1480 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1481 if (lalu->execute_mask) {
1482 bc->force_add_cf = 1;
1483 break;
1484 }
1485 }
1486 } else
1487 bc->force_add_cf = 1;
1488 }
1489
1490 /* cf can contains only alu or only vtx or only tex */
1491 if (bc->cf_last == NULL || bc->force_add_cf) {
1492 r = r600_bytecode_add_cf(bc);
1493 if (r) {
1494 free(nalu);
1495 return r;
1496 }
1497 }
1498 bc->cf_last->inst = type;
1499
1500 /* Check AR usage and load it if required */
1501 for (i = 0; i < 3; i++)
1502 if (nalu->src[i].rel && !bc->ar_loaded)
1503 load_ar(bc);
1504
1505 if (nalu->dst.rel && !bc->ar_loaded)
1506 load_ar(bc);
1507
1508 /* Setup the kcache for this ALU instruction. This will start a new
1509 * ALU clause if needed. */
1510 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1511 free(nalu);
1512 return r;
1513 }
1514
1515 if (!bc->cf_last->curr_bs_head) {
1516 bc->cf_last->curr_bs_head = nalu;
1517 }
1518 /* number of gpr == the last gpr used in any alu */
1519 for (i = 0; i < 3; i++) {
1520 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1521 bc->ngpr = nalu->src[i].sel + 1;
1522 }
1523 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1524 r600_bytecode_special_constants(nalu->src[i].value,
1525 &nalu->src[i].sel, &nalu->src[i].neg);
1526 }
1527 if (nalu->dst.sel >= bc->ngpr) {
1528 bc->ngpr = nalu->dst.sel + 1;
1529 }
1530 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1531 /* each alu use 2 dwords */
1532 bc->cf_last->ndw += 2;
1533 bc->ndw += 2;
1534
1535 /* process cur ALU instructions for bank swizzle */
1536 if (nalu->last) {
1537 uint32_t literal[4];
1538 unsigned nliteral;
1539 struct r600_bytecode_alu *slots[5];
1540 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1541 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1542 if (r)
1543 return r;
1544
1545 if (bc->cf_last->prev_bs_head) {
1546 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1547 if (r)
1548 return r;
1549 }
1550
1551 if (bc->cf_last->prev_bs_head) {
1552 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1553 if (r)
1554 return r;
1555 }
1556
1557 r = check_and_set_bank_swizzle(bc, slots);
1558 if (r)
1559 return r;
1560
1561 for (i = 0, nliteral = 0; i < max_slots; i++) {
1562 if (slots[i]) {
1563 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1564 if (r)
1565 return r;
1566 }
1567 }
1568 bc->cf_last->ndw += align(nliteral, 2);
1569
1570 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1571 * worst case */
1572 if ((bc->cf_last->ndw >> 1) >= 120) {
1573 bc->force_add_cf = 1;
1574 }
1575
1576 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1577 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1578 bc->cf_last->curr_bs_head = NULL;
1579 }
1580
1581 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1582 insert_nop_r6xx(bc);
1583
1584 return 0;
1585 }
1586
1587 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1588 {
1589 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1590 }
1591
1592 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1593 {
1594 switch (bc->chip_class) {
1595 case R600:
1596 return 8;
1597
1598 case R700:
1599 case EVERGREEN:
1600 case CAYMAN:
1601 return 16;
1602
1603 default:
1604 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1605 return 8;
1606 }
1607 }
1608
1609 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1610 {
1611 switch (bc->chip_class) {
1612 case R700:
1613 case R600:
1614 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1615 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1616 case EVERGREEN:
1617 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1618 case CAYMAN:
1619 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1620 default:
1621 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1622 return FALSE;
1623 }
1624 }
1625
1626 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1627 {
1628 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1629 int r;
1630
1631 if (nvtx == NULL)
1632 return -ENOMEM;
1633 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1634
1635 /* cf can contains only alu or only vtx or only tex */
1636 if (bc->cf_last == NULL ||
1637 last_inst_was_not_vtx_fetch(bc) ||
1638 bc->force_add_cf) {
1639 r = r600_bytecode_add_cf(bc);
1640 if (r) {
1641 free(nvtx);
1642 return r;
1643 }
1644 switch (bc->chip_class) {
1645 case R600:
1646 case R700:
1647 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1648 break;
1649 case EVERGREEN:
1650 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1651 break;
1652 case CAYMAN:
1653 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1654 break;
1655 default:
1656 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1657 free(nvtx);
1658 return -EINVAL;
1659 }
1660 }
1661 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1662 /* each fetch use 4 dwords */
1663 bc->cf_last->ndw += 4;
1664 bc->ndw += 4;
1665 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1666 bc->force_add_cf = 1;
1667
1668 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1669 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1670
1671 return 0;
1672 }
1673
1674 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1675 {
1676 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1677 int r;
1678
1679 if (ntex == NULL)
1680 return -ENOMEM;
1681 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1682
1683 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1684 if (bc->cf_last != NULL &&
1685 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1686 struct r600_bytecode_tex *ttex;
1687 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1688 if (ttex->dst_gpr == ntex->src_gpr) {
1689 bc->force_add_cf = 1;
1690 break;
1691 }
1692 }
1693 /* slight hack to make gradients always go into same cf */
1694 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1695 bc->force_add_cf = 1;
1696 }
1697
1698 /* cf can contains only alu or only vtx or only tex */
1699 if (bc->cf_last == NULL ||
1700 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1701 bc->force_add_cf) {
1702 r = r600_bytecode_add_cf(bc);
1703 if (r) {
1704 free(ntex);
1705 return r;
1706 }
1707 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1708 }
1709 if (ntex->src_gpr >= bc->ngpr) {
1710 bc->ngpr = ntex->src_gpr + 1;
1711 }
1712 if (ntex->dst_gpr >= bc->ngpr) {
1713 bc->ngpr = ntex->dst_gpr + 1;
1714 }
1715 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1716 /* each texture fetch use 4 dwords */
1717 bc->cf_last->ndw += 4;
1718 bc->ndw += 4;
1719 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1720 bc->force_add_cf = 1;
1721 return 0;
1722 }
1723
1724 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1725 {
1726 int r;
1727 r = r600_bytecode_add_cf(bc);
1728 if (r)
1729 return r;
1730
1731 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1732 bc->cf_last->inst = inst;
1733 return 0;
1734 }
1735
1736 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1737 {
1738 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1739 }
1740
1741 /* common to all 3 families */
1742 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1743 {
1744 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1745 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1746 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1747 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1748 if (bc->chip_class < CAYMAN)
1749 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1750 id++;
1751 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1752 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1753 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1754 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1755 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1756 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1757 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1758 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1759 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1760 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1761 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1762 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1763 if (bc->chip_class < CAYMAN)
1764 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1765 id++;
1766 bc->bytecode[id++] = 0;
1767 return 0;
1768 }
1769
1770 /* common to all 3 families */
1771 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1772 {
1773 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1774 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1775 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1776 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1777 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1778 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1779 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1780 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1781 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1782 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1783 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1784 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1785 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1786 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1787 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1788 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1789 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1790 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1791 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1792 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1793 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1794 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1795 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1796 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1797 bc->bytecode[id++] = 0;
1798 return 0;
1799 }
1800
1801 /* r600 only, r700/eg bits in r700_asm.c */
1802 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1803 {
1804 /* don't replace gpr by pv or ps for destination register */
1805 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1806 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1807 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1808 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1809 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1810 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1811 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1812 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1813 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1814 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1815 S_SQ_ALU_WORD0_LAST(alu->last);
1816
1817 if (alu->is_op3) {
1818 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1819 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1820 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1821 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1822 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1823 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1824 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1825 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1826 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1827 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1828 } else {
1829 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1830 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1831 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1832 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1833 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1834 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1835 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1836 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1837 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1838 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1839 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1840 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1841 }
1842 return 0;
1843 }
1844
1845 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1846 {
1847 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1848 *bytecode++ = cf->inst |
1849 S_SQ_CF_WORD1_BARRIER(1) |
1850 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1851 }
1852
1853 /* common for r600/r700 - eg in eg_asm.c */
1854 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1855 {
1856 unsigned id = cf->id;
1857
1858 switch (cf->inst) {
1859 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1860 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1861 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1862 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1863 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1864 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1865 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1866 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1867
1868 bc->bytecode[id++] = cf->inst |
1869 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1870 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1871 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1872 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1873 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1874 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1875 break;
1876 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1877 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1878 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1879 if (bc->chip_class == R700)
1880 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1881 else
1882 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1883 break;
1884 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1885 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1886 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1887 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1888 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1889 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1890 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1891 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1892 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1893 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1894 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1895 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1896 cf->output.inst |
1897 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1898 break;
1899 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1900 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1901 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1902 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1903 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1904 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1905 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1906 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1907 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1908 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1909 cf->output.inst |
1910 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1911 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1912 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1913 break;
1914 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1915 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1916 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1917 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1918 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
1919 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1920 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1921 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1922 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1923 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1924 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1925 bc->bytecode[id++] = cf->inst |
1926 S_SQ_CF_WORD1_BARRIER(1) |
1927 S_SQ_CF_WORD1_COND(cf->cond) |
1928 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1929
1930 break;
1931 default:
1932 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1933 return -EINVAL;
1934 }
1935 return 0;
1936 }
1937
1938 int r600_bytecode_build(struct r600_bytecode *bc)
1939 {
1940 struct r600_bytecode_cf *cf;
1941 struct r600_bytecode_alu *alu;
1942 struct r600_bytecode_vtx *vtx;
1943 struct r600_bytecode_tex *tex;
1944 uint32_t literal[4];
1945 unsigned nliteral;
1946 unsigned addr;
1947 int i, r;
1948
1949 if (bc->callstack[0].max > 0)
1950 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1951 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1952 bc->nstack = 1;
1953 }
1954
1955 /* first path compute addr of each CF block */
1956 /* addr start after all the CF instructions */
1957 addr = bc->cf_last->id + 2;
1958 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1959 if (bc->chip_class >= EVERGREEN) {
1960 switch (cf->inst) {
1961 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1962 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1963 /* fetch node need to be 16 bytes aligned*/
1964 addr += 3;
1965 addr &= 0xFFFFFFFCUL;
1966 break;
1967 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1968 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1969 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1970 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1971 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1972 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1973 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1974 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1975 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1976 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1977 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1978 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1979 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1980 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1981 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1982 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1983 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1984 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1985 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1986 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1987 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1988 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1989 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1990 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1991 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1992 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1993 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
1994 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1995 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1996 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1997 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1998 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1999 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2000 case CF_NATIVE:
2001 break;
2002 default:
2003 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2004 return -EINVAL;
2005 }
2006 } else {
2007 switch (cf->inst) {
2008 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2009 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2010 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2011 /* fetch node need to be 16 bytes aligned*/
2012 addr += 3;
2013 addr &= 0xFFFFFFFCUL;
2014 break;
2015 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2016 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2017 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2018 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2019 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2020 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2021 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2022 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2023 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2024 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2025 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2026 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2027 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2028 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2029 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2030 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2031 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2032 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2033 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2034 break;
2035 default:
2036 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2037 return -EINVAL;
2038 }
2039 }
2040 cf->addr = addr;
2041 addr += cf->ndw;
2042 bc->ndw = cf->addr + cf->ndw;
2043 }
2044 free(bc->bytecode);
2045 bc->bytecode = calloc(1, bc->ndw * 4);
2046 if (bc->bytecode == NULL)
2047 return -ENOMEM;
2048 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2049 addr = cf->addr;
2050 if (bc->chip_class >= EVERGREEN) {
2051 r = eg_bytecode_cf_build(bc, cf);
2052 if (r)
2053 return r;
2054
2055 switch (cf->inst) {
2056 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2057 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2058 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2059 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2060 nliteral = 0;
2061 memset(literal, 0, sizeof(literal));
2062 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2063 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2064 if (r)
2065 return r;
2066 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2067 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2068
2069 switch(bc->chip_class) {
2070 case EVERGREEN: /* eg alu is same encoding as r700 */
2071 case CAYMAN:
2072 r = r700_bytecode_alu_build(bc, alu, addr);
2073 break;
2074 default:
2075 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2076 return -EINVAL;
2077 }
2078 if (r)
2079 return r;
2080 addr += 2;
2081 if (alu->last) {
2082 for (i = 0; i < align(nliteral, 2); ++i) {
2083 bc->bytecode[addr++] = literal[i];
2084 }
2085 nliteral = 0;
2086 memset(literal, 0, sizeof(literal));
2087 }
2088 }
2089 break;
2090 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2091 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2092 r = r600_bytecode_vtx_build(bc, vtx, addr);
2093 if (r)
2094 return r;
2095 addr += 4;
2096 }
2097 break;
2098 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2099 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2100 assert(bc->chip_class >= EVERGREEN);
2101 r = r600_bytecode_vtx_build(bc, vtx, addr);
2102 if (r)
2103 return r;
2104 addr += 4;
2105 }
2106 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2107 r = r600_bytecode_tex_build(bc, tex, addr);
2108 if (r)
2109 return r;
2110 addr += 4;
2111 }
2112 break;
2113 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2114 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2115 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2116 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2117 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2118 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2119 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2120 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2121 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2122 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2123 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2124 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2125 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2126 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2127 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2128 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2129 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2130 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2131 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2132 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2133 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2134 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2135 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2136 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2137 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2138 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2139 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2140 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2141 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2142 break;
2143 case CF_NATIVE:
2144 break;
2145 default:
2146 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2147 return -EINVAL;
2148 }
2149 } else {
2150 r = r600_bytecode_cf_build(bc, cf);
2151 if (r)
2152 return r;
2153
2154 switch (cf->inst) {
2155 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2156 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2157 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2158 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2159 nliteral = 0;
2160 memset(literal, 0, sizeof(literal));
2161 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2162 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2163 if (r)
2164 return r;
2165 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2166 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2167
2168 switch(bc->chip_class) {
2169 case R600:
2170 r = r600_bytecode_alu_build(bc, alu, addr);
2171 break;
2172 case R700:
2173 r = r700_bytecode_alu_build(bc, alu, addr);
2174 break;
2175 default:
2176 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2177 return -EINVAL;
2178 }
2179 if (r)
2180 return r;
2181 addr += 2;
2182 if (alu->last) {
2183 for (i = 0; i < align(nliteral, 2); ++i) {
2184 bc->bytecode[addr++] = literal[i];
2185 }
2186 nliteral = 0;
2187 memset(literal, 0, sizeof(literal));
2188 }
2189 }
2190 break;
2191 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2192 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2193 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2194 r = r600_bytecode_vtx_build(bc, vtx, addr);
2195 if (r)
2196 return r;
2197 addr += 4;
2198 }
2199 break;
2200 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2201 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2202 r = r600_bytecode_tex_build(bc, tex, addr);
2203 if (r)
2204 return r;
2205 addr += 4;
2206 }
2207 break;
2208 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2209 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2210 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2211 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2212 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2213 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2214 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2215 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2216 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2217 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2218 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2219 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2220 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2221 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2222 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2223 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2224 break;
2225 default:
2226 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2227 return -EINVAL;
2228 }
2229 }
2230 }
2231 return 0;
2232 }
2233
2234 void r600_bytecode_clear(struct r600_bytecode *bc)
2235 {
2236 struct r600_bytecode_cf *cf = NULL, *next_cf;
2237
2238 free(bc->bytecode);
2239 bc->bytecode = NULL;
2240
2241 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2242 struct r600_bytecode_alu *alu = NULL, *next_alu;
2243 struct r600_bytecode_tex *tex = NULL, *next_tex;
2244 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2245
2246 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2247 free(alu);
2248 }
2249
2250 LIST_INITHEAD(&cf->alu);
2251
2252 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2253 free(tex);
2254 }
2255
2256 LIST_INITHEAD(&cf->tex);
2257
2258 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2259 free(vtx);
2260 }
2261
2262 LIST_INITHEAD(&cf->vtx);
2263
2264 free(cf);
2265 }
2266
2267 LIST_INITHEAD(&cf->list);
2268 }
2269
2270 void r600_bytecode_dump(struct r600_bytecode *bc)
2271 {
2272 struct r600_bytecode_cf *cf = NULL;
2273 struct r600_bytecode_alu *alu = NULL;
2274 struct r600_bytecode_vtx *vtx = NULL;
2275 struct r600_bytecode_tex *tex = NULL;
2276
2277 unsigned i, id;
2278 uint32_t literal[4];
2279 unsigned nliteral;
2280 char chip = '6';
2281
2282 switch (bc->chip_class) {
2283 case R700:
2284 chip = '7';
2285 break;
2286 case EVERGREEN:
2287 chip = 'E';
2288 break;
2289 case CAYMAN:
2290 chip = 'C';
2291 break;
2292 case R600:
2293 default:
2294 chip = '6';
2295 break;
2296 }
2297 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2298 fprintf(stderr, " %c\n", chip);
2299
2300 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2301 id = cf->id;
2302
2303 if (bc->chip_class >= EVERGREEN) {
2304 switch (cf->inst) {
2305 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2306 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2307 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2308 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2309 if (cf->eg_alu_extended) {
2310 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2311 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2312 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2313 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2314 id++;
2315 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2316 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2317 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2318 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2319 id++;
2320 }
2321
2322 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2323 fprintf(stderr, "ADDR:%d ", cf->addr);
2324 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2325 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2326 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2327 id++;
2328 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2329 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2330 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2331 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2332 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2333 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2334 break;
2335 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2336 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2337 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2338 fprintf(stderr, "ADDR:%d\n", cf->addr);
2339 id++;
2340 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2341 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2342 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2343 break;
2344 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2345 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2346 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2347 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2348 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2349 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2350 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2351 id++;
2352 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2353 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2354 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2355 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2356 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2357 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2358 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2359 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2360 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2361 break;
2362 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2363 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2364 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2365 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2366 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2367 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2368 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2369 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2370 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2371 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2372 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2373 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2374 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2375 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2376 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2377 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2378 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2379 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2380 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2381 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2382 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2383 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2384 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2385 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2386 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2387 id++;
2388 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2389 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2390 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2391 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2392 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2393 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2394 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2395 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2396 fprintf(stderr, "INST:%d ", cf->output.inst);
2397 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2398 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2399 break;
2400 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2401 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2402 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2403 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2404 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2405 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2406 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2407 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2408 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2409 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2410 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2411 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2412 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2413 id++;
2414 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2415 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2416 fprintf(stderr, "COND:%X ", cf->cond);
2417 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2418 break;
2419 case CF_NATIVE:
2420 fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
2421 fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
2422 break;
2423 default:
2424 R600_ERR("Unknown instruction %0x\n", cf->inst);
2425 }
2426 } else {
2427 switch (cf->inst) {
2428 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2429 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2430 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2431 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2432 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2433 fprintf(stderr, "ADDR:%d ", cf->addr);
2434 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2435 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2436 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2437 id++;
2438 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2439 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2440 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2441 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2442 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2443 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2444 break;
2445 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2446 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2447 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2448 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2449 fprintf(stderr, "ADDR:%d\n", cf->addr);
2450 id++;
2451 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2452 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2453 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2454 break;
2455 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2456 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2457 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2458 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2459 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2460 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2461 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2462 id++;
2463 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2464 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2465 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2466 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2467 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2468 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2469 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2470 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2471 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2472 break;
2473 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2474 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2475 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2476 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2477 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2478 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2479 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2480 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2481 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2482 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2483 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2484 id++;
2485 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2486 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2487 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2488 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2489 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2490 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2491 fprintf(stderr, "INST:%d ", cf->output.inst);
2492 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2493 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2494 break;
2495 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2496 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2497 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2498 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2499 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2500 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2501 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2502 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2503 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2504 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2505 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2506 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2507 id++;
2508 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2509 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2510 fprintf(stderr, "COND:%X ", cf->cond);
2511 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2512 break;
2513 default:
2514 R600_ERR("Unknown instruction %0x\n", cf->inst);
2515 }
2516 }
2517
2518 id = cf->addr;
2519 nliteral = 0;
2520 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2521 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2522
2523 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2524 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2525 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2526 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2527 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2528 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2529 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2530 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2531 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2532 fprintf(stderr, "IM:%d) ", alu->index_mode);
2533 fprintf(stderr, "PRED_SEL:%d ", alu->pred_sel);
2534 fprintf(stderr, "LAST:%d)\n", alu->last);
2535 id++;
2536 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2537 fprintf(stderr, "INST:0x%x ", alu->inst);
2538 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2539 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2540 fprintf(stderr, "REL:%d ", alu->dst.rel);
2541 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2542 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2543 if (alu->is_op3) {
2544 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2545 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2546 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2547 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2548 } else {
2549 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2550 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2551 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2552 fprintf(stderr, "OMOD:%d ", alu->omod);
2553 fprintf(stderr, "EXECUTE_MASK:%d ", alu->execute_mask);
2554 fprintf(stderr, "UPDATE_PRED:%d\n", alu->update_pred);
2555 }
2556
2557 id++;
2558 if (alu->last) {
2559 for (i = 0; i < nliteral; i++, id++) {
2560 float *f = (float*)(bc->bytecode + id);
2561 fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
2562 *(bc->bytecode + id));
2563 }
2564 id += nliteral & 1;
2565 nliteral = 0;
2566 }
2567 }
2568
2569 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2570 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2571 fprintf(stderr, "INST:0x%x ", tex->inst);
2572 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2573 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2574 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2575 id++;
2576 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2577 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2578 fprintf(stderr, "REL:%d ", tex->dst_rel);
2579 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2580 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2581 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2582 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2583 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2584 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2585 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2586 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2587 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2588 id++;
2589 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2590 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2591 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2592 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2593 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2594 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2595 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2596 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2597 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2598 id++;
2599 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2600 id++;
2601 }
2602
2603 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2604 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2605 fprintf(stderr, "INST:%d ", vtx->inst);
2606 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2607 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2608 id++;
2609 /* This assumes that no semantic fetches exist */
2610 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2611 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2612 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2613 if (bc->chip_class < CAYMAN)
2614 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2615 else
2616 fprintf(stderr, "SEL_Y:%d) ", 0);
2617 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2618 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2619 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2620 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2621 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2622 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2623 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2624 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2625 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2626 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2627 id++;
2628 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2629 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2630 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2631 /* XXX */
2632 id++;
2633 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2634 id++;
2635 }
2636 }
2637
2638 fprintf(stderr, "--------------------------------------\n");
2639 }
2640
2641 void r600_vertex_data_type(enum pipe_format pformat,
2642 unsigned *format,
2643 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2644 {
2645 const struct util_format_description *desc;
2646 unsigned i;
2647
2648 *format = 0;
2649 *num_format = 0;
2650 *format_comp = 0;
2651 *endian = ENDIAN_NONE;
2652
2653 desc = util_format_description(pformat);
2654 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2655 goto out_unknown;
2656 }
2657
2658 /* Find the first non-VOID channel. */
2659 for (i = 0; i < 4; i++) {
2660 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2661 break;
2662 }
2663 }
2664
2665 *endian = r600_endian_swap(desc->channel[i].size);
2666
2667 switch (desc->channel[i].type) {
2668 /* Half-floats, floats, ints */
2669 case UTIL_FORMAT_TYPE_FLOAT:
2670 switch (desc->channel[i].size) {
2671 case 16:
2672 switch (desc->nr_channels) {
2673 case 1:
2674 *format = FMT_16_FLOAT;
2675 break;
2676 case 2:
2677 *format = FMT_16_16_FLOAT;
2678 break;
2679 case 3:
2680 case 4:
2681 *format = FMT_16_16_16_16_FLOAT;
2682 break;
2683 }
2684 break;
2685 case 32:
2686 switch (desc->nr_channels) {
2687 case 1:
2688 *format = FMT_32_FLOAT;
2689 break;
2690 case 2:
2691 *format = FMT_32_32_FLOAT;
2692 break;
2693 case 3:
2694 *format = FMT_32_32_32_FLOAT;
2695 break;
2696 case 4:
2697 *format = FMT_32_32_32_32_FLOAT;
2698 break;
2699 }
2700 break;
2701 default:
2702 goto out_unknown;
2703 }
2704 break;
2705 /* Unsigned ints */
2706 case UTIL_FORMAT_TYPE_UNSIGNED:
2707 /* Signed ints */
2708 case UTIL_FORMAT_TYPE_SIGNED:
2709 switch (desc->channel[i].size) {
2710 case 8:
2711 switch (desc->nr_channels) {
2712 case 1:
2713 *format = FMT_8;
2714 break;
2715 case 2:
2716 *format = FMT_8_8;
2717 break;
2718 case 3:
2719 case 4:
2720 *format = FMT_8_8_8_8;
2721 break;
2722 }
2723 break;
2724 case 10:
2725 if (desc->nr_channels != 4)
2726 goto out_unknown;
2727
2728 *format = FMT_2_10_10_10;
2729 break;
2730 case 16:
2731 switch (desc->nr_channels) {
2732 case 1:
2733 *format = FMT_16;
2734 break;
2735 case 2:
2736 *format = FMT_16_16;
2737 break;
2738 case 3:
2739 case 4:
2740 *format = FMT_16_16_16_16;
2741 break;
2742 }
2743 break;
2744 case 32:
2745 switch (desc->nr_channels) {
2746 case 1:
2747 *format = FMT_32;
2748 break;
2749 case 2:
2750 *format = FMT_32_32;
2751 break;
2752 case 3:
2753 *format = FMT_32_32_32;
2754 break;
2755 case 4:
2756 *format = FMT_32_32_32_32;
2757 break;
2758 }
2759 break;
2760 default:
2761 goto out_unknown;
2762 }
2763 break;
2764 default:
2765 goto out_unknown;
2766 }
2767
2768 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2769 *format_comp = 1;
2770 }
2771
2772 *num_format = 0;
2773 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2774 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2775 if (!desc->channel[i].normalized) {
2776 if (desc->channel[i].pure_integer)
2777 *num_format = 1;
2778 else
2779 *num_format = 2;
2780 }
2781 }
2782 return;
2783 out_unknown:
2784 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2785 }
2786
2787 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2788 unsigned count,
2789 const struct pipe_vertex_element *elements)
2790 {
2791 struct r600_context *rctx = (struct r600_context *)ctx;
2792 static int dump_shaders = -1;
2793 struct r600_bytecode bc;
2794 struct r600_bytecode_vtx vtx;
2795 const struct util_format_description *desc;
2796 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2797 unsigned format, num_format, format_comp, endian;
2798 uint32_t *bytecode;
2799 int i, j, r, fs_size;
2800 struct r600_fetch_shader *shader;
2801
2802 assert(count < 32);
2803
2804 memset(&bc, 0, sizeof(bc));
2805 r600_bytecode_init(&bc, rctx->chip_class, rctx->family,
2806 rctx->screen->msaa_texture_support);
2807
2808 for (i = 0; i < count; i++) {
2809 if (elements[i].instance_divisor > 1) {
2810 if (rctx->chip_class == CAYMAN) {
2811 for (j = 0; j < 4; j++) {
2812 struct r600_bytecode_alu alu;
2813 memset(&alu, 0, sizeof(alu));
2814 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2815 alu.src[0].sel = 0;
2816 alu.src[0].chan = 3;
2817 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2818 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2819 alu.dst.sel = i + 1;
2820 alu.dst.chan = j;
2821 alu.dst.write = j == 3;
2822 alu.last = j == 3;
2823 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2824 r600_bytecode_clear(&bc);
2825 return NULL;
2826 }
2827 }
2828 } else {
2829 struct r600_bytecode_alu alu;
2830 memset(&alu, 0, sizeof(alu));
2831 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2832 alu.src[0].sel = 0;
2833 alu.src[0].chan = 3;
2834 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2835 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2836 alu.dst.sel = i + 1;
2837 alu.dst.chan = 3;
2838 alu.dst.write = 1;
2839 alu.last = 1;
2840 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2841 r600_bytecode_clear(&bc);
2842 return NULL;
2843 }
2844 }
2845 }
2846 }
2847
2848 for (i = 0; i < count; i++) {
2849 r600_vertex_data_type(elements[i].src_format,
2850 &format, &num_format, &format_comp, &endian);
2851
2852 desc = util_format_description(elements[i].src_format);
2853 if (desc == NULL) {
2854 r600_bytecode_clear(&bc);
2855 R600_ERR("unknown format %d\n", elements[i].src_format);
2856 return NULL;
2857 }
2858
2859 if (elements[i].src_offset > 65535) {
2860 r600_bytecode_clear(&bc);
2861 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2862 return NULL;
2863 }
2864
2865 memset(&vtx, 0, sizeof(vtx));
2866 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2867 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2868 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2869 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2870 vtx.mega_fetch_count = 0x1F;
2871 vtx.dst_gpr = i + 1;
2872 vtx.dst_sel_x = desc->swizzle[0];
2873 vtx.dst_sel_y = desc->swizzle[1];
2874 vtx.dst_sel_z = desc->swizzle[2];
2875 vtx.dst_sel_w = desc->swizzle[3];
2876 vtx.data_format = format;
2877 vtx.num_format_all = num_format;
2878 vtx.format_comp_all = format_comp;
2879 vtx.srf_mode_all = 1;
2880 vtx.offset = elements[i].src_offset;
2881 vtx.endian = endian;
2882
2883 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2884 r600_bytecode_clear(&bc);
2885 return NULL;
2886 }
2887 }
2888
2889 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2890
2891 if ((r = r600_bytecode_build(&bc))) {
2892 r600_bytecode_clear(&bc);
2893 return NULL;
2894 }
2895
2896 if (dump_shaders == -1)
2897 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2898
2899 if (dump_shaders) {
2900 fprintf(stderr, "--------------------------------------------------------------\n");
2901 r600_bytecode_dump(&bc);
2902 fprintf(stderr, "______________________________________________________________\n");
2903 }
2904
2905 fs_size = bc.ndw*4;
2906
2907 /* Allocate the CSO. */
2908 shader = CALLOC_STRUCT(r600_fetch_shader);
2909 if (!shader) {
2910 r600_bytecode_clear(&bc);
2911 return NULL;
2912 }
2913
2914 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2915 (struct pipe_resource**)&shader->buffer);
2916 if (!shader->buffer) {
2917 r600_bytecode_clear(&bc);
2918 FREE(shader);
2919 return NULL;
2920 }
2921
2922 bytecode = r600_buffer_mmap_sync_with_rings(rctx, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2923 bytecode += shader->offset / 4;
2924
2925 if (R600_BIG_ENDIAN) {
2926 for (i = 0; i < fs_size / 4; ++i) {
2927 bytecode[i] = bswap_32(bc.bytecode[i]);
2928 }
2929 } else {
2930 memcpy(bytecode, bc.bytecode, fs_size);
2931 }
2932 rctx->ws->buffer_unmap(shader->buffer->cs_buf);
2933
2934 r600_bytecode_clear(&bc);
2935 return shader;
2936 }
2937
2938 void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2939 {
2940 /* WORD0 */
2941 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2942 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2943 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2944 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2945 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2946 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2947 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2948 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2949 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2950 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2951 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2952
2953 /* WORD1 */
2954 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2955 if (alu->bank_swizzle)
2956 alu->bank_swizzle_force = alu->bank_swizzle;
2957 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2958 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2959 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2960 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2961 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2962 {
2963 alu->is_op3 = 1;
2964 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2965 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2966 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2967 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2968 alu->inst = G_SQ_ALU_WORD1_OP3_ALU_INST(word1);
2969 }
2970 else /*ALU_DWORD1_OP2*/
2971 {
2972 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2973 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2974 alu->inst = G_SQ_ALU_WORD1_OP2_ALU_INST(word1);
2975 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2976 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2977 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2978 alu->execute_mask =
2979 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2980 }
2981 }
2982
2983 void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2984 {
2985 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2986 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2987 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2988 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2989
2990 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2991 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2992 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2993 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2994 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2995 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2996 output->inst = R600_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
2997 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2998 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2999 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
3000 }