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23350e259676889f6e6fc61f56a8d897c92646e0
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <byteswap.h>
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "r600_pipe.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600_asm.h"
33 #include "r600_formats.h"
34 #include "r600d.h"
35
36 #define NUM_OF_CYCLES 3
37 #define NUM_OF_COMPONENTS 4
38
39 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
40 {
41 if(alu->is_op3)
42 return 3;
43
44 switch (bc->chip_class) {
45 case R600:
46 case R700:
47 switch (alu->inst) {
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
49 return 0;
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
92 return 2;
93
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
116 return 1;
117 default: R600_ERR(
118 "Need instruction operand number for 0x%x.\n", alu->inst);
119 }
120 break;
121 case EVERGREEN:
122 case CAYMAN:
123 switch (alu->inst) {
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
125 return 0;
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
170 return 2;
171
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0:
194 return 1;
195 default: R600_ERR(
196 "Need instruction operand number for 0x%x.\n", alu->inst);
197 }
198 break;
199 }
200
201 return 3;
202 }
203
204 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
205
206 static struct r600_bytecode_cf *r600_bytecode_cf(void)
207 {
208 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
209
210 if (cf == NULL)
211 return NULL;
212 LIST_INITHEAD(&cf->list);
213 LIST_INITHEAD(&cf->alu);
214 LIST_INITHEAD(&cf->vtx);
215 LIST_INITHEAD(&cf->tex);
216 return cf;
217 }
218
219 static struct r600_bytecode_alu *r600_bytecode_alu(void)
220 {
221 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
222
223 if (alu == NULL)
224 return NULL;
225 LIST_INITHEAD(&alu->list);
226 return alu;
227 }
228
229 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
230 {
231 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
232
233 if (vtx == NULL)
234 return NULL;
235 LIST_INITHEAD(&vtx->list);
236 return vtx;
237 }
238
239 static struct r600_bytecode_tex *r600_bytecode_tex(void)
240 {
241 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
242
243 if (tex == NULL)
244 return NULL;
245 LIST_INITHEAD(&tex->list);
246 return tex;
247 }
248
249 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class)
250 {
251 LIST_INITHEAD(&bc->cf);
252 bc->chip_class = chip_class;
253 }
254
255 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
256 {
257 struct r600_bytecode_cf *cf = r600_bytecode_cf();
258
259 if (cf == NULL)
260 return -ENOMEM;
261 LIST_ADDTAIL(&cf->list, &bc->cf);
262 if (bc->cf_last)
263 cf->id = bc->cf_last->id + 2;
264 bc->cf_last = cf;
265 bc->ncf++;
266 bc->ndw += 2;
267 bc->force_add_cf = 0;
268 bc->ar_loaded = 0;
269 return 0;
270 }
271
272 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
273 {
274 int r;
275
276 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
277 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
278 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
279 output->type == bc->cf_last->output.type &&
280 output->elem_size == bc->cf_last->output.elem_size &&
281 output->swizzle_x == bc->cf_last->output.swizzle_x &&
282 output->swizzle_y == bc->cf_last->output.swizzle_y &&
283 output->swizzle_z == bc->cf_last->output.swizzle_z &&
284 output->swizzle_w == bc->cf_last->output.swizzle_w &&
285 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
286
287 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
288 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
289
290 bc->cf_last->output.end_of_program |= output->end_of_program;
291 bc->cf_last->output.inst = output->inst;
292 bc->cf_last->output.gpr = output->gpr;
293 bc->cf_last->output.array_base = output->array_base;
294 bc->cf_last->output.burst_count += output->burst_count;
295 return 0;
296
297 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
298 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
299
300 bc->cf_last->output.end_of_program |= output->end_of_program;
301 bc->cf_last->output.inst = output->inst;
302 bc->cf_last->output.burst_count += output->burst_count;
303 return 0;
304 }
305 }
306
307 r = r600_bytecode_add_cf(bc);
308 if (r)
309 return r;
310 bc->cf_last->inst = output->inst;
311 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
312 return 0;
313 }
314
315 /* alu instructions that can ony exits once per group */
316 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
317 {
318 switch (bc->chip_class) {
319 case R600:
320 case R700:
321 return !alu->is_op3 && (
322 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
323 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
324 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
325 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
326 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
327 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
328 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
329 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
330 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
331 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
332 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
333 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
334 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
335 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
336 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
337 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
338 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
339 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
340 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
341 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
342 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
343 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
348 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
356 case EVERGREEN:
357 case CAYMAN:
358 default:
359 return !alu->is_op3 && (
360 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
361 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
362 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
363 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
364 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
365 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
366 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
367 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
368 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
369 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
370 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
371 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
372 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
373 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
374 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
375 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
376 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
377 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
378 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
379 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
380 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
381 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
394 }
395 }
396
397 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
398 {
399 switch (bc->chip_class) {
400 case R600:
401 case R700:
402 return !alu->is_op3 && (
403 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
404 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
405 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
406 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
407 case EVERGREEN:
408 case CAYMAN:
409 default:
410 return !alu->is_op3 && (
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
415 }
416 }
417
418 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
419 {
420 switch (bc->chip_class) {
421 case R600:
422 case R700:
423 return !alu->is_op3 &&
424 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
425 case EVERGREEN:
426 case CAYMAN:
427 default:
428 return !alu->is_op3 &&
429 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
430 }
431 }
432
433 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
434 {
435 switch (bc->chip_class) {
436 case R600:
437 case R700:
438 return !alu->is_op3 && (
439 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
440 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
441 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
442 case EVERGREEN:
443 case CAYMAN:
444 default:
445 return !alu->is_op3 && (
446 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
447 }
448 }
449
450 /* alu instructions that can only execute on the vector unit */
451 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
452 {
453 switch (bc->chip_class) {
454 case R600:
455 case R700:
456 return is_alu_reduction_inst(bc, alu) ||
457 is_alu_mova_inst(bc, alu);
458 case EVERGREEN:
459 case CAYMAN:
460 default:
461 return is_alu_reduction_inst(bc, alu) ||
462 is_alu_mova_inst(bc, alu) ||
463 (alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
464 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR ||
465 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY ||
466 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW);
467 }
468 }
469
470 /* alu instructions that can only execute on the trans unit */
471 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
472 {
473 switch (bc->chip_class) {
474 case R600:
475 case R700:
476 if (!alu->is_op3)
477 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
478 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
479 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT ||
480 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
481 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
482 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
483 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
484 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
485 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
486 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
487 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
488 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
489 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
490 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
491 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
492 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
493 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
494 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
495 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
496 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
497 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
498 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
499 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
500 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
501 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
502 else
503 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
504 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
505 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
506 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
507 case EVERGREEN:
508 case CAYMAN:
509 default:
510 if (!alu->is_op3)
511 /* Note that FLT_TO_INT_* instructions are vector-only instructions
512 * on Evergreen, despite what the documentation says. FLT_TO_INT
513 * can do both vector and scalar. */
514 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
515 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
516 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
517 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
518 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
519 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
520 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
521 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
522 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT ||
523 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
524 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
525 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
526 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
527 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
528 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
529 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
530 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
531 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
532 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
533 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
534 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
535 else
536 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
537 }
538 }
539
540 /* alu instructions that can execute on any unit */
541 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
542 {
543 return !is_alu_vec_unit_inst(bc, alu) &&
544 !is_alu_trans_unit_inst(bc, alu);
545 }
546
547 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
548 struct r600_bytecode_alu *assignment[5])
549 {
550 struct r600_bytecode_alu *alu;
551 unsigned i, chan, trans;
552 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
553
554 for (i = 0; i < max_slots; i++)
555 assignment[i] = NULL;
556
557 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
558 chan = alu->dst.chan;
559 if (max_slots == 4)
560 trans = 0;
561 else if (is_alu_trans_unit_inst(bc, alu))
562 trans = 1;
563 else if (is_alu_vec_unit_inst(bc, alu))
564 trans = 0;
565 else if (assignment[chan])
566 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
567 else
568 trans = 0;
569
570 if (trans) {
571 if (assignment[4]) {
572 assert(0); /* ALU.Trans has already been allocated. */
573 return -1;
574 }
575 assignment[4] = alu;
576 } else {
577 if (assignment[chan]) {
578 assert(0); /* ALU.chan has already been allocated. */
579 return -1;
580 }
581 assignment[chan] = alu;
582 }
583
584 if (alu->last)
585 break;
586 }
587 return 0;
588 }
589
590 struct alu_bank_swizzle {
591 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
592 int hw_cfile_addr[4];
593 int hw_cfile_elem[4];
594 };
595
596 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
597 [SQ_ALU_VEC_012] = { 0, 1, 2 },
598 [SQ_ALU_VEC_021] = { 0, 2, 1 },
599 [SQ_ALU_VEC_120] = { 1, 2, 0 },
600 [SQ_ALU_VEC_102] = { 1, 0, 2 },
601 [SQ_ALU_VEC_201] = { 2, 0, 1 },
602 [SQ_ALU_VEC_210] = { 2, 1, 0 }
603 };
604
605 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
606 [SQ_ALU_SCL_210] = { 2, 1, 0 },
607 [SQ_ALU_SCL_122] = { 1, 2, 2 },
608 [SQ_ALU_SCL_212] = { 2, 1, 2 },
609 [SQ_ALU_SCL_221] = { 2, 2, 1 }
610 };
611
612 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
613 {
614 int i, cycle, component;
615 /* set up gpr use */
616 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
617 for (component = 0; component < NUM_OF_COMPONENTS; component++)
618 bs->hw_gpr[cycle][component] = -1;
619 for (i = 0; i < 4; i++)
620 bs->hw_cfile_addr[i] = -1;
621 for (i = 0; i < 4; i++)
622 bs->hw_cfile_elem[i] = -1;
623 }
624
625 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
626 {
627 if (bs->hw_gpr[cycle][chan] == -1)
628 bs->hw_gpr[cycle][chan] = sel;
629 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
630 /* Another scalar operation has already used the GPR read port for the channel. */
631 return -1;
632 }
633 return 0;
634 }
635
636 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
637 {
638 int res, num_res = 4;
639 if (bc->chip_class >= R700) {
640 num_res = 2;
641 chan /= 2;
642 }
643 for (res = 0; res < num_res; ++res) {
644 if (bs->hw_cfile_addr[res] == -1) {
645 bs->hw_cfile_addr[res] = sel;
646 bs->hw_cfile_elem[res] = chan;
647 return 0;
648 } else if (bs->hw_cfile_addr[res] == sel &&
649 bs->hw_cfile_elem[res] == chan)
650 return 0; /* Read for this scalar element already reserved, nothing to do here. */
651 }
652 /* All cfile read ports are used, cannot reference vector element. */
653 return -1;
654 }
655
656 static int is_gpr(unsigned sel)
657 {
658 return (sel >= 0 && sel <= 127);
659 }
660
661 /* CB constants start at 512, and get translated to a kcache index when ALU
662 * clauses are constructed. Note that we handle kcache constants the same way
663 * as (the now gone) cfile constants, is that really required? */
664 static int is_cfile(unsigned sel)
665 {
666 return (sel > 255 && sel < 512) ||
667 (sel > 511 && sel < 4607) || /* Kcache before translation. */
668 (sel > 127 && sel < 192); /* Kcache after translation. */
669 }
670
671 static int is_const(int sel)
672 {
673 return is_cfile(sel) ||
674 (sel >= V_SQ_ALU_SRC_0 &&
675 sel <= V_SQ_ALU_SRC_LITERAL);
676 }
677
678 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
679 struct alu_bank_swizzle *bs, int bank_swizzle)
680 {
681 int r, src, num_src, sel, elem, cycle;
682
683 num_src = r600_bytecode_get_num_operands(bc, alu);
684 for (src = 0; src < num_src; src++) {
685 sel = alu->src[src].sel;
686 elem = alu->src[src].chan;
687 if (is_gpr(sel)) {
688 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
689 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
690 /* Nothing to do; special-case optimization,
691 * second source uses first source’s reservation. */
692 continue;
693 else {
694 r = reserve_gpr(bs, sel, elem, cycle);
695 if (r)
696 return r;
697 }
698 } else if (is_cfile(sel)) {
699 r = reserve_cfile(bc, bs, sel, elem);
700 if (r)
701 return r;
702 }
703 /* No restrictions on PV, PS, literal or special constants. */
704 }
705 return 0;
706 }
707
708 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
709 struct alu_bank_swizzle *bs, int bank_swizzle)
710 {
711 int r, src, num_src, const_count, sel, elem, cycle;
712
713 num_src = r600_bytecode_get_num_operands(bc, alu);
714 for (const_count = 0, src = 0; src < num_src; ++src) {
715 sel = alu->src[src].sel;
716 elem = alu->src[src].chan;
717 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
718 if (const_count >= 2)
719 /* More than two references to a constant in
720 * transcendental operation. */
721 return -1;
722 else
723 const_count++;
724 }
725 if (is_cfile(sel)) {
726 r = reserve_cfile(bc, bs, sel, elem);
727 if (r)
728 return r;
729 }
730 }
731 for (src = 0; src < num_src; ++src) {
732 sel = alu->src[src].sel;
733 elem = alu->src[src].chan;
734 if (is_gpr(sel)) {
735 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
736 if (cycle < const_count)
737 /* Cycle for GPR load conflicts with
738 * constant load in transcendental operation. */
739 return -1;
740 r = reserve_gpr(bs, sel, elem, cycle);
741 if (r)
742 return r;
743 }
744 /* PV PS restrictions */
745 if (const_count && (sel == 254 || sel == 255)) {
746 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
747 if (cycle < const_count)
748 return -1;
749 }
750 }
751 return 0;
752 }
753
754 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
755 struct r600_bytecode_alu *slots[5])
756 {
757 struct alu_bank_swizzle bs;
758 int bank_swizzle[5];
759 int i, r = 0, forced = 1;
760 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
761 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
762
763 for (i = 0; i < max_slots; i++) {
764 if (slots[i]) {
765 if (slots[i]->bank_swizzle_force) {
766 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
767 } else {
768 forced = 0;
769 }
770 }
771
772 if (i < 4 && slots[i])
773 scalar_only = false;
774 }
775 if (forced)
776 return 0;
777
778 /* Just check every possible combination of bank swizzle.
779 * Not very efficent, but works on the first try in most of the cases. */
780 for (i = 0; i < 4; i++)
781 if (!slots[i] || !slots[i]->bank_swizzle_force)
782 bank_swizzle[i] = SQ_ALU_VEC_012;
783 else
784 bank_swizzle[i] = slots[i]->bank_swizzle;
785
786 bank_swizzle[4] = SQ_ALU_SCL_210;
787 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
788
789 if (max_slots == 4) {
790 for (i = 0; i < max_slots; i++) {
791 if (bank_swizzle[i] == SQ_ALU_VEC_210)
792 return -1;
793 }
794 }
795 init_bank_swizzle(&bs);
796 if (scalar_only == false) {
797 for (i = 0; i < 4; i++) {
798 if (slots[i]) {
799 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
800 if (r)
801 break;
802 }
803 }
804 } else
805 r = 0;
806
807 if (!r && slots[4] && max_slots == 5) {
808 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
809 }
810 if (!r) {
811 for (i = 0; i < max_slots; i++) {
812 if (slots[i])
813 slots[i]->bank_swizzle = bank_swizzle[i];
814 }
815 return 0;
816 }
817
818 if (scalar_only) {
819 bank_swizzle[4]++;
820 } else {
821 for (i = 0; i < max_slots; i++) {
822 if (!slots[i] || !slots[i]->bank_swizzle_force) {
823 bank_swizzle[i]++;
824 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
825 break;
826 else
827 bank_swizzle[i] = SQ_ALU_VEC_012;
828 }
829 }
830 }
831 }
832
833 /* Couldn't find a working swizzle. */
834 return -1;
835 }
836
837 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
838 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
839 {
840 struct r600_bytecode_alu *prev[5];
841 int gpr[5], chan[5];
842 int i, j, r, src, num_src;
843 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
844
845 r = assign_alu_units(bc, alu_prev, prev);
846 if (r)
847 return r;
848
849 for (i = 0; i < max_slots; ++i) {
850 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
851 gpr[i] = prev[i]->dst.sel;
852 /* cube writes more than PV.X */
853 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
854 chan[i] = 0;
855 else
856 chan[i] = prev[i]->dst.chan;
857 } else
858 gpr[i] = -1;
859 }
860
861 for (i = 0; i < max_slots; ++i) {
862 struct r600_bytecode_alu *alu = slots[i];
863 if(!alu)
864 continue;
865
866 num_src = r600_bytecode_get_num_operands(bc, alu);
867 for (src = 0; src < num_src; ++src) {
868 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
869 continue;
870
871 if (bc->chip_class < CAYMAN) {
872 if (alu->src[src].sel == gpr[4] &&
873 alu->src[src].chan == chan[4]) {
874 alu->src[src].sel = V_SQ_ALU_SRC_PS;
875 alu->src[src].chan = 0;
876 continue;
877 }
878 }
879
880 for (j = 0; j < 4; ++j) {
881 if (alu->src[src].sel == gpr[j] &&
882 alu->src[src].chan == j) {
883 alu->src[src].sel = V_SQ_ALU_SRC_PV;
884 alu->src[src].chan = chan[j];
885 break;
886 }
887 }
888 }
889 }
890
891 return 0;
892 }
893
894 void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
895 {
896 switch(value) {
897 case 0:
898 *sel = V_SQ_ALU_SRC_0;
899 break;
900 case 1:
901 *sel = V_SQ_ALU_SRC_1_INT;
902 break;
903 case -1:
904 *sel = V_SQ_ALU_SRC_M_1_INT;
905 break;
906 case 0x3F800000: /* 1.0f */
907 *sel = V_SQ_ALU_SRC_1;
908 break;
909 case 0x3F000000: /* 0.5f */
910 *sel = V_SQ_ALU_SRC_0_5;
911 break;
912 case 0xBF800000: /* -1.0f */
913 *sel = V_SQ_ALU_SRC_1;
914 *neg ^= 1;
915 break;
916 case 0xBF000000: /* -0.5f */
917 *sel = V_SQ_ALU_SRC_0_5;
918 *neg ^= 1;
919 break;
920 default:
921 *sel = V_SQ_ALU_SRC_LITERAL;
922 break;
923 }
924 }
925
926 /* compute how many literal are needed */
927 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
928 uint32_t literal[4], unsigned *nliteral)
929 {
930 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
931 unsigned i, j;
932
933 for (i = 0; i < num_src; ++i) {
934 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
935 uint32_t value = alu->src[i].value;
936 unsigned found = 0;
937 for (j = 0; j < *nliteral; ++j) {
938 if (literal[j] == value) {
939 found = 1;
940 break;
941 }
942 }
943 if (!found) {
944 if (*nliteral >= 4)
945 return -EINVAL;
946 literal[(*nliteral)++] = value;
947 }
948 }
949 }
950 return 0;
951 }
952
953 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
954 struct r600_bytecode_alu *alu,
955 uint32_t literal[4], unsigned nliteral)
956 {
957 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
958 unsigned i, j;
959
960 for (i = 0; i < num_src; ++i) {
961 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
962 uint32_t value = alu->src[i].value;
963 for (j = 0; j < nliteral; ++j) {
964 if (literal[j] == value) {
965 alu->src[i].chan = j;
966 break;
967 }
968 }
969 }
970 }
971 }
972
973 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
974 struct r600_bytecode_alu *alu_prev)
975 {
976 struct r600_bytecode_alu *prev[5];
977 struct r600_bytecode_alu *result[5] = { NULL };
978
979 uint32_t literal[4], prev_literal[4];
980 unsigned nliteral = 0, prev_nliteral = 0;
981
982 int i, j, r, src, num_src;
983 int num_once_inst = 0;
984 int have_mova = 0, have_rel = 0;
985 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
986
987 r = assign_alu_units(bc, alu_prev, prev);
988 if (r)
989 return r;
990
991 for (i = 0; i < max_slots; ++i) {
992 struct r600_bytecode_alu *alu;
993
994 /* check number of literals */
995 if (prev[i]) {
996 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
997 return 0;
998 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
999 return 0;
1000 if (is_alu_mova_inst(bc, prev[i])) {
1001 if (have_rel)
1002 return 0;
1003 have_mova = 1;
1004 }
1005 num_once_inst += is_alu_once_inst(bc, prev[i]);
1006 }
1007 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1008 return 0;
1009
1010 /* Let's check used slots. */
1011 if (prev[i] && !slots[i]) {
1012 result[i] = prev[i];
1013 continue;
1014 } else if (prev[i] && slots[i]) {
1015 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1016 /* Trans unit is still free try to use it. */
1017 if (is_alu_any_unit_inst(bc, slots[i])) {
1018 result[i] = prev[i];
1019 result[4] = slots[i];
1020 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1021 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1022 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1023 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1024 return 0;
1025
1026 result[i] = slots[i];
1027 result[4] = prev[i];
1028 } else
1029 return 0;
1030 } else
1031 return 0;
1032 } else if(!slots[i]) {
1033 continue;
1034 } else {
1035 if (max_slots == 5 && slots[i] && prev[4] &&
1036 slots[i]->dst.sel == prev[4]->dst.sel &&
1037 slots[i]->dst.chan == prev[4]->dst.chan &&
1038 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1039 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1040 return 0;
1041
1042 result[i] = slots[i];
1043 }
1044
1045 alu = slots[i];
1046 num_once_inst += is_alu_once_inst(bc, alu);
1047
1048 /* Let's check dst gpr. */
1049 if (alu->dst.rel) {
1050 if (have_mova)
1051 return 0;
1052 have_rel = 1;
1053 }
1054
1055 /* Let's check source gprs */
1056 num_src = r600_bytecode_get_num_operands(bc, alu);
1057 for (src = 0; src < num_src; ++src) {
1058 if (alu->src[src].rel) {
1059 if (have_mova)
1060 return 0;
1061 have_rel = 1;
1062 }
1063
1064 /* Constants don't matter. */
1065 if (!is_gpr(alu->src[src].sel))
1066 continue;
1067
1068 for (j = 0; j < max_slots; ++j) {
1069 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1070 continue;
1071
1072 /* If it's relative then we can't determin which gpr is really used. */
1073 if (prev[j]->dst.chan == alu->src[src].chan &&
1074 (prev[j]->dst.sel == alu->src[src].sel ||
1075 prev[j]->dst.rel || alu->src[src].rel))
1076 return 0;
1077 }
1078 }
1079 }
1080
1081 /* more than one PRED_ or KILL_ ? */
1082 if (num_once_inst > 1)
1083 return 0;
1084
1085 /* check if the result can still be swizzlet */
1086 r = check_and_set_bank_swizzle(bc, result);
1087 if (r)
1088 return 0;
1089
1090 /* looks like everything worked out right, apply the changes */
1091
1092 /* undo adding previus literals */
1093 bc->cf_last->ndw -= align(prev_nliteral, 2);
1094
1095 /* sort instructions */
1096 for (i = 0; i < max_slots; ++i) {
1097 slots[i] = result[i];
1098 if (result[i]) {
1099 LIST_DEL(&result[i]->list);
1100 result[i]->last = 0;
1101 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1102 }
1103 }
1104
1105 /* determine new last instruction */
1106 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1107
1108 /* determine new first instruction */
1109 for (i = 0; i < max_slots; ++i) {
1110 if (result[i]) {
1111 bc->cf_last->curr_bs_head = result[i];
1112 break;
1113 }
1114 }
1115
1116 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1117 bc->cf_last->prev2_bs_head = NULL;
1118
1119 return 0;
1120 }
1121
1122 /* This code handles kcache lines as single blocks of 32 constants. We could
1123 * probably do slightly better by recognizing that we actually have two
1124 * consecutive lines of 16 constants, but the resulting code would also be
1125 * somewhat more complicated. */
1126 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1127 {
1128 struct r600_bytecode_kcache *kcache = bc->cf_last->kcache;
1129 unsigned int required_lines;
1130 unsigned int free_lines = 0;
1131 unsigned int cache_line[3];
1132 unsigned int count = 0;
1133 unsigned int i, j;
1134 int r;
1135
1136 /* Collect required cache lines. */
1137 for (i = 0; i < 3; ++i) {
1138 boolean found = false;
1139 unsigned int line;
1140
1141 if (alu->src[i].sel < 512)
1142 continue;
1143
1144 line = ((alu->src[i].sel - 512) / 32) * 2;
1145
1146 for (j = 0; j < count; ++j) {
1147 if (cache_line[j] == line) {
1148 found = true;
1149 break;
1150 }
1151 }
1152
1153 if (!found)
1154 cache_line[count++] = line;
1155 }
1156
1157 /* This should never actually happen. */
1158 if (count >= 3) return -ENOMEM;
1159
1160 for (i = 0; i < 2; ++i) {
1161 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1162 ++free_lines;
1163 }
1164 }
1165
1166 /* Filter lines pulled in by previous intructions. Note that this is
1167 * only for the required_lines count, we can't remove these from the
1168 * cache_line array since we may have to start a new ALU clause. */
1169 for (i = 0, required_lines = count; i < count; ++i) {
1170 for (j = 0; j < 2; ++j) {
1171 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1172 kcache[j].addr == cache_line[i]) {
1173 --required_lines;
1174 break;
1175 }
1176 }
1177 }
1178
1179 /* Start a new ALU clause if needed. */
1180 if (required_lines > free_lines) {
1181 if ((r = r600_bytecode_add_cf(bc))) {
1182 return r;
1183 }
1184 bc->cf_last->inst = type;
1185 kcache = bc->cf_last->kcache;
1186 }
1187
1188 /* Setup the kcache lines. */
1189 for (i = 0; i < count; ++i) {
1190 boolean found = false;
1191
1192 for (j = 0; j < 2; ++j) {
1193 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1194 kcache[j].addr == cache_line[i]) {
1195 found = true;
1196 break;
1197 }
1198 }
1199
1200 if (found) continue;
1201
1202 for (j = 0; j < 2; ++j) {
1203 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1204 kcache[j].bank = 0;
1205 kcache[j].addr = cache_line[i];
1206 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1207 break;
1208 }
1209 }
1210 }
1211
1212 /* Alter the src operands to refer to the kcache. */
1213 for (i = 0; i < 3; ++i) {
1214 static const unsigned int base[] = {128, 160, 256, 288};
1215 unsigned int line;
1216
1217 if (alu->src[i].sel < 512)
1218 continue;
1219
1220 alu->src[i].sel -= 512;
1221 line = (alu->src[i].sel / 32) * 2;
1222
1223 for (j = 0; j < 2; ++j) {
1224 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1225 kcache[j].addr == line) {
1226 alu->src[i].sel &= 0x1f;
1227 alu->src[i].sel += base[j];
1228 break;
1229 }
1230 }
1231 }
1232
1233 return 0;
1234 }
1235
1236 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1237 static int load_ar(struct r600_bytecode *bc)
1238 {
1239 struct r600_bytecode_alu alu;
1240 int r;
1241
1242 if (bc->ar_loaded)
1243 return 0;
1244
1245 /* hack to avoid making MOVA the last instruction in the clause */
1246 if ((bc->cf_last->ndw>>1) >= 110)
1247 bc->force_add_cf = 1;
1248
1249 memset(&alu, 0, sizeof(alu));
1250 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1251 alu.src[0].sel = bc->ar_reg;
1252 alu.last = 1;
1253 r = r600_bytecode_add_alu(bc, &alu);
1254 if (r)
1255 return r;
1256
1257 bc->cf_last->r6xx_uses_waterfall = 1;
1258 bc->ar_loaded = 1;
1259 return 0;
1260 }
1261
1262 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1263 {
1264 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1265 struct r600_bytecode_alu *lalu;
1266 int i, r;
1267
1268 if (nalu == NULL)
1269 return -ENOMEM;
1270 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1271
1272 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1273 /* check if we could add it anyway */
1274 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1275 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1276 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1277 if (lalu->predicate) {
1278 bc->force_add_cf = 1;
1279 break;
1280 }
1281 }
1282 } else
1283 bc->force_add_cf = 1;
1284 }
1285
1286 /* cf can contains only alu or only vtx or only tex */
1287 if (bc->cf_last == NULL || bc->force_add_cf) {
1288 r = r600_bytecode_add_cf(bc);
1289 if (r) {
1290 free(nalu);
1291 return r;
1292 }
1293 }
1294 bc->cf_last->inst = type;
1295
1296 /* Check AR usage and load it if required */
1297 for (i = 0; i < 3; i++)
1298 if (nalu->src[i].rel && !bc->ar_loaded)
1299 load_ar(bc);
1300
1301 if (nalu->dst.rel && !bc->ar_loaded)
1302 load_ar(bc);
1303
1304 /* Setup the kcache for this ALU instruction. This will start a new
1305 * ALU clause if needed. */
1306 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1307 free(nalu);
1308 return r;
1309 }
1310
1311 if (!bc->cf_last->curr_bs_head) {
1312 bc->cf_last->curr_bs_head = nalu;
1313 }
1314 /* number of gpr == the last gpr used in any alu */
1315 for (i = 0; i < 3; i++) {
1316 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1317 bc->ngpr = nalu->src[i].sel + 1;
1318 }
1319 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1320 r600_bytecode_special_constants(nalu->src[i].value,
1321 &nalu->src[i].sel, &nalu->src[i].neg);
1322 }
1323 if (nalu->dst.sel >= bc->ngpr) {
1324 bc->ngpr = nalu->dst.sel + 1;
1325 }
1326 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1327 /* each alu use 2 dwords */
1328 bc->cf_last->ndw += 2;
1329 bc->ndw += 2;
1330
1331 /* process cur ALU instructions for bank swizzle */
1332 if (nalu->last) {
1333 uint32_t literal[4];
1334 unsigned nliteral;
1335 struct r600_bytecode_alu *slots[5];
1336 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1337 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1338 if (r)
1339 return r;
1340
1341 if (bc->cf_last->prev_bs_head) {
1342 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1343 if (r)
1344 return r;
1345 }
1346
1347 if (bc->cf_last->prev_bs_head) {
1348 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1349 if (r)
1350 return r;
1351 }
1352
1353 r = check_and_set_bank_swizzle(bc, slots);
1354 if (r)
1355 return r;
1356
1357 for (i = 0, nliteral = 0; i < max_slots; i++) {
1358 if (slots[i]) {
1359 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1360 if (r)
1361 return r;
1362 }
1363 }
1364 bc->cf_last->ndw += align(nliteral, 2);
1365
1366 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1367 * worst case */
1368 if ((bc->cf_last->ndw >> 1) >= 120) {
1369 bc->force_add_cf = 1;
1370 }
1371
1372 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1373 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1374 bc->cf_last->curr_bs_head = NULL;
1375 }
1376 return 0;
1377 }
1378
1379 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1380 {
1381 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1382 }
1383
1384 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1385 {
1386 switch (bc->chip_class) {
1387 case R600:
1388 return 8;
1389
1390 case R700:
1391 case EVERGREEN:
1392 case CAYMAN:
1393 return 16;
1394
1395 default:
1396 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1397 return 8;
1398 }
1399 }
1400
1401 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1402 {
1403 switch (bc->chip_class) {
1404 case R700:
1405 case R600:
1406 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1407 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1408 case EVERGREEN:
1409 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1410 case CAYMAN:
1411 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1412 default:
1413 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1414 return FALSE;
1415 }
1416 }
1417
1418 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1419 {
1420 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1421 int r;
1422
1423 if (nvtx == NULL)
1424 return -ENOMEM;
1425 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1426
1427 /* cf can contains only alu or only vtx or only tex */
1428 if (bc->cf_last == NULL ||
1429 last_inst_was_not_vtx_fetch(bc) ||
1430 bc->force_add_cf) {
1431 r = r600_bytecode_add_cf(bc);
1432 if (r) {
1433 free(nvtx);
1434 return r;
1435 }
1436 switch (bc->chip_class) {
1437 case R600:
1438 case R700:
1439 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1440 break;
1441 case EVERGREEN:
1442 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1443 break;
1444 case CAYMAN:
1445 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1446 break;
1447 default:
1448 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1449 return -EINVAL;
1450 }
1451 }
1452 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1453 /* each fetch use 4 dwords */
1454 bc->cf_last->ndw += 4;
1455 bc->ndw += 4;
1456 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1457 bc->force_add_cf = 1;
1458 return 0;
1459 }
1460
1461 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1462 {
1463 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1464 int r;
1465
1466 if (ntex == NULL)
1467 return -ENOMEM;
1468 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1469
1470 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1471 if (bc->cf_last != NULL &&
1472 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1473 struct r600_bytecode_tex *ttex;
1474 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1475 if (ttex->dst_gpr == ntex->src_gpr) {
1476 bc->force_add_cf = 1;
1477 break;
1478 }
1479 }
1480 /* slight hack to make gradients always go into same cf */
1481 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1482 bc->force_add_cf = 1;
1483 }
1484
1485 /* cf can contains only alu or only vtx or only tex */
1486 if (bc->cf_last == NULL ||
1487 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1488 bc->force_add_cf) {
1489 r = r600_bytecode_add_cf(bc);
1490 if (r) {
1491 free(ntex);
1492 return r;
1493 }
1494 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1495 }
1496 if (ntex->src_gpr >= bc->ngpr) {
1497 bc->ngpr = ntex->src_gpr + 1;
1498 }
1499 if (ntex->dst_gpr >= bc->ngpr) {
1500 bc->ngpr = ntex->dst_gpr + 1;
1501 }
1502 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1503 /* each texture fetch use 4 dwords */
1504 bc->cf_last->ndw += 4;
1505 bc->ndw += 4;
1506 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1507 bc->force_add_cf = 1;
1508 return 0;
1509 }
1510
1511 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1512 {
1513 int r;
1514 r = r600_bytecode_add_cf(bc);
1515 if (r)
1516 return r;
1517
1518 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1519 bc->cf_last->inst = inst;
1520 return 0;
1521 }
1522
1523 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1524 {
1525 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1526 }
1527
1528 /* common to all 3 families */
1529 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1530 {
1531 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1532 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1533 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1534 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1535 if (bc->chip_class < CAYMAN)
1536 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1537 id++;
1538 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1539 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1540 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1541 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1542 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1543 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1544 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1545 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1546 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1547 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1548 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1549 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1550 if (bc->chip_class < CAYMAN)
1551 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1552 id++;
1553 bc->bytecode[id++] = 0;
1554 return 0;
1555 }
1556
1557 /* common to all 3 families */
1558 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1559 {
1560 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1561 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1562 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1563 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1564 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1565 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1566 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1567 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1568 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1569 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1570 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1571 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1572 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1573 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1574 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1575 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1576 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1577 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1578 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1579 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1580 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1581 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1582 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1583 bc->bytecode[id++] = 0;
1584 return 0;
1585 }
1586
1587 /* r600 only, r700/eg bits in r700_asm.c */
1588 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1589 {
1590 /* don't replace gpr by pv or ps for destination register */
1591 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1592 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1593 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1594 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1595 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1596 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1597 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1598 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1599 S_SQ_ALU_WORD0_LAST(alu->last);
1600
1601 if (alu->is_op3) {
1602 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1603 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1604 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1605 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1606 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1607 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1608 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1609 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1610 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1611 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1612 } else {
1613 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1614 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1615 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1616 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1617 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1618 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1619 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1620 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1621 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1622 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1623 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1624 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1625 }
1626 return 0;
1627 }
1628
1629 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1630 {
1631 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1632 *bytecode++ = cf->inst |
1633 S_SQ_CF_WORD1_BARRIER(1) |
1634 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1635 }
1636
1637 /* common for r600/r700 - eg in eg_asm.c */
1638 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1639 {
1640 unsigned id = cf->id;
1641
1642 switch (cf->inst) {
1643 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1644 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1645 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1646 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1647 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1648 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1649 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1650 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1651
1652 bc->bytecode[id++] = cf->inst |
1653 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1654 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1655 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1656 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1657 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1658 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1659 break;
1660 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1661 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1662 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1663 if (bc->chip_class == R700)
1664 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1665 else
1666 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1667 break;
1668 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1669 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1670 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1671 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1672 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1673 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1674 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1675 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1676 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1677 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1678 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1679 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1680 cf->output.inst |
1681 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1682 break;
1683 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1684 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1685 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1686 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1687 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1688 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1689 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1690 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1691 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1692 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1693 cf->output.inst |
1694 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1695 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1696 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1697 break;
1698 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1699 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1700 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1701 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1702 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1703 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1704 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1705 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1706 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1707 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1708 bc->bytecode[id++] = cf->inst |
1709 S_SQ_CF_WORD1_BARRIER(1) |
1710 S_SQ_CF_WORD1_COND(cf->cond) |
1711 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1712
1713 break;
1714 default:
1715 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1716 return -EINVAL;
1717 }
1718 return 0;
1719 }
1720
1721 int r600_bytecode_build(struct r600_bytecode *bc)
1722 {
1723 struct r600_bytecode_cf *cf;
1724 struct r600_bytecode_alu *alu;
1725 struct r600_bytecode_vtx *vtx;
1726 struct r600_bytecode_tex *tex;
1727 uint32_t literal[4];
1728 unsigned nliteral;
1729 unsigned addr;
1730 int i, r;
1731
1732 if (bc->callstack[0].max > 0)
1733 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1734 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1735 bc->nstack = 1;
1736 }
1737
1738 /* first path compute addr of each CF block */
1739 /* addr start after all the CF instructions */
1740 addr = bc->cf_last->id + 2;
1741 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1742 if (bc->chip_class >= EVERGREEN) {
1743 switch (cf->inst) {
1744 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1745 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1746 /* fetch node need to be 16 bytes aligned*/
1747 addr += 3;
1748 addr &= 0xFFFFFFFCUL;
1749 break;
1750 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1751 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1752 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1753 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1754 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1755 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1756 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1757 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1758 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1759 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1760 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1761 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1762 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1763 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1764 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1765 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1766 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1767 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1768 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1769 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1770 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1771 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1772 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1773 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1774 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1775 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1776 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1777 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1778 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1779 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1780 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1781 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1782 break;
1783 default:
1784 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1785 return -EINVAL;
1786 }
1787 } else {
1788 switch (cf->inst) {
1789 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1790 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1791 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1792 /* fetch node need to be 16 bytes aligned*/
1793 addr += 3;
1794 addr &= 0xFFFFFFFCUL;
1795 break;
1796 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1797 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1798 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1799 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1800 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1801 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1802 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1803 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1804 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1805 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1806 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1807 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1808 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1809 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1810 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1811 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1812 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1813 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1814 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1815 break;
1816 default:
1817 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1818 return -EINVAL;
1819 }
1820 }
1821 cf->addr = addr;
1822 addr += cf->ndw;
1823 bc->ndw = cf->addr + cf->ndw;
1824 }
1825 free(bc->bytecode);
1826 bc->bytecode = calloc(1, bc->ndw * 4);
1827 if (bc->bytecode == NULL)
1828 return -ENOMEM;
1829 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1830 addr = cf->addr;
1831 if (bc->chip_class >= EVERGREEN) {
1832 r = eg_bytecode_cf_build(bc, cf);
1833 if (r)
1834 return r;
1835
1836 switch (cf->inst) {
1837 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1838 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1839 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1840 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1841 nliteral = 0;
1842 memset(literal, 0, sizeof(literal));
1843 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1844 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1845 if (r)
1846 return r;
1847 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1848 switch(bc->chip_class) {
1849 case EVERGREEN: /* eg alu is same encoding as r700 */
1850 case CAYMAN:
1851 r = r700_bytecode_alu_build(bc, alu, addr);
1852 break;
1853 default:
1854 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1855 return -EINVAL;
1856 }
1857 if (r)
1858 return r;
1859 addr += 2;
1860 if (alu->last) {
1861 for (i = 0; i < align(nliteral, 2); ++i) {
1862 bc->bytecode[addr++] = literal[i];
1863 }
1864 nliteral = 0;
1865 memset(literal, 0, sizeof(literal));
1866 }
1867 }
1868 break;
1869 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1870 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1871 r = r600_bytecode_vtx_build(bc, vtx, addr);
1872 if (r)
1873 return r;
1874 addr += 4;
1875 }
1876 break;
1877 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1878 if (bc->chip_class == CAYMAN) {
1879 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1880 r = r600_bytecode_vtx_build(bc, vtx, addr);
1881 if (r)
1882 return r;
1883 addr += 4;
1884 }
1885 }
1886 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1887 r = r600_bytecode_tex_build(bc, tex, addr);
1888 if (r)
1889 return r;
1890 addr += 4;
1891 }
1892 break;
1893 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1894 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1895 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1896 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1897 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1898 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1899 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1900 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1901 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1902 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1903 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1904 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1905 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1906 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1907 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1908 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1909 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1910 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1911 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1912 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1913 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1914 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1915 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1916 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1917 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1918 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1919 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1920 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1921 break;
1922 default:
1923 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1924 return -EINVAL;
1925 }
1926 } else {
1927 r = r600_bytecode_cf_build(bc, cf);
1928 if (r)
1929 return r;
1930
1931 switch (cf->inst) {
1932 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1933 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1934 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1935 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1936 nliteral = 0;
1937 memset(literal, 0, sizeof(literal));
1938 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1939 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1940 if (r)
1941 return r;
1942 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1943 switch(bc->chip_class) {
1944 case R600:
1945 r = r600_bytecode_alu_build(bc, alu, addr);
1946 break;
1947 case R700:
1948 r = r700_bytecode_alu_build(bc, alu, addr);
1949 break;
1950 default:
1951 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1952 return -EINVAL;
1953 }
1954 if (r)
1955 return r;
1956 addr += 2;
1957 if (alu->last) {
1958 for (i = 0; i < align(nliteral, 2); ++i) {
1959 bc->bytecode[addr++] = literal[i];
1960 }
1961 nliteral = 0;
1962 memset(literal, 0, sizeof(literal));
1963 }
1964 }
1965 break;
1966 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1967 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1968 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1969 r = r600_bytecode_vtx_build(bc, vtx, addr);
1970 if (r)
1971 return r;
1972 addr += 4;
1973 }
1974 break;
1975 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1976 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1977 r = r600_bytecode_tex_build(bc, tex, addr);
1978 if (r)
1979 return r;
1980 addr += 4;
1981 }
1982 break;
1983 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1984 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1985 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1986 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1987 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1988 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1989 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1990 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1991 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1992 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1993 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1994 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1995 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1996 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1997 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1998 break;
1999 default:
2000 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2001 return -EINVAL;
2002 }
2003 }
2004 }
2005 return 0;
2006 }
2007
2008 void r600_bytecode_clear(struct r600_bytecode *bc)
2009 {
2010 struct r600_bytecode_cf *cf = NULL, *next_cf;
2011
2012 free(bc->bytecode);
2013 bc->bytecode = NULL;
2014
2015 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2016 struct r600_bytecode_alu *alu = NULL, *next_alu;
2017 struct r600_bytecode_tex *tex = NULL, *next_tex;
2018 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2019
2020 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2021 free(alu);
2022 }
2023
2024 LIST_INITHEAD(&cf->alu);
2025
2026 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2027 free(tex);
2028 }
2029
2030 LIST_INITHEAD(&cf->tex);
2031
2032 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2033 free(vtx);
2034 }
2035
2036 LIST_INITHEAD(&cf->vtx);
2037
2038 free(cf);
2039 }
2040
2041 LIST_INITHEAD(&cf->list);
2042 }
2043
2044 void r600_bytecode_dump(struct r600_bytecode *bc)
2045 {
2046 struct r600_bytecode_cf *cf = NULL;
2047 struct r600_bytecode_alu *alu = NULL;
2048 struct r600_bytecode_vtx *vtx = NULL;
2049 struct r600_bytecode_tex *tex = NULL;
2050
2051 unsigned i, id;
2052 uint32_t literal[4];
2053 unsigned nliteral;
2054 char chip = '6';
2055
2056 switch (bc->chip_class) {
2057 case R700:
2058 chip = '7';
2059 break;
2060 case EVERGREEN:
2061 chip = 'E';
2062 break;
2063 case CAYMAN:
2064 chip = 'C';
2065 break;
2066 case R600:
2067 default:
2068 chip = '6';
2069 break;
2070 }
2071 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2072 fprintf(stderr, " %c\n", chip);
2073
2074 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2075 id = cf->id;
2076
2077 if (bc->chip_class >= EVERGREEN) {
2078 switch (cf->inst) {
2079 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2080 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2081 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2082 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2083 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2084 fprintf(stderr, "ADDR:%d ", cf->addr);
2085 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2086 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2087 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2088 id++;
2089 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2090 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2091 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2092 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2093 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2094 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2095 break;
2096 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2097 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2098 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2099 fprintf(stderr, "ADDR:%d\n", cf->addr);
2100 id++;
2101 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2102 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2103 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2104 break;
2105 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2106 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2107 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2108 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2109 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2110 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2111 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2112 id++;
2113 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2114 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2115 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2116 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2117 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2118 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2119 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2120 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2121 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2122 break;
2123 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2124 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2125 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2126 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2127 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2128 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2129 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2130 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2131 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2132 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2133 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2134 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2135 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2136 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2137 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2138 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2139 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2140 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2141 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2142 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2143 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2144 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2145 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2146 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2147 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2148 id++;
2149 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2150 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2151 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2152 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2153 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2154 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2155 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2156 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2157 fprintf(stderr, "INST:%d ", cf->output.inst);
2158 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2159 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2160 break;
2161 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2162 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2163 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2164 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2165 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2166 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2167 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2168 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2169 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2170 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2171 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2172 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2173 id++;
2174 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2175 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2176 fprintf(stderr, "COND:%X ", cf->cond);
2177 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2178 break;
2179 default:
2180 R600_ERR("Unknown instruction %0x\n", cf->inst);
2181 }
2182 } else {
2183 switch (cf->inst) {
2184 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2185 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2186 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2187 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2188 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2189 fprintf(stderr, "ADDR:%d ", cf->addr);
2190 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2191 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2192 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2193 id++;
2194 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2195 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2196 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2197 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2198 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2199 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2200 break;
2201 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2202 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2203 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2204 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2205 fprintf(stderr, "ADDR:%d\n", cf->addr);
2206 id++;
2207 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2208 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2209 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2210 break;
2211 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2212 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2213 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2214 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2215 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2216 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2217 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2218 id++;
2219 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2220 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2221 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2222 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2223 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2224 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2225 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2226 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2227 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2228 break;
2229 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2230 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2231 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2232 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2233 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2234 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2235 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2236 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2237 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2238 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2239 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2240 id++;
2241 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2242 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2243 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2244 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2245 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2246 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2247 fprintf(stderr, "INST:%d ", cf->output.inst);
2248 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2249 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2250 break;
2251 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2252 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2253 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2254 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2255 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2256 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2257 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2258 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2259 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2260 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2261 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2262 id++;
2263 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2264 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2265 fprintf(stderr, "COND:%X ", cf->cond);
2266 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2267 break;
2268 default:
2269 R600_ERR("Unknown instruction %0x\n", cf->inst);
2270 }
2271 }
2272
2273 id = cf->addr;
2274 nliteral = 0;
2275 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2276 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2277
2278 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2279 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2280 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2281 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2282 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2283 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2284 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2285 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2286 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
2287 fprintf(stderr, "LAST:%d)\n", alu->last);
2288 id++;
2289 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2290 fprintf(stderr, "INST:0x%x ", alu->inst);
2291 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2292 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2293 fprintf(stderr, "REL:%d ", alu->dst.rel);
2294 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2295 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2296 if (alu->is_op3) {
2297 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2298 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2299 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2300 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2301 } else {
2302 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2303 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2304 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2305 fprintf(stderr, "OMOD:%d ", alu->omod);
2306 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
2307 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
2308 }
2309
2310 id++;
2311 if (alu->last) {
2312 for (i = 0; i < nliteral; i++, id++) {
2313 float *f = (float*)(bc->bytecode + id);
2314 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
2315 }
2316 id += nliteral & 1;
2317 nliteral = 0;
2318 }
2319 }
2320
2321 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2322 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2323 fprintf(stderr, "INST:0x%x ", tex->inst);
2324 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2325 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2326 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2327 id++;
2328 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2329 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2330 fprintf(stderr, "REL:%d ", tex->dst_rel);
2331 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2332 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2333 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2334 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2335 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2336 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2337 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2338 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2339 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2340 id++;
2341 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2342 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2343 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2344 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2345 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2346 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2347 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2348 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2349 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2350 id++;
2351 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2352 id++;
2353 }
2354
2355 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2356 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2357 fprintf(stderr, "INST:%d ", vtx->inst);
2358 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2359 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2360 id++;
2361 /* This assumes that no semantic fetches exist */
2362 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2363 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2364 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2365 if (bc->chip_class < CAYMAN)
2366 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2367 else
2368 fprintf(stderr, "SEL_Y:%d) ", 0);
2369 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2370 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2371 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2372 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2373 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2374 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2375 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2376 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2377 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2378 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2379 id++;
2380 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2381 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2382 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2383 /* TODO */
2384 id++;
2385 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2386 id++;
2387 }
2388 }
2389
2390 fprintf(stderr, "--------------------------------------\n");
2391 }
2392
2393 static void r600_vertex_data_type(enum pipe_format pformat,
2394 unsigned *format,
2395 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2396 {
2397 const struct util_format_description *desc;
2398 unsigned i;
2399
2400 *format = 0;
2401 *num_format = 0;
2402 *format_comp = 0;
2403 *endian = ENDIAN_NONE;
2404
2405 desc = util_format_description(pformat);
2406 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2407 goto out_unknown;
2408 }
2409
2410 /* Find the first non-VOID channel. */
2411 for (i = 0; i < 4; i++) {
2412 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2413 break;
2414 }
2415 }
2416
2417 *endian = r600_endian_swap(desc->channel[i].size);
2418
2419 switch (desc->channel[i].type) {
2420 /* Half-floats, floats, ints */
2421 case UTIL_FORMAT_TYPE_FLOAT:
2422 switch (desc->channel[i].size) {
2423 case 16:
2424 switch (desc->nr_channels) {
2425 case 1:
2426 *format = FMT_16_FLOAT;
2427 break;
2428 case 2:
2429 *format = FMT_16_16_FLOAT;
2430 break;
2431 case 3:
2432 case 4:
2433 *format = FMT_16_16_16_16_FLOAT;
2434 break;
2435 }
2436 break;
2437 case 32:
2438 switch (desc->nr_channels) {
2439 case 1:
2440 *format = FMT_32_FLOAT;
2441 break;
2442 case 2:
2443 *format = FMT_32_32_FLOAT;
2444 break;
2445 case 3:
2446 *format = FMT_32_32_32_FLOAT;
2447 break;
2448 case 4:
2449 *format = FMT_32_32_32_32_FLOAT;
2450 break;
2451 }
2452 break;
2453 default:
2454 goto out_unknown;
2455 }
2456 break;
2457 /* Unsigned ints */
2458 case UTIL_FORMAT_TYPE_UNSIGNED:
2459 /* Signed ints */
2460 case UTIL_FORMAT_TYPE_SIGNED:
2461 switch (desc->channel[i].size) {
2462 case 8:
2463 switch (desc->nr_channels) {
2464 case 1:
2465 *format = FMT_8;
2466 break;
2467 case 2:
2468 *format = FMT_8_8;
2469 break;
2470 case 3:
2471 case 4:
2472 *format = FMT_8_8_8_8;
2473 break;
2474 }
2475 break;
2476 case 10:
2477 if (desc->nr_channels != 4)
2478 goto out_unknown;
2479
2480 *format = FMT_2_10_10_10;
2481 break;
2482 case 16:
2483 switch (desc->nr_channels) {
2484 case 1:
2485 *format = FMT_16;
2486 break;
2487 case 2:
2488 *format = FMT_16_16;
2489 break;
2490 case 3:
2491 case 4:
2492 *format = FMT_16_16_16_16;
2493 break;
2494 }
2495 break;
2496 case 32:
2497 switch (desc->nr_channels) {
2498 case 1:
2499 *format = FMT_32;
2500 break;
2501 case 2:
2502 *format = FMT_32_32;
2503 break;
2504 case 3:
2505 *format = FMT_32_32_32;
2506 break;
2507 case 4:
2508 *format = FMT_32_32_32_32;
2509 break;
2510 }
2511 break;
2512 default:
2513 goto out_unknown;
2514 }
2515 break;
2516 default:
2517 goto out_unknown;
2518 }
2519
2520 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2521 *format_comp = 1;
2522 }
2523
2524 *num_format = 0;
2525 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2526 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2527 if (!desc->channel[i].normalized) {
2528 if (desc->channel[i].pure_integer)
2529 *num_format = 1;
2530 else
2531 *num_format = 2;
2532 }
2533 }
2534 return;
2535 out_unknown:
2536 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2537 }
2538
2539 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2540 {
2541 static int dump_shaders = -1;
2542
2543 struct r600_bytecode bc;
2544 struct r600_bytecode_vtx vtx;
2545 struct pipe_vertex_element *elements = ve->elements;
2546 const struct util_format_description *desc;
2547 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2548 unsigned format, num_format, format_comp, endian;
2549 u32 *bytecode;
2550 int i, r;
2551
2552 /* Vertex element offsets need special handling. If the offset is
2553 * bigger than what we can put in the fetch instruction we need to
2554 * alter the vertex resource offset. In order to simplify code we
2555 * will bind one resource per element in such cases. It's a worst
2556 * case scenario. */
2557 for (i = 0; i < ve->count; i++) {
2558 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2559 if (ve->vbuffer_offset[i]) {
2560 ve->vbuffer_need_offset = 1;
2561 }
2562 }
2563
2564 memset(&bc, 0, sizeof(bc));
2565 r600_bytecode_init(&bc, rctx->chip_class);
2566
2567 for (i = 0; i < ve->count; i++) {
2568 if (elements[i].instance_divisor > 1) {
2569 struct r600_bytecode_alu alu;
2570
2571 memset(&alu, 0, sizeof(alu));
2572 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2573 alu.src[0].sel = 0;
2574 alu.src[0].chan = 3;
2575
2576 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2577 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2578
2579 alu.dst.sel = i + 1;
2580 alu.dst.chan = 3;
2581 alu.dst.write = 1;
2582 alu.last = 1;
2583
2584 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2585 r600_bytecode_clear(&bc);
2586 return r;
2587 }
2588 }
2589 }
2590
2591 for (i = 0; i < ve->count; i++) {
2592 unsigned vbuffer_index;
2593 r600_vertex_data_type(ve->elements[i].src_format,
2594 &format, &num_format, &format_comp, &endian);
2595 desc = util_format_description(ve->elements[i].src_format);
2596 if (desc == NULL) {
2597 r600_bytecode_clear(&bc);
2598 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2599 return -EINVAL;
2600 }
2601
2602 /* see above for vbuffer_need_offset explanation */
2603 vbuffer_index = elements[i].vertex_buffer_index;
2604 memset(&vtx, 0, sizeof(vtx));
2605 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2606 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2607 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2608 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2609 vtx.mega_fetch_count = 0x1F;
2610 vtx.dst_gpr = i + 1;
2611 vtx.dst_sel_x = desc->swizzle[0];
2612 vtx.dst_sel_y = desc->swizzle[1];
2613 vtx.dst_sel_z = desc->swizzle[2];
2614 vtx.dst_sel_w = desc->swizzle[3];
2615 vtx.data_format = format;
2616 vtx.num_format_all = num_format;
2617 vtx.format_comp_all = format_comp;
2618 vtx.srf_mode_all = 1;
2619 vtx.offset = elements[i].src_offset;
2620 vtx.endian = endian;
2621
2622 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2623 r600_bytecode_clear(&bc);
2624 return r;
2625 }
2626 }
2627
2628 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2629
2630 if ((r = r600_bytecode_build(&bc))) {
2631 r600_bytecode_clear(&bc);
2632 return r;
2633 }
2634
2635 if (dump_shaders == -1)
2636 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2637
2638 if (dump_shaders) {
2639 fprintf(stderr, "--------------------------------------------------------------\n");
2640 r600_bytecode_dump(&bc);
2641 fprintf(stderr, "______________________________________________________________\n");
2642 }
2643
2644 ve->fs_size = bc.ndw*4;
2645
2646 ve->fetch_shader = (struct r600_resource*)
2647 pipe_buffer_create(rctx->context.screen,
2648 PIPE_BIND_CUSTOM,
2649 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2650 if (ve->fetch_shader == NULL) {
2651 r600_bytecode_clear(&bc);
2652 return -ENOMEM;
2653 }
2654
2655 bytecode = rctx->ws->buffer_map(ve->fetch_shader->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
2656 if (bytecode == NULL) {
2657 r600_bytecode_clear(&bc);
2658 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2659 return -ENOMEM;
2660 }
2661
2662 if (R600_BIG_ENDIAN) {
2663 for (i = 0; i < ve->fs_size / 4; ++i) {
2664 bytecode[i] = bswap_32(bc.bytecode[i]);
2665 }
2666 } else {
2667 memcpy(bytecode, bc.bytecode, ve->fs_size);
2668 }
2669
2670 rctx->ws->buffer_unmap(ve->fetch_shader->buf);
2671 r600_bytecode_clear(&bc);
2672
2673 if (rctx->chip_class >= EVERGREEN)
2674 evergreen_fetch_shader(&rctx->context, ve);
2675 else
2676 r600_fetch_shader(&rctx->context, ve);
2677
2678 return 0;
2679 }