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r600g: fix vertex format fallback
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
39 {
40 if(alu->is_op3)
41 return 3;
42
43 switch (bc->chiprev) {
44 case CHIPREV_R600:
45 case CHIPREV_R700:
46 switch (alu->inst) {
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
48 return 0;
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
68 return 2;
69
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
87 return 1;
88 default: R600_ERR(
89 "Need instruction operand number for 0x%x.\n", alu->inst);
90 }
91 break;
92 case CHIPREV_EVERGREEN:
93 switch (alu->inst) {
94 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
95 return 0;
96 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
97 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
98 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
99 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
100 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
101 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
103 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
117 return 2;
118
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
135 return 1;
136 default: R600_ERR(
137 "Need instruction operand number for 0x%x.\n", alu->inst);
138 }
139 break;
140 }
141
142 return 3;
143 }
144
145 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
146
147 static struct r600_bc_cf *r600_bc_cf(void)
148 {
149 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
150
151 if (cf == NULL)
152 return NULL;
153 LIST_INITHEAD(&cf->list);
154 LIST_INITHEAD(&cf->alu);
155 LIST_INITHEAD(&cf->vtx);
156 LIST_INITHEAD(&cf->tex);
157 return cf;
158 }
159
160 static struct r600_bc_alu *r600_bc_alu(void)
161 {
162 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
163
164 if (alu == NULL)
165 return NULL;
166 LIST_INITHEAD(&alu->list);
167 return alu;
168 }
169
170 static struct r600_bc_vtx *r600_bc_vtx(void)
171 {
172 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
173
174 if (vtx == NULL)
175 return NULL;
176 LIST_INITHEAD(&vtx->list);
177 return vtx;
178 }
179
180 static struct r600_bc_tex *r600_bc_tex(void)
181 {
182 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
183
184 if (tex == NULL)
185 return NULL;
186 LIST_INITHEAD(&tex->list);
187 return tex;
188 }
189
190 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
191 {
192 LIST_INITHEAD(&bc->cf);
193 bc->family = family;
194 switch (bc->family) {
195 case CHIP_R600:
196 case CHIP_RV610:
197 case CHIP_RV630:
198 case CHIP_RV670:
199 case CHIP_RV620:
200 case CHIP_RV635:
201 case CHIP_RS780:
202 case CHIP_RS880:
203 bc->chiprev = CHIPREV_R600;
204 break;
205 case CHIP_RV770:
206 case CHIP_RV730:
207 case CHIP_RV710:
208 case CHIP_RV740:
209 bc->chiprev = CHIPREV_R700;
210 break;
211 case CHIP_CEDAR:
212 case CHIP_REDWOOD:
213 case CHIP_JUNIPER:
214 case CHIP_CYPRESS:
215 case CHIP_HEMLOCK:
216 case CHIP_PALM:
217 case CHIP_BARTS:
218 case CHIP_TURKS:
219 case CHIP_CAICOS:
220 bc->chiprev = CHIPREV_EVERGREEN;
221 break;
222 default:
223 R600_ERR("unknown family %d\n", bc->family);
224 return -EINVAL;
225 }
226 return 0;
227 }
228
229 static int r600_bc_add_cf(struct r600_bc *bc)
230 {
231 struct r600_bc_cf *cf = r600_bc_cf();
232
233 if (cf == NULL)
234 return -ENOMEM;
235 LIST_ADDTAIL(&cf->list, &bc->cf);
236 if (bc->cf_last)
237 cf->id = bc->cf_last->id + 2;
238 bc->cf_last = cf;
239 bc->ncf++;
240 bc->ndw += 2;
241 bc->force_add_cf = 0;
242 return 0;
243 }
244
245 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
246 {
247 int r;
248
249 r = r600_bc_add_cf(bc);
250 if (r)
251 return r;
252 bc->cf_last->inst = output->inst;
253 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
254 return 0;
255 }
256
257 /* alu instructions that can ony exits once per group */
258 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
259 {
260 switch (bc->chiprev) {
261 case CHIPREV_R600:
262 case CHIPREV_R700:
263 return !alu->is_op3 && (
264 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
265 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
266 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
267 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
268 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
269 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
270 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
271 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
272 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
273 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
274 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
275 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
276 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
277 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
278 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
279 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
280 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
281 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
282 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
283 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
284 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
285 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
286 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
287 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
288 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
289 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
290 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
291 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
292 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
293 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
294 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
295 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
296 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
297 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
298 case CHIPREV_EVERGREEN:
299 default:
300 return !alu->is_op3 && (
301 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
302 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
303 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
304 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
305 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
306 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
307 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
308 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
309 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
310 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
311 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
312 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
313 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
314 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
315 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
316 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
317 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
318 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
319 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
320 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
321 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
322 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
323 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
324 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
325 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
326 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
327 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
328 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
329 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
330 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
331 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
332 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
333 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
334 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
335 }
336 }
337
338 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
339 {
340 switch (bc->chiprev) {
341 case CHIPREV_R600:
342 case CHIPREV_R700:
343 return !alu->is_op3 && (
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
348 case CHIPREV_EVERGREEN:
349 default:
350 return !alu->is_op3 && (
351 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
352 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
353 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
354 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
355 }
356 }
357
358 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
359 {
360 switch (bc->chiprev) {
361 case CHIPREV_R600:
362 case CHIPREV_R700:
363 return !alu->is_op3 && (
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
367 case CHIPREV_EVERGREEN:
368 default:
369 return !alu->is_op3 && (
370 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
371 }
372 }
373
374 /* alu instructions that can only execute on the vector unit */
375 static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
376 {
377 return is_alu_reduction_inst(bc, alu) ||
378 is_alu_mova_inst(bc, alu);
379 }
380
381 /* alu instructions that can only execute on the trans unit */
382 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
383 {
384 switch (bc->chiprev) {
385 case CHIPREV_R600:
386 case CHIPREV_R700:
387 if (!alu->is_op3)
388 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
389 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
390 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
391 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
392 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
393 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
394 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
395 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
396 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
397 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
398 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
399 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
400 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
401 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
402 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
403 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
404 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
405 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
406 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
407 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
408 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
409 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
410 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
411 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
412 else
413 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
414 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
415 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
416 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
417 case CHIPREV_EVERGREEN:
418 default:
419 if (!alu->is_op3)
420 /* Note that FLT_TO_INT* instructions are vector instructions
421 * on Evergreen, despite what the documentation says. */
422 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
423 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
424 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
425 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
426 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
427 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
428 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
429 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
430 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
431 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
433 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
434 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
435 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
436 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
437 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
438 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
439 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
440 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
441 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
442 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
443 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
444 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
445 else
446 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
447 }
448 }
449
450 /* alu instructions that can execute on any unit */
451 static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
452 {
453 return !is_alu_vec_unit_inst(bc, alu) &&
454 !is_alu_trans_unit_inst(bc, alu);
455 }
456
457 static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
458 struct r600_bc_alu *assignment[5])
459 {
460 struct r600_bc_alu *alu;
461 unsigned i, chan, trans;
462
463 for (i = 0; i < 5; i++)
464 assignment[i] = NULL;
465
466 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
467 chan = alu->dst.chan;
468 if (is_alu_trans_unit_inst(bc, alu))
469 trans = 1;
470 else if (is_alu_vec_unit_inst(bc, alu))
471 trans = 0;
472 else if (assignment[chan])
473 trans = 1; // assume ALU_INST_PREFER_VECTOR
474 else
475 trans = 0;
476
477 if (trans) {
478 if (assignment[4]) {
479 assert(0); //ALU.Trans has already been allocated
480 return -1;
481 }
482 assignment[4] = alu;
483 } else {
484 if (assignment[chan]) {
485 assert(0); //ALU.chan has already been allocated
486 return -1;
487 }
488 assignment[chan] = alu;
489 }
490
491 if (alu->last)
492 break;
493 }
494 return 0;
495 }
496
497 struct alu_bank_swizzle {
498 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
499 int hw_cfile_addr[4];
500 int hw_cfile_elem[4];
501 };
502
503 const unsigned cycle_for_bank_swizzle_vec[][3] = {
504 [SQ_ALU_VEC_012] = { 0, 1, 2 },
505 [SQ_ALU_VEC_021] = { 0, 2, 1 },
506 [SQ_ALU_VEC_120] = { 1, 2, 0 },
507 [SQ_ALU_VEC_102] = { 1, 0, 2 },
508 [SQ_ALU_VEC_201] = { 2, 0, 1 },
509 [SQ_ALU_VEC_210] = { 2, 1, 0 }
510 };
511
512 const unsigned cycle_for_bank_swizzle_scl[][3] = {
513 [SQ_ALU_SCL_210] = { 2, 1, 0 },
514 [SQ_ALU_SCL_122] = { 1, 2, 2 },
515 [SQ_ALU_SCL_212] = { 2, 1, 2 },
516 [SQ_ALU_SCL_221] = { 2, 2, 1 }
517 };
518
519 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
520 {
521 int i, cycle, component;
522 /* set up gpr use */
523 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
524 for (component = 0; component < NUM_OF_COMPONENTS; component++)
525 bs->hw_gpr[cycle][component] = -1;
526 for (i = 0; i < 4; i++)
527 bs->hw_cfile_addr[i] = -1;
528 for (i = 0; i < 4; i++)
529 bs->hw_cfile_elem[i] = -1;
530 }
531
532 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
533 {
534 if (bs->hw_gpr[cycle][chan] == -1)
535 bs->hw_gpr[cycle][chan] = sel;
536 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
537 // Another scalar operation has already used GPR read port for channel
538 return -1;
539 }
540 return 0;
541 }
542
543 static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
544 {
545 int res, num_res = 4;
546 if (bc->chiprev >= CHIPREV_R700) {
547 num_res = 2;
548 chan /= 2;
549 }
550 for (res = 0; res < num_res; ++res) {
551 if (bs->hw_cfile_addr[res] == -1) {
552 bs->hw_cfile_addr[res] = sel;
553 bs->hw_cfile_elem[res] = chan;
554 return 0;
555 } else if (bs->hw_cfile_addr[res] == sel &&
556 bs->hw_cfile_elem[res] == chan)
557 return 0; // Read for this scalar element already reserved, nothing to do here.
558 }
559 // All cfile read ports are used, cannot reference vector element
560 return -1;
561 }
562
563 static int is_gpr(unsigned sel)
564 {
565 return (sel >= 0 && sel <= 127);
566 }
567
568 /* CB constants start at 512, and get translated to a kcache index when ALU
569 * clauses are constructed. Note that we handle kcache constants the same way
570 * as (the now gone) cfile constants, is that really required? */
571 static int is_cfile(unsigned sel)
572 {
573 return (sel > 255 && sel < 512) ||
574 (sel > 511 && sel < 4607) || // Kcache before translate
575 (sel > 127 && sel < 192); // Kcache after translate
576 }
577
578 static int is_const(int sel)
579 {
580 return is_cfile(sel) ||
581 (sel >= V_SQ_ALU_SRC_0 &&
582 sel <= V_SQ_ALU_SRC_LITERAL);
583 }
584
585 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
586 struct alu_bank_swizzle *bs, int bank_swizzle)
587 {
588 int r, src, num_src, sel, elem, cycle;
589
590 num_src = r600_bc_get_num_operands(bc, alu);
591 for (src = 0; src < num_src; src++) {
592 sel = alu->src[src].sel;
593 elem = alu->src[src].chan;
594 if (is_gpr(sel)) {
595 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
596 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
597 // Nothing to do; special-case optimization,
598 // second source uses first source’s reservation
599 continue;
600 else {
601 r = reserve_gpr(bs, sel, elem, cycle);
602 if (r)
603 return r;
604 }
605 } else if (is_cfile(sel)) {
606 r = reserve_cfile(bc, bs, sel, elem);
607 if (r)
608 return r;
609 }
610 // No restrictions on PV, PS, literal or special constants
611 }
612 return 0;
613 }
614
615 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
616 struct alu_bank_swizzle *bs, int bank_swizzle)
617 {
618 int r, src, num_src, const_count, sel, elem, cycle;
619
620 num_src = r600_bc_get_num_operands(bc, alu);
621 for (const_count = 0, src = 0; src < num_src; ++src) {
622 sel = alu->src[src].sel;
623 elem = alu->src[src].chan;
624 if (is_const(sel)) { // Any constant, including literal and inline constants
625 if (const_count >= 2)
626 // More than two references to a constant in
627 // transcendental operation.
628 return -1;
629 else
630 const_count++;
631 }
632 if (is_cfile(sel)) {
633 r = reserve_cfile(bc, bs, sel, elem);
634 if (r)
635 return r;
636 }
637 }
638 for (src = 0; src < num_src; ++src) {
639 sel = alu->src[src].sel;
640 elem = alu->src[src].chan;
641 if (is_gpr(sel)) {
642 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
643 if (cycle < const_count)
644 // Cycle for GPR load conflicts with
645 // constant load in transcendental operation.
646 return -1;
647 r = reserve_gpr(bs, sel, elem, cycle);
648 if (r)
649 return r;
650 }
651 // Constants already processed
652 // No restrictions on PV, PS
653 }
654 return 0;
655 }
656
657 static int check_and_set_bank_swizzle(struct r600_bc *bc,
658 struct r600_bc_alu *slots[5])
659 {
660 struct alu_bank_swizzle bs;
661 int bank_swizzle[5];
662 int i, r = 0, forced = 0;
663
664 for (i = 0; i < 5; i++)
665 if (slots[i] && slots[i]->bank_swizzle_force) {
666 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
667 forced = 1;
668 }
669
670 if (forced)
671 return 0;
672
673 // just check every possible combination of bank swizzle
674 // not very efficent, but works on the first try in most of the cases
675 for (i = 0; i < 4; i++)
676 bank_swizzle[i] = SQ_ALU_VEC_012;
677 bank_swizzle[4] = SQ_ALU_SCL_210;
678 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
679 init_bank_swizzle(&bs);
680 for (i = 0; i < 4; i++) {
681 if (slots[i]) {
682 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
683 if (r)
684 break;
685 }
686 }
687 if (!r && slots[4]) {
688 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
689 }
690 if (!r) {
691 for (i = 0; i < 5; i++) {
692 if (slots[i])
693 slots[i]->bank_swizzle = bank_swizzle[i];
694 }
695 return 0;
696 }
697
698 for (i = 0; i < 5; i++) {
699 bank_swizzle[i]++;
700 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
701 break;
702 else
703 bank_swizzle[i] = SQ_ALU_VEC_012;
704 }
705 }
706
707 // couldn't find a working swizzle
708 return -1;
709 }
710
711 static int replace_gpr_with_pv_ps(struct r600_bc *bc,
712 struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
713 {
714 struct r600_bc_alu *prev[5];
715 int gpr[5], chan[5];
716 int i, j, r, src, num_src;
717
718 r = assign_alu_units(bc, alu_prev, prev);
719 if (r)
720 return r;
721
722 for (i = 0; i < 5; ++i) {
723 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
724 gpr[i] = prev[i]->dst.sel;
725 if (is_alu_reduction_inst(bc, prev[i]))
726 chan[i] = 0;
727 else
728 chan[i] = prev[i]->dst.chan;
729 } else
730 gpr[i] = -1;
731 }
732
733 for (i = 0; i < 5; ++i) {
734 struct r600_bc_alu *alu = slots[i];
735 if(!alu)
736 continue;
737
738 num_src = r600_bc_get_num_operands(bc, alu);
739 for (src = 0; src < num_src; ++src) {
740 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
741 continue;
742
743 if (alu->src[src].sel == gpr[4] &&
744 alu->src[src].chan == chan[4]) {
745 alu->src[src].sel = V_SQ_ALU_SRC_PS;
746 alu->src[src].chan = 0;
747 continue;
748 }
749
750 for (j = 0; j < 4; ++j) {
751 if (alu->src[src].sel == gpr[j] &&
752 alu->src[src].chan == j) {
753 alu->src[src].sel = V_SQ_ALU_SRC_PV;
754 alu->src[src].chan = chan[j];
755 break;
756 }
757 }
758 }
759 }
760
761 return 0;
762 }
763
764 void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
765 {
766 switch(value) {
767 case 0:
768 *sel = V_SQ_ALU_SRC_0;
769 break;
770 case 1:
771 *sel = V_SQ_ALU_SRC_1_INT;
772 break;
773 case -1:
774 *sel = V_SQ_ALU_SRC_M_1_INT;
775 break;
776 case 0x3F800000: // 1.0f
777 *sel = V_SQ_ALU_SRC_1;
778 break;
779 case 0x3F000000: // 0.5f
780 *sel = V_SQ_ALU_SRC_0_5;
781 break;
782 case 0xBF800000: // -1.0f
783 *sel = V_SQ_ALU_SRC_1;
784 *neg ^= 1;
785 break;
786 case 0xBF000000: // -0.5f
787 *sel = V_SQ_ALU_SRC_0_5;
788 *neg ^= 1;
789 break;
790 default:
791 *sel = V_SQ_ALU_SRC_LITERAL;
792 break;
793 }
794 }
795
796 /* compute how many literal are needed */
797 static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
798 uint32_t literal[4], unsigned *nliteral)
799 {
800 unsigned num_src = r600_bc_get_num_operands(bc, alu);
801 unsigned i, j;
802
803 for (i = 0; i < num_src; ++i) {
804 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
805 uint32_t value = alu->src[i].value[alu->src[i].chan];
806 unsigned found = 0;
807 for (j = 0; j < *nliteral; ++j) {
808 if (literal[j] == value) {
809 found = 1;
810 break;
811 }
812 }
813 if (!found) {
814 if (*nliteral >= 4)
815 return -EINVAL;
816 literal[(*nliteral)++] = value;
817 }
818 }
819 }
820 return 0;
821 }
822
823 static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
824 struct r600_bc_alu *alu,
825 uint32_t literal[4], unsigned nliteral)
826 {
827 unsigned num_src = r600_bc_get_num_operands(bc, alu);
828 unsigned i, j;
829
830 for (i = 0; i < num_src; ++i) {
831 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
832 uint32_t value = alu->src[i].value[alu->src[i].chan];
833 for (j = 0; j < nliteral; ++j) {
834 if (literal[j] == value) {
835 alu->src[i].chan = j;
836 break;
837 }
838 }
839 }
840 }
841 }
842
843 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
844 struct r600_bc_alu *alu_prev)
845 {
846 struct r600_bc_alu *prev[5];
847 struct r600_bc_alu *result[5] = { NULL };
848
849 uint32_t literal[4], prev_literal[4];
850 unsigned nliteral = 0, prev_nliteral = 0;
851
852 int i, j, r, src, num_src;
853 int num_once_inst = 0;
854 int have_mova = 0, have_rel = 0;
855
856 r = assign_alu_units(bc, alu_prev, prev);
857 if (r)
858 return r;
859
860 for (i = 0; i < 5; ++i) {
861 struct r600_bc_alu *alu;
862
863 /* check number of literals */
864 if (prev[i]) {
865 if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
866 return 0;
867 if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
868 return 0;
869 if (is_alu_mova_inst(bc, prev[i])) {
870 if (have_rel)
871 return 0;
872 have_mova = 1;
873 }
874 num_once_inst += is_alu_once_inst(bc, prev[i]);
875 }
876 if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
877 return 0;
878
879 // let's check used slots
880 if (prev[i] && !slots[i]) {
881 result[i] = prev[i];
882 continue;
883 } else if (prev[i] && slots[i]) {
884 if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
885 // trans unit is still free try to use it
886 if (is_alu_any_unit_inst(bc, slots[i])) {
887 result[i] = prev[i];
888 result[4] = slots[i];
889 } else if (is_alu_any_unit_inst(bc, prev[i])) {
890 result[i] = slots[i];
891 result[4] = prev[i];
892 } else
893 return 0;
894 } else
895 return 0;
896 } else if(!slots[i]) {
897 continue;
898 } else
899 result[i] = slots[i];
900
901 // let's check source gprs
902 alu = slots[i];
903 num_once_inst += is_alu_once_inst(bc, alu);
904
905 num_src = r600_bc_get_num_operands(bc, alu);
906 for (src = 0; src < num_src; ++src) {
907 if (alu->src[src].rel) {
908 if (have_mova)
909 return 0;
910 have_rel = 1;
911 }
912
913 // constants doesn't matter
914 if (!is_gpr(alu->src[src].sel))
915 continue;
916
917 for (j = 0; j < 5; ++j) {
918 if (!prev[j] || !prev[j]->dst.write)
919 continue;
920
921 // if it's relative then we can't determin which gpr is really used
922 if (prev[j]->dst.chan == alu->src[src].chan &&
923 (prev[j]->dst.sel == alu->src[src].sel ||
924 prev[j]->dst.rel || alu->src[src].rel))
925 return 0;
926 }
927 }
928 }
929
930 /* more than one PRED_ or KILL_ ? */
931 if (num_once_inst > 1)
932 return 0;
933
934 /* check if the result can still be swizzlet */
935 r = check_and_set_bank_swizzle(bc, result);
936 if (r)
937 return 0;
938
939 /* looks like everything worked out right, apply the changes */
940
941 /* undo adding previus literals */
942 bc->cf_last->ndw -= align(prev_nliteral, 2);
943
944 /* sort instructions */
945 for (i = 0; i < 5; ++i) {
946 slots[i] = result[i];
947 if (result[i]) {
948 LIST_DEL(&result[i]->list);
949 result[i]->last = 0;
950 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
951 }
952 }
953
954 /* determine new last instruction */
955 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
956
957 /* determine new first instruction */
958 for (i = 0; i < 5; ++i) {
959 if (result[i]) {
960 bc->cf_last->curr_bs_head = result[i];
961 break;
962 }
963 }
964
965 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
966 bc->cf_last->prev2_bs_head = NULL;
967
968 return 0;
969 }
970
971 /* This code handles kcache lines as single blocks of 32 constants. We could
972 * probably do slightly better by recognizing that we actually have two
973 * consecutive lines of 16 constants, but the resulting code would also be
974 * somewhat more complicated. */
975 static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
976 {
977 struct r600_bc_kcache *kcache = bc->cf_last->kcache;
978 unsigned int required_lines;
979 unsigned int free_lines = 0;
980 unsigned int cache_line[3];
981 unsigned int count = 0;
982 unsigned int i, j;
983 int r;
984
985 /* Collect required cache lines. */
986 for (i = 0; i < 3; ++i) {
987 bool found = false;
988 unsigned int line;
989
990 if (alu->src[i].sel < 512)
991 continue;
992
993 line = ((alu->src[i].sel - 512) / 32) * 2;
994
995 for (j = 0; j < count; ++j) {
996 if (cache_line[j] == line) {
997 found = true;
998 break;
999 }
1000 }
1001
1002 if (!found)
1003 cache_line[count++] = line;
1004 }
1005
1006 /* This should never actually happen. */
1007 if (count >= 3) return -ENOMEM;
1008
1009 for (i = 0; i < 2; ++i) {
1010 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1011 ++free_lines;
1012 }
1013 }
1014
1015 /* Filter lines pulled in by previous intructions. Note that this is
1016 * only for the required_lines count, we can't remove these from the
1017 * cache_line array since we may have to start a new ALU clause. */
1018 for (i = 0, required_lines = count; i < count; ++i) {
1019 for (j = 0; j < 2; ++j) {
1020 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1021 kcache[j].addr == cache_line[i]) {
1022 --required_lines;
1023 break;
1024 }
1025 }
1026 }
1027
1028 /* Start a new ALU clause if needed. */
1029 if (required_lines > free_lines) {
1030 if ((r = r600_bc_add_cf(bc))) {
1031 return r;
1032 }
1033 bc->cf_last->inst = (type << 3);
1034 kcache = bc->cf_last->kcache;
1035 }
1036
1037 /* Setup the kcache lines. */
1038 for (i = 0; i < count; ++i) {
1039 bool found = false;
1040
1041 for (j = 0; j < 2; ++j) {
1042 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1043 kcache[j].addr == cache_line[i]) {
1044 found = true;
1045 break;
1046 }
1047 }
1048
1049 if (found) continue;
1050
1051 for (j = 0; j < 2; ++j) {
1052 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1053 kcache[j].bank = 0;
1054 kcache[j].addr = cache_line[i];
1055 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1056 break;
1057 }
1058 }
1059 }
1060
1061 /* Alter the src operands to refer to the kcache. */
1062 for (i = 0; i < 3; ++i) {
1063 static const unsigned int base[] = {128, 160, 256, 288};
1064 unsigned int line;
1065
1066 if (alu->src[i].sel < 512)
1067 continue;
1068
1069 alu->src[i].sel -= 512;
1070 line = (alu->src[i].sel / 32) * 2;
1071
1072 for (j = 0; j < 2; ++j) {
1073 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1074 kcache[j].addr == line) {
1075 alu->src[i].sel &= 0x1f;
1076 alu->src[i].sel += base[j];
1077 break;
1078 }
1079 }
1080 }
1081
1082 return 0;
1083 }
1084
1085 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
1086 {
1087 struct r600_bc_alu *nalu = r600_bc_alu();
1088 struct r600_bc_alu *lalu;
1089 int i, r;
1090
1091 if (nalu == NULL)
1092 return -ENOMEM;
1093 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
1094
1095 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1096 /* check if we could add it anyway */
1097 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1098 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1099 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1100 if (lalu->predicate) {
1101 bc->force_add_cf = 1;
1102 break;
1103 }
1104 }
1105 } else
1106 bc->force_add_cf = 1;
1107 }
1108
1109 /* cf can contains only alu or only vtx or only tex */
1110 if (bc->cf_last == NULL || bc->force_add_cf) {
1111 r = r600_bc_add_cf(bc);
1112 if (r) {
1113 free(nalu);
1114 return r;
1115 }
1116 }
1117 bc->cf_last->inst = (type << 3);
1118
1119 /* Setup the kcache for this ALU instruction. This will start a new
1120 * ALU clause if needed. */
1121 if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
1122 free(nalu);
1123 return r;
1124 }
1125
1126 if (!bc->cf_last->curr_bs_head) {
1127 bc->cf_last->curr_bs_head = nalu;
1128 }
1129 /* number of gpr == the last gpr used in any alu */
1130 for (i = 0; i < 3; i++) {
1131 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1132 bc->ngpr = nalu->src[i].sel + 1;
1133 }
1134 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1135 r600_bc_special_constants(
1136 nalu->src[i].value[nalu->src[i].chan],
1137 &nalu->src[i].sel, &nalu->src[i].neg);
1138 }
1139 if (nalu->dst.sel >= bc->ngpr) {
1140 bc->ngpr = nalu->dst.sel + 1;
1141 }
1142 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1143 /* each alu use 2 dwords */
1144 bc->cf_last->ndw += 2;
1145 bc->ndw += 2;
1146
1147 /* process cur ALU instructions for bank swizzle */
1148 if (nalu->last) {
1149 uint32_t literal[4];
1150 unsigned nliteral;
1151 struct r600_bc_alu *slots[5];
1152 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1153 if (r)
1154 return r;
1155
1156 if (bc->cf_last->prev_bs_head) {
1157 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1158 if (r)
1159 return r;
1160 }
1161
1162 if (bc->cf_last->prev_bs_head) {
1163 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1164 if (r)
1165 return r;
1166 }
1167
1168 r = check_and_set_bank_swizzle(bc, slots);
1169 if (r)
1170 return r;
1171
1172 for (i = 0, nliteral = 0; i < 5; i++) {
1173 if (slots[i]) {
1174 r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
1175 if (r)
1176 return r;
1177 }
1178 }
1179 bc->cf_last->ndw += align(nliteral, 2);
1180
1181 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1182 * worst case */
1183 if ((bc->cf_last->ndw >> 1) >= 120) {
1184 bc->force_add_cf = 1;
1185 }
1186
1187 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1188 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1189 bc->cf_last->curr_bs_head = NULL;
1190 }
1191 return 0;
1192 }
1193
1194 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
1195 {
1196 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1197 }
1198
1199 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
1200 {
1201 struct r600_bc_vtx *nvtx = r600_bc_vtx();
1202 int r;
1203
1204 if (nvtx == NULL)
1205 return -ENOMEM;
1206 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
1207
1208 /* cf can contains only alu or only vtx or only tex */
1209 if (bc->cf_last == NULL ||
1210 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1211 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
1212 bc->force_add_cf) {
1213 r = r600_bc_add_cf(bc);
1214 if (r) {
1215 free(nvtx);
1216 return r;
1217 }
1218 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1219 }
1220 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1221 /* each fetch use 4 dwords */
1222 bc->cf_last->ndw += 4;
1223 bc->ndw += 4;
1224 if ((bc->cf_last->ndw / 4) > 7)
1225 bc->force_add_cf = 1;
1226 return 0;
1227 }
1228
1229 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
1230 {
1231 struct r600_bc_tex *ntex = r600_bc_tex();
1232 int r;
1233
1234 if (ntex == NULL)
1235 return -ENOMEM;
1236 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
1237
1238 /* cf can contains only alu or only vtx or only tex */
1239 if (bc->cf_last == NULL ||
1240 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1241 bc->force_add_cf) {
1242 r = r600_bc_add_cf(bc);
1243 if (r) {
1244 free(ntex);
1245 return r;
1246 }
1247 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1248 }
1249 if (ntex->src_gpr >= bc->ngpr) {
1250 bc->ngpr = ntex->src_gpr + 1;
1251 }
1252 if (ntex->dst_gpr >= bc->ngpr) {
1253 bc->ngpr = ntex->dst_gpr + 1;
1254 }
1255 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1256 /* each texture fetch use 4 dwords */
1257 bc->cf_last->ndw += 4;
1258 bc->ndw += 4;
1259 if ((bc->cf_last->ndw / 4) > 7)
1260 bc->force_add_cf = 1;
1261 return 0;
1262 }
1263
1264 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
1265 {
1266 int r;
1267 r = r600_bc_add_cf(bc);
1268 if (r)
1269 return r;
1270
1271 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1272 bc->cf_last->inst = inst;
1273 return 0;
1274 }
1275
1276 /* common to all 3 families */
1277 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
1278 {
1279 unsigned fetch_resource_start = 0;
1280
1281 /* check if we are fetch shader */
1282 /* fetch shader can also access vertex resource,
1283 * first fetch shader resource is at 160
1284 */
1285 if (bc->type == -1) {
1286 switch (bc->chiprev) {
1287 /* r600 */
1288 case CHIPREV_R600:
1289 /* r700 */
1290 case CHIPREV_R700:
1291 fetch_resource_start = 160;
1292 break;
1293 /* evergreen */
1294 case CHIPREV_EVERGREEN:
1295 fetch_resource_start = 0;
1296 break;
1297 default:
1298 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
1299 __FILE__, __func__, __LINE__, bc->chiprev);
1300 break;
1301 }
1302 }
1303 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
1304 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1305 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
1306 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1307 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1308 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1309 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1310 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1311 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1312 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1313 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1314 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1315 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1316 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1317 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
1318 bc->bytecode[id++] = 0;
1319 return 0;
1320 }
1321
1322 /* common to all 3 families */
1323 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
1324 {
1325 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1326 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1327 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1328 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1329 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1330 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1331 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1332 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1333 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1334 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1335 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1336 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1337 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1338 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1339 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1340 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1341 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1342 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1343 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1344 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1345 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1346 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1347 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1348 bc->bytecode[id++] = 0;
1349 return 0;
1350 }
1351
1352 /* r600 only, r700/eg bits in r700_asm.c */
1353 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1354 {
1355 /* don't replace gpr by pv or ps for destination register */
1356 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1357 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1358 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1359 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1360 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1361 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1362 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1363 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1364 S_SQ_ALU_WORD0_LAST(alu->last);
1365
1366 if (alu->is_op3) {
1367 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1368 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1369 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1370 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1371 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1372 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1373 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1374 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1375 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1376 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1377 } else {
1378 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1379 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1380 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1381 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1382 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1383 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1384 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1385 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1386 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1387 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1388 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1389 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1390 }
1391 return 0;
1392 }
1393
1394 /* common for r600/r700 - eg in eg_asm.c */
1395 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1396 {
1397 unsigned id = cf->id;
1398
1399 switch (cf->inst) {
1400 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1401 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1402 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1403 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1404 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1405 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1406 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1407 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1408
1409 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1410 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1411 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1412 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1413 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1414 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
1415 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1416 break;
1417 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1418 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1419 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1420 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1421 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1422 S_SQ_CF_WORD1_BARRIER(1) |
1423 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1424 break;
1425 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1426 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1427 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1428 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1429 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1430 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1431 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1432 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1433 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1434 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1435 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1436 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1437 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1438 break;
1439 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1440 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1441 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1442 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1443 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1444 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1445 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1446 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1447 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1448 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1449 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1450 S_SQ_CF_WORD1_BARRIER(1) |
1451 S_SQ_CF_WORD1_COND(cf->cond) |
1452 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1453
1454 break;
1455 default:
1456 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1457 return -EINVAL;
1458 }
1459 return 0;
1460 }
1461
1462 int r600_bc_build(struct r600_bc *bc)
1463 {
1464 struct r600_bc_cf *cf;
1465 struct r600_bc_alu *alu;
1466 struct r600_bc_vtx *vtx;
1467 struct r600_bc_tex *tex;
1468 uint32_t literal[4];
1469 unsigned nliteral;
1470 unsigned addr;
1471 int i, r;
1472
1473 if (bc->callstack[0].max > 0)
1474 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1475 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1476 bc->nstack = 1;
1477 }
1478
1479 /* first path compute addr of each CF block */
1480 /* addr start after all the CF instructions */
1481 addr = bc->cf_last->id + 2;
1482 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1483 switch (cf->inst) {
1484 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1485 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1486 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1487 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1488 break;
1489 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1490 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1491 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1492 /* fetch node need to be 16 bytes aligned*/
1493 addr += 3;
1494 addr &= 0xFFFFFFFCUL;
1495 break;
1496 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1497 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1498 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1499 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1500 break;
1501 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1502 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1503 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1504 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1505 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1506 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1507 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1508 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1509 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1510 break;
1511 default:
1512 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1513 return -EINVAL;
1514 }
1515 cf->addr = addr;
1516 addr += cf->ndw;
1517 bc->ndw = cf->addr + cf->ndw;
1518 }
1519 free(bc->bytecode);
1520 bc->bytecode = calloc(1, bc->ndw * 4);
1521 if (bc->bytecode == NULL)
1522 return -ENOMEM;
1523 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1524 addr = cf->addr;
1525 if (bc->chiprev == CHIPREV_EVERGREEN)
1526 r = eg_bc_cf_build(bc, cf);
1527 else
1528 r = r600_bc_cf_build(bc, cf);
1529 if (r)
1530 return r;
1531 switch (cf->inst) {
1532 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1533 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1534 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1535 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1536 nliteral = 0;
1537 memset(literal, 0, sizeof(literal));
1538 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1539 r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1540 if (r)
1541 return r;
1542 r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
1543 switch(bc->chiprev) {
1544 case CHIPREV_R600:
1545 r = r600_bc_alu_build(bc, alu, addr);
1546 break;
1547 case CHIPREV_R700:
1548 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
1549 r = r700_bc_alu_build(bc, alu, addr);
1550 break;
1551 default:
1552 R600_ERR("unknown family %d\n", bc->family);
1553 return -EINVAL;
1554 }
1555 if (r)
1556 return r;
1557 addr += 2;
1558 if (alu->last) {
1559 for (i = 0; i < align(nliteral, 2); ++i) {
1560 bc->bytecode[addr++] = literal[i];
1561 }
1562 nliteral = 0;
1563 memset(literal, 0, sizeof(literal));
1564 }
1565 }
1566 break;
1567 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1568 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1569 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1570 r = r600_bc_vtx_build(bc, vtx, addr);
1571 if (r)
1572 return r;
1573 addr += 4;
1574 }
1575 break;
1576 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1577 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1578 r = r600_bc_tex_build(bc, tex, addr);
1579 if (r)
1580 return r;
1581 addr += 4;
1582 }
1583 break;
1584 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1585 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1586 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1587 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1588 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1589 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1590 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1591 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1592 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1593 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1594 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1595 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1596 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1597 break;
1598 default:
1599 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1600 return -EINVAL;
1601 }
1602 }
1603 return 0;
1604 }
1605
1606 void r600_bc_clear(struct r600_bc *bc)
1607 {
1608 struct r600_bc_cf *cf = NULL, *next_cf;
1609
1610 free(bc->bytecode);
1611 bc->bytecode = NULL;
1612
1613 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1614 struct r600_bc_alu *alu = NULL, *next_alu;
1615 struct r600_bc_tex *tex = NULL, *next_tex;
1616 struct r600_bc_tex *vtx = NULL, *next_vtx;
1617
1618 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1619 free(alu);
1620 }
1621
1622 LIST_INITHEAD(&cf->alu);
1623
1624 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1625 free(tex);
1626 }
1627
1628 LIST_INITHEAD(&cf->tex);
1629
1630 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1631 free(vtx);
1632 }
1633
1634 LIST_INITHEAD(&cf->vtx);
1635
1636 free(cf);
1637 }
1638
1639 LIST_INITHEAD(&cf->list);
1640 }
1641
1642 void r600_bc_dump(struct r600_bc *bc)
1643 {
1644 struct r600_bc_cf *cf = NULL;
1645 struct r600_bc_alu *alu = NULL;
1646 struct r600_bc_vtx *vtx = NULL;
1647 struct r600_bc_tex *tex = NULL;
1648
1649 unsigned i, id;
1650 uint32_t literal[4];
1651 unsigned nliteral;
1652 char chip = '6';
1653
1654 switch (bc->chiprev) {
1655 case 1:
1656 chip = '7';
1657 break;
1658 case 2:
1659 chip = 'E';
1660 break;
1661 case 0:
1662 default:
1663 chip = '6';
1664 break;
1665 }
1666 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1667 fprintf(stderr, " %c\n", chip);
1668
1669 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1670 id = cf->id;
1671
1672 switch (cf->inst) {
1673 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1674 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1675 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1676 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1677 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1678 fprintf(stderr, "ADDR:%d ", cf->addr);
1679 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1680 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1681 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1682 id++;
1683 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1684 fprintf(stderr, "INST:%d ", cf->inst);
1685 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1686 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1687 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1688 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1689 break;
1690 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1691 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1692 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1693 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1694 fprintf(stderr, "ADDR:%d\n", cf->addr);
1695 id++;
1696 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1697 fprintf(stderr, "INST:%d ", cf->inst);
1698 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1699 break;
1700 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1701 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1702 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1703 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1704 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1705 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1706 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1707 id++;
1708 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1709 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1710 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1711 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1712 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1713 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1714 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1715 fprintf(stderr, "INST:%d ", cf->output.inst);
1716 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1717 break;
1718 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1719 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1720 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1721 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1722 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1723 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1724 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1725 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1726 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1727 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1728 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1729 id++;
1730 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1731 fprintf(stderr, "INST:%d ", cf->inst);
1732 fprintf(stderr, "COND:%X ", cf->cond);
1733 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1734 break;
1735 }
1736
1737 id = cf->addr;
1738 nliteral = 0;
1739 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1740 r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1741
1742 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1743 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1744 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1745 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1746 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1747 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1748 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1749 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1750 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1751 fprintf(stderr, "LAST:%d)\n", alu->last);
1752 id++;
1753 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1754 fprintf(stderr, "INST:%d ", alu->inst);
1755 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1756 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1757 fprintf(stderr, "REL:%d ", alu->dst.rel);
1758 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1759 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1760 if (alu->is_op3) {
1761 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1762 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1763 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1764 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1765 } else {
1766 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1767 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1768 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1769 fprintf(stderr, "OMOD:%d ", alu->omod);
1770 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1771 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1772 }
1773
1774 id++;
1775 if (alu->last) {
1776 for (i = 0; i < nliteral; i++, id++) {
1777 float *f = (float*)(bc->bytecode + id);
1778 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1779 }
1780 id += nliteral & 1;
1781 nliteral = 0;
1782 }
1783 }
1784
1785 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1786 //TODO
1787 }
1788
1789 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1790 //TODO
1791 }
1792 }
1793
1794 fprintf(stderr, "--------------------------------------\n");
1795 }
1796
1797 void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1798 {
1799 struct r600_pipe_state *rstate;
1800 unsigned i = 0;
1801
1802 if (count > 8) {
1803 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1804 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1805 S_SQ_CF_WORD1_BARRIER(1) |
1806 S_SQ_CF_WORD1_COUNT(8 - 1);
1807 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1808 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1809 S_SQ_CF_WORD1_BARRIER(1) |
1810 S_SQ_CF_WORD1_COUNT(count - 8 - 1);
1811 } else {
1812 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1813 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1814 S_SQ_CF_WORD1_BARRIER(1) |
1815 S_SQ_CF_WORD1_COUNT(count - 1);
1816 }
1817 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1818 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1819 S_SQ_CF_WORD1_BARRIER(1);
1820
1821 rstate = &ve->rstate;
1822 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1823 rstate->nregs = 0;
1824 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1825 0x00000000, 0xFFFFFFFF, NULL);
1826 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1827 0x00000000, 0xFFFFFFFF, NULL);
1828 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1829 r600_bo_offset(ve->fetch_shader) >> 8,
1830 0xFFFFFFFF, ve->fetch_shader);
1831 }
1832
1833 void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1834 {
1835 struct r600_pipe_state *rstate;
1836 unsigned i = 0;
1837
1838 if (count > 8) {
1839 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1840 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1841 S_SQ_CF_WORD1_BARRIER(1) |
1842 S_SQ_CF_WORD1_COUNT(8 - 1);
1843 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1844 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1845 S_SQ_CF_WORD1_BARRIER(1) |
1846 S_SQ_CF_WORD1_COUNT((count - 8) - 1);
1847 } else {
1848 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1849 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1850 S_SQ_CF_WORD1_BARRIER(1) |
1851 S_SQ_CF_WORD1_COUNT(count - 1);
1852 }
1853 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1854 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1855 S_SQ_CF_WORD1_BARRIER(1);
1856
1857 rstate = &ve->rstate;
1858 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1859 rstate->nregs = 0;
1860 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1861 0x00000000, 0xFFFFFFFF, NULL);
1862 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1863 0x00000000, 0xFFFFFFFF, NULL);
1864 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1865 r600_bo_offset(ve->fetch_shader) >> 8,
1866 0xFFFFFFFF, ve->fetch_shader);
1867 }
1868
1869 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1870 unsigned *num_format, unsigned *format_comp)
1871 {
1872 const struct util_format_description *desc;
1873 unsigned i;
1874
1875 *format = 0;
1876 *num_format = 0;
1877 *format_comp = 0;
1878
1879 desc = util_format_description(pformat);
1880 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1881 goto out_unknown;
1882 }
1883
1884 /* Find the first non-VOID channel. */
1885 for (i = 0; i < 4; i++) {
1886 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1887 break;
1888 }
1889 }
1890
1891 switch (desc->channel[i].type) {
1892 /* Half-floats, floats, ints */
1893 case UTIL_FORMAT_TYPE_FLOAT:
1894 switch (desc->channel[i].size) {
1895 case 16:
1896 switch (desc->nr_channels) {
1897 case 1:
1898 *format = FMT_16_FLOAT;
1899 break;
1900 case 2:
1901 *format = FMT_16_16_FLOAT;
1902 break;
1903 case 3:
1904 case 4:
1905 *format = FMT_16_16_16_16_FLOAT;
1906 break;
1907 }
1908 break;
1909 case 32:
1910 switch (desc->nr_channels) {
1911 case 1:
1912 *format = FMT_32_FLOAT;
1913 break;
1914 case 2:
1915 *format = FMT_32_32_FLOAT;
1916 break;
1917 case 3:
1918 *format = FMT_32_32_32_FLOAT;
1919 break;
1920 case 4:
1921 *format = FMT_32_32_32_32_FLOAT;
1922 break;
1923 }
1924 break;
1925 default:
1926 goto out_unknown;
1927 }
1928 break;
1929 /* Unsigned ints */
1930 case UTIL_FORMAT_TYPE_UNSIGNED:
1931 /* Signed ints */
1932 case UTIL_FORMAT_TYPE_SIGNED:
1933 switch (desc->channel[i].size) {
1934 case 8:
1935 switch (desc->nr_channels) {
1936 case 1:
1937 *format = FMT_8;
1938 break;
1939 case 2:
1940 *format = FMT_8_8;
1941 break;
1942 case 3:
1943 case 4:
1944 *format = FMT_8_8_8_8;
1945 break;
1946 }
1947 break;
1948 case 16:
1949 switch (desc->nr_channels) {
1950 case 1:
1951 *format = FMT_16;
1952 break;
1953 case 2:
1954 *format = FMT_16_16;
1955 break;
1956 case 3:
1957 case 4:
1958 *format = FMT_16_16_16_16;
1959 break;
1960 }
1961 break;
1962 case 32:
1963 switch (desc->nr_channels) {
1964 case 1:
1965 *format = FMT_32;
1966 break;
1967 case 2:
1968 *format = FMT_32_32;
1969 break;
1970 case 3:
1971 *format = FMT_32_32_32;
1972 break;
1973 case 4:
1974 *format = FMT_32_32_32_32;
1975 break;
1976 }
1977 break;
1978 default:
1979 goto out_unknown;
1980 }
1981 break;
1982 default:
1983 goto out_unknown;
1984 }
1985
1986 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1987 *format_comp = 1;
1988 }
1989 if (desc->channel[i].normalized) {
1990 *num_format = 0;
1991 } else {
1992 *num_format = 2;
1993 }
1994 return;
1995 out_unknown:
1996 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
1997 }
1998
1999 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2000 {
2001 unsigned ndw, i;
2002 u32 *bytecode;
2003 unsigned fetch_resource_start = 0, format, num_format, format_comp;
2004 struct pipe_vertex_element *elements = ve->elements;
2005 const struct util_format_description *desc;
2006
2007 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
2008 ndw = 8 + ve->count * 4;
2009 ve->fs_size = ndw * 4;
2010
2011 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
2012 ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
2013 if (ve->fetch_shader == NULL) {
2014 return -ENOMEM;
2015 }
2016
2017 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
2018 if (bytecode == NULL) {
2019 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2020 return -ENOMEM;
2021 }
2022
2023 if (rctx->family >= CHIP_CEDAR) {
2024 eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2025 } else {
2026 r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2027 fetch_resource_start = 160;
2028 }
2029
2030 /* vertex elements offset need special handling, if offset is bigger
2031 * than what we can put in fetch instruction then we need to alterate
2032 * the vertex resource offset. In such case in order to simplify code
2033 * we will bound one resource per elements. It's a worst case scenario.
2034 */
2035 for (i = 0; i < ve->count; i++) {
2036 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2037 if (ve->vbuffer_offset[i]) {
2038 ve->vbuffer_need_offset = 1;
2039 }
2040 }
2041
2042 for (i = 0; i < ve->count; i++) {
2043 unsigned vbuffer_index;
2044 r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
2045 desc = util_format_description(ve->hw_format[i]);
2046 if (desc == NULL) {
2047 R600_ERR("unknown format %d\n", ve->hw_format[i]);
2048 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2049 return -EINVAL;
2050 }
2051
2052 /* see above for vbuffer_need_offset explanation */
2053 vbuffer_index = elements[i].vertex_buffer_index;
2054 if (ve->vbuffer_need_offset) {
2055 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
2056 } else {
2057 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
2058 }
2059 bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
2060 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
2061 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
2062 bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
2063 S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
2064 S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
2065 S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
2066 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
2067 S_SQ_VTX_WORD1_DATA_FORMAT(format) |
2068 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
2069 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
2070 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
2071 S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
2072 bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
2073 S_SQ_VTX_WORD2_MEGA_FETCH(1);
2074 bytecode[8 + i * 4 + 3] = 0;
2075 }
2076 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
2077 return 0;
2078 }