2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
36 #include "sb/sb_public.h"
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
41 static inline bool alu_writes(struct r600_bytecode_alu
*alu
)
43 return alu
->dst
.write
|| alu
->is_op3
;
46 static inline unsigned int r600_bytecode_get_num_operands(
47 struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
49 return r600_isa_alu(alu
->op
)->src_count
;
52 int r700_bytecode_alu_build(struct r600_bytecode
*bc
,
53 struct r600_bytecode_alu
*alu
, unsigned id
);
55 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
57 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
61 LIST_INITHEAD(&cf
->list
);
62 LIST_INITHEAD(&cf
->alu
);
63 LIST_INITHEAD(&cf
->vtx
);
64 LIST_INITHEAD(&cf
->tex
);
65 LIST_INITHEAD(&cf
->gds
);
69 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
71 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
75 LIST_INITHEAD(&alu
->list
);
79 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
81 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
85 LIST_INITHEAD(&vtx
->list
);
89 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
91 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
95 LIST_INITHEAD(&tex
->list
);
99 static struct r600_bytecode_gds
*r600_bytecode_gds(void)
101 struct r600_bytecode_gds
*gds
= CALLOC_STRUCT(r600_bytecode_gds
);
105 LIST_INITHEAD(&gds
->list
);
109 static unsigned stack_entry_size(enum radeon_family chip
) {
111 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
112 * Aruba/Sumo/Sumo2/redwood/juniper
113 * 32: R630/R730/R710/Palm/Cedar
117 * Wavefront Size 16 32 48 64
118 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
119 * Columns per Row (R9xx+) 8 4 4 4 */
122 /* FIXME: are some chips missing here? */
123 /* wavefront size 16 */
128 /* wavefront size 32 */
137 /* wavefront size 64 */
143 void r600_bytecode_init(struct r600_bytecode
*bc
,
144 enum chip_class chip_class
,
145 enum radeon_family family
,
146 bool has_compressed_msaa_texturing
)
148 static unsigned next_shader_id
= 0;
150 bc
->debug_id
= ++next_shader_id
;
152 if ((chip_class
== R600
) &&
153 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
154 bc
->ar_handling
= AR_HANDLE_RV6XX
;
155 bc
->r6xx_nop_after_rel_dst
= 1;
157 bc
->ar_handling
= AR_HANDLE_NORMAL
;
158 bc
->r6xx_nop_after_rel_dst
= 0;
161 LIST_INITHEAD(&bc
->cf
);
162 bc
->chip_class
= chip_class
;
164 bc
->has_compressed_msaa_texturing
= has_compressed_msaa_texturing
;
165 bc
->stack
.entry_size
= stack_entry_size(family
);
168 int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
170 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
174 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
176 cf
->id
= bc
->cf_last
->id
+ 2;
177 if (bc
->cf_last
->eg_alu_extended
) {
178 /* take into account extended alu size */
186 bc
->force_add_cf
= 0;
191 int r600_bytecode_add_output(struct r600_bytecode
*bc
,
192 const struct r600_bytecode_output
*output
)
196 if (output
->gpr
>= bc
->ngpr
)
197 bc
->ngpr
= output
->gpr
+ 1;
199 if (bc
->cf_last
&& (bc
->cf_last
->op
== output
->op
||
200 (bc
->cf_last
->op
== CF_OP_EXPORT
&&
201 output
->op
== CF_OP_EXPORT_DONE
)) &&
202 output
->type
== bc
->cf_last
->output
.type
&&
203 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
204 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
205 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
206 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
207 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
208 output
->comp_mask
== bc
->cf_last
->output
.comp_mask
&&
209 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
211 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
212 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
214 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
215 bc
->cf_last
->output
.gpr
= output
->gpr
;
216 bc
->cf_last
->output
.array_base
= output
->array_base
;
217 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
220 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
221 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
223 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
224 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
229 r
= r600_bytecode_add_cf(bc
);
232 bc
->cf_last
->op
= output
->op
;
233 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
234 bc
->cf_last
->barrier
= 1;
238 /* alu instructions that can ony exits once per group */
239 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
241 return r600_isa_alu(alu
->op
)->flags
& (AF_KILL
| AF_PRED
) || alu
->is_lds_idx_op
|| alu
->op
== ALU_OP0_GROUP_BARRIER
;
244 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
246 return (r600_isa_alu(alu
->op
)->flags
& AF_REPL
) &&
247 (r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
) == AF_4V
);
250 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
252 return r600_isa_alu(alu
->op
)->flags
& AF_MOVA
;
255 static int alu_uses_rel(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
257 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
264 for (src
= 0; src
< num_src
; ++src
) {
265 if (alu
->src
[src
].rel
) {
272 static int is_lds_read(int sel
)
274 return sel
== EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
|| sel
== EG_V_SQ_ALU_SRC_LDS_OQ_B_POP
;
277 static int alu_uses_lds(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
279 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
282 for (src
= 0; src
< num_src
; ++src
) {
283 if (is_lds_read(alu
->src
[src
].sel
)) {
290 static int is_alu_64bit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
292 const struct alu_op_info
*op
= r600_isa_alu(alu
->op
);
293 return (op
->flags
& AF_64
);
296 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
298 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
299 return !(slots
& AF_S
);
302 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
304 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
305 return !(slots
& AF_V
);
308 /* alu instructions that can execute on any unit */
309 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
311 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
312 return slots
== AF_VS
;
315 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
317 return alu
->op
== ALU_OP0_NOP
;
320 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
321 struct r600_bytecode_alu
*assignment
[5])
323 struct r600_bytecode_alu
*alu
;
324 unsigned i
, chan
, trans
;
325 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
327 for (i
= 0; i
< max_slots
; i
++)
328 assignment
[i
] = NULL
;
330 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
331 chan
= alu
->dst
.chan
;
334 else if (is_alu_trans_unit_inst(bc
, alu
))
336 else if (is_alu_vec_unit_inst(bc
, alu
))
338 else if (assignment
[chan
])
339 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
345 assert(0); /* ALU.Trans has already been allocated. */
350 if (assignment
[chan
]) {
351 assert(0); /* ALU.chan has already been allocated. */
354 assignment
[chan
] = alu
;
363 struct alu_bank_swizzle
{
364 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
365 int hw_cfile_addr
[4];
366 int hw_cfile_elem
[4];
369 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
370 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
371 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
372 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
373 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
374 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
375 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
378 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
379 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
380 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
381 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
382 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
385 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
387 int i
, cycle
, component
;
389 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
390 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
391 bs
->hw_gpr
[cycle
][component
] = -1;
392 for (i
= 0; i
< 4; i
++)
393 bs
->hw_cfile_addr
[i
] = -1;
394 for (i
= 0; i
< 4; i
++)
395 bs
->hw_cfile_elem
[i
] = -1;
398 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
400 if (bs
->hw_gpr
[cycle
][chan
] == -1)
401 bs
->hw_gpr
[cycle
][chan
] = sel
;
402 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
403 /* Another scalar operation has already used the GPR read port for the channel. */
409 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
411 int res
, num_res
= 4;
412 if (bc
->chip_class
>= R700
) {
416 for (res
= 0; res
< num_res
; ++res
) {
417 if (bs
->hw_cfile_addr
[res
] == -1) {
418 bs
->hw_cfile_addr
[res
] = sel
;
419 bs
->hw_cfile_elem
[res
] = chan
;
421 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
422 bs
->hw_cfile_elem
[res
] == chan
)
423 return 0; /* Read for this scalar element already reserved, nothing to do here. */
425 /* All cfile read ports are used, cannot reference vector element. */
429 static int is_gpr(unsigned sel
)
434 /* CB constants start at 512, and get translated to a kcache index when ALU
435 * clauses are constructed. Note that we handle kcache constants the same way
436 * as (the now gone) cfile constants, is that really required? */
437 static int is_cfile(unsigned sel
)
439 return (sel
> 255 && sel
< 512) ||
440 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
441 (sel
> 127 && sel
< 192); /* Kcache after translation. */
444 static int is_const(int sel
)
446 return is_cfile(sel
) ||
447 (sel
>= V_SQ_ALU_SRC_0
&&
448 sel
<= V_SQ_ALU_SRC_LITERAL
);
451 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
452 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
454 int r
, src
, num_src
, sel
, elem
, cycle
;
456 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
457 for (src
= 0; src
< num_src
; src
++) {
458 sel
= alu
->src
[src
].sel
;
459 elem
= alu
->src
[src
].chan
;
461 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
462 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
463 /* Nothing to do; special-case optimization,
464 * second source uses first source’s reservation. */
467 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
471 } else if (is_cfile(sel
)) {
472 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
476 /* No restrictions on PV, PS, literal or special constants. */
481 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
482 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
484 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
486 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
487 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
488 sel
= alu
->src
[src
].sel
;
489 elem
= alu
->src
[src
].chan
;
490 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
491 if (const_count
>= 2)
492 /* More than two references to a constant in
493 * transcendental operation. */
499 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
504 for (src
= 0; src
< num_src
; ++src
) {
505 sel
= alu
->src
[src
].sel
;
506 elem
= alu
->src
[src
].chan
;
508 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
509 if (cycle
< const_count
)
510 /* Cycle for GPR load conflicts with
511 * constant load in transcendental operation. */
513 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
517 /* PV PS restrictions */
518 if (const_count
&& (sel
== 254 || sel
== 255)) {
519 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
520 if (cycle
< const_count
)
527 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
528 struct r600_bytecode_alu
*slots
[5])
530 struct alu_bank_swizzle bs
;
532 int i
, r
= 0, forced
= 1;
533 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
534 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
536 for (i
= 0; i
< max_slots
; i
++) {
538 if (slots
[i
]->bank_swizzle_force
) {
539 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
545 if (i
< 4 && slots
[i
])
551 /* Just check every possible combination of bank swizzle.
552 * Not very efficent, but works on the first try in most of the cases. */
553 for (i
= 0; i
< 4; i
++)
554 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
555 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
557 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
559 bank_swizzle
[4] = SQ_ALU_SCL_210
;
560 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
562 init_bank_swizzle(&bs
);
563 if (scalar_only
== false) {
564 for (i
= 0; i
< 4; i
++) {
566 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
574 if (!r
&& max_slots
== 5 && slots
[4]) {
575 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
578 for (i
= 0; i
< max_slots
; i
++) {
580 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
588 for (i
= 0; i
< max_slots
; i
++) {
589 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
591 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
593 else if (i
< max_slots
- 1)
594 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
602 /* Couldn't find a working swizzle. */
606 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
607 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
609 struct r600_bytecode_alu
*prev
[5];
611 int i
, j
, r
, src
, num_src
;
612 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
614 r
= assign_alu_units(bc
, alu_prev
, prev
);
618 for (i
= 0; i
< max_slots
; ++i
) {
619 if (prev
[i
] && alu_writes(prev
[i
]) && !prev
[i
]->dst
.rel
) {
621 if (is_alu_64bit_inst(bc
, prev
[i
])) {
626 gpr
[i
] = prev
[i
]->dst
.sel
;
627 /* cube writes more than PV.X */
628 if (is_alu_reduction_inst(bc
, prev
[i
]))
631 chan
[i
] = prev
[i
]->dst
.chan
;
636 for (i
= 0; i
< max_slots
; ++i
) {
637 struct r600_bytecode_alu
*alu
= slots
[i
];
641 if (is_alu_64bit_inst(bc
, alu
))
643 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
644 for (src
= 0; src
< num_src
; ++src
) {
645 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
648 if (bc
->chip_class
< CAYMAN
) {
649 if (alu
->src
[src
].sel
== gpr
[4] &&
650 alu
->src
[src
].chan
== chan
[4] &&
651 alu_prev
->pred_sel
== alu
->pred_sel
) {
652 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
653 alu
->src
[src
].chan
= 0;
658 for (j
= 0; j
< 4; ++j
) {
659 if (alu
->src
[src
].sel
== gpr
[j
] &&
660 alu
->src
[src
].chan
== j
&&
661 alu_prev
->pred_sel
== alu
->pred_sel
) {
662 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
663 alu
->src
[src
].chan
= chan
[j
];
673 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
, unsigned abs
)
677 *sel
= V_SQ_ALU_SRC_0
;
680 *sel
= V_SQ_ALU_SRC_1_INT
;
683 *sel
= V_SQ_ALU_SRC_M_1_INT
;
685 case 0x3F800000: /* 1.0f */
686 *sel
= V_SQ_ALU_SRC_1
;
688 case 0x3F000000: /* 0.5f */
689 *sel
= V_SQ_ALU_SRC_0_5
;
691 case 0xBF800000: /* -1.0f */
692 *sel
= V_SQ_ALU_SRC_1
;
695 case 0xBF000000: /* -0.5f */
696 *sel
= V_SQ_ALU_SRC_0_5
;
700 *sel
= V_SQ_ALU_SRC_LITERAL
;
705 /* compute how many literal are needed */
706 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
707 uint32_t literal
[4], unsigned *nliteral
)
709 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
712 for (i
= 0; i
< num_src
; ++i
) {
713 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
714 uint32_t value
= alu
->src
[i
].value
;
716 for (j
= 0; j
< *nliteral
; ++j
) {
717 if (literal
[j
] == value
) {
725 literal
[(*nliteral
)++] = value
;
732 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
733 struct r600_bytecode_alu
*alu
,
734 uint32_t literal
[4], unsigned nliteral
)
736 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
739 for (i
= 0; i
< num_src
; ++i
) {
740 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
741 uint32_t value
= alu
->src
[i
].value
;
742 for (j
= 0; j
< nliteral
; ++j
) {
743 if (literal
[j
] == value
) {
744 alu
->src
[i
].chan
= j
;
752 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
753 struct r600_bytecode_alu
*alu_prev
)
755 struct r600_bytecode_alu
*prev
[5];
756 struct r600_bytecode_alu
*result
[5] = { NULL
};
758 uint32_t literal
[4], prev_literal
[4];
759 unsigned nliteral
= 0, prev_nliteral
= 0;
761 int i
, j
, r
, src
, num_src
;
762 int num_once_inst
= 0;
763 int have_mova
= 0, have_rel
= 0;
764 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
766 r
= assign_alu_units(bc
, alu_prev
, prev
);
770 for (i
= 0; i
< max_slots
; ++i
) {
772 if (prev
[i
]->pred_sel
)
774 if (is_alu_once_inst(bc
, prev
[i
]))
778 if (slots
[i
]->pred_sel
)
780 if (is_alu_once_inst(bc
, slots
[i
]))
785 for (i
= 0; i
< max_slots
; ++i
) {
786 struct r600_bytecode_alu
*alu
;
788 if (num_once_inst
> 0)
791 /* check number of literals */
793 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
795 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
797 if (is_alu_mova_inst(bc
, prev
[i
])) {
803 if (alu_uses_rel(bc
, prev
[i
])) {
809 if (alu_uses_lds(bc
, prev
[i
]))
812 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
814 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
817 /* Let's check used slots. */
818 if (prev
[i
] && !slots
[i
]) {
821 } else if (prev
[i
] && slots
[i
]) {
822 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
823 /* Trans unit is still free try to use it. */
824 if (is_alu_any_unit_inst(bc
, slots
[i
]) && !alu_uses_lds(bc
, slots
[i
])) {
826 result
[4] = slots
[i
];
827 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
828 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
829 alu_writes(slots
[i
]) &&
833 result
[i
] = slots
[i
];
839 } else if(!slots
[i
]) {
842 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
843 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
844 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
845 alu_writes(slots
[i
]) &&
849 result
[i
] = slots
[i
];
853 num_once_inst
+= is_alu_once_inst(bc
, alu
);
855 /* don't reschedule NOPs */
856 if (is_nop_inst(bc
, alu
))
859 if (is_alu_mova_inst(bc
, alu
)) {
866 if (alu_uses_rel(bc
, alu
)) {
873 if (alu
->op
== ALU_OP0_SET_CF_IDX0
||
874 alu
->op
== ALU_OP0_SET_CF_IDX1
)
875 return 0; /* data hazard with MOVA */
877 /* Let's check source gprs */
878 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
879 for (src
= 0; src
< num_src
; ++src
) {
881 /* Constants don't matter. */
882 if (!is_gpr(alu
->src
[src
].sel
))
885 for (j
= 0; j
< max_slots
; ++j
) {
886 if (!prev
[j
] || !alu_writes(prev
[j
]))
889 /* If it's relative then we can't determin which gpr is really used. */
890 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
891 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
892 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
898 /* more than one PRED_ or KILL_ ? */
899 if (num_once_inst
> 1)
902 /* check if the result can still be swizzlet */
903 r
= check_and_set_bank_swizzle(bc
, result
);
907 /* looks like everything worked out right, apply the changes */
909 /* undo adding previus literals */
910 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
912 /* sort instructions */
913 for (i
= 0; i
< max_slots
; ++i
) {
914 slots
[i
] = result
[i
];
916 LIST_DEL(&result
[i
]->list
);
918 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
922 /* determine new last instruction */
923 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
925 /* determine new first instruction */
926 for (i
= 0; i
< max_slots
; ++i
) {
928 bc
->cf_last
->curr_bs_head
= result
[i
];
933 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
934 bc
->cf_last
->prev2_bs_head
= NULL
;
939 /* we'll keep kcache sets sorted by bank & addr */
940 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
941 struct r600_bytecode_kcache
*kcache
,
942 unsigned bank
, unsigned line
, unsigned index_mode
)
944 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
946 for (i
= 0; i
< kcache_banks
; i
++) {
947 if (kcache
[i
].mode
) {
950 if (kcache
[i
].bank
< bank
)
953 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
954 kcache
[i
].bank
> bank
) {
955 /* try to insert new line */
956 if (kcache
[kcache_banks
-1].mode
) {
957 /* all sets are in use */
961 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
962 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
963 kcache
[i
].bank
= bank
;
964 kcache
[i
].addr
= line
;
965 kcache
[i
].index_mode
= index_mode
;
969 d
= line
- kcache
[i
].addr
;
973 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
974 /* we are prepending the line to the current set,
975 * discarding the existing second line,
976 * so we'll have to insert line+2 after it */
979 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
980 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
983 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
987 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
991 } else { /* free kcache set - use it */
992 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
993 kcache
[i
].bank
= bank
;
994 kcache
[i
].addr
= line
;
995 kcache
[i
].index_mode
= index_mode
;
1002 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
1003 struct r600_bytecode_kcache
*kcache
,
1004 struct r600_bytecode_alu
*alu
)
1008 for (i
= 0; i
< 3; i
++) {
1009 unsigned bank
, line
, sel
= alu
->src
[i
].sel
, index_mode
;
1014 bank
= alu
->src
[i
].kc_bank
;
1015 line
= (sel
-512)>>4;
1016 index_mode
= alu
->src
[i
].kc_rel
? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1018 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
, index_mode
)))
1024 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
1025 struct r600_bytecode_alu
*alu
,
1026 struct r600_bytecode_kcache
* kcache
)
1030 /* Alter the src operands to refer to the kcache. */
1031 for (i
= 0; i
< 3; ++i
) {
1032 static const unsigned int base
[] = {128, 160, 256, 288};
1033 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
1041 for (j
= 0; j
< 4 && !found
; ++j
) {
1042 switch (kcache
[j
].mode
) {
1043 case V_SQ_CF_KCACHE_NOP
:
1044 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
1045 R600_ERR("unexpected kcache line mode\n");
1048 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
1049 kcache
[j
].addr
<= line
&&
1050 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1051 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1052 alu
->src
[i
].sel
+= base
[j
];
1061 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
,
1062 struct r600_bytecode_alu
*alu
,
1065 struct r600_bytecode_kcache kcache_sets
[4];
1066 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1069 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1071 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1072 /* can't alloc, need to start new clause */
1073 if ((r
= r600_bytecode_add_cf(bc
))) {
1076 bc
->cf_last
->op
= type
;
1078 /* retry with the new clause */
1079 kcache
= bc
->cf_last
->kcache
;
1080 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1081 /* can't alloc again- should never happen */
1085 /* update kcache sets */
1086 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1089 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1090 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
||
1091 kcache
[0].index_mode
|| kcache
[1].index_mode
|| kcache
[2].index_mode
|| kcache
[3].index_mode
) {
1092 if (bc
->chip_class
< EVERGREEN
)
1094 bc
->cf_last
->eg_alu_extended
= 1;
1100 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1102 struct r600_bytecode_alu alu
;
1105 for (i
= 0; i
< 4; i
++) {
1106 memset(&alu
, 0, sizeof(alu
));
1107 alu
.op
= ALU_OP0_NOP
;
1108 alu
.src
[0].chan
= i
;
1110 alu
.last
= (i
== 3);
1111 r
= r600_bytecode_add_alu(bc
, &alu
);
1118 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1119 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1121 struct r600_bytecode_alu alu
;
1127 /* hack to avoid making MOVA the last instruction in the clause */
1128 if ((bc
->cf_last
->ndw
>>1) >= 110)
1129 bc
->force_add_cf
= 1;
1131 memset(&alu
, 0, sizeof(alu
));
1132 alu
.op
= ALU_OP1_MOVA_GPR_INT
;
1133 alu
.src
[0].sel
= bc
->ar_reg
;
1134 alu
.src
[0].chan
= bc
->ar_chan
;
1136 alu
.index_mode
= INDEX_MODE_LOOP
;
1137 r
= r600_bytecode_add_alu(bc
, &alu
);
1141 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1146 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1147 static int load_ar(struct r600_bytecode
*bc
)
1149 struct r600_bytecode_alu alu
;
1152 if (bc
->ar_handling
)
1153 return load_ar_r6xx(bc
);
1158 /* hack to avoid making MOVA the last instruction in the clause */
1159 if ((bc
->cf_last
->ndw
>>1) >= 110)
1160 bc
->force_add_cf
= 1;
1162 memset(&alu
, 0, sizeof(alu
));
1163 alu
.op
= ALU_OP1_MOVA_INT
;
1164 alu
.src
[0].sel
= bc
->ar_reg
;
1165 alu
.src
[0].chan
= bc
->ar_chan
;
1167 r
= r600_bytecode_add_alu(bc
, &alu
);
1171 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1176 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
,
1177 const struct r600_bytecode_alu
*alu
, unsigned type
)
1179 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1180 struct r600_bytecode_alu
*lalu
;
1185 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1188 /* will fail later since alu does not support it. */
1189 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1192 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->op
!= type
) {
1193 /* check if we could add it anyway */
1194 if (bc
->cf_last
->op
== CF_OP_ALU
&&
1195 type
== CF_OP_ALU_PUSH_BEFORE
) {
1196 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1197 if (lalu
->execute_mask
) {
1198 bc
->force_add_cf
= 1;
1203 bc
->force_add_cf
= 1;
1206 /* cf can contains only alu or only vtx or only tex */
1207 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1208 r
= r600_bytecode_add_cf(bc
);
1214 bc
->cf_last
->op
= type
;
1216 /* Load index register if required */
1217 if (bc
->chip_class
>= EVERGREEN
) {
1218 for (i
= 0; i
< 3; i
++)
1219 if (nalu
->src
[i
].kc_bank
&& nalu
->src
[i
].kc_rel
)
1220 egcm_load_index_reg(bc
, 0, true);
1223 /* Check AR usage and load it if required */
1224 for (i
= 0; i
< 3; i
++)
1225 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1228 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1231 /* Setup the kcache for this ALU instruction. This will start a new
1232 * ALU clause if needed. */
1233 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1238 if (!bc
->cf_last
->curr_bs_head
) {
1239 bc
->cf_last
->curr_bs_head
= nalu
;
1241 /* number of gpr == the last gpr used in any alu */
1242 for (i
= 0; i
< 3; i
++) {
1243 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1244 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1246 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1247 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1248 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
, nalu
->src
[i
].abs
);
1250 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1251 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1253 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1254 /* each alu use 2 dwords */
1255 bc
->cf_last
->ndw
+= 2;
1258 /* process cur ALU instructions for bank swizzle */
1260 uint32_t literal
[4];
1262 struct r600_bytecode_alu
*slots
[5];
1263 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1264 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1268 if (bc
->cf_last
->prev_bs_head
) {
1269 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1274 if (bc
->cf_last
->prev_bs_head
) {
1275 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1280 r
= check_and_set_bank_swizzle(bc
, slots
);
1284 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1286 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1291 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1293 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1295 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1296 bc
->force_add_cf
= 1;
1299 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1300 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1301 bc
->cf_last
->curr_bs_head
= NULL
;
1304 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1305 insert_nop_r6xx(bc
);
1310 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1312 return r600_bytecode_add_alu_type(bc
, alu
, CF_OP_ALU
);
1315 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1317 switch (bc
->chip_class
) {
1327 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1332 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1334 return !((r600_isa_cf(bc
->cf_last
->op
)->flags
& CF_FETCH
) &&
1335 (bc
->chip_class
== CAYMAN
||
1336 bc
->cf_last
->op
!= CF_OP_TEX
));
1339 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1341 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1346 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1348 /* Load index register if required */
1349 if (bc
->chip_class
>= EVERGREEN
) {
1350 if (vtx
->buffer_index_mode
)
1351 egcm_load_index_reg(bc
, 0, false);
1354 /* cf can contains only alu or only vtx or only tex */
1355 if (bc
->cf_last
== NULL
||
1356 last_inst_was_not_vtx_fetch(bc
) ||
1358 r
= r600_bytecode_add_cf(bc
);
1363 switch (bc
->chip_class
) {
1367 bc
->cf_last
->op
= CF_OP_VTX
;
1370 bc
->cf_last
->op
= CF_OP_TEX
;
1373 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1378 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1379 /* each fetch use 4 dwords */
1380 bc
->cf_last
->ndw
+= 4;
1382 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1383 bc
->force_add_cf
= 1;
1385 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1386 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1391 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1393 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1398 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1400 /* Load index register if required */
1401 if (bc
->chip_class
>= EVERGREEN
) {
1402 if (tex
->sampler_index_mode
|| tex
->resource_index_mode
)
1403 egcm_load_index_reg(bc
, 1, false);
1406 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1407 if (bc
->cf_last
!= NULL
&&
1408 bc
->cf_last
->op
== CF_OP_TEX
) {
1409 struct r600_bytecode_tex
*ttex
;
1410 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1411 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1412 bc
->force_add_cf
= 1;
1416 /* slight hack to make gradients always go into same cf */
1417 if (ntex
->op
== FETCH_OP_SET_GRADIENTS_H
)
1418 bc
->force_add_cf
= 1;
1421 /* cf can contains only alu or only vtx or only tex */
1422 if (bc
->cf_last
== NULL
||
1423 bc
->cf_last
->op
!= CF_OP_TEX
||
1425 r
= r600_bytecode_add_cf(bc
);
1430 bc
->cf_last
->op
= CF_OP_TEX
;
1432 if (ntex
->src_gpr
>= bc
->ngpr
) {
1433 bc
->ngpr
= ntex
->src_gpr
+ 1;
1435 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1436 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1438 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1439 /* each texture fetch use 4 dwords */
1440 bc
->cf_last
->ndw
+= 4;
1442 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1443 bc
->force_add_cf
= 1;
1447 int r600_bytecode_add_gds(struct r600_bytecode
*bc
, const struct r600_bytecode_gds
*gds
)
1449 struct r600_bytecode_gds
*ngds
= r600_bytecode_gds();
1454 memcpy(ngds
, gds
, sizeof(struct r600_bytecode_gds
));
1456 if (bc
->cf_last
== NULL
||
1457 bc
->cf_last
->op
!= CF_OP_GDS
||
1459 r
= r600_bytecode_add_cf(bc
);
1464 bc
->cf_last
->op
= CF_OP_GDS
;
1467 LIST_ADDTAIL(&ngds
->list
, &bc
->cf_last
->gds
);
1468 bc
->cf_last
->ndw
+= 4; /* each GDS uses 4 dwords */
1469 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1470 bc
->force_add_cf
= 1;
1474 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, unsigned op
)
1477 r
= r600_bytecode_add_cf(bc
);
1481 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1482 bc
->cf_last
->op
= op
;
1486 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1488 return r600_bytecode_add_cfinst(bc
, CF_OP_CF_END
);
1491 /* common to all 3 families */
1492 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1494 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1495 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1496 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1497 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1498 if (bc
->chip_class
< CAYMAN
)
1499 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1501 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1502 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1503 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1504 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1505 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1506 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1507 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1508 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1509 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1510 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1511 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1512 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1513 if (bc
->chip_class
>= EVERGREEN
)
1514 bc
->bytecode
[id
] |= ((vtx
->buffer_index_mode
& 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1515 if (bc
->chip_class
< CAYMAN
)
1516 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1518 bc
->bytecode
[id
++] = 0;
1522 /* common to all 3 families */
1523 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1525 bc
->bytecode
[id
] = S_SQ_TEX_WORD0_TEX_INST(
1526 r600_isa_fetch_opcode(bc
->isa
->hw_class
, tex
->op
)) |
1527 EG_S_SQ_TEX_WORD0_INST_MOD(tex
->inst_mod
) |
1528 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1529 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1530 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1531 if (bc
->chip_class
>= EVERGREEN
)
1532 bc
->bytecode
[id
] |= ((tex
->sampler_index_mode
& 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1533 ((tex
->resource_index_mode
& 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1535 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1536 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1537 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1538 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1539 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1540 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1541 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1542 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1543 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1544 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1545 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1546 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1547 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1548 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1549 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1550 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1551 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1552 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1553 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1554 bc
->bytecode
[id
++] = 0;
1558 /* r600 only, r700/eg bits in r700_asm.c */
1559 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1561 unsigned opcode
= r600_isa_alu_opcode(bc
->isa
->hw_class
, alu
->op
);
1563 /* don't replace gpr by pv or ps for destination register */
1564 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1565 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1566 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1567 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1568 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1569 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1570 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1571 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1572 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1573 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1574 S_SQ_ALU_WORD0_LAST(alu
->last
);
1577 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1578 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1579 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1580 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1581 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1582 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1583 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1584 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1585 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1586 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode
) |
1587 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1589 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1590 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1591 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1592 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1593 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1594 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1595 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1596 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1597 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode
) |
1598 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1599 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1600 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1605 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1607 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1608 *bytecode
++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600
, cf
->op
)) |
1609 S_SQ_CF_WORD1_BARRIER(1) |
1610 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1613 /* common for r600/r700 - eg in eg_asm.c */
1614 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1616 unsigned id
= cf
->id
;
1617 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1618 unsigned opcode
= r600_isa_cf_opcode(bc
->isa
->hw_class
, cf
->op
);
1621 if (cf
->op
== CF_NATIVE
) {
1622 bc
->bytecode
[id
++] = cf
->isa
[0];
1623 bc
->bytecode
[id
++] = cf
->isa
[1];
1624 } else if (cfop
->flags
& CF_ALU
) {
1625 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1626 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1627 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1628 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1630 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode
) |
1631 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1632 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1633 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1634 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1635 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1636 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1637 } else if (cfop
->flags
& CF_FETCH
) {
1638 if (bc
->chip_class
== R700
)
1639 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1641 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1642 } else if (cfop
->flags
& CF_EXP
) {
1643 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1644 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1645 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1646 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1647 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1648 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1649 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1650 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1651 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1652 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1653 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1654 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1655 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1656 } else if (cfop
->flags
& CF_MEM
) {
1657 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1658 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1659 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1660 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1661 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1662 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1663 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1664 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1665 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
) |
1666 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1667 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1669 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1670 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(opcode
) |
1671 S_SQ_CF_WORD1_BARRIER(1) |
1672 S_SQ_CF_WORD1_COND(cf
->cond
) |
1673 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
) |
1674 S_SQ_CF_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1679 int r600_bytecode_build(struct r600_bytecode
*bc
)
1681 struct r600_bytecode_cf
*cf
;
1682 struct r600_bytecode_alu
*alu
;
1683 struct r600_bytecode_vtx
*vtx
;
1684 struct r600_bytecode_tex
*tex
;
1685 struct r600_bytecode_gds
*gds
;
1686 uint32_t literal
[4];
1691 if (!bc
->nstack
) { // If not 0, Stack_size already provided by llvm
1692 if (bc
->stack
.max_entries
)
1693 bc
->nstack
= bc
->stack
.max_entries
;
1694 else if (bc
->type
== PIPE_SHADER_VERTEX
||
1695 bc
->type
== PIPE_SHADER_TESS_EVAL
||
1696 bc
->type
== PIPE_SHADER_TESS_CTRL
)
1700 /* first path compute addr of each CF block */
1701 /* addr start after all the CF instructions */
1702 addr
= bc
->cf_last
->id
+ 2;
1703 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1704 if (r600_isa_cf(cf
->op
)->flags
& CF_FETCH
) {
1706 addr
&= 0xFFFFFFFCUL
;
1710 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1713 bc
->bytecode
= calloc(4, bc
->ndw
);
1714 if (bc
->bytecode
== NULL
)
1716 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1717 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1719 if (bc
->chip_class
>= EVERGREEN
)
1720 r
= eg_bytecode_cf_build(bc
, cf
);
1722 r
= r600_bytecode_cf_build(bc
, cf
);
1725 if (cfop
->flags
& CF_ALU
) {
1727 memset(literal
, 0, sizeof(literal
));
1728 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1729 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
1732 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
1733 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
1735 switch(bc
->chip_class
) {
1737 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
1740 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
1744 r
= eg_bytecode_alu_build(bc
, alu
, addr
);
1747 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
1754 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
1755 bc
->bytecode
[addr
++] = literal
[i
];
1758 memset(literal
, 0, sizeof(literal
));
1761 } else if (cf
->op
== CF_OP_VTX
) {
1762 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1763 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1768 } else if (cf
->op
== CF_OP_GDS
) {
1769 assert(bc
->chip_class
>= EVERGREEN
);
1770 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
1771 r
= eg_bytecode_gds_build(bc
, gds
, addr
);
1776 } else if (cf
->op
== CF_OP_TEX
) {
1777 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1778 assert(bc
->chip_class
>= EVERGREEN
);
1779 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1784 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1785 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
1795 void r600_bytecode_clear(struct r600_bytecode
*bc
)
1797 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
1800 bc
->bytecode
= NULL
;
1802 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
1803 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
1804 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
1805 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
1806 struct r600_bytecode_gds
*gds
= NULL
, *next_gds
;
1808 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
1812 LIST_INITHEAD(&cf
->alu
);
1814 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
1818 LIST_INITHEAD(&cf
->tex
);
1820 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
1824 LIST_INITHEAD(&cf
->vtx
);
1826 LIST_FOR_EACH_ENTRY_SAFE(gds
, next_gds
, &cf
->gds
, list
) {
1830 LIST_INITHEAD(&cf
->gds
);
1835 LIST_INITHEAD(&cf
->list
);
1838 static int print_swizzle(unsigned swz
)
1840 const char * swzchars
= "xyzw01?_";
1841 assert(swz
<8 && swz
!= 6);
1842 return fprintf(stderr
, "%c", swzchars
[swz
]);
1845 static int print_sel(unsigned sel
, unsigned rel
, unsigned index_mode
,
1846 unsigned need_brackets
)
1849 if (rel
&& index_mode
>= 5 && sel
< 128)
1850 o
+= fprintf(stderr
, "G");
1851 if (rel
|| need_brackets
) {
1852 o
+= fprintf(stderr
, "[");
1854 o
+= fprintf(stderr
, "%d", sel
);
1856 if (index_mode
== 0 || index_mode
== 6)
1857 o
+= fprintf(stderr
, "+AR");
1858 else if (index_mode
== 4)
1859 o
+= fprintf(stderr
, "+AL");
1861 if (rel
|| need_brackets
) {
1862 o
+= fprintf(stderr
, "]");
1867 static int print_dst(struct r600_bytecode_alu
*alu
)
1870 unsigned sel
= alu
->dst
.sel
;
1871 char reg_char
= 'R';
1872 if (sel
> 128 - 4) { /* clause temporary gpr */
1877 if (alu_writes(alu
)) {
1878 o
+= fprintf(stderr
, "%c", reg_char
);
1879 o
+= print_sel(alu
->dst
.sel
, alu
->dst
.rel
, alu
->index_mode
, 0);
1881 o
+= fprintf(stderr
, "__");
1883 o
+= fprintf(stderr
, ".");
1884 o
+= print_swizzle(alu
->dst
.chan
);
1888 static int print_src(struct r600_bytecode_alu
*alu
, unsigned idx
)
1891 struct r600_bytecode_alu_src
*src
= &alu
->src
[idx
];
1892 unsigned sel
= src
->sel
, need_sel
= 1, need_chan
= 1, need_brackets
= 0;
1895 o
+= fprintf(stderr
,"-");
1897 o
+= fprintf(stderr
,"|");
1899 if (sel
< 128 - 4) {
1900 o
+= fprintf(stderr
, "R");
1901 } else if (sel
< 128) {
1902 o
+= fprintf(stderr
, "T");
1904 } else if (sel
< 160) {
1905 o
+= fprintf(stderr
, "KC0");
1908 } else if (sel
< 192) {
1909 o
+= fprintf(stderr
, "KC1");
1912 } else if (sel
>= 512) {
1913 o
+= fprintf(stderr
, "C%d", src
->kc_bank
);
1916 } else if (sel
>= 448) {
1917 o
+= fprintf(stderr
, "Param");
1920 } else if (sel
>= 288) {
1921 o
+= fprintf(stderr
, "KC3");
1924 } else if (sel
>= 256) {
1925 o
+= fprintf(stderr
, "KC2");
1932 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A
:
1933 o
+= fprintf(stderr
, "LDS_A[0x%08X]", src
->value
);
1935 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B
:
1936 o
+= fprintf(stderr
, "LDS_B[0x%08X]", src
->value
);
1938 case EG_V_SQ_ALU_SRC_LDS_OQ_A
:
1939 o
+= fprintf(stderr
, "LDS_OQ_A");
1942 case EG_V_SQ_ALU_SRC_LDS_OQ_B
:
1943 o
+= fprintf(stderr
, "LDS_OQ_B");
1946 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
:
1947 o
+= fprintf(stderr
, "LDS_OQ_A_POP");
1950 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP
:
1951 o
+= fprintf(stderr
, "LDS_OQ_B_POP");
1954 case V_SQ_ALU_SRC_PS
:
1955 o
+= fprintf(stderr
, "PS");
1957 case V_SQ_ALU_SRC_PV
:
1958 o
+= fprintf(stderr
, "PV");
1961 case V_SQ_ALU_SRC_LITERAL
:
1962 o
+= fprintf(stderr
, "[0x%08X %f]", src
->value
, u_bitcast_u2f(src
->value
));
1964 case V_SQ_ALU_SRC_0_5
:
1965 o
+= fprintf(stderr
, "0.5");
1967 case V_SQ_ALU_SRC_M_1_INT
:
1968 o
+= fprintf(stderr
, "-1");
1970 case V_SQ_ALU_SRC_1_INT
:
1971 o
+= fprintf(stderr
, "1");
1973 case V_SQ_ALU_SRC_1
:
1974 o
+= fprintf(stderr
, "1.0");
1976 case V_SQ_ALU_SRC_0
:
1977 o
+= fprintf(stderr
, "0");
1980 o
+= fprintf(stderr
, "??IMM_%d", sel
);
1986 o
+= print_sel(sel
, src
->rel
, alu
->index_mode
, need_brackets
);
1989 o
+= fprintf(stderr
, ".");
1990 o
+= print_swizzle(src
->chan
);
1994 o
+= fprintf(stderr
,"|");
1999 static int print_indent(int p
, int c
)
2003 o
+= fprintf(stderr
, " ");
2007 void r600_bytecode_disasm(struct r600_bytecode
*bc
)
2009 const char *index_mode
[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2010 static int index
= 0;
2011 struct r600_bytecode_cf
*cf
= NULL
;
2012 struct r600_bytecode_alu
*alu
= NULL
;
2013 struct r600_bytecode_vtx
*vtx
= NULL
;
2014 struct r600_bytecode_tex
*tex
= NULL
;
2015 struct r600_bytecode_gds
*gds
= NULL
;
2017 unsigned i
, id
, ngr
= 0, last
;
2018 uint32_t literal
[4];
2022 switch (bc
->chip_class
) {
2037 fprintf(stderr
, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2038 bc
->ndw
, bc
->ngpr
, bc
->nstack
);
2039 fprintf(stderr
, "shader %d -- %c\n", index
++, chip
);
2041 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2043 if (cf
->op
== CF_NATIVE
) {
2044 fprintf(stderr
, "%04d %08X %08X CF_NATIVE\n", id
, bc
->bytecode
[id
],
2045 bc
->bytecode
[id
+ 1]);
2047 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
2048 if (cfop
->flags
& CF_ALU
) {
2049 if (cf
->eg_alu_extended
) {
2050 fprintf(stderr
, "%04d %08X %08X %s\n", id
, bc
->bytecode
[id
],
2051 bc
->bytecode
[id
+ 1], "ALU_EXT");
2054 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2055 bc
->bytecode
[id
+ 1], cfop
->name
);
2056 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 2, cf
->addr
);
2057 for (i
= 0; i
< 4; ++i
) {
2058 if (cf
->kcache
[i
].mode
) {
2059 int c_start
= (cf
->kcache
[i
].addr
<< 4);
2060 int c_end
= c_start
+ (cf
->kcache
[i
].mode
<< 4);
2061 fprintf(stderr
, "KC%d[CB%d:%d-%d%s%s] ",
2062 i
, cf
->kcache
[i
].bank
, c_start
, c_end
,
2063 cf
->kcache
[i
].index_mode
? " " : "",
2064 cf
->kcache
[i
].index_mode
? index_mode
[cf
->kcache
[i
].index_mode
] : "");
2067 fprintf(stderr
, "\n");
2068 } else if (cfop
->flags
& CF_FETCH
) {
2069 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2070 bc
->bytecode
[id
+ 1], cfop
->name
);
2071 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 4, cf
->addr
);
2072 fprintf(stderr
, "\n");
2073 } else if (cfop
->flags
& CF_EXP
) {
2075 const char *exp_type
[] = {"PIXEL", "POS ", "PARAM"};
2076 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2077 bc
->bytecode
[id
+ 1], cfop
->name
);
2078 o
+= print_indent(o
, 43);
2079 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2080 if (cf
->output
.burst_count
> 1) {
2081 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2082 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2084 o
+= print_indent(o
, 55);
2085 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2086 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2088 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2089 o
+= print_indent(o
, 55);
2090 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2093 o
+= print_swizzle(cf
->output
.swizzle_x
);
2094 o
+= print_swizzle(cf
->output
.swizzle_y
);
2095 o
+= print_swizzle(cf
->output
.swizzle_z
);
2096 o
+= print_swizzle(cf
->output
.swizzle_w
);
2098 print_indent(o
, 67);
2100 fprintf(stderr
, " ES:%X ", cf
->output
.elem_size
);
2102 fprintf(stderr
, "NO_BARRIER ");
2103 if (cf
->end_of_program
)
2104 fprintf(stderr
, "EOP ");
2105 fprintf(stderr
, "\n");
2106 } else if (r600_isa_cf(cf
->op
)->flags
& CF_MEM
) {
2108 const char *exp_type
[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2110 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
,
2111 bc
->bytecode
[id
], bc
->bytecode
[id
+ 1], cfop
->name
);
2112 o
+= print_indent(o
, 43);
2113 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2114 if (cf
->output
.burst_count
> 1) {
2115 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2116 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2117 o
+= print_indent(o
, 55);
2118 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2119 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2121 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2122 o
+= print_indent(o
, 55);
2123 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2125 for (i
= 0; i
< 4; ++i
) {
2126 if (cf
->output
.comp_mask
& (1 << i
))
2127 o
+= print_swizzle(i
);
2129 o
+= print_swizzle(7);
2132 if (cf
->output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
)
2133 o
+= fprintf(stderr
, " R%d", cf
->output
.index_gpr
);
2135 o
+= print_indent(o
, 67);
2137 fprintf(stderr
, " ES:%i ", cf
->output
.elem_size
);
2138 if (cf
->output
.array_size
!= 0xFFF)
2139 fprintf(stderr
, "AS:%i ", cf
->output
.array_size
);
2141 fprintf(stderr
, "NO_BARRIER ");
2142 if (cf
->end_of_program
)
2143 fprintf(stderr
, "EOP ");
2144 fprintf(stderr
, "\n");
2146 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2147 bc
->bytecode
[id
+ 1], cfop
->name
);
2148 fprintf(stderr
, "@%d ", cf
->cf_addr
);
2150 fprintf(stderr
, "CND:%X ", cf
->cond
);
2152 fprintf(stderr
, "POP:%X ", cf
->pop_count
);
2153 if (cf
->count
&& (cfop
->flags
& CF_EMIT
))
2154 fprintf(stderr
, "STREAM%d ", cf
->count
);
2155 if (cf
->end_of_program
)
2156 fprintf(stderr
, "EOP ");
2157 fprintf(stderr
, "\n");
2164 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2165 const char *omod_str
[] = {"","*2","*4","/2"};
2166 const struct alu_op_info
*aop
= r600_isa_alu(alu
->op
);
2169 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2170 o
+= fprintf(stderr
, " %04d %08X %08X ", id
, bc
->bytecode
[id
], bc
->bytecode
[id
+1]);
2172 o
+= fprintf(stderr
, "%4d ", ++ngr
);
2174 o
+= fprintf(stderr
, " ");
2175 o
+= fprintf(stderr
, "%c%c %c ", alu
->execute_mask
? 'M':' ',
2176 alu
->update_pred
? 'P':' ',
2177 alu
->pred_sel
? alu
->pred_sel
==2 ? '0':'1':' ');
2179 o
+= fprintf(stderr
, "%s%s%s ", aop
->name
,
2180 omod_str
[alu
->omod
], alu
->dst
.clamp
? "_sat":"");
2182 o
+= print_indent(o
,60);
2183 o
+= print_dst(alu
);
2184 for (i
= 0; i
< aop
->src_count
; ++i
) {
2185 o
+= fprintf(stderr
, i
== 0 ? ", ": ", ");
2186 o
+= print_src(alu
, i
);
2189 if (alu
->bank_swizzle
) {
2190 o
+= print_indent(o
,75);
2191 o
+= fprintf(stderr
, " BS:%d", alu
->bank_swizzle
);
2194 fprintf(stderr
, "\n");
2198 for (i
= 0; i
< nliteral
; i
++, id
++) {
2199 float *f
= (float*)(bc
->bytecode
+ id
);
2200 o
= fprintf(stderr
, " %04d %08X", id
, bc
->bytecode
[id
]);
2201 print_indent(o
, 60);
2202 fprintf(stderr
, " %f (%d)\n", *f
, *(bc
->bytecode
+ id
));
2210 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2212 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2213 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2215 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(tex
->op
)->name
);
2217 o
+= print_indent(o
, 50);
2219 o
+= fprintf(stderr
, "R%d.", tex
->dst_gpr
);
2220 o
+= print_swizzle(tex
->dst_sel_x
);
2221 o
+= print_swizzle(tex
->dst_sel_y
);
2222 o
+= print_swizzle(tex
->dst_sel_z
);
2223 o
+= print_swizzle(tex
->dst_sel_w
);
2225 o
+= fprintf(stderr
, ", R%d.", tex
->src_gpr
);
2226 o
+= print_swizzle(tex
->src_sel_x
);
2227 o
+= print_swizzle(tex
->src_sel_y
);
2228 o
+= print_swizzle(tex
->src_sel_z
);
2229 o
+= print_swizzle(tex
->src_sel_w
);
2231 o
+= fprintf(stderr
, ", RID:%d", tex
->resource_id
);
2232 o
+= fprintf(stderr
, ", SID:%d ", tex
->sampler_id
);
2234 if (tex
->sampler_index_mode
)
2235 fprintf(stderr
, "SQ_%s ", index_mode
[tex
->sampler_index_mode
]);
2238 fprintf(stderr
, "LB:%d ", tex
->lod_bias
);
2240 fprintf(stderr
, "CT:%c%c%c%c ",
2241 tex
->coord_type_x
? 'N' : 'U',
2242 tex
->coord_type_y
? 'N' : 'U',
2243 tex
->coord_type_z
? 'N' : 'U',
2244 tex
->coord_type_w
? 'N' : 'U');
2247 fprintf(stderr
, "OX:%d ", tex
->offset_x
);
2249 fprintf(stderr
, "OY:%d ", tex
->offset_y
);
2251 fprintf(stderr
, "OZ:%d ", tex
->offset_z
);
2254 fprintf(stderr
, "\n");
2257 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2259 const char * fetch_type
[] = {"VERTEX", "INSTANCE", ""};
2260 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2261 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2263 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(vtx
->op
)->name
);
2265 o
+= print_indent(o
, 50);
2267 o
+= fprintf(stderr
, "R%d.", vtx
->dst_gpr
);
2268 o
+= print_swizzle(vtx
->dst_sel_x
);
2269 o
+= print_swizzle(vtx
->dst_sel_y
);
2270 o
+= print_swizzle(vtx
->dst_sel_z
);
2271 o
+= print_swizzle(vtx
->dst_sel_w
);
2273 o
+= fprintf(stderr
, ", R%d.", vtx
->src_gpr
);
2274 o
+= print_swizzle(vtx
->src_sel_x
);
2277 fprintf(stderr
, " +%db", vtx
->offset
);
2279 o
+= print_indent(o
, 55);
2281 fprintf(stderr
, ", RID:%d ", vtx
->buffer_id
);
2283 fprintf(stderr
, "%s ", fetch_type
[vtx
->fetch_type
]);
2285 if (bc
->chip_class
< CAYMAN
&& vtx
->mega_fetch_count
)
2286 fprintf(stderr
, "MFC:%d ", vtx
->mega_fetch_count
);
2288 if (bc
->chip_class
>= EVERGREEN
&& vtx
->buffer_index_mode
)
2289 fprintf(stderr
, "SQ_%s ", index_mode
[vtx
->buffer_index_mode
]);
2291 fprintf(stderr
, "UCF:%d ", vtx
->use_const_fields
);
2292 fprintf(stderr
, "FMT(DTA:%d ", vtx
->data_format
);
2293 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2294 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2295 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2300 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
2302 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2303 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2305 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(gds
->op
)->name
);
2307 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2308 o
+= fprintf(stderr
, "R%d.", gds
->dst_gpr
);
2309 o
+= print_swizzle(gds
->dst_sel_x
);
2310 o
+= print_swizzle(gds
->dst_sel_y
);
2311 o
+= print_swizzle(gds
->dst_sel_z
);
2312 o
+= print_swizzle(gds
->dst_sel_w
);
2315 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr
);
2316 o
+= print_swizzle(gds
->src_sel_x
);
2317 o
+= print_swizzle(gds
->src_sel_y
);
2318 o
+= print_swizzle(gds
->src_sel_z
);
2320 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2321 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr2
);
2323 fprintf(stderr
, "\n");
2328 fprintf(stderr
, "--------------------------------------\n");
2331 void r600_vertex_data_type(enum pipe_format pformat
,
2333 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2335 const struct util_format_description
*desc
;
2341 *endian
= ENDIAN_NONE
;
2343 if (pformat
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2344 *format
= FMT_10_11_11_FLOAT
;
2345 *endian
= r600_endian_swap(32);
2349 if (pformat
== PIPE_FORMAT_B5G6R5_UNORM
) {
2350 *format
= FMT_5_6_5
;
2351 *endian
= r600_endian_swap(16);
2355 desc
= util_format_description(pformat
);
2356 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2360 /* Find the first non-VOID channel. */
2361 for (i
= 0; i
< 4; i
++) {
2362 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2367 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2369 switch (desc
->channel
[i
].type
) {
2370 /* Half-floats, floats, ints */
2371 case UTIL_FORMAT_TYPE_FLOAT
:
2372 switch (desc
->channel
[i
].size
) {
2374 switch (desc
->nr_channels
) {
2376 *format
= FMT_16_FLOAT
;
2379 *format
= FMT_16_16_FLOAT
;
2383 *format
= FMT_16_16_16_16_FLOAT
;
2388 switch (desc
->nr_channels
) {
2390 *format
= FMT_32_FLOAT
;
2393 *format
= FMT_32_32_FLOAT
;
2396 *format
= FMT_32_32_32_FLOAT
;
2399 *format
= FMT_32_32_32_32_FLOAT
;
2408 case UTIL_FORMAT_TYPE_UNSIGNED
:
2410 case UTIL_FORMAT_TYPE_SIGNED
:
2411 switch (desc
->channel
[i
].size
) {
2413 switch (desc
->nr_channels
) {
2422 *format
= FMT_8_8_8_8
;
2427 if (desc
->nr_channels
!= 4)
2430 *format
= FMT_2_10_10_10
;
2433 switch (desc
->nr_channels
) {
2438 *format
= FMT_16_16
;
2442 *format
= FMT_16_16_16_16
;
2447 switch (desc
->nr_channels
) {
2452 *format
= FMT_32_32
;
2455 *format
= FMT_32_32_32
;
2458 *format
= FMT_32_32_32_32
;
2470 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2475 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2476 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2477 if (!desc
->channel
[i
].normalized
) {
2478 if (desc
->channel
[i
].pure_integer
)
2486 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2489 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2491 const struct pipe_vertex_element
*elements
)
2493 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2494 struct r600_bytecode bc
;
2495 struct r600_bytecode_vtx vtx
;
2496 const struct util_format_description
*desc
;
2497 unsigned fetch_resource_start
= rctx
->b
.chip_class
>= EVERGREEN
? 0 : 160;
2498 unsigned format
, num_format
, format_comp
, endian
;
2500 int i
, j
, r
, fs_size
;
2501 struct r600_fetch_shader
*shader
;
2502 unsigned no_sb
= rctx
->screen
->b
.debug_flags
& DBG_NO_SB
;
2503 unsigned sb_disasm
= !no_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
2507 memset(&bc
, 0, sizeof(bc
));
2508 r600_bytecode_init(&bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2509 rctx
->screen
->has_compressed_msaa_texturing
);
2513 for (i
= 0; i
< count
; i
++) {
2514 if (elements
[i
].instance_divisor
> 1) {
2515 if (rctx
->b
.chip_class
== CAYMAN
) {
2516 for (j
= 0; j
< 4; j
++) {
2517 struct r600_bytecode_alu alu
;
2518 memset(&alu
, 0, sizeof(alu
));
2519 alu
.op
= ALU_OP2_MULHI_UINT
;
2521 alu
.src
[0].chan
= 3;
2522 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2523 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2524 alu
.dst
.sel
= i
+ 1;
2526 alu
.dst
.write
= j
== 3;
2528 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2529 r600_bytecode_clear(&bc
);
2534 struct r600_bytecode_alu alu
;
2535 memset(&alu
, 0, sizeof(alu
));
2536 alu
.op
= ALU_OP2_MULHI_UINT
;
2538 alu
.src
[0].chan
= 3;
2539 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2540 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2541 alu
.dst
.sel
= i
+ 1;
2545 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2546 r600_bytecode_clear(&bc
);
2553 for (i
= 0; i
< count
; i
++) {
2554 r600_vertex_data_type(elements
[i
].src_format
,
2555 &format
, &num_format
, &format_comp
, &endian
);
2557 desc
= util_format_description(elements
[i
].src_format
);
2559 r600_bytecode_clear(&bc
);
2560 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2564 if (elements
[i
].src_offset
> 65535) {
2565 r600_bytecode_clear(&bc
);
2566 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2570 memset(&vtx
, 0, sizeof(vtx
));
2571 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2572 vtx
.fetch_type
= elements
[i
].instance_divisor
? SQ_VTX_FETCH_INSTANCE_DATA
: SQ_VTX_FETCH_VERTEX_DATA
;
2573 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2574 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2575 vtx
.mega_fetch_count
= 0x1F;
2576 vtx
.dst_gpr
= i
+ 1;
2577 vtx
.dst_sel_x
= desc
->swizzle
[0];
2578 vtx
.dst_sel_y
= desc
->swizzle
[1];
2579 vtx
.dst_sel_z
= desc
->swizzle
[2];
2580 vtx
.dst_sel_w
= desc
->swizzle
[3];
2581 vtx
.data_format
= format
;
2582 vtx
.num_format_all
= num_format
;
2583 vtx
.format_comp_all
= format_comp
;
2584 vtx
.offset
= elements
[i
].src_offset
;
2585 vtx
.endian
= endian
;
2587 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2588 r600_bytecode_clear(&bc
);
2593 r600_bytecode_add_cfinst(&bc
, CF_OP_RET
);
2595 if ((r
= r600_bytecode_build(&bc
))) {
2596 r600_bytecode_clear(&bc
);
2600 if (rctx
->screen
->b
.debug_flags
& DBG_FS
) {
2601 fprintf(stderr
, "--------------------------------------------------------------\n");
2602 fprintf(stderr
, "Vertex elements state:\n");
2603 for (i
= 0; i
< count
; i
++) {
2604 fprintf(stderr
, " ");
2605 util_dump_vertex_element(stderr
, elements
+i
);
2606 fprintf(stderr
, "\n");
2610 r600_bytecode_disasm(&bc
);
2612 fprintf(stderr
, "______________________________________________________________\n");
2614 r600_sb_bytecode_process(rctx
, &bc
, NULL
, 1 /*dump*/, 0 /*optimize*/);
2620 /* Allocate the CSO. */
2621 shader
= CALLOC_STRUCT(r600_fetch_shader
);
2623 r600_bytecode_clear(&bc
);
2627 u_suballocator_alloc(rctx
->allocator_fetch_shader
, fs_size
, 256,
2629 (struct pipe_resource
**)&shader
->buffer
);
2630 if (!shader
->buffer
) {
2631 r600_bytecode_clear(&bc
);
2636 bytecode
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->buffer
, PIPE_TRANSFER_WRITE
| PIPE_TRANSFER_UNSYNCHRONIZED
);
2637 bytecode
+= shader
->offset
/ 4;
2639 if (R600_BIG_ENDIAN
) {
2640 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2641 bytecode
[i
] = util_cpu_to_le32(bc
.bytecode
[i
]);
2644 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2646 rctx
->b
.ws
->buffer_unmap(shader
->buffer
->buf
);
2648 r600_bytecode_clear(&bc
);
2652 void r600_bytecode_alu_read(struct r600_bytecode
*bc
,
2653 struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2656 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2657 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2658 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2659 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2660 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2661 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2662 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2663 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2664 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2665 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2666 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2669 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2670 if (alu
->bank_swizzle
)
2671 alu
->bank_swizzle_force
= alu
->bank_swizzle
;
2672 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2673 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2674 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2675 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2676 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2679 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2680 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2681 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2682 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2683 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2684 G_SQ_ALU_WORD1_OP3_ALU_INST(word1
), /* is_op3 = */ 1);
2687 else /*ALU_DWORD1_OP2*/
2689 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2690 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2691 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2692 G_SQ_ALU_WORD1_OP2_ALU_INST(word1
), /* is_op3 = */ 0);
2693 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2694 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2695 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2697 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);
2702 void r600_bytecode_export_read(struct r600_bytecode
*bc
,
2703 struct r600_bytecode_output
*output
, uint32_t word0
, uint32_t word1
)
2705 output
->array_base
= G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0
);
2706 output
->type
= G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0
);
2707 output
->gpr
= G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0
);
2708 output
->elem_size
= G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0
);
2710 output
->swizzle_x
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1
);
2711 output
->swizzle_y
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1
);
2712 output
->swizzle_z
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1
);
2713 output
->swizzle_w
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1
);
2714 output
->burst_count
= G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1
);
2715 output
->end_of_program
= G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1
);
2716 output
->op
= r600_isa_cf_by_opcode(bc
->isa
,
2717 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1
), 0);
2718 output
->barrier
= G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1
);
2719 output
->array_size
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1
);
2720 output
->comp_mask
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1
);