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r600g: fix queries and predication
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <byteswap.h>
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "r600_pipe.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600_asm.h"
33 #include "r600_formats.h"
34 #include "r600d.h"
35
36 #define NUM_OF_CYCLES 3
37 #define NUM_OF_COMPONENTS 4
38
39 static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
40 {
41 if(alu->is_op3)
42 return 3;
43
44 switch (bc->chip_class) {
45 case R600:
46 case R700:
47 switch (alu->inst) {
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
49 return 0;
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
71 return 2;
72
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
91 return 1;
92 default: R600_ERR(
93 "Need instruction operand number for 0x%x.\n", alu->inst);
94 }
95 break;
96 case EVERGREEN:
97 case CAYMAN:
98 switch (alu->inst) {
99 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
100 return 0;
101 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
103 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
117 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
118 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
124 return 2;
125
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
143 return 1;
144 default: R600_ERR(
145 "Need instruction operand number for 0x%x.\n", alu->inst);
146 }
147 break;
148 }
149
150 return 3;
151 }
152
153 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
154
155 static struct r600_bc_cf *r600_bc_cf(void)
156 {
157 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
158
159 if (cf == NULL)
160 return NULL;
161 LIST_INITHEAD(&cf->list);
162 LIST_INITHEAD(&cf->alu);
163 LIST_INITHEAD(&cf->vtx);
164 LIST_INITHEAD(&cf->tex);
165 return cf;
166 }
167
168 static struct r600_bc_alu *r600_bc_alu(void)
169 {
170 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
171
172 if (alu == NULL)
173 return NULL;
174 LIST_INITHEAD(&alu->list);
175 return alu;
176 }
177
178 static struct r600_bc_vtx *r600_bc_vtx(void)
179 {
180 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
181
182 if (vtx == NULL)
183 return NULL;
184 LIST_INITHEAD(&vtx->list);
185 return vtx;
186 }
187
188 static struct r600_bc_tex *r600_bc_tex(void)
189 {
190 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
191
192 if (tex == NULL)
193 return NULL;
194 LIST_INITHEAD(&tex->list);
195 return tex;
196 }
197
198 void r600_bc_init(struct r600_bc *bc, enum chip_class chip_class)
199 {
200 LIST_INITHEAD(&bc->cf);
201 bc->chip_class = chip_class;
202 }
203
204 static int r600_bc_add_cf(struct r600_bc *bc)
205 {
206 struct r600_bc_cf *cf = r600_bc_cf();
207
208 if (cf == NULL)
209 return -ENOMEM;
210 LIST_ADDTAIL(&cf->list, &bc->cf);
211 if (bc->cf_last)
212 cf->id = bc->cf_last->id + 2;
213 bc->cf_last = cf;
214 bc->ncf++;
215 bc->ndw += 2;
216 bc->force_add_cf = 0;
217 return 0;
218 }
219
220 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
221 {
222 int r;
223
224 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
225 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
226 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
227 output->type == bc->cf_last->output.type &&
228 output->elem_size == bc->cf_last->output.elem_size &&
229 output->swizzle_x == bc->cf_last->output.swizzle_x &&
230 output->swizzle_y == bc->cf_last->output.swizzle_y &&
231 output->swizzle_z == bc->cf_last->output.swizzle_z &&
232 output->swizzle_w == bc->cf_last->output.swizzle_w &&
233 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
234
235 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
236 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
237
238 bc->cf_last->output.end_of_program |= output->end_of_program;
239 bc->cf_last->output.inst = output->inst;
240 bc->cf_last->output.gpr = output->gpr;
241 bc->cf_last->output.array_base = output->array_base;
242 bc->cf_last->output.burst_count += output->burst_count;
243 return 0;
244
245 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
246 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
247
248 bc->cf_last->output.end_of_program |= output->end_of_program;
249 bc->cf_last->output.inst = output->inst;
250 bc->cf_last->output.burst_count += output->burst_count;
251 return 0;
252 }
253 }
254
255 r = r600_bc_add_cf(bc);
256 if (r)
257 return r;
258 bc->cf_last->inst = output->inst;
259 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
260 return 0;
261 }
262
263 /* alu instructions that can ony exits once per group */
264 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
265 {
266 switch (bc->chip_class) {
267 case R600:
268 case R700:
269 return !alu->is_op3 && (
270 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
271 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
272 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
273 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
274 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
275 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
276 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
277 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
278 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
279 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
280 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
281 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
282 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
283 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
284 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
285 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
286 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
287 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
288 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
289 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
290 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
291 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
292 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
293 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
294 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
295 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
296 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
297 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
298 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
299 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
300 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
301 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
302 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
303 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
304 case EVERGREEN:
305 case CAYMAN:
306 default:
307 return !alu->is_op3 && (
308 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
309 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
310 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
311 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
312 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
313 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
314 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
315 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
316 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
317 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
318 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
319 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
320 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
321 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
322 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
323 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
324 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
325 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
326 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
327 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
328 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
329 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
330 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
331 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
332 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
333 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
334 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
335 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
336 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
337 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
338 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
339 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
340 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
341 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
342 }
343 }
344
345 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
346 {
347 switch (bc->chip_class) {
348 case R600:
349 case R700:
350 return !alu->is_op3 && (
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
355 case EVERGREEN:
356 case CAYMAN:
357 default:
358 return !alu->is_op3 && (
359 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
360 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
361 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
362 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
363 }
364 }
365
366 static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
367 {
368 switch (bc->chip_class) {
369 case R600:
370 case R700:
371 return !alu->is_op3 &&
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
373 case EVERGREEN:
374 case CAYMAN:
375 default:
376 return !alu->is_op3 &&
377 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
378 }
379 }
380
381 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
382 {
383 switch (bc->chip_class) {
384 case R600:
385 case R700:
386 return !alu->is_op3 && (
387 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
388 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
389 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
390 case EVERGREEN:
391 case CAYMAN:
392 default:
393 return !alu->is_op3 && (
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
395 }
396 }
397
398 /* alu instructions that can only execute on the vector unit */
399 static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
400 {
401 return is_alu_reduction_inst(bc, alu) ||
402 is_alu_mova_inst(bc, alu) ||
403 (bc->chip_class == EVERGREEN &&
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR);
405 }
406
407 /* alu instructions that can only execute on the trans unit */
408 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
409 {
410 switch (bc->chip_class) {
411 case R600:
412 case R700:
413 if (!alu->is_op3)
414 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
415 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
416 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
417 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
418 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
419 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
420 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
421 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
422 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
423 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
424 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
425 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
426 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
427 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
428 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
429 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
430 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
431 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
432 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
433 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
434 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
435 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
436 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
437 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
438 else
439 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
440 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
441 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
442 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
443 case EVERGREEN:
444 case CAYMAN:
445 default:
446 if (!alu->is_op3)
447 /* Note that FLT_TO_INT_* instructions are vector-only instructions
448 * on Evergreen, despite what the documentation says. FLT_TO_INT
449 * can do both vector and scalar. */
450 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
451 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
452 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
453 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
454 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
455 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
456 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
457 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
458 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
459 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
460 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
461 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
462 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
463 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
464 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
465 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
466 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
467 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
468 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
469 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
470 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
471 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
472 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
473 else
474 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
475 }
476 }
477
478 /* alu instructions that can execute on any unit */
479 static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
480 {
481 return !is_alu_vec_unit_inst(bc, alu) &&
482 !is_alu_trans_unit_inst(bc, alu);
483 }
484
485 static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
486 struct r600_bc_alu *assignment[5])
487 {
488 struct r600_bc_alu *alu;
489 unsigned i, chan, trans;
490 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
491
492 for (i = 0; i < max_slots; i++)
493 assignment[i] = NULL;
494
495 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
496 chan = alu->dst.chan;
497 if (max_slots == 4)
498 trans = 0;
499 else if (is_alu_trans_unit_inst(bc, alu))
500 trans = 1;
501 else if (is_alu_vec_unit_inst(bc, alu))
502 trans = 0;
503 else if (assignment[chan])
504 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
505 else
506 trans = 0;
507
508 if (trans) {
509 if (assignment[4]) {
510 assert(0); /* ALU.Trans has already been allocated. */
511 return -1;
512 }
513 assignment[4] = alu;
514 } else {
515 if (assignment[chan]) {
516 assert(0); /* ALU.chan has already been allocated. */
517 return -1;
518 }
519 assignment[chan] = alu;
520 }
521
522 if (alu->last)
523 break;
524 }
525 return 0;
526 }
527
528 struct alu_bank_swizzle {
529 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
530 int hw_cfile_addr[4];
531 int hw_cfile_elem[4];
532 };
533
534 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
535 [SQ_ALU_VEC_012] = { 0, 1, 2 },
536 [SQ_ALU_VEC_021] = { 0, 2, 1 },
537 [SQ_ALU_VEC_120] = { 1, 2, 0 },
538 [SQ_ALU_VEC_102] = { 1, 0, 2 },
539 [SQ_ALU_VEC_201] = { 2, 0, 1 },
540 [SQ_ALU_VEC_210] = { 2, 1, 0 }
541 };
542
543 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
544 [SQ_ALU_SCL_210] = { 2, 1, 0 },
545 [SQ_ALU_SCL_122] = { 1, 2, 2 },
546 [SQ_ALU_SCL_212] = { 2, 1, 2 },
547 [SQ_ALU_SCL_221] = { 2, 2, 1 }
548 };
549
550 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
551 {
552 int i, cycle, component;
553 /* set up gpr use */
554 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
555 for (component = 0; component < NUM_OF_COMPONENTS; component++)
556 bs->hw_gpr[cycle][component] = -1;
557 for (i = 0; i < 4; i++)
558 bs->hw_cfile_addr[i] = -1;
559 for (i = 0; i < 4; i++)
560 bs->hw_cfile_elem[i] = -1;
561 }
562
563 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
564 {
565 if (bs->hw_gpr[cycle][chan] == -1)
566 bs->hw_gpr[cycle][chan] = sel;
567 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
568 /* Another scalar operation has already used the GPR read port for the channel. */
569 return -1;
570 }
571 return 0;
572 }
573
574 static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
575 {
576 int res, num_res = 4;
577 if (bc->chip_class >= R700) {
578 num_res = 2;
579 chan /= 2;
580 }
581 for (res = 0; res < num_res; ++res) {
582 if (bs->hw_cfile_addr[res] == -1) {
583 bs->hw_cfile_addr[res] = sel;
584 bs->hw_cfile_elem[res] = chan;
585 return 0;
586 } else if (bs->hw_cfile_addr[res] == sel &&
587 bs->hw_cfile_elem[res] == chan)
588 return 0; /* Read for this scalar element already reserved, nothing to do here. */
589 }
590 /* All cfile read ports are used, cannot reference vector element. */
591 return -1;
592 }
593
594 static int is_gpr(unsigned sel)
595 {
596 return (sel >= 0 && sel <= 127);
597 }
598
599 /* CB constants start at 512, and get translated to a kcache index when ALU
600 * clauses are constructed. Note that we handle kcache constants the same way
601 * as (the now gone) cfile constants, is that really required? */
602 static int is_cfile(unsigned sel)
603 {
604 return (sel > 255 && sel < 512) ||
605 (sel > 511 && sel < 4607) || /* Kcache before translation. */
606 (sel > 127 && sel < 192); /* Kcache after translation. */
607 }
608
609 static int is_const(int sel)
610 {
611 return is_cfile(sel) ||
612 (sel >= V_SQ_ALU_SRC_0 &&
613 sel <= V_SQ_ALU_SRC_LITERAL);
614 }
615
616 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
617 struct alu_bank_swizzle *bs, int bank_swizzle)
618 {
619 int r, src, num_src, sel, elem, cycle;
620
621 num_src = r600_bc_get_num_operands(bc, alu);
622 for (src = 0; src < num_src; src++) {
623 sel = alu->src[src].sel;
624 elem = alu->src[src].chan;
625 if (is_gpr(sel)) {
626 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
627 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
628 /* Nothing to do; special-case optimization,
629 * second source uses first source’s reservation. */
630 continue;
631 else {
632 r = reserve_gpr(bs, sel, elem, cycle);
633 if (r)
634 return r;
635 }
636 } else if (is_cfile(sel)) {
637 r = reserve_cfile(bc, bs, sel, elem);
638 if (r)
639 return r;
640 }
641 /* No restrictions on PV, PS, literal or special constants. */
642 }
643 return 0;
644 }
645
646 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
647 struct alu_bank_swizzle *bs, int bank_swizzle)
648 {
649 int r, src, num_src, const_count, sel, elem, cycle;
650
651 num_src = r600_bc_get_num_operands(bc, alu);
652 for (const_count = 0, src = 0; src < num_src; ++src) {
653 sel = alu->src[src].sel;
654 elem = alu->src[src].chan;
655 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
656 if (const_count >= 2)
657 /* More than two references to a constant in
658 * transcendental operation. */
659 return -1;
660 else
661 const_count++;
662 }
663 if (is_cfile(sel)) {
664 r = reserve_cfile(bc, bs, sel, elem);
665 if (r)
666 return r;
667 }
668 }
669 for (src = 0; src < num_src; ++src) {
670 sel = alu->src[src].sel;
671 elem = alu->src[src].chan;
672 if (is_gpr(sel)) {
673 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
674 if (cycle < const_count)
675 /* Cycle for GPR load conflicts with
676 * constant load in transcendental operation. */
677 return -1;
678 r = reserve_gpr(bs, sel, elem, cycle);
679 if (r)
680 return r;
681 }
682 /* PV PS restrictions */
683 if (const_count && (sel == 254 || sel == 255)) {
684 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
685 if (cycle < const_count)
686 return -1;
687 }
688 }
689 return 0;
690 }
691
692 static int check_and_set_bank_swizzle(struct r600_bc *bc,
693 struct r600_bc_alu *slots[5])
694 {
695 struct alu_bank_swizzle bs;
696 int bank_swizzle[5];
697 int i, r = 0, forced = 0;
698 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
699 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
700
701 for (i = 0; i < max_slots; i++) {
702 if (slots[i] && slots[i]->bank_swizzle_force) {
703 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
704 forced = 1;
705 }
706 if (i < 4 && slots[i])
707 scalar_only = false;
708 }
709 if (forced)
710 return 0;
711
712 /* Just check every possible combination of bank swizzle.
713 * Not very efficent, but works on the first try in most of the cases. */
714 for (i = 0; i < 4; i++)
715 bank_swizzle[i] = SQ_ALU_VEC_012;
716 bank_swizzle[4] = SQ_ALU_SCL_210;
717 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
718
719 if (max_slots == 4) {
720 for (i = 0; i < max_slots; i++) {
721 if (bank_swizzle[i] == SQ_ALU_VEC_210)
722 return -1;
723 }
724 }
725 init_bank_swizzle(&bs);
726 if (scalar_only == false) {
727 for (i = 0; i < 4; i++) {
728 if (slots[i]) {
729 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
730 if (r)
731 break;
732 }
733 }
734 } else
735 r = 0;
736
737 if (!r && slots[4] && max_slots == 5) {
738 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
739 }
740 if (!r) {
741 for (i = 0; i < max_slots; i++) {
742 if (slots[i])
743 slots[i]->bank_swizzle = bank_swizzle[i];
744 }
745 return 0;
746 }
747
748 if (scalar_only) {
749 bank_swizzle[4]++;
750 } else {
751 for (i = 0; i < max_slots; i++) {
752 bank_swizzle[i]++;
753 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
754 break;
755 else
756 bank_swizzle[i] = SQ_ALU_VEC_012;
757 }
758 }
759 }
760
761 /* Couldn't find a working swizzle. */
762 return -1;
763 }
764
765 static int replace_gpr_with_pv_ps(struct r600_bc *bc,
766 struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
767 {
768 struct r600_bc_alu *prev[5];
769 int gpr[5], chan[5];
770 int i, j, r, src, num_src;
771 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
772
773 r = assign_alu_units(bc, alu_prev, prev);
774 if (r)
775 return r;
776
777 for (i = 0; i < max_slots; ++i) {
778 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
779 gpr[i] = prev[i]->dst.sel;
780 /* cube writes more than PV.X */
781 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
782 chan[i] = 0;
783 else
784 chan[i] = prev[i]->dst.chan;
785 } else
786 gpr[i] = -1;
787 }
788
789 for (i = 0; i < max_slots; ++i) {
790 struct r600_bc_alu *alu = slots[i];
791 if(!alu)
792 continue;
793
794 num_src = r600_bc_get_num_operands(bc, alu);
795 for (src = 0; src < num_src; ++src) {
796 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
797 continue;
798
799 if (bc->chip_class < CAYMAN) {
800 if (alu->src[src].sel == gpr[4] &&
801 alu->src[src].chan == chan[4]) {
802 alu->src[src].sel = V_SQ_ALU_SRC_PS;
803 alu->src[src].chan = 0;
804 continue;
805 }
806 }
807
808 for (j = 0; j < 4; ++j) {
809 if (alu->src[src].sel == gpr[j] &&
810 alu->src[src].chan == j) {
811 alu->src[src].sel = V_SQ_ALU_SRC_PV;
812 alu->src[src].chan = chan[j];
813 break;
814 }
815 }
816 }
817 }
818
819 return 0;
820 }
821
822 void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
823 {
824 switch(value) {
825 case 0:
826 *sel = V_SQ_ALU_SRC_0;
827 break;
828 case 1:
829 *sel = V_SQ_ALU_SRC_1_INT;
830 break;
831 case -1:
832 *sel = V_SQ_ALU_SRC_M_1_INT;
833 break;
834 case 0x3F800000: /* 1.0f */
835 *sel = V_SQ_ALU_SRC_1;
836 break;
837 case 0x3F000000: /* 0.5f */
838 *sel = V_SQ_ALU_SRC_0_5;
839 break;
840 case 0xBF800000: /* -1.0f */
841 *sel = V_SQ_ALU_SRC_1;
842 *neg ^= 1;
843 break;
844 case 0xBF000000: /* -0.5f */
845 *sel = V_SQ_ALU_SRC_0_5;
846 *neg ^= 1;
847 break;
848 default:
849 *sel = V_SQ_ALU_SRC_LITERAL;
850 break;
851 }
852 }
853
854 /* compute how many literal are needed */
855 static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
856 uint32_t literal[4], unsigned *nliteral)
857 {
858 unsigned num_src = r600_bc_get_num_operands(bc, alu);
859 unsigned i, j;
860
861 for (i = 0; i < num_src; ++i) {
862 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
863 uint32_t value = alu->src[i].value;
864 unsigned found = 0;
865 for (j = 0; j < *nliteral; ++j) {
866 if (literal[j] == value) {
867 found = 1;
868 break;
869 }
870 }
871 if (!found) {
872 if (*nliteral >= 4)
873 return -EINVAL;
874 literal[(*nliteral)++] = value;
875 }
876 }
877 }
878 return 0;
879 }
880
881 static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
882 struct r600_bc_alu *alu,
883 uint32_t literal[4], unsigned nliteral)
884 {
885 unsigned num_src = r600_bc_get_num_operands(bc, alu);
886 unsigned i, j;
887
888 for (i = 0; i < num_src; ++i) {
889 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
890 uint32_t value = alu->src[i].value;
891 for (j = 0; j < nliteral; ++j) {
892 if (literal[j] == value) {
893 alu->src[i].chan = j;
894 break;
895 }
896 }
897 }
898 }
899 }
900
901 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
902 struct r600_bc_alu *alu_prev)
903 {
904 struct r600_bc_alu *prev[5];
905 struct r600_bc_alu *result[5] = { NULL };
906
907 uint32_t literal[4], prev_literal[4];
908 unsigned nliteral = 0, prev_nliteral = 0;
909
910 int i, j, r, src, num_src;
911 int num_once_inst = 0;
912 int have_mova = 0, have_rel = 0;
913 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
914
915 r = assign_alu_units(bc, alu_prev, prev);
916 if (r)
917 return r;
918
919 for (i = 0; i < max_slots; ++i) {
920 struct r600_bc_alu *alu;
921
922 /* check number of literals */
923 if (prev[i]) {
924 if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
925 return 0;
926 if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
927 return 0;
928 if (is_alu_mova_inst(bc, prev[i])) {
929 if (have_rel)
930 return 0;
931 have_mova = 1;
932 }
933 num_once_inst += is_alu_once_inst(bc, prev[i]);
934 }
935 if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
936 return 0;
937
938 /* Let's check used slots. */
939 if (prev[i] && !slots[i]) {
940 result[i] = prev[i];
941 continue;
942 } else if (prev[i] && slots[i]) {
943 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
944 /* Trans unit is still free try to use it. */
945 if (is_alu_any_unit_inst(bc, slots[i])) {
946 result[i] = prev[i];
947 result[4] = slots[i];
948 } else if (is_alu_any_unit_inst(bc, prev[i])) {
949 result[i] = slots[i];
950 result[4] = prev[i];
951 } else
952 return 0;
953 } else
954 return 0;
955 } else if(!slots[i]) {
956 continue;
957 } else
958 result[i] = slots[i];
959
960 alu = slots[i];
961 num_once_inst += is_alu_once_inst(bc, alu);
962
963 /* Let's check dst gpr. */
964 if (alu->dst.rel) {
965 if (have_mova)
966 return 0;
967 have_rel = 1;
968 }
969
970 /* Let's check source gprs */
971 num_src = r600_bc_get_num_operands(bc, alu);
972 for (src = 0; src < num_src; ++src) {
973 if (alu->src[src].rel) {
974 if (have_mova)
975 return 0;
976 have_rel = 1;
977 }
978
979 /* Constants don't matter. */
980 if (!is_gpr(alu->src[src].sel))
981 continue;
982
983 for (j = 0; j < max_slots; ++j) {
984 if (!prev[j] || !prev[j]->dst.write)
985 continue;
986
987 /* If it's relative then we can't determin which gpr is really used. */
988 if (prev[j]->dst.chan == alu->src[src].chan &&
989 (prev[j]->dst.sel == alu->src[src].sel ||
990 prev[j]->dst.rel || alu->src[src].rel))
991 return 0;
992 }
993 }
994 }
995
996 /* more than one PRED_ or KILL_ ? */
997 if (num_once_inst > 1)
998 return 0;
999
1000 /* check if the result can still be swizzlet */
1001 r = check_and_set_bank_swizzle(bc, result);
1002 if (r)
1003 return 0;
1004
1005 /* looks like everything worked out right, apply the changes */
1006
1007 /* undo adding previus literals */
1008 bc->cf_last->ndw -= align(prev_nliteral, 2);
1009
1010 /* sort instructions */
1011 for (i = 0; i < max_slots; ++i) {
1012 slots[i] = result[i];
1013 if (result[i]) {
1014 LIST_DEL(&result[i]->list);
1015 result[i]->last = 0;
1016 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1017 }
1018 }
1019
1020 /* determine new last instruction */
1021 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
1022
1023 /* determine new first instruction */
1024 for (i = 0; i < max_slots; ++i) {
1025 if (result[i]) {
1026 bc->cf_last->curr_bs_head = result[i];
1027 break;
1028 }
1029 }
1030
1031 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1032 bc->cf_last->prev2_bs_head = NULL;
1033
1034 return 0;
1035 }
1036
1037 /* This code handles kcache lines as single blocks of 32 constants. We could
1038 * probably do slightly better by recognizing that we actually have two
1039 * consecutive lines of 16 constants, but the resulting code would also be
1040 * somewhat more complicated. */
1041 static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
1042 {
1043 struct r600_bc_kcache *kcache = bc->cf_last->kcache;
1044 unsigned int required_lines;
1045 unsigned int free_lines = 0;
1046 unsigned int cache_line[3];
1047 unsigned int count = 0;
1048 unsigned int i, j;
1049 int r;
1050
1051 /* Collect required cache lines. */
1052 for (i = 0; i < 3; ++i) {
1053 boolean found = false;
1054 unsigned int line;
1055
1056 if (alu->src[i].sel < 512)
1057 continue;
1058
1059 line = ((alu->src[i].sel - 512) / 32) * 2;
1060
1061 for (j = 0; j < count; ++j) {
1062 if (cache_line[j] == line) {
1063 found = true;
1064 break;
1065 }
1066 }
1067
1068 if (!found)
1069 cache_line[count++] = line;
1070 }
1071
1072 /* This should never actually happen. */
1073 if (count >= 3) return -ENOMEM;
1074
1075 for (i = 0; i < 2; ++i) {
1076 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1077 ++free_lines;
1078 }
1079 }
1080
1081 /* Filter lines pulled in by previous intructions. Note that this is
1082 * only for the required_lines count, we can't remove these from the
1083 * cache_line array since we may have to start a new ALU clause. */
1084 for (i = 0, required_lines = count; i < count; ++i) {
1085 for (j = 0; j < 2; ++j) {
1086 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1087 kcache[j].addr == cache_line[i]) {
1088 --required_lines;
1089 break;
1090 }
1091 }
1092 }
1093
1094 /* Start a new ALU clause if needed. */
1095 if (required_lines > free_lines) {
1096 if ((r = r600_bc_add_cf(bc))) {
1097 return r;
1098 }
1099 bc->cf_last->inst = (type << 3);
1100 kcache = bc->cf_last->kcache;
1101 }
1102
1103 /* Setup the kcache lines. */
1104 for (i = 0; i < count; ++i) {
1105 boolean found = false;
1106
1107 for (j = 0; j < 2; ++j) {
1108 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1109 kcache[j].addr == cache_line[i]) {
1110 found = true;
1111 break;
1112 }
1113 }
1114
1115 if (found) continue;
1116
1117 for (j = 0; j < 2; ++j) {
1118 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1119 kcache[j].bank = 0;
1120 kcache[j].addr = cache_line[i];
1121 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1122 break;
1123 }
1124 }
1125 }
1126
1127 /* Alter the src operands to refer to the kcache. */
1128 for (i = 0; i < 3; ++i) {
1129 static const unsigned int base[] = {128, 160, 256, 288};
1130 unsigned int line;
1131
1132 if (alu->src[i].sel < 512)
1133 continue;
1134
1135 alu->src[i].sel -= 512;
1136 line = (alu->src[i].sel / 32) * 2;
1137
1138 for (j = 0; j < 2; ++j) {
1139 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1140 kcache[j].addr == line) {
1141 alu->src[i].sel &= 0x1f;
1142 alu->src[i].sel += base[j];
1143 break;
1144 }
1145 }
1146 }
1147
1148 return 0;
1149 }
1150
1151 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
1152 {
1153 struct r600_bc_alu *nalu = r600_bc_alu();
1154 struct r600_bc_alu *lalu;
1155 int i, r;
1156
1157 if (nalu == NULL)
1158 return -ENOMEM;
1159 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
1160
1161 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1162 /* check if we could add it anyway */
1163 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1164 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1165 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1166 if (lalu->predicate) {
1167 bc->force_add_cf = 1;
1168 break;
1169 }
1170 }
1171 } else
1172 bc->force_add_cf = 1;
1173 }
1174
1175 /* cf can contains only alu or only vtx or only tex */
1176 if (bc->cf_last == NULL || bc->force_add_cf) {
1177 r = r600_bc_add_cf(bc);
1178 if (r) {
1179 free(nalu);
1180 return r;
1181 }
1182 }
1183 bc->cf_last->inst = (type << 3);
1184
1185 /* Setup the kcache for this ALU instruction. This will start a new
1186 * ALU clause if needed. */
1187 if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
1188 free(nalu);
1189 return r;
1190 }
1191
1192 if (!bc->cf_last->curr_bs_head) {
1193 bc->cf_last->curr_bs_head = nalu;
1194 }
1195 /* number of gpr == the last gpr used in any alu */
1196 for (i = 0; i < 3; i++) {
1197 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1198 bc->ngpr = nalu->src[i].sel + 1;
1199 }
1200 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1201 r600_bc_special_constants(nalu->src[i].value,
1202 &nalu->src[i].sel, &nalu->src[i].neg);
1203 }
1204 if (nalu->dst.sel >= bc->ngpr) {
1205 bc->ngpr = nalu->dst.sel + 1;
1206 }
1207 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1208 /* each alu use 2 dwords */
1209 bc->cf_last->ndw += 2;
1210 bc->ndw += 2;
1211
1212 /* process cur ALU instructions for bank swizzle */
1213 if (nalu->last) {
1214 uint32_t literal[4];
1215 unsigned nliteral;
1216 struct r600_bc_alu *slots[5];
1217 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1218 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1219 if (r)
1220 return r;
1221
1222 if (bc->cf_last->prev_bs_head) {
1223 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1224 if (r)
1225 return r;
1226 }
1227
1228 if (bc->cf_last->prev_bs_head) {
1229 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1230 if (r)
1231 return r;
1232 }
1233
1234 r = check_and_set_bank_swizzle(bc, slots);
1235 if (r)
1236 return r;
1237
1238 for (i = 0, nliteral = 0; i < max_slots; i++) {
1239 if (slots[i]) {
1240 r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
1241 if (r)
1242 return r;
1243 }
1244 }
1245 bc->cf_last->ndw += align(nliteral, 2);
1246
1247 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1248 * worst case */
1249 if ((bc->cf_last->ndw >> 1) >= 120) {
1250 bc->force_add_cf = 1;
1251 }
1252
1253 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1254 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1255 bc->cf_last->curr_bs_head = NULL;
1256 }
1257 return 0;
1258 }
1259
1260 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
1261 {
1262 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1263 }
1264
1265 static unsigned r600_bc_num_tex_and_vtx_instructions(const struct r600_bc *bc)
1266 {
1267 switch (bc->chip_class) {
1268 case R600:
1269 return 8;
1270
1271 case R700:
1272 return 16;
1273
1274 case EVERGREEN:
1275 case CAYMAN:
1276 return 64;
1277
1278 default:
1279 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1280 return 8;
1281 }
1282 }
1283
1284 static inline boolean last_inst_was_vtx_fetch(struct r600_bc *bc)
1285 {
1286 if (bc->chip_class == CAYMAN) {
1287 if (bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC)
1288 return TRUE;
1289 } else {
1290 if (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1291 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC)
1292 return TRUE;
1293 }
1294 return FALSE;
1295 }
1296
1297 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
1298 {
1299 struct r600_bc_vtx *nvtx = r600_bc_vtx();
1300 int r;
1301
1302 if (nvtx == NULL)
1303 return -ENOMEM;
1304 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
1305
1306 /* cf can contains only alu or only vtx or only tex */
1307 if (bc->cf_last == NULL ||
1308 last_inst_was_vtx_fetch(bc) ||
1309 bc->force_add_cf) {
1310 r = r600_bc_add_cf(bc);
1311 if (r) {
1312 free(nvtx);
1313 return r;
1314 }
1315 if (bc->chip_class == CAYMAN)
1316 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1317 else
1318 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1319 }
1320 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1321 /* each fetch use 4 dwords */
1322 bc->cf_last->ndw += 4;
1323 bc->ndw += 4;
1324 if ((bc->cf_last->ndw / 4) >= r600_bc_num_tex_and_vtx_instructions(bc))
1325 bc->force_add_cf = 1;
1326 return 0;
1327 }
1328
1329 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
1330 {
1331 struct r600_bc_tex *ntex = r600_bc_tex();
1332 int r;
1333
1334 if (ntex == NULL)
1335 return -ENOMEM;
1336 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
1337
1338 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1339 if (bc->cf_last != NULL &&
1340 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
1341 struct r600_bc_tex *ttex;
1342 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1343 if (ttex->dst_gpr == ntex->src_gpr) {
1344 bc->force_add_cf = 1;
1345 break;
1346 }
1347 }
1348 /* slight hack to make gradients always go into same cf */
1349 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1350 bc->force_add_cf = 1;
1351 }
1352
1353 /* cf can contains only alu or only vtx or only tex */
1354 if (bc->cf_last == NULL ||
1355 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1356 bc->force_add_cf) {
1357 r = r600_bc_add_cf(bc);
1358 if (r) {
1359 free(ntex);
1360 return r;
1361 }
1362 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1363 }
1364 if (ntex->src_gpr >= bc->ngpr) {
1365 bc->ngpr = ntex->src_gpr + 1;
1366 }
1367 if (ntex->dst_gpr >= bc->ngpr) {
1368 bc->ngpr = ntex->dst_gpr + 1;
1369 }
1370 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1371 /* each texture fetch use 4 dwords */
1372 bc->cf_last->ndw += 4;
1373 bc->ndw += 4;
1374 if ((bc->cf_last->ndw / 4) >= r600_bc_num_tex_and_vtx_instructions(bc))
1375 bc->force_add_cf = 1;
1376 return 0;
1377 }
1378
1379 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
1380 {
1381 int r;
1382 r = r600_bc_add_cf(bc);
1383 if (r)
1384 return r;
1385
1386 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1387 bc->cf_last->inst = inst;
1388 return 0;
1389 }
1390
1391 int cm_bc_add_cf_end(struct r600_bc *bc)
1392 {
1393 return r600_bc_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1394 }
1395
1396 /* common to all 3 families */
1397 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
1398 {
1399 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1400 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1401 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1402 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1403 if (bc->chip_class < CAYMAN)
1404 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1405 id++;
1406 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1407 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1408 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1409 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1410 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1411 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1412 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1413 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1414 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1415 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1416 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1417 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1418 if (bc->chip_class < CAYMAN)
1419 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1420 id++;
1421 bc->bytecode[id++] = 0;
1422 return 0;
1423 }
1424
1425 /* common to all 3 families */
1426 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
1427 {
1428 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1429 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1430 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1431 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1432 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1433 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1434 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1435 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1436 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1437 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1438 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1439 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1440 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1441 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1442 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1443 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1444 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1445 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1446 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1447 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1448 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1449 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1450 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1451 bc->bytecode[id++] = 0;
1452 return 0;
1453 }
1454
1455 /* r600 only, r700/eg bits in r700_asm.c */
1456 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1457 {
1458 /* don't replace gpr by pv or ps for destination register */
1459 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1460 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1461 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1462 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1463 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1464 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1465 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1466 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1467 S_SQ_ALU_WORD0_LAST(alu->last);
1468
1469 if (alu->is_op3) {
1470 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1471 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1472 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1473 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1474 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1475 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1476 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1477 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1478 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1479 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1480 } else {
1481 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1482 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1483 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1484 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1485 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1486 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1487 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1488 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1489 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1490 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1491 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1492 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1493 }
1494 return 0;
1495 }
1496
1497 static void r600_bc_cf_vtx_build(uint32_t *bytecode, const struct r600_bc_cf *cf)
1498 {
1499 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1500 *bytecode++ = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1501 S_SQ_CF_WORD1_BARRIER(1) |
1502 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1503 }
1504
1505 /* common for r600/r700 - eg in eg_asm.c */
1506 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1507 {
1508 unsigned id = cf->id;
1509
1510 switch (cf->inst) {
1511 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1512 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1513 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1514 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1515 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1516 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1517 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1518 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1519
1520 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1521 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1522 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1523 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1524 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1525 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1526 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1527 break;
1528 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1529 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1530 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1531 if (bc->chip_class == R700)
1532 r700_bc_cf_vtx_build(&bc->bytecode[id], cf);
1533 else
1534 r600_bc_cf_vtx_build(&bc->bytecode[id], cf);
1535 break;
1536 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1537 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1538 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1539 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1540 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1541 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1542 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1543 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1544 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1545 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1546 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1547 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1548 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1549 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1550 break;
1551 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1552 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1553 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1554 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1555 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1556 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1557 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1558 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1559 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1560 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1561 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1562 S_SQ_CF_WORD1_BARRIER(1) |
1563 S_SQ_CF_WORD1_COND(cf->cond) |
1564 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1565
1566 break;
1567 default:
1568 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1569 return -EINVAL;
1570 }
1571 return 0;
1572 }
1573
1574 int r600_bc_build(struct r600_bc *bc)
1575 {
1576 struct r600_bc_cf *cf;
1577 struct r600_bc_alu *alu;
1578 struct r600_bc_vtx *vtx;
1579 struct r600_bc_tex *tex;
1580 uint32_t literal[4];
1581 unsigned nliteral;
1582 unsigned addr;
1583 int i, r;
1584
1585 if (bc->callstack[0].max > 0)
1586 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1587 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1588 bc->nstack = 1;
1589 }
1590
1591 /* first path compute addr of each CF block */
1592 /* addr start after all the CF instructions */
1593 addr = bc->cf_last->id + 2;
1594 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1595 switch (cf->inst) {
1596 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1597 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1598 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1599 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1600 break;
1601 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1602 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1603 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1604 /* fetch node need to be 16 bytes aligned*/
1605 addr += 3;
1606 addr &= 0xFFFFFFFCUL;
1607 break;
1608 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1609 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1610 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1611 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1612 break;
1613 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1614 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1615 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1616 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1617 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1618 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1619 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1620 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1621 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1622 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1623 break;
1624 default:
1625 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1626 return -EINVAL;
1627 }
1628 cf->addr = addr;
1629 addr += cf->ndw;
1630 bc->ndw = cf->addr + cf->ndw;
1631 }
1632 free(bc->bytecode);
1633 bc->bytecode = calloc(1, bc->ndw * 4);
1634 if (bc->bytecode == NULL)
1635 return -ENOMEM;
1636 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1637 addr = cf->addr;
1638 if (bc->chip_class >= EVERGREEN)
1639 r = eg_bc_cf_build(bc, cf);
1640 else
1641 r = r600_bc_cf_build(bc, cf);
1642 if (r)
1643 return r;
1644 switch (cf->inst) {
1645 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1646 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1647 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1648 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1649 nliteral = 0;
1650 memset(literal, 0, sizeof(literal));
1651 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1652 r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1653 if (r)
1654 return r;
1655 r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
1656 switch(bc->chip_class) {
1657 case R600:
1658 r = r600_bc_alu_build(bc, alu, addr);
1659 break;
1660 case R700:
1661 case EVERGREEN: /* eg alu is same encoding as r700 */
1662 case CAYMAN: /* eg alu is same encoding as r700 */
1663 r = r700_bc_alu_build(bc, alu, addr);
1664 break;
1665 default:
1666 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1667 return -EINVAL;
1668 }
1669 if (r)
1670 return r;
1671 addr += 2;
1672 if (alu->last) {
1673 for (i = 0; i < align(nliteral, 2); ++i) {
1674 bc->bytecode[addr++] = literal[i];
1675 }
1676 nliteral = 0;
1677 memset(literal, 0, sizeof(literal));
1678 }
1679 }
1680 break;
1681 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1682 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1683 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1684 r = r600_bc_vtx_build(bc, vtx, addr);
1685 if (r)
1686 return r;
1687 addr += 4;
1688 }
1689 break;
1690 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1691 if (bc->chip_class == CAYMAN) {
1692 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1693 r = r600_bc_vtx_build(bc, vtx, addr);
1694 if (r)
1695 return r;
1696 addr += 4;
1697 }
1698 }
1699 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1700 r = r600_bc_tex_build(bc, tex, addr);
1701 if (r)
1702 return r;
1703 addr += 4;
1704 }
1705 break;
1706 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1707 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1708 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1709 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1710 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1711 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1712 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1713 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1714 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1715 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1716 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1717 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1718 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1719 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1720 break;
1721 default:
1722 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1723 return -EINVAL;
1724 }
1725 }
1726 return 0;
1727 }
1728
1729 void r600_bc_clear(struct r600_bc *bc)
1730 {
1731 struct r600_bc_cf *cf = NULL, *next_cf;
1732
1733 free(bc->bytecode);
1734 bc->bytecode = NULL;
1735
1736 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1737 struct r600_bc_alu *alu = NULL, *next_alu;
1738 struct r600_bc_tex *tex = NULL, *next_tex;
1739 struct r600_bc_tex *vtx = NULL, *next_vtx;
1740
1741 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1742 free(alu);
1743 }
1744
1745 LIST_INITHEAD(&cf->alu);
1746
1747 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1748 free(tex);
1749 }
1750
1751 LIST_INITHEAD(&cf->tex);
1752
1753 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1754 free(vtx);
1755 }
1756
1757 LIST_INITHEAD(&cf->vtx);
1758
1759 free(cf);
1760 }
1761
1762 LIST_INITHEAD(&cf->list);
1763 }
1764
1765 void r600_bc_dump(struct r600_bc *bc)
1766 {
1767 struct r600_bc_cf *cf = NULL;
1768 struct r600_bc_alu *alu = NULL;
1769 struct r600_bc_vtx *vtx = NULL;
1770 struct r600_bc_tex *tex = NULL;
1771
1772 unsigned i, id;
1773 uint32_t literal[4];
1774 unsigned nliteral;
1775 char chip = '6';
1776
1777 switch (bc->chip_class) {
1778 case R700:
1779 chip = '7';
1780 break;
1781 case EVERGREEN:
1782 chip = 'E';
1783 break;
1784 case CAYMAN:
1785 chip = 'C';
1786 break;
1787 case R600:
1788 default:
1789 chip = '6';
1790 break;
1791 }
1792 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1793 fprintf(stderr, " %c\n", chip);
1794
1795 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1796 id = cf->id;
1797
1798 switch (cf->inst) {
1799 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1800 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1801 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1802 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1803 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1804 fprintf(stderr, "ADDR:%d ", cf->addr);
1805 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1806 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1807 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1808 id++;
1809 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1810 fprintf(stderr, "INST:%d ", cf->inst);
1811 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1812 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1813 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1814 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1815 break;
1816 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1817 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1818 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1819 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1820 fprintf(stderr, "ADDR:%d\n", cf->addr);
1821 id++;
1822 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1823 fprintf(stderr, "INST:%d ", cf->inst);
1824 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1825 break;
1826 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1827 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1828 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1829 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1830 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1831 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1832 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1833 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1834 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1835 id++;
1836 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1837 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1838 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1839 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1840 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1841 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1842 fprintf(stderr, "INST:%d ", cf->output.inst);
1843 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
1844 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1845 break;
1846 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1847 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1848 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1849 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1850 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1851 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1852 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1853 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1854 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1855 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1856 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1857 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1858 id++;
1859 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1860 fprintf(stderr, "INST:%d ", cf->inst);
1861 fprintf(stderr, "COND:%X ", cf->cond);
1862 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1863 break;
1864 }
1865
1866 id = cf->addr;
1867 nliteral = 0;
1868 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1869 r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1870
1871 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1872 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1873 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1874 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1875 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1876 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1877 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1878 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1879 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1880 fprintf(stderr, "LAST:%d)\n", alu->last);
1881 id++;
1882 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1883 fprintf(stderr, "INST:%d ", alu->inst);
1884 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1885 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1886 fprintf(stderr, "REL:%d ", alu->dst.rel);
1887 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1888 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1889 if (alu->is_op3) {
1890 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1891 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1892 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1893 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1894 } else {
1895 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1896 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1897 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1898 fprintf(stderr, "OMOD:%d ", alu->omod);
1899 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1900 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1901 }
1902
1903 id++;
1904 if (alu->last) {
1905 for (i = 0; i < nliteral; i++, id++) {
1906 float *f = (float*)(bc->bytecode + id);
1907 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1908 }
1909 id += nliteral & 1;
1910 nliteral = 0;
1911 }
1912 }
1913
1914 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1915 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1916 fprintf(stderr, "INST:%d ", tex->inst);
1917 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
1918 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
1919 fprintf(stderr, "REL:%d)\n", tex->src_rel);
1920 id++;
1921 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1922 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
1923 fprintf(stderr, "REL:%d ", tex->dst_rel);
1924 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
1925 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
1926 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
1927 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
1928 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
1929 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
1930 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
1931 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
1932 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
1933 id++;
1934 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1935 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
1936 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
1937 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
1938 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
1939 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
1940 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
1941 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
1942 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
1943 id++;
1944 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
1945 id++;
1946 }
1947
1948 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1949 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1950 fprintf(stderr, "INST:%d ", vtx->inst);
1951 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
1952 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
1953 id++;
1954 /* This assumes that no semantic fetches exist */
1955 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1956 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
1957 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
1958 if (bc->chip_class < CAYMAN)
1959 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
1960 else
1961 fprintf(stderr, "SEL_Y:%d) ", 0);
1962 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
1963 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
1964 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
1965 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
1966 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
1967 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
1968 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
1969 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
1970 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
1971 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
1972 id++;
1973 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1974 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
1975 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
1976 /* TODO */
1977 id++;
1978 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
1979 id++;
1980 }
1981 }
1982
1983 fprintf(stderr, "--------------------------------------\n");
1984 }
1985
1986 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1987 unsigned *num_format, unsigned *format_comp, unsigned *endian)
1988 {
1989 const struct util_format_description *desc;
1990 unsigned i;
1991
1992 *format = 0;
1993 *num_format = 0;
1994 *format_comp = 0;
1995 *endian = ENDIAN_NONE;
1996
1997 desc = util_format_description(pformat);
1998 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1999 goto out_unknown;
2000 }
2001
2002 /* Find the first non-VOID channel. */
2003 for (i = 0; i < 4; i++) {
2004 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2005 break;
2006 }
2007 }
2008
2009 *endian = r600_endian_swap(desc->channel[i].size);
2010
2011 switch (desc->channel[i].type) {
2012 /* Half-floats, floats, ints */
2013 case UTIL_FORMAT_TYPE_FLOAT:
2014 switch (desc->channel[i].size) {
2015 case 16:
2016 switch (desc->nr_channels) {
2017 case 1:
2018 *format = FMT_16_FLOAT;
2019 break;
2020 case 2:
2021 *format = FMT_16_16_FLOAT;
2022 break;
2023 case 3:
2024 case 4:
2025 *format = FMT_16_16_16_16_FLOAT;
2026 break;
2027 }
2028 break;
2029 case 32:
2030 switch (desc->nr_channels) {
2031 case 1:
2032 *format = FMT_32_FLOAT;
2033 break;
2034 case 2:
2035 *format = FMT_32_32_FLOAT;
2036 break;
2037 case 3:
2038 *format = FMT_32_32_32_FLOAT;
2039 break;
2040 case 4:
2041 *format = FMT_32_32_32_32_FLOAT;
2042 break;
2043 }
2044 break;
2045 default:
2046 goto out_unknown;
2047 }
2048 break;
2049 /* Unsigned ints */
2050 case UTIL_FORMAT_TYPE_UNSIGNED:
2051 /* Signed ints */
2052 case UTIL_FORMAT_TYPE_SIGNED:
2053 switch (desc->channel[i].size) {
2054 case 8:
2055 switch (desc->nr_channels) {
2056 case 1:
2057 *format = FMT_8;
2058 break;
2059 case 2:
2060 *format = FMT_8_8;
2061 break;
2062 case 3:
2063 case 4:
2064 *format = FMT_8_8_8_8;
2065 break;
2066 }
2067 break;
2068 case 16:
2069 switch (desc->nr_channels) {
2070 case 1:
2071 *format = FMT_16;
2072 break;
2073 case 2:
2074 *format = FMT_16_16;
2075 break;
2076 case 3:
2077 case 4:
2078 *format = FMT_16_16_16_16;
2079 break;
2080 }
2081 break;
2082 case 32:
2083 switch (desc->nr_channels) {
2084 case 1:
2085 *format = FMT_32;
2086 break;
2087 case 2:
2088 *format = FMT_32_32;
2089 break;
2090 case 3:
2091 *format = FMT_32_32_32;
2092 break;
2093 case 4:
2094 *format = FMT_32_32_32_32;
2095 break;
2096 }
2097 break;
2098 default:
2099 goto out_unknown;
2100 }
2101 break;
2102 default:
2103 goto out_unknown;
2104 }
2105
2106 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2107 *format_comp = 1;
2108 }
2109 if (desc->channel[i].normalized) {
2110 *num_format = 0;
2111 } else {
2112 *num_format = 2;
2113 }
2114 return;
2115 out_unknown:
2116 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2117 }
2118
2119 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2120 {
2121 static int dump_shaders = -1;
2122
2123 struct r600_bc bc;
2124 struct r600_bc_vtx vtx;
2125 struct pipe_vertex_element *elements = ve->elements;
2126 const struct util_format_description *desc;
2127 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2128 unsigned format, num_format, format_comp, endian;
2129 u32 *bytecode;
2130 int i, r;
2131
2132 /* Vertex element offsets need special handling. If the offset is
2133 * bigger than what we can put in the fetch instruction we need to
2134 * alter the vertex resource offset. In order to simplify code we
2135 * will bind one resource per element in such cases. It's a worst
2136 * case scenario. */
2137 for (i = 0; i < ve->count; i++) {
2138 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2139 if (ve->vbuffer_offset[i]) {
2140 ve->vbuffer_need_offset = 1;
2141 }
2142 }
2143
2144 memset(&bc, 0, sizeof(bc));
2145 r600_bc_init(&bc, rctx->chip_class);
2146
2147 for (i = 0; i < ve->count; i++) {
2148 if (elements[i].instance_divisor > 1) {
2149 struct r600_bc_alu alu;
2150
2151 memset(&alu, 0, sizeof(alu));
2152 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2153 alu.src[0].sel = 0;
2154 alu.src[0].chan = 3;
2155
2156 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2157 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2158
2159 alu.dst.sel = i + 1;
2160 alu.dst.chan = 3;
2161 alu.dst.write = 1;
2162 alu.last = 1;
2163
2164 if ((r = r600_bc_add_alu(&bc, &alu))) {
2165 r600_bc_clear(&bc);
2166 return r;
2167 }
2168 }
2169 }
2170
2171 for (i = 0; i < ve->count; i++) {
2172 unsigned vbuffer_index;
2173 r600_vertex_data_type(ve->elements[i].src_format, &format, &num_format, &format_comp, &endian);
2174 desc = util_format_description(ve->elements[i].src_format);
2175 if (desc == NULL) {
2176 r600_bc_clear(&bc);
2177 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2178 return -EINVAL;
2179 }
2180
2181 /* see above for vbuffer_need_offset explanation */
2182 vbuffer_index = elements[i].vertex_buffer_index;
2183 memset(&vtx, 0, sizeof(vtx));
2184 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2185 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2186 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2187 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2188 vtx.mega_fetch_count = 0x1F;
2189 vtx.dst_gpr = i + 1;
2190 vtx.dst_sel_x = desc->swizzle[0];
2191 vtx.dst_sel_y = desc->swizzle[1];
2192 vtx.dst_sel_z = desc->swizzle[2];
2193 vtx.dst_sel_w = desc->swizzle[3];
2194 vtx.data_format = format;
2195 vtx.num_format_all = num_format;
2196 vtx.format_comp_all = format_comp;
2197 vtx.srf_mode_all = 1;
2198 vtx.offset = elements[i].src_offset;
2199 vtx.endian = endian;
2200
2201 if ((r = r600_bc_add_vtx(&bc, &vtx))) {
2202 r600_bc_clear(&bc);
2203 return r;
2204 }
2205 }
2206
2207 r600_bc_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2208
2209 if ((r = r600_bc_build(&bc))) {
2210 r600_bc_clear(&bc);
2211 return r;
2212 }
2213
2214 if (dump_shaders == -1)
2215 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2216
2217 if (dump_shaders) {
2218 fprintf(stderr, "--------------------------------------------------------------\n");
2219 r600_bc_dump(&bc);
2220 fprintf(stderr, "______________________________________________________________\n");
2221 }
2222
2223 ve->fs_size = bc.ndw*4;
2224
2225 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
2226 ve->fetch_shader = r600_bo(rctx->radeon, ve->fs_size, 256, PIPE_BIND_VERTEX_BUFFER, PIPE_USAGE_IMMUTABLE);
2227 if (ve->fetch_shader == NULL) {
2228 r600_bc_clear(&bc);
2229 return -ENOMEM;
2230 }
2231
2232 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
2233 if (bytecode == NULL) {
2234 r600_bc_clear(&bc);
2235 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2236 return -ENOMEM;
2237 }
2238
2239 if (R600_BIG_ENDIAN) {
2240 for (i = 0; i < ve->fs_size / 4; ++i) {
2241 bytecode[i] = bswap_32(bc.bytecode[i]);
2242 }
2243 } else {
2244 memcpy(bytecode, bc.bytecode, ve->fs_size);
2245 }
2246
2247 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
2248 r600_bc_clear(&bc);
2249
2250 if (rctx->chip_class >= EVERGREEN)
2251 evergreen_fetch_shader(&rctx->context, ve);
2252 else
2253 r600_fetch_shader(&rctx->context, ve);
2254
2255 return 0;
2256 }