2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
35 #include "sb/sb_public.h"
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
40 static inline unsigned int r600_bytecode_get_num_operands(
41 struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
43 return r600_isa_alu(alu
->op
)->src_count
;
46 int r700_bytecode_alu_build(struct r600_bytecode
*bc
,
47 struct r600_bytecode_alu
*alu
, unsigned id
);
49 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
51 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
55 LIST_INITHEAD(&cf
->list
);
56 LIST_INITHEAD(&cf
->alu
);
57 LIST_INITHEAD(&cf
->vtx
);
58 LIST_INITHEAD(&cf
->tex
);
62 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
64 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
68 LIST_INITHEAD(&alu
->list
);
72 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
74 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
78 LIST_INITHEAD(&vtx
->list
);
82 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
84 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
88 LIST_INITHEAD(&tex
->list
);
92 static unsigned stack_entry_size(enum radeon_family chip
) {
94 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
95 * Aruba/Sumo/Sumo2/redwood/juniper
96 * 32: R630/R730/R710/Palm/Cedar
100 * Wavefront Size 16 32 48 64
101 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
102 * Columns per Row (R9xx+) 8 4 4 4 */
105 /* FIXME: are some chips missing here? */
106 /* wavefront size 16 */
111 /* wavefront size 32 */
120 /* wavefront size 64 */
126 void r600_bytecode_init(struct r600_bytecode
*bc
,
127 enum chip_class chip_class
,
128 enum radeon_family family
,
129 bool has_compressed_msaa_texturing
)
131 static unsigned next_shader_id
= 0;
133 bc
->debug_id
= ++next_shader_id
;
135 if ((chip_class
== R600
) &&
136 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
137 bc
->ar_handling
= AR_HANDLE_RV6XX
;
138 bc
->r6xx_nop_after_rel_dst
= 1;
140 bc
->ar_handling
= AR_HANDLE_NORMAL
;
141 bc
->r6xx_nop_after_rel_dst
= 0;
144 LIST_INITHEAD(&bc
->cf
);
145 bc
->chip_class
= chip_class
;
147 bc
->has_compressed_msaa_texturing
= has_compressed_msaa_texturing
;
148 bc
->stack
.entry_size
= stack_entry_size(family
);
151 int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
153 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
157 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
159 cf
->id
= bc
->cf_last
->id
+ 2;
160 if (bc
->cf_last
->eg_alu_extended
) {
161 /* take into account extended alu size */
169 bc
->force_add_cf
= 0;
174 int r600_bytecode_add_output(struct r600_bytecode
*bc
,
175 const struct r600_bytecode_output
*output
)
179 if (output
->gpr
>= bc
->ngpr
)
180 bc
->ngpr
= output
->gpr
+ 1;
182 if (bc
->cf_last
&& (bc
->cf_last
->op
== output
->op
||
183 (bc
->cf_last
->op
== CF_OP_EXPORT
&&
184 output
->op
== CF_OP_EXPORT_DONE
)) &&
185 output
->type
== bc
->cf_last
->output
.type
&&
186 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
187 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
188 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
189 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
190 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
191 output
->comp_mask
== bc
->cf_last
->output
.comp_mask
&&
192 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
194 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
195 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
197 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
198 bc
->cf_last
->output
.gpr
= output
->gpr
;
199 bc
->cf_last
->output
.array_base
= output
->array_base
;
200 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
203 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
204 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
206 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
207 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
212 r
= r600_bytecode_add_cf(bc
);
215 bc
->cf_last
->op
= output
->op
;
216 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
217 bc
->cf_last
->barrier
= 1;
221 /* alu instructions that can ony exits once per group */
222 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
224 return r600_isa_alu(alu
->op
)->flags
& (AF_KILL
| AF_PRED
);
227 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
229 return (r600_isa_alu(alu
->op
)->flags
& AF_REPL
) &&
230 (r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
) == AF_4V
);
233 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
235 return r600_isa_alu(alu
->op
)->flags
& AF_MOVA
;
238 static int alu_uses_rel(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
240 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
247 for (src
= 0; src
< num_src
; ++src
) {
248 if (alu
->src
[src
].rel
) {
255 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
257 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
258 return !(slots
& AF_S
);
261 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
263 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
264 return !(slots
& AF_V
);
267 /* alu instructions that can execute on any unit */
268 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
270 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
271 return slots
== AF_VS
;
274 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
276 return alu
->op
== ALU_OP0_NOP
;
279 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
280 struct r600_bytecode_alu
*assignment
[5])
282 struct r600_bytecode_alu
*alu
;
283 unsigned i
, chan
, trans
;
284 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
286 for (i
= 0; i
< max_slots
; i
++)
287 assignment
[i
] = NULL
;
289 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
290 chan
= alu
->dst
.chan
;
293 else if (is_alu_trans_unit_inst(bc
, alu
))
295 else if (is_alu_vec_unit_inst(bc
, alu
))
297 else if (assignment
[chan
])
298 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
304 assert(0); /* ALU.Trans has already been allocated. */
309 if (assignment
[chan
]) {
310 assert(0); /* ALU.chan has already been allocated. */
313 assignment
[chan
] = alu
;
322 struct alu_bank_swizzle
{
323 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
324 int hw_cfile_addr
[4];
325 int hw_cfile_elem
[4];
328 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
329 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
330 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
331 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
332 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
333 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
334 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
337 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
338 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
339 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
340 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
341 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
344 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
346 int i
, cycle
, component
;
348 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
349 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
350 bs
->hw_gpr
[cycle
][component
] = -1;
351 for (i
= 0; i
< 4; i
++)
352 bs
->hw_cfile_addr
[i
] = -1;
353 for (i
= 0; i
< 4; i
++)
354 bs
->hw_cfile_elem
[i
] = -1;
357 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
359 if (bs
->hw_gpr
[cycle
][chan
] == -1)
360 bs
->hw_gpr
[cycle
][chan
] = sel
;
361 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
362 /* Another scalar operation has already used the GPR read port for the channel. */
368 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
370 int res
, num_res
= 4;
371 if (bc
->chip_class
>= R700
) {
375 for (res
= 0; res
< num_res
; ++res
) {
376 if (bs
->hw_cfile_addr
[res
] == -1) {
377 bs
->hw_cfile_addr
[res
] = sel
;
378 bs
->hw_cfile_elem
[res
] = chan
;
380 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
381 bs
->hw_cfile_elem
[res
] == chan
)
382 return 0; /* Read for this scalar element already reserved, nothing to do here. */
384 /* All cfile read ports are used, cannot reference vector element. */
388 static int is_gpr(unsigned sel
)
393 /* CB constants start at 512, and get translated to a kcache index when ALU
394 * clauses are constructed. Note that we handle kcache constants the same way
395 * as (the now gone) cfile constants, is that really required? */
396 static int is_cfile(unsigned sel
)
398 return (sel
> 255 && sel
< 512) ||
399 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
400 (sel
> 127 && sel
< 192); /* Kcache after translation. */
403 static int is_const(int sel
)
405 return is_cfile(sel
) ||
406 (sel
>= V_SQ_ALU_SRC_0
&&
407 sel
<= V_SQ_ALU_SRC_LITERAL
);
410 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
411 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
413 int r
, src
, num_src
, sel
, elem
, cycle
;
415 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
416 for (src
= 0; src
< num_src
; src
++) {
417 sel
= alu
->src
[src
].sel
;
418 elem
= alu
->src
[src
].chan
;
420 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
421 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
422 /* Nothing to do; special-case optimization,
423 * second source uses first source’s reservation. */
426 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
430 } else if (is_cfile(sel
)) {
431 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
435 /* No restrictions on PV, PS, literal or special constants. */
440 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
441 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
443 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
445 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
446 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
447 sel
= alu
->src
[src
].sel
;
448 elem
= alu
->src
[src
].chan
;
449 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
450 if (const_count
>= 2)
451 /* More than two references to a constant in
452 * transcendental operation. */
458 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
463 for (src
= 0; src
< num_src
; ++src
) {
464 sel
= alu
->src
[src
].sel
;
465 elem
= alu
->src
[src
].chan
;
467 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
468 if (cycle
< const_count
)
469 /* Cycle for GPR load conflicts with
470 * constant load in transcendental operation. */
472 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
476 /* PV PS restrictions */
477 if (const_count
&& (sel
== 254 || sel
== 255)) {
478 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
479 if (cycle
< const_count
)
486 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
487 struct r600_bytecode_alu
*slots
[5])
489 struct alu_bank_swizzle bs
;
491 int i
, r
= 0, forced
= 1;
492 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
493 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
495 for (i
= 0; i
< max_slots
; i
++) {
497 if (slots
[i
]->bank_swizzle_force
) {
498 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
504 if (i
< 4 && slots
[i
])
510 /* Just check every possible combination of bank swizzle.
511 * Not very efficent, but works on the first try in most of the cases. */
512 for (i
= 0; i
< 4; i
++)
513 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
514 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
516 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
518 bank_swizzle
[4] = SQ_ALU_SCL_210
;
519 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
521 init_bank_swizzle(&bs
);
522 if (scalar_only
== false) {
523 for (i
= 0; i
< 4; i
++) {
525 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
533 if (!r
&& max_slots
== 5 && slots
[4]) {
534 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
537 for (i
= 0; i
< max_slots
; i
++) {
539 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
547 for (i
= 0; i
< max_slots
; i
++) {
548 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
550 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
552 else if (i
< max_slots
- 1)
553 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
561 /* Couldn't find a working swizzle. */
565 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
566 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
568 struct r600_bytecode_alu
*prev
[5];
570 int i
, j
, r
, src
, num_src
;
571 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
573 r
= assign_alu_units(bc
, alu_prev
, prev
);
577 for (i
= 0; i
< max_slots
; ++i
) {
578 if (prev
[i
] && (prev
[i
]->dst
.write
|| prev
[i
]->is_op3
) && !prev
[i
]->dst
.rel
) {
579 gpr
[i
] = prev
[i
]->dst
.sel
;
580 /* cube writes more than PV.X */
581 if (is_alu_reduction_inst(bc
, prev
[i
]))
584 chan
[i
] = prev
[i
]->dst
.chan
;
589 for (i
= 0; i
< max_slots
; ++i
) {
590 struct r600_bytecode_alu
*alu
= slots
[i
];
594 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
595 for (src
= 0; src
< num_src
; ++src
) {
596 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
599 if (bc
->chip_class
< CAYMAN
) {
600 if (alu
->src
[src
].sel
== gpr
[4] &&
601 alu
->src
[src
].chan
== chan
[4] &&
602 alu_prev
->pred_sel
== alu
->pred_sel
) {
603 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
604 alu
->src
[src
].chan
= 0;
609 for (j
= 0; j
< 4; ++j
) {
610 if (alu
->src
[src
].sel
== gpr
[j
] &&
611 alu
->src
[src
].chan
== j
&&
612 alu_prev
->pred_sel
== alu
->pred_sel
) {
613 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
614 alu
->src
[src
].chan
= chan
[j
];
624 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
)
628 *sel
= V_SQ_ALU_SRC_0
;
631 *sel
= V_SQ_ALU_SRC_1_INT
;
634 *sel
= V_SQ_ALU_SRC_M_1_INT
;
636 case 0x3F800000: /* 1.0f */
637 *sel
= V_SQ_ALU_SRC_1
;
639 case 0x3F000000: /* 0.5f */
640 *sel
= V_SQ_ALU_SRC_0_5
;
642 case 0xBF800000: /* -1.0f */
643 *sel
= V_SQ_ALU_SRC_1
;
646 case 0xBF000000: /* -0.5f */
647 *sel
= V_SQ_ALU_SRC_0_5
;
651 *sel
= V_SQ_ALU_SRC_LITERAL
;
656 /* compute how many literal are needed */
657 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
658 uint32_t literal
[4], unsigned *nliteral
)
660 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
663 for (i
= 0; i
< num_src
; ++i
) {
664 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
665 uint32_t value
= alu
->src
[i
].value
;
667 for (j
= 0; j
< *nliteral
; ++j
) {
668 if (literal
[j
] == value
) {
676 literal
[(*nliteral
)++] = value
;
683 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
684 struct r600_bytecode_alu
*alu
,
685 uint32_t literal
[4], unsigned nliteral
)
687 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
690 for (i
= 0; i
< num_src
; ++i
) {
691 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
692 uint32_t value
= alu
->src
[i
].value
;
693 for (j
= 0; j
< nliteral
; ++j
) {
694 if (literal
[j
] == value
) {
695 alu
->src
[i
].chan
= j
;
703 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
704 struct r600_bytecode_alu
*alu_prev
)
706 struct r600_bytecode_alu
*prev
[5];
707 struct r600_bytecode_alu
*result
[5] = { NULL
};
709 uint32_t literal
[4], prev_literal
[4];
710 unsigned nliteral
= 0, prev_nliteral
= 0;
712 int i
, j
, r
, src
, num_src
;
713 int num_once_inst
= 0;
714 int have_mova
= 0, have_rel
= 0;
715 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
717 r
= assign_alu_units(bc
, alu_prev
, prev
);
721 for (i
= 0; i
< max_slots
; ++i
) {
723 if (prev
[i
]->pred_sel
)
725 if (is_alu_once_inst(bc
, prev
[i
]))
729 if (slots
[i
]->pred_sel
)
731 if (is_alu_once_inst(bc
, slots
[i
]))
736 for (i
= 0; i
< max_slots
; ++i
) {
737 struct r600_bytecode_alu
*alu
;
739 if (num_once_inst
> 0)
742 /* check number of literals */
744 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
746 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
748 if (is_alu_mova_inst(bc
, prev
[i
])) {
754 if (alu_uses_rel(bc
, prev
[i
])) {
761 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
763 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
766 /* Let's check used slots. */
767 if (prev
[i
] && !slots
[i
]) {
770 } else if (prev
[i
] && slots
[i
]) {
771 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
772 /* Trans unit is still free try to use it. */
773 if (is_alu_any_unit_inst(bc
, slots
[i
])) {
775 result
[4] = slots
[i
];
776 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
777 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
778 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
779 (prev
[i
]->dst
.write
== 1 || prev
[i
]->is_op3
))
782 result
[i
] = slots
[i
];
788 } else if(!slots
[i
]) {
791 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
792 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
793 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
794 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
795 (prev
[4]->dst
.write
== 1 || prev
[4]->is_op3
))
798 result
[i
] = slots
[i
];
802 num_once_inst
+= is_alu_once_inst(bc
, alu
);
804 /* don't reschedule NOPs */
805 if (is_nop_inst(bc
, alu
))
808 if (is_alu_mova_inst(bc
, alu
)) {
815 if (alu_uses_rel(bc
, alu
)) {
822 if (alu
->op
== ALU_OP0_SET_CF_IDX0
||
823 alu
->op
== ALU_OP0_SET_CF_IDX1
)
824 return 0; /* data hazard with MOVA */
826 /* Let's check source gprs */
827 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
828 for (src
= 0; src
< num_src
; ++src
) {
830 /* Constants don't matter. */
831 if (!is_gpr(alu
->src
[src
].sel
))
834 for (j
= 0; j
< max_slots
; ++j
) {
835 if (!prev
[j
] || !(prev
[j
]->dst
.write
|| prev
[j
]->is_op3
))
838 /* If it's relative then we can't determin which gpr is really used. */
839 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
840 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
841 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
847 /* more than one PRED_ or KILL_ ? */
848 if (num_once_inst
> 1)
851 /* check if the result can still be swizzlet */
852 r
= check_and_set_bank_swizzle(bc
, result
);
856 /* looks like everything worked out right, apply the changes */
858 /* undo adding previus literals */
859 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
861 /* sort instructions */
862 for (i
= 0; i
< max_slots
; ++i
) {
863 slots
[i
] = result
[i
];
865 LIST_DEL(&result
[i
]->list
);
867 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
871 /* determine new last instruction */
872 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
874 /* determine new first instruction */
875 for (i
= 0; i
< max_slots
; ++i
) {
877 bc
->cf_last
->curr_bs_head
= result
[i
];
882 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
883 bc
->cf_last
->prev2_bs_head
= NULL
;
888 /* we'll keep kcache sets sorted by bank & addr */
889 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
890 struct r600_bytecode_kcache
*kcache
,
891 unsigned bank
, unsigned line
, unsigned index_mode
)
893 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
895 for (i
= 0; i
< kcache_banks
; i
++) {
896 if (kcache
[i
].mode
) {
899 if (kcache
[i
].bank
< bank
)
902 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
903 kcache
[i
].bank
> bank
) {
904 /* try to insert new line */
905 if (kcache
[kcache_banks
-1].mode
) {
906 /* all sets are in use */
910 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
911 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
912 kcache
[i
].bank
= bank
;
913 kcache
[i
].addr
= line
;
914 kcache
[i
].index_mode
= index_mode
;
918 d
= line
- kcache
[i
].addr
;
922 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
923 /* we are prepending the line to the current set,
924 * discarding the existing second line,
925 * so we'll have to insert line+2 after it */
928 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
929 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
932 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
936 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
940 } else { /* free kcache set - use it */
941 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
942 kcache
[i
].bank
= bank
;
943 kcache
[i
].addr
= line
;
944 kcache
[i
].index_mode
= index_mode
;
951 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
952 struct r600_bytecode_kcache
*kcache
,
953 struct r600_bytecode_alu
*alu
)
957 for (i
= 0; i
< 3; i
++) {
958 unsigned bank
, line
, sel
= alu
->src
[i
].sel
, index_mode
;
963 bank
= alu
->src
[i
].kc_bank
;
965 index_mode
= alu
->src
[i
].kc_rel
? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
967 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
, index_mode
)))
973 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
974 struct r600_bytecode_alu
*alu
,
975 struct r600_bytecode_kcache
* kcache
)
979 /* Alter the src operands to refer to the kcache. */
980 for (i
= 0; i
< 3; ++i
) {
981 static const unsigned int base
[] = {128, 160, 256, 288};
982 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
990 for (j
= 0; j
< 4 && !found
; ++j
) {
991 switch (kcache
[j
].mode
) {
992 case V_SQ_CF_KCACHE_NOP
:
993 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
994 R600_ERR("unexpected kcache line mode\n");
997 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
998 kcache
[j
].addr
<= line
&&
999 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1000 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1001 alu
->src
[i
].sel
+= base
[j
];
1010 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
,
1011 struct r600_bytecode_alu
*alu
,
1014 struct r600_bytecode_kcache kcache_sets
[4];
1015 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1018 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1020 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1021 /* can't alloc, need to start new clause */
1022 if ((r
= r600_bytecode_add_cf(bc
))) {
1025 bc
->cf_last
->op
= type
;
1027 /* retry with the new clause */
1028 kcache
= bc
->cf_last
->kcache
;
1029 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1030 /* can't alloc again- should never happen */
1034 /* update kcache sets */
1035 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1038 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1039 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
||
1040 kcache
[0].index_mode
|| kcache
[1].index_mode
|| kcache
[2].index_mode
|| kcache
[3].index_mode
) {
1041 if (bc
->chip_class
< EVERGREEN
)
1043 bc
->cf_last
->eg_alu_extended
= 1;
1049 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1051 struct r600_bytecode_alu alu
;
1054 for (i
= 0; i
< 4; i
++) {
1055 memset(&alu
, 0, sizeof(alu
));
1056 alu
.op
= ALU_OP0_NOP
;
1057 alu
.src
[0].chan
= i
;
1059 alu
.last
= (i
== 3);
1060 r
= r600_bytecode_add_alu(bc
, &alu
);
1067 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1068 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1070 struct r600_bytecode_alu alu
;
1076 /* hack to avoid making MOVA the last instruction in the clause */
1077 if ((bc
->cf_last
->ndw
>>1) >= 110)
1078 bc
->force_add_cf
= 1;
1080 memset(&alu
, 0, sizeof(alu
));
1081 alu
.op
= ALU_OP1_MOVA_GPR_INT
;
1082 alu
.src
[0].sel
= bc
->ar_reg
;
1083 alu
.src
[0].chan
= bc
->ar_chan
;
1085 alu
.index_mode
= INDEX_MODE_LOOP
;
1086 r
= r600_bytecode_add_alu(bc
, &alu
);
1090 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1095 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1096 static int load_ar(struct r600_bytecode
*bc
)
1098 struct r600_bytecode_alu alu
;
1101 if (bc
->ar_handling
)
1102 return load_ar_r6xx(bc
);
1107 /* hack to avoid making MOVA the last instruction in the clause */
1108 if ((bc
->cf_last
->ndw
>>1) >= 110)
1109 bc
->force_add_cf
= 1;
1111 memset(&alu
, 0, sizeof(alu
));
1112 alu
.op
= ALU_OP1_MOVA_INT
;
1113 alu
.src
[0].sel
= bc
->ar_reg
;
1114 alu
.src
[0].chan
= bc
->ar_chan
;
1116 r
= r600_bytecode_add_alu(bc
, &alu
);
1120 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1125 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
,
1126 const struct r600_bytecode_alu
*alu
, unsigned type
)
1128 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1129 struct r600_bytecode_alu
*lalu
;
1134 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1137 /* will fail later since alu does not support it. */
1138 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1141 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->op
!= type
) {
1142 /* check if we could add it anyway */
1143 if (bc
->cf_last
->op
== CF_OP_ALU
&&
1144 type
== CF_OP_ALU_PUSH_BEFORE
) {
1145 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1146 if (lalu
->execute_mask
) {
1147 bc
->force_add_cf
= 1;
1152 bc
->force_add_cf
= 1;
1155 /* cf can contains only alu or only vtx or only tex */
1156 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1157 r
= r600_bytecode_add_cf(bc
);
1163 bc
->cf_last
->op
= type
;
1165 /* Load index register if required */
1166 if (bc
->chip_class
>= EVERGREEN
) {
1167 for (i
= 0; i
< 3; i
++)
1168 if (nalu
->src
[i
].kc_bank
&& nalu
->src
[i
].kc_rel
)
1169 egcm_load_index_reg(bc
, 0, true);
1172 /* Check AR usage and load it if required */
1173 for (i
= 0; i
< 3; i
++)
1174 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1177 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1180 /* Setup the kcache for this ALU instruction. This will start a new
1181 * ALU clause if needed. */
1182 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1187 if (!bc
->cf_last
->curr_bs_head
) {
1188 bc
->cf_last
->curr_bs_head
= nalu
;
1190 /* number of gpr == the last gpr used in any alu */
1191 for (i
= 0; i
< 3; i
++) {
1192 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1193 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1195 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1196 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1197 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
);
1199 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1200 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1202 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1203 /* each alu use 2 dwords */
1204 bc
->cf_last
->ndw
+= 2;
1207 /* process cur ALU instructions for bank swizzle */
1209 uint32_t literal
[4];
1211 struct r600_bytecode_alu
*slots
[5];
1212 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1213 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1217 if (bc
->cf_last
->prev_bs_head
) {
1218 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1223 if (bc
->cf_last
->prev_bs_head
) {
1224 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1229 r
= check_and_set_bank_swizzle(bc
, slots
);
1233 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1235 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1240 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1242 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1244 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1245 bc
->force_add_cf
= 1;
1248 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1249 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1250 bc
->cf_last
->curr_bs_head
= NULL
;
1253 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1254 insert_nop_r6xx(bc
);
1259 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1261 return r600_bytecode_add_alu_type(bc
, alu
, CF_OP_ALU
);
1264 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1266 switch (bc
->chip_class
) {
1276 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1281 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1283 return !((r600_isa_cf(bc
->cf_last
->op
)->flags
& CF_FETCH
) &&
1284 (bc
->chip_class
== CAYMAN
||
1285 bc
->cf_last
->op
!= CF_OP_TEX
));
1288 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1290 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1295 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1297 /* Load index register if required */
1298 if (bc
->chip_class
>= EVERGREEN
) {
1299 if (vtx
->buffer_index_mode
)
1300 egcm_load_index_reg(bc
, 0, false);
1303 /* cf can contains only alu or only vtx or only tex */
1304 if (bc
->cf_last
== NULL
||
1305 last_inst_was_not_vtx_fetch(bc
) ||
1307 r
= r600_bytecode_add_cf(bc
);
1312 switch (bc
->chip_class
) {
1316 bc
->cf_last
->op
= CF_OP_VTX
;
1319 bc
->cf_last
->op
= CF_OP_TEX
;
1322 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1327 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1328 /* each fetch use 4 dwords */
1329 bc
->cf_last
->ndw
+= 4;
1331 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1332 bc
->force_add_cf
= 1;
1334 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1335 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1340 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1342 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1347 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1349 /* Load index register if required */
1350 if (bc
->chip_class
>= EVERGREEN
) {
1351 if (tex
->sampler_index_mode
|| tex
->resource_index_mode
)
1352 egcm_load_index_reg(bc
, 1, false);
1355 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1356 if (bc
->cf_last
!= NULL
&&
1357 bc
->cf_last
->op
== CF_OP_TEX
) {
1358 struct r600_bytecode_tex
*ttex
;
1359 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1360 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1361 bc
->force_add_cf
= 1;
1365 /* slight hack to make gradients always go into same cf */
1366 if (ntex
->op
== FETCH_OP_SET_GRADIENTS_H
)
1367 bc
->force_add_cf
= 1;
1370 /* cf can contains only alu or only vtx or only tex */
1371 if (bc
->cf_last
== NULL
||
1372 bc
->cf_last
->op
!= CF_OP_TEX
||
1374 r
= r600_bytecode_add_cf(bc
);
1379 bc
->cf_last
->op
= CF_OP_TEX
;
1381 if (ntex
->src_gpr
>= bc
->ngpr
) {
1382 bc
->ngpr
= ntex
->src_gpr
+ 1;
1384 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1385 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1387 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1388 /* each texture fetch use 4 dwords */
1389 bc
->cf_last
->ndw
+= 4;
1391 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1392 bc
->force_add_cf
= 1;
1396 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, unsigned op
)
1399 r
= r600_bytecode_add_cf(bc
);
1403 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1404 bc
->cf_last
->op
= op
;
1408 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1410 return r600_bytecode_add_cfinst(bc
, CF_OP_CF_END
);
1413 /* common to all 3 families */
1414 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1416 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1417 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1418 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1419 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1420 if (bc
->chip_class
< CAYMAN
)
1421 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1423 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1424 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1425 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1426 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1427 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1428 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1429 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1430 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1431 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1432 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1433 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1434 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1435 if (bc
->chip_class
>= EVERGREEN
)
1436 bc
->bytecode
[id
] |= ((vtx
->buffer_index_mode
& 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1437 if (bc
->chip_class
< CAYMAN
)
1438 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1440 bc
->bytecode
[id
++] = 0;
1444 /* common to all 3 families */
1445 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1447 bc
->bytecode
[id
] = S_SQ_TEX_WORD0_TEX_INST(
1448 r600_isa_fetch_opcode(bc
->isa
->hw_class
, tex
->op
)) |
1449 EG_S_SQ_TEX_WORD0_INST_MOD(tex
->inst_mod
) |
1450 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1451 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1452 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1453 if (bc
->chip_class
>= EVERGREEN
)
1454 bc
->bytecode
[id
] |= ((tex
->sampler_index_mode
& 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1455 ((tex
->resource_index_mode
& 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1457 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1458 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1459 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1460 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1461 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1462 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1463 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1464 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1465 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1466 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1467 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1468 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1469 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1470 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1471 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1472 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1473 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1474 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1475 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1476 bc
->bytecode
[id
++] = 0;
1480 /* r600 only, r700/eg bits in r700_asm.c */
1481 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1483 unsigned opcode
= r600_isa_alu_opcode(bc
->isa
->hw_class
, alu
->op
);
1485 /* don't replace gpr by pv or ps for destination register */
1486 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1487 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1488 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1489 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1490 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1491 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1492 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1493 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1494 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1495 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1496 S_SQ_ALU_WORD0_LAST(alu
->last
);
1499 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1500 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1501 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1502 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1503 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1504 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1505 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1506 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1507 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1508 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode
) |
1509 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1511 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1512 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1513 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1514 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1515 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1516 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1517 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1518 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1519 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode
) |
1520 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1521 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1522 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1527 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1529 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1530 *bytecode
++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600
, cf
->op
)) |
1531 S_SQ_CF_WORD1_BARRIER(1) |
1532 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1535 /* common for r600/r700 - eg in eg_asm.c */
1536 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1538 unsigned id
= cf
->id
;
1539 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1540 unsigned opcode
= r600_isa_cf_opcode(bc
->isa
->hw_class
, cf
->op
);
1543 if (cf
->op
== CF_NATIVE
) {
1544 bc
->bytecode
[id
++] = cf
->isa
[0];
1545 bc
->bytecode
[id
++] = cf
->isa
[1];
1546 } else if (cfop
->flags
& CF_ALU
) {
1547 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1548 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1549 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1550 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1552 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode
) |
1553 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1554 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1555 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1556 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1557 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1558 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1559 } else if (cfop
->flags
& CF_FETCH
) {
1560 if (bc
->chip_class
== R700
)
1561 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1563 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1564 } else if (cfop
->flags
& CF_EXP
) {
1565 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1566 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1567 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1568 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1569 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1570 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1571 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1572 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1573 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1574 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1575 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1576 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1577 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1578 } else if (cfop
->flags
& CF_MEM
) {
1579 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1580 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1581 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1582 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1583 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1584 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1585 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1586 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1587 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
) |
1588 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1589 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1591 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1592 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(opcode
) |
1593 S_SQ_CF_WORD1_BARRIER(1) |
1594 S_SQ_CF_WORD1_COND(cf
->cond
) |
1595 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
) |
1596 S_SQ_CF_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1601 int r600_bytecode_build(struct r600_bytecode
*bc
)
1603 struct r600_bytecode_cf
*cf
;
1604 struct r600_bytecode_alu
*alu
;
1605 struct r600_bytecode_vtx
*vtx
;
1606 struct r600_bytecode_tex
*tex
;
1607 uint32_t literal
[4];
1612 if (!bc
->nstack
) // If not 0, Stack_size already provided by llvm
1613 bc
->nstack
= bc
->stack
.max_entries
;
1615 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1619 /* first path compute addr of each CF block */
1620 /* addr start after all the CF instructions */
1621 addr
= bc
->cf_last
->id
+ 2;
1622 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1623 if (r600_isa_cf(cf
->op
)->flags
& CF_FETCH
) {
1625 addr
&= 0xFFFFFFFCUL
;
1629 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1632 bc
->bytecode
= calloc(4, bc
->ndw
);
1633 if (bc
->bytecode
== NULL
)
1635 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1636 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1638 if (bc
->chip_class
>= EVERGREEN
)
1639 r
= eg_bytecode_cf_build(bc
, cf
);
1641 r
= r600_bytecode_cf_build(bc
, cf
);
1644 if (cfop
->flags
& CF_ALU
) {
1646 memset(literal
, 0, sizeof(literal
));
1647 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1648 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
1651 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
1652 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
1654 switch(bc
->chip_class
) {
1656 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
1659 case EVERGREEN
: /* eg alu is same encoding as r700 */
1661 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
1664 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
1671 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
1672 bc
->bytecode
[addr
++] = literal
[i
];
1675 memset(literal
, 0, sizeof(literal
));
1678 } else if (cf
->op
== CF_OP_VTX
) {
1679 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1680 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1685 } else if (cf
->op
== CF_OP_TEX
) {
1686 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1687 assert(bc
->chip_class
>= EVERGREEN
);
1688 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1693 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1694 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
1704 void r600_bytecode_clear(struct r600_bytecode
*bc
)
1706 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
1709 bc
->bytecode
= NULL
;
1711 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
1712 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
1713 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
1714 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
1716 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
1720 LIST_INITHEAD(&cf
->alu
);
1722 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
1726 LIST_INITHEAD(&cf
->tex
);
1728 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
1732 LIST_INITHEAD(&cf
->vtx
);
1737 LIST_INITHEAD(&cf
->list
);
1740 static int print_swizzle(unsigned swz
)
1742 const char * swzchars
= "xyzw01?_";
1743 assert(swz
<8 && swz
!= 6);
1744 return fprintf(stderr
, "%c", swzchars
[swz
]);
1747 static int print_sel(unsigned sel
, unsigned rel
, unsigned index_mode
,
1748 unsigned need_brackets
)
1751 if (rel
&& index_mode
>= 5 && sel
< 128)
1752 o
+= fprintf(stderr
, "G");
1753 if (rel
|| need_brackets
) {
1754 o
+= fprintf(stderr
, "[");
1756 o
+= fprintf(stderr
, "%d", sel
);
1758 if (index_mode
== 0 || index_mode
== 6)
1759 o
+= fprintf(stderr
, "+AR");
1760 else if (index_mode
== 4)
1761 o
+= fprintf(stderr
, "+AL");
1763 if (rel
|| need_brackets
) {
1764 o
+= fprintf(stderr
, "]");
1769 static int print_dst(struct r600_bytecode_alu
*alu
)
1772 unsigned sel
= alu
->dst
.sel
;
1773 char reg_char
= 'R';
1774 if (sel
> 128 - 4) { /* clause temporary gpr */
1779 if (alu
->dst
.write
|| alu
->is_op3
) {
1780 o
+= fprintf(stderr
, "%c", reg_char
);
1781 o
+= print_sel(alu
->dst
.sel
, alu
->dst
.rel
, alu
->index_mode
, 0);
1783 o
+= fprintf(stderr
, "__");
1785 o
+= fprintf(stderr
, ".");
1786 o
+= print_swizzle(alu
->dst
.chan
);
1790 static int print_src(struct r600_bytecode_alu
*alu
, unsigned idx
)
1793 struct r600_bytecode_alu_src
*src
= &alu
->src
[idx
];
1794 unsigned sel
= src
->sel
, need_sel
= 1, need_chan
= 1, need_brackets
= 0;
1797 o
+= fprintf(stderr
,"-");
1799 o
+= fprintf(stderr
,"|");
1801 if (sel
< 128 - 4) {
1802 o
+= fprintf(stderr
, "R");
1803 } else if (sel
< 128) {
1804 o
+= fprintf(stderr
, "T");
1806 } else if (sel
< 160) {
1807 o
+= fprintf(stderr
, "KC0");
1810 } else if (sel
< 192) {
1811 o
+= fprintf(stderr
, "KC1");
1814 } else if (sel
>= 512) {
1815 o
+= fprintf(stderr
, "C%d", src
->kc_bank
);
1818 } else if (sel
>= 448) {
1819 o
+= fprintf(stderr
, "Param");
1822 } else if (sel
>= 288) {
1823 o
+= fprintf(stderr
, "KC3");
1826 } else if (sel
>= 256) {
1827 o
+= fprintf(stderr
, "KC2");
1834 case V_SQ_ALU_SRC_PS
:
1835 o
+= fprintf(stderr
, "PS");
1837 case V_SQ_ALU_SRC_PV
:
1838 o
+= fprintf(stderr
, "PV");
1841 case V_SQ_ALU_SRC_LITERAL
:
1842 o
+= fprintf(stderr
, "[0x%08X %f]", src
->value
, *(float*)&src
->value
);
1844 case V_SQ_ALU_SRC_0_5
:
1845 o
+= fprintf(stderr
, "0.5");
1847 case V_SQ_ALU_SRC_M_1_INT
:
1848 o
+= fprintf(stderr
, "-1");
1850 case V_SQ_ALU_SRC_1_INT
:
1851 o
+= fprintf(stderr
, "1");
1853 case V_SQ_ALU_SRC_1
:
1854 o
+= fprintf(stderr
, "1.0");
1856 case V_SQ_ALU_SRC_0
:
1857 o
+= fprintf(stderr
, "0");
1860 o
+= fprintf(stderr
, "??IMM_%d", sel
);
1866 o
+= print_sel(sel
, src
->rel
, alu
->index_mode
, need_brackets
);
1869 o
+= fprintf(stderr
, ".");
1870 o
+= print_swizzle(src
->chan
);
1874 o
+= fprintf(stderr
,"|");
1879 static int print_indent(int p
, int c
)
1883 o
+= fprintf(stderr
, " ");
1887 void r600_bytecode_disasm(struct r600_bytecode
*bc
)
1889 const char *index_mode
[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
1890 static int index
= 0;
1891 struct r600_bytecode_cf
*cf
= NULL
;
1892 struct r600_bytecode_alu
*alu
= NULL
;
1893 struct r600_bytecode_vtx
*vtx
= NULL
;
1894 struct r600_bytecode_tex
*tex
= NULL
;
1896 unsigned i
, id
, ngr
= 0, last
;
1897 uint32_t literal
[4];
1901 switch (bc
->chip_class
) {
1916 fprintf(stderr
, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1917 bc
->ndw
, bc
->ngpr
, bc
->nstack
);
1918 fprintf(stderr
, "shader %d -- %c\n", index
++, chip
);
1920 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1922 if (cf
->op
== CF_NATIVE
) {
1923 fprintf(stderr
, "%04d %08X %08X CF_NATIVE\n", id
, bc
->bytecode
[id
],
1924 bc
->bytecode
[id
+ 1]);
1926 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1927 if (cfop
->flags
& CF_ALU
) {
1928 if (cf
->eg_alu_extended
) {
1929 fprintf(stderr
, "%04d %08X %08X %s\n", id
, bc
->bytecode
[id
],
1930 bc
->bytecode
[id
+ 1], "ALU_EXT");
1933 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
1934 bc
->bytecode
[id
+ 1], cfop
->name
);
1935 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 2, cf
->addr
);
1936 for (i
= 0; i
< 4; ++i
) {
1937 if (cf
->kcache
[i
].mode
) {
1938 int c_start
= (cf
->kcache
[i
].addr
<< 4);
1939 int c_end
= c_start
+ (cf
->kcache
[i
].mode
<< 4);
1940 fprintf(stderr
, "KC%d[CB%d:%d-%d%s%s] ",
1941 i
, cf
->kcache
[i
].bank
, c_start
, c_end
,
1942 cf
->kcache
[i
].index_mode
? " " : "",
1943 cf
->kcache
[i
].index_mode
? index_mode
[cf
->kcache
[i
].index_mode
] : "");
1946 fprintf(stderr
, "\n");
1947 } else if (cfop
->flags
& CF_FETCH
) {
1948 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
1949 bc
->bytecode
[id
+ 1], cfop
->name
);
1950 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 4, cf
->addr
);
1951 fprintf(stderr
, "\n");
1952 } else if (cfop
->flags
& CF_EXP
) {
1954 const char *exp_type
[] = {"PIXEL", "POS ", "PARAM"};
1955 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
1956 bc
->bytecode
[id
+ 1], cfop
->name
);
1957 o
+= print_indent(o
, 43);
1958 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
1959 if (cf
->output
.burst_count
> 1) {
1960 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
1961 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
1963 o
+= print_indent(o
, 55);
1964 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
1965 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
1967 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
1968 o
+= print_indent(o
, 55);
1969 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
1972 o
+= print_swizzle(cf
->output
.swizzle_x
);
1973 o
+= print_swizzle(cf
->output
.swizzle_y
);
1974 o
+= print_swizzle(cf
->output
.swizzle_z
);
1975 o
+= print_swizzle(cf
->output
.swizzle_w
);
1977 print_indent(o
, 67);
1979 fprintf(stderr
, " ES:%X ", cf
->output
.elem_size
);
1981 fprintf(stderr
, "NO_BARRIER ");
1982 if (cf
->end_of_program
)
1983 fprintf(stderr
, "EOP ");
1984 fprintf(stderr
, "\n");
1985 } else if (r600_isa_cf(cf
->op
)->flags
& CF_MEM
) {
1987 const char *exp_type
[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
1989 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
,
1990 bc
->bytecode
[id
], bc
->bytecode
[id
+ 1], cfop
->name
);
1991 o
+= print_indent(o
, 43);
1992 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
1993 if (cf
->output
.burst_count
> 1) {
1994 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
1995 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
1996 o
+= print_indent(o
, 55);
1997 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
1998 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2000 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2001 o
+= print_indent(o
, 55);
2002 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2004 for (i
= 0; i
< 4; ++i
) {
2005 if (cf
->output
.comp_mask
& (1 << i
))
2006 o
+= print_swizzle(i
);
2008 o
+= print_swizzle(7);
2011 if (cf
->output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
)
2012 o
+= fprintf(stderr
, " R%d", cf
->output
.index_gpr
);
2014 o
+= print_indent(o
, 67);
2016 fprintf(stderr
, " ES:%i ", cf
->output
.elem_size
);
2017 if (cf
->output
.array_size
!= 0xFFF)
2018 fprintf(stderr
, "AS:%i ", cf
->output
.array_size
);
2020 fprintf(stderr
, "NO_BARRIER ");
2021 if (cf
->end_of_program
)
2022 fprintf(stderr
, "EOP ");
2023 fprintf(stderr
, "\n");
2025 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2026 bc
->bytecode
[id
+ 1], cfop
->name
);
2027 fprintf(stderr
, "@%d ", cf
->cf_addr
);
2029 fprintf(stderr
, "CND:%X ", cf
->cond
);
2031 fprintf(stderr
, "POP:%X ", cf
->pop_count
);
2032 fprintf(stderr
, "\n");
2039 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2040 const char *omod_str
[] = {"","*2","*4","/2"};
2041 const struct alu_op_info
*aop
= r600_isa_alu(alu
->op
);
2044 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2045 o
+= fprintf(stderr
, " %04d %08X %08X ", id
, bc
->bytecode
[id
], bc
->bytecode
[id
+1]);
2047 o
+= fprintf(stderr
, "%4d ", ++ngr
);
2049 o
+= fprintf(stderr
, " ");
2050 o
+= fprintf(stderr
, "%c%c %c ", alu
->execute_mask
? 'M':' ',
2051 alu
->update_pred
? 'P':' ',
2052 alu
->pred_sel
? alu
->pred_sel
==2 ? '0':'1':' ');
2054 o
+= fprintf(stderr
, "%s%s%s ", aop
->name
,
2055 omod_str
[alu
->omod
], alu
->dst
.clamp
? "_sat":"");
2057 o
+= print_indent(o
,60);
2058 o
+= print_dst(alu
);
2059 for (i
= 0; i
< aop
->src_count
; ++i
) {
2060 o
+= fprintf(stderr
, i
== 0 ? ", ": ", ");
2061 o
+= print_src(alu
, i
);
2064 if (alu
->bank_swizzle
) {
2065 o
+= print_indent(o
,75);
2066 o
+= fprintf(stderr
, " BS:%d", alu
->bank_swizzle
);
2069 fprintf(stderr
, "\n");
2073 for (i
= 0; i
< nliteral
; i
++, id
++) {
2074 float *f
= (float*)(bc
->bytecode
+ id
);
2075 o
= fprintf(stderr
, " %04d %08X", id
, bc
->bytecode
[id
]);
2076 print_indent(o
, 60);
2077 fprintf(stderr
, " %f (%d)\n", *f
, *(bc
->bytecode
+ id
));
2085 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2087 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2088 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2090 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(tex
->op
)->name
);
2092 o
+= print_indent(o
, 50);
2094 o
+= fprintf(stderr
, "R%d.", tex
->dst_gpr
);
2095 o
+= print_swizzle(tex
->dst_sel_x
);
2096 o
+= print_swizzle(tex
->dst_sel_y
);
2097 o
+= print_swizzle(tex
->dst_sel_z
);
2098 o
+= print_swizzle(tex
->dst_sel_w
);
2100 o
+= fprintf(stderr
, ", R%d.", tex
->src_gpr
);
2101 o
+= print_swizzle(tex
->src_sel_x
);
2102 o
+= print_swizzle(tex
->src_sel_y
);
2103 o
+= print_swizzle(tex
->src_sel_z
);
2104 o
+= print_swizzle(tex
->src_sel_w
);
2106 o
+= fprintf(stderr
, ", RID:%d", tex
->resource_id
);
2107 o
+= fprintf(stderr
, ", SID:%d ", tex
->sampler_id
);
2109 if (tex
->sampler_index_mode
)
2110 fprintf(stderr
, "SQ_%s ", index_mode
[tex
->sampler_index_mode
]);
2113 fprintf(stderr
, "LB:%d ", tex
->lod_bias
);
2115 fprintf(stderr
, "CT:%c%c%c%c ",
2116 tex
->coord_type_x
? 'N' : 'U',
2117 tex
->coord_type_y
? 'N' : 'U',
2118 tex
->coord_type_z
? 'N' : 'U',
2119 tex
->coord_type_w
? 'N' : 'U');
2122 fprintf(stderr
, "OX:%d ", tex
->offset_x
);
2124 fprintf(stderr
, "OY:%d ", tex
->offset_y
);
2126 fprintf(stderr
, "OZ:%d ", tex
->offset_z
);
2129 fprintf(stderr
, "\n");
2132 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2134 const char * fetch_type
[] = {"VERTEX", "INSTANCE", ""};
2135 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2136 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2138 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(vtx
->op
)->name
);
2140 o
+= print_indent(o
, 50);
2142 o
+= fprintf(stderr
, "R%d.", vtx
->dst_gpr
);
2143 o
+= print_swizzle(vtx
->dst_sel_x
);
2144 o
+= print_swizzle(vtx
->dst_sel_y
);
2145 o
+= print_swizzle(vtx
->dst_sel_z
);
2146 o
+= print_swizzle(vtx
->dst_sel_w
);
2148 o
+= fprintf(stderr
, ", R%d.", vtx
->src_gpr
);
2149 o
+= print_swizzle(vtx
->src_sel_x
);
2152 fprintf(stderr
, " +%db", vtx
->offset
);
2154 o
+= print_indent(o
, 55);
2156 fprintf(stderr
, ", RID:%d ", vtx
->buffer_id
);
2158 fprintf(stderr
, "%s ", fetch_type
[vtx
->fetch_type
]);
2160 if (bc
->chip_class
< CAYMAN
&& vtx
->mega_fetch_count
)
2161 fprintf(stderr
, "MFC:%d ", vtx
->mega_fetch_count
);
2163 if (bc
->chip_class
>= EVERGREEN
&& vtx
->buffer_index_mode
)
2164 fprintf(stderr
, "SQ_%s ", index_mode
[vtx
->buffer_index_mode
]);
2166 fprintf(stderr
, "UCF:%d ", vtx
->use_const_fields
);
2167 fprintf(stderr
, "FMT(DTA:%d ", vtx
->data_format
);
2168 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2169 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2170 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2176 fprintf(stderr
, "--------------------------------------\n");
2179 void r600_vertex_data_type(enum pipe_format pformat
,
2181 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2183 const struct util_format_description
*desc
;
2189 *endian
= ENDIAN_NONE
;
2191 if (pformat
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2192 *format
= FMT_10_11_11_FLOAT
;
2193 *endian
= r600_endian_swap(32);
2197 desc
= util_format_description(pformat
);
2198 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2202 /* Find the first non-VOID channel. */
2203 for (i
= 0; i
< 4; i
++) {
2204 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2209 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2211 switch (desc
->channel
[i
].type
) {
2212 /* Half-floats, floats, ints */
2213 case UTIL_FORMAT_TYPE_FLOAT
:
2214 switch (desc
->channel
[i
].size
) {
2216 switch (desc
->nr_channels
) {
2218 *format
= FMT_16_FLOAT
;
2221 *format
= FMT_16_16_FLOAT
;
2225 *format
= FMT_16_16_16_16_FLOAT
;
2230 switch (desc
->nr_channels
) {
2232 *format
= FMT_32_FLOAT
;
2235 *format
= FMT_32_32_FLOAT
;
2238 *format
= FMT_32_32_32_FLOAT
;
2241 *format
= FMT_32_32_32_32_FLOAT
;
2250 case UTIL_FORMAT_TYPE_UNSIGNED
:
2252 case UTIL_FORMAT_TYPE_SIGNED
:
2253 switch (desc
->channel
[i
].size
) {
2255 switch (desc
->nr_channels
) {
2264 *format
= FMT_8_8_8_8
;
2269 if (desc
->nr_channels
!= 4)
2272 *format
= FMT_2_10_10_10
;
2275 switch (desc
->nr_channels
) {
2280 *format
= FMT_16_16
;
2284 *format
= FMT_16_16_16_16
;
2289 switch (desc
->nr_channels
) {
2294 *format
= FMT_32_32
;
2297 *format
= FMT_32_32_32
;
2300 *format
= FMT_32_32_32_32
;
2312 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2317 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2318 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2319 if (!desc
->channel
[i
].normalized
) {
2320 if (desc
->channel
[i
].pure_integer
)
2328 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2331 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2333 const struct pipe_vertex_element
*elements
)
2335 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2336 struct r600_bytecode bc
;
2337 struct r600_bytecode_vtx vtx
;
2338 const struct util_format_description
*desc
;
2339 unsigned fetch_resource_start
= rctx
->b
.chip_class
>= EVERGREEN
? 0 : 160;
2340 unsigned format
, num_format
, format_comp
, endian
;
2342 int i
, j
, r
, fs_size
;
2343 struct r600_fetch_shader
*shader
;
2344 unsigned no_sb
= rctx
->screen
->b
.debug_flags
& DBG_NO_SB
;
2345 unsigned sb_disasm
= !no_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
2349 memset(&bc
, 0, sizeof(bc
));
2350 r600_bytecode_init(&bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2351 rctx
->screen
->has_compressed_msaa_texturing
);
2355 for (i
= 0; i
< count
; i
++) {
2356 if (elements
[i
].instance_divisor
> 1) {
2357 if (rctx
->b
.chip_class
== CAYMAN
) {
2358 for (j
= 0; j
< 4; j
++) {
2359 struct r600_bytecode_alu alu
;
2360 memset(&alu
, 0, sizeof(alu
));
2361 alu
.op
= ALU_OP2_MULHI_UINT
;
2363 alu
.src
[0].chan
= 3;
2364 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2365 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2366 alu
.dst
.sel
= i
+ 1;
2368 alu
.dst
.write
= j
== 3;
2370 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2371 r600_bytecode_clear(&bc
);
2376 struct r600_bytecode_alu alu
;
2377 memset(&alu
, 0, sizeof(alu
));
2378 alu
.op
= ALU_OP2_MULHI_UINT
;
2380 alu
.src
[0].chan
= 3;
2381 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2382 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2383 alu
.dst
.sel
= i
+ 1;
2387 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2388 r600_bytecode_clear(&bc
);
2395 for (i
= 0; i
< count
; i
++) {
2396 r600_vertex_data_type(elements
[i
].src_format
,
2397 &format
, &num_format
, &format_comp
, &endian
);
2399 desc
= util_format_description(elements
[i
].src_format
);
2401 r600_bytecode_clear(&bc
);
2402 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2406 if (elements
[i
].src_offset
> 65535) {
2407 r600_bytecode_clear(&bc
);
2408 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2412 memset(&vtx
, 0, sizeof(vtx
));
2413 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2414 vtx
.fetch_type
= elements
[i
].instance_divisor
? SQ_VTX_FETCH_INSTANCE_DATA
: SQ_VTX_FETCH_VERTEX_DATA
;
2415 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2416 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2417 vtx
.mega_fetch_count
= 0x1F;
2418 vtx
.dst_gpr
= i
+ 1;
2419 vtx
.dst_sel_x
= desc
->swizzle
[0];
2420 vtx
.dst_sel_y
= desc
->swizzle
[1];
2421 vtx
.dst_sel_z
= desc
->swizzle
[2];
2422 vtx
.dst_sel_w
= desc
->swizzle
[3];
2423 vtx
.data_format
= format
;
2424 vtx
.num_format_all
= num_format
;
2425 vtx
.format_comp_all
= format_comp
;
2426 vtx
.offset
= elements
[i
].src_offset
;
2427 vtx
.endian
= endian
;
2429 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2430 r600_bytecode_clear(&bc
);
2435 r600_bytecode_add_cfinst(&bc
, CF_OP_RET
);
2437 if ((r
= r600_bytecode_build(&bc
))) {
2438 r600_bytecode_clear(&bc
);
2442 if (rctx
->screen
->b
.debug_flags
& DBG_FS
) {
2443 fprintf(stderr
, "--------------------------------------------------------------\n");
2444 fprintf(stderr
, "Vertex elements state:\n");
2445 for (i
= 0; i
< count
; i
++) {
2446 fprintf(stderr
, " ");
2447 util_dump_vertex_element(stderr
, elements
+i
);
2448 fprintf(stderr
, "\n");
2452 r600_bytecode_disasm(&bc
);
2454 fprintf(stderr
, "______________________________________________________________\n");
2456 r600_sb_bytecode_process(rctx
, &bc
, NULL
, 1 /*dump*/, 0 /*optimize*/);
2462 /* Allocate the CSO. */
2463 shader
= CALLOC_STRUCT(r600_fetch_shader
);
2465 r600_bytecode_clear(&bc
);
2469 u_suballocator_alloc(rctx
->allocator_fetch_shader
, fs_size
, &shader
->offset
,
2470 (struct pipe_resource
**)&shader
->buffer
);
2471 if (!shader
->buffer
) {
2472 r600_bytecode_clear(&bc
);
2477 bytecode
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->buffer
, PIPE_TRANSFER_WRITE
| PIPE_TRANSFER_UNSYNCHRONIZED
);
2478 bytecode
+= shader
->offset
/ 4;
2480 if (R600_BIG_ENDIAN
) {
2481 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2482 bytecode
[i
] = util_cpu_to_le32(bc
.bytecode
[i
]);
2485 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2487 rctx
->b
.ws
->buffer_unmap(shader
->buffer
->cs_buf
);
2489 r600_bytecode_clear(&bc
);
2493 void r600_bytecode_alu_read(struct r600_bytecode
*bc
,
2494 struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2497 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2498 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2499 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2500 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2501 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2502 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2503 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2504 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2505 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2506 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2507 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2510 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2511 if (alu
->bank_swizzle
)
2512 alu
->bank_swizzle_force
= alu
->bank_swizzle
;
2513 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2514 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2515 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2516 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2517 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2520 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2521 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2522 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2523 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2524 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2525 G_SQ_ALU_WORD1_OP3_ALU_INST(word1
), /* is_op3 = */ 1);
2528 else /*ALU_DWORD1_OP2*/
2530 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2531 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2532 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2533 G_SQ_ALU_WORD1_OP2_ALU_INST(word1
), /* is_op3 = */ 0);
2534 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2535 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2536 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2538 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);
2543 void r600_bytecode_export_read(struct r600_bytecode
*bc
,
2544 struct r600_bytecode_output
*output
, uint32_t word0
, uint32_t word1
)
2546 output
->array_base
= G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0
);
2547 output
->type
= G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0
);
2548 output
->gpr
= G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0
);
2549 output
->elem_size
= G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0
);
2551 output
->swizzle_x
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1
);
2552 output
->swizzle_y
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1
);
2553 output
->swizzle_z
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1
);
2554 output
->swizzle_w
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1
);
2555 output
->burst_count
= G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1
);
2556 output
->end_of_program
= G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1
);
2557 output
->op
= r600_isa_cf_by_opcode(bc
->isa
,
2558 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1
), 0);
2559 output
->barrier
= G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1
);
2560 output
->array_size
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1
);
2561 output
->comp_mask
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1
);