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Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 #define PREV_ALU(alu) LIST_ENTRY(struct r600_bc_alu, alu->list.prev, list)
39 #define NEXT_ALU(alu) LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)
40
41 static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
42 {
43 if(alu->is_op3)
44 return 3;
45
46 switch (bc->chiprev) {
47 case CHIPREV_R600:
48 case CHIPREV_R700:
49 switch (alu->inst) {
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
51 return 0;
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
73 return 2;
74
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
93 return 1;
94 default: R600_ERR(
95 "Need instruction operand number for 0x%x.\n", alu->inst);
96 }
97 break;
98 case CHIPREV_EVERGREEN:
99 switch (alu->inst) {
100 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
101 return 0;
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
103 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
117 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
118 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
125 return 2;
126
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
144 return 1;
145 default: R600_ERR(
146 "Need instruction operand number for 0x%x.\n", alu->inst);
147 }
148 break;
149 }
150
151 return 3;
152 }
153
154 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
155
156 static struct r600_bc_cf *r600_bc_cf(void)
157 {
158 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
159
160 if (cf == NULL)
161 return NULL;
162 LIST_INITHEAD(&cf->list);
163 LIST_INITHEAD(&cf->alu);
164 LIST_INITHEAD(&cf->vtx);
165 LIST_INITHEAD(&cf->tex);
166 cf->barrier = 1;
167 return cf;
168 }
169
170 static struct r600_bc_alu *r600_bc_alu(void)
171 {
172 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
173
174 if (alu == NULL)
175 return NULL;
176 LIST_INITHEAD(&alu->list);
177 return alu;
178 }
179
180 static struct r600_bc_vtx *r600_bc_vtx(void)
181 {
182 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
183
184 if (vtx == NULL)
185 return NULL;
186 LIST_INITHEAD(&vtx->list);
187 return vtx;
188 }
189
190 static struct r600_bc_tex *r600_bc_tex(void)
191 {
192 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
193
194 if (tex == NULL)
195 return NULL;
196 LIST_INITHEAD(&tex->list);
197 return tex;
198 }
199
200 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
201 {
202 LIST_INITHEAD(&bc->cf);
203 bc->family = family;
204 switch (bc->family) {
205 case CHIP_R600:
206 case CHIP_RV610:
207 case CHIP_RV630:
208 case CHIP_RV670:
209 case CHIP_RV620:
210 case CHIP_RV635:
211 case CHIP_RS780:
212 case CHIP_RS880:
213 bc->chiprev = CHIPREV_R600;
214 break;
215 case CHIP_RV770:
216 case CHIP_RV730:
217 case CHIP_RV710:
218 case CHIP_RV740:
219 bc->chiprev = CHIPREV_R700;
220 break;
221 case CHIP_CEDAR:
222 case CHIP_REDWOOD:
223 case CHIP_JUNIPER:
224 case CHIP_CYPRESS:
225 case CHIP_HEMLOCK:
226 case CHIP_PALM:
227 case CHIP_BARTS:
228 case CHIP_TURKS:
229 case CHIP_CAICOS:
230 bc->chiprev = CHIPREV_EVERGREEN;
231 break;
232 default:
233 R600_ERR("unknown family %d\n", bc->family);
234 return -EINVAL;
235 }
236 return 0;
237 }
238
239 static int r600_bc_add_cf(struct r600_bc *bc)
240 {
241 struct r600_bc_cf *cf = r600_bc_cf();
242
243 if (cf == NULL)
244 return -ENOMEM;
245 LIST_ADDTAIL(&cf->list, &bc->cf);
246 if (bc->cf_last)
247 cf->id = bc->cf_last->id + 2;
248 bc->cf_last = cf;
249 bc->ncf++;
250 bc->ndw += 2;
251 bc->force_add_cf = 0;
252 return 0;
253 }
254
255 static void r600_bc_remove_cf(struct r600_bc *bc, struct r600_bc_cf *cf)
256 {
257 struct r600_bc_cf *other;
258 LIST_FOR_EACH_ENTRY(other, &bc->cf, list) {
259 if (other->id > cf->id)
260 other->id -= 2;
261 if (other->cf_addr > cf->id)
262 other->cf_addr -= 2;
263 }
264 LIST_DEL(&cf->list);
265 free(cf);
266 }
267
268 static void r600_bc_move_cf(struct r600_bc *bc, struct r600_bc_cf *cf, struct r600_bc_cf *next)
269 {
270 struct r600_bc_cf *prev = LIST_ENTRY(struct r600_bc_cf, next->list.prev, list);
271 unsigned old_id = cf->id;
272 unsigned new_id = next->list.prev == &bc->cf ? 0 : prev->id + 2;
273 struct r600_bc_cf *other;
274
275 if (prev == cf || next == cf)
276 return; /* position hasn't changed */
277
278 LIST_DEL(&cf->list);
279 LIST_FOR_EACH_ENTRY(other, &bc->cf, list) {
280 if (other->id > old_id)
281 other->id -= 2;
282 if (other->id >= new_id)
283 other->id += 2;
284 if (other->cf_addr > old_id)
285 other->cf_addr -= 2;
286 if (other->cf_addr > new_id)
287 other->cf_addr += 2;
288 }
289 cf->id = new_id;
290 LIST_ADD(&cf->list, &prev->list);
291 }
292
293 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
294 {
295 int r;
296
297 if (bc->cf_last && bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
298 output->type == bc->cf_last->output.type &&
299 output->elem_size == bc->cf_last->output.elem_size &&
300 output->swizzle_x == bc->cf_last->output.swizzle_x &&
301 output->swizzle_y == bc->cf_last->output.swizzle_y &&
302 output->swizzle_z == bc->cf_last->output.swizzle_z &&
303 output->swizzle_w == bc->cf_last->output.swizzle_w &&
304 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
305
306 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
307 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
308
309 bc->cf_last->output.gpr = output->gpr;
310 bc->cf_last->output.array_base = output->array_base;
311 bc->cf_last->output.burst_count += output->burst_count;
312 return 0;
313
314 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
315 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
316
317 bc->cf_last->output.burst_count += output->burst_count;
318 return 0;
319 }
320 }
321
322 r = r600_bc_add_cf(bc);
323 if (r)
324 return r;
325 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
326 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
327 bc->cf_last->output.burst_count = 1;
328 return 0;
329 }
330
331 /* alu predicate instructions */
332 static int is_alu_pred_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
333 {
334 switch (bc->chiprev) {
335 case CHIPREV_R600:
336 case CHIPREV_R700:
337 return !alu->is_op3 && (
338 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
339 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
340 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
341 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
342 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
343 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
348 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
362 case CHIPREV_EVERGREEN:
363 default:
364 return !alu->is_op3 && (
365 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
366 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
367 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
368 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
369 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
370 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
371 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
372 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
373 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
374 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
375 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
376 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
377 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
378 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
379 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
380 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
381 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
389 }
390 }
391
392 /* alu kill instructions */
393 static int is_alu_kill_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
394 {
395 switch (bc->chiprev) {
396 case CHIPREV_R600:
397 case CHIPREV_R700:
398 return !alu->is_op3 && (
399 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
400 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
401 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
402 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
403 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
404 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
405 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
406 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
407 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
408 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT);
409 case CHIPREV_EVERGREEN:
410 default:
411 return !alu->is_op3 && (
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
415 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
416 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
417 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
418 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
419 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
420 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
421 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT);
422 }
423 }
424
425 /* alu instructions that can ony exits once per group */
426 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
427 {
428 return is_alu_kill_inst(bc, alu) ||
429 is_alu_pred_inst(bc, alu);
430 }
431
432 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
433 {
434 switch (bc->chiprev) {
435 case CHIPREV_R600:
436 case CHIPREV_R700:
437 return !alu->is_op3 && (
438 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
439 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
440 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
441 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
442 case CHIPREV_EVERGREEN:
443 default:
444 return !alu->is_op3 && (
445 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
446 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
447 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
448 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
449 }
450 }
451
452 static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
453 {
454 switch (bc->chiprev) {
455 case CHIPREV_R600:
456 case CHIPREV_R700:
457 return !alu->is_op3 &&
458 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
459 case CHIPREV_EVERGREEN:
460 default:
461 return !alu->is_op3 &&
462 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
463 }
464 }
465
466 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
467 {
468 switch (bc->chiprev) {
469 case CHIPREV_R600:
470 case CHIPREV_R700:
471 return !alu->is_op3 && (
472 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
473 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
474 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
475 case CHIPREV_EVERGREEN:
476 default:
477 return !alu->is_op3 && (
478 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
479 }
480 }
481
482 /* alu instructions that can only execute on the vector unit */
483 static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
484 {
485 return is_alu_reduction_inst(bc, alu) ||
486 is_alu_mova_inst(bc, alu);
487 }
488
489 /* alu instructions that can only execute on the trans unit */
490 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
491 {
492 switch (bc->chiprev) {
493 case CHIPREV_R600:
494 case CHIPREV_R700:
495 if (!alu->is_op3)
496 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
497 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
498 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
499 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
500 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
501 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
502 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
503 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
504 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
505 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
506 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
507 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
508 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
509 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
510 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
511 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
512 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
513 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
514 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
515 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
516 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
517 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
518 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
519 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
520 else
521 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
522 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
523 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
524 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
525 case CHIPREV_EVERGREEN:
526 default:
527 if (!alu->is_op3)
528 /* Note that FLT_TO_INT* instructions are vector instructions
529 * on Evergreen, despite what the documentation says. */
530 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
531 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
532 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
533 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
534 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
535 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
536 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
537 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
538 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
539 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
540 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
541 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
542 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
543 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
544 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
545 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
546 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
547 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
548 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
549 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
550 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
551 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
552 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
553 else
554 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
555 }
556 }
557
558 /* alu instructions that can execute on any unit */
559 static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
560 {
561 return !is_alu_vec_unit_inst(bc, alu) &&
562 !is_alu_trans_unit_inst(bc, alu);
563 }
564
565 static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
566 struct r600_bc_alu *assignment[5])
567 {
568 struct r600_bc_alu *alu;
569 unsigned i, chan, trans;
570
571 for (i = 0; i < 5; i++)
572 assignment[i] = NULL;
573
574 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
575 chan = alu->dst.chan;
576 if (is_alu_trans_unit_inst(bc, alu))
577 trans = 1;
578 else if (is_alu_vec_unit_inst(bc, alu))
579 trans = 0;
580 else if (assignment[chan])
581 trans = 1; // assume ALU_INST_PREFER_VECTOR
582 else
583 trans = 0;
584
585 if (trans) {
586 if (assignment[4]) {
587 assert(0); //ALU.Trans has already been allocated
588 return -1;
589 }
590 assignment[4] = alu;
591 } else {
592 if (assignment[chan]) {
593 assert(0); //ALU.chan has already been allocated
594 return -1;
595 }
596 assignment[chan] = alu;
597 }
598
599 if (alu->last)
600 break;
601 }
602 return 0;
603 }
604
605 struct alu_bank_swizzle {
606 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
607 int hw_cfile_addr[4];
608 int hw_cfile_elem[4];
609 };
610
611 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
612 [SQ_ALU_VEC_012] = { 0, 1, 2 },
613 [SQ_ALU_VEC_021] = { 0, 2, 1 },
614 [SQ_ALU_VEC_120] = { 1, 2, 0 },
615 [SQ_ALU_VEC_102] = { 1, 0, 2 },
616 [SQ_ALU_VEC_201] = { 2, 0, 1 },
617 [SQ_ALU_VEC_210] = { 2, 1, 0 }
618 };
619
620 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
621 [SQ_ALU_SCL_210] = { 2, 1, 0 },
622 [SQ_ALU_SCL_122] = { 1, 2, 2 },
623 [SQ_ALU_SCL_212] = { 2, 1, 2 },
624 [SQ_ALU_SCL_221] = { 2, 2, 1 }
625 };
626
627 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
628 {
629 int i, cycle, component;
630 /* set up gpr use */
631 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
632 for (component = 0; component < NUM_OF_COMPONENTS; component++)
633 bs->hw_gpr[cycle][component] = -1;
634 for (i = 0; i < 4; i++)
635 bs->hw_cfile_addr[i] = -1;
636 for (i = 0; i < 4; i++)
637 bs->hw_cfile_elem[i] = -1;
638 }
639
640 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
641 {
642 if (bs->hw_gpr[cycle][chan] == -1)
643 bs->hw_gpr[cycle][chan] = sel;
644 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
645 // Another scalar operation has already used GPR read port for channel
646 return -1;
647 }
648 return 0;
649 }
650
651 static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
652 {
653 int res, num_res = 4;
654 if (bc->chiprev >= CHIPREV_R700) {
655 num_res = 2;
656 chan /= 2;
657 }
658 for (res = 0; res < num_res; ++res) {
659 if (bs->hw_cfile_addr[res] == -1) {
660 bs->hw_cfile_addr[res] = sel;
661 bs->hw_cfile_elem[res] = chan;
662 return 0;
663 } else if (bs->hw_cfile_addr[res] == sel &&
664 bs->hw_cfile_elem[res] == chan)
665 return 0; // Read for this scalar element already reserved, nothing to do here.
666 }
667 // All cfile read ports are used, cannot reference vector element
668 return -1;
669 }
670
671 static int is_gpr(unsigned sel)
672 {
673 return (sel >= 0 && sel <= 127);
674 }
675
676 /* CB constants start at 512, and get translated to a kcache index when ALU
677 * clauses are constructed. Note that we handle kcache constants the same way
678 * as (the now gone) cfile constants, is that really required? */
679 static int is_cfile(unsigned sel)
680 {
681 return (sel > 255 && sel < 512) ||
682 (sel > 511 && sel < 4607) || // Kcache before translate
683 (sel > 127 && sel < 192); // Kcache after translate
684 }
685
686 static int is_const(int sel)
687 {
688 return is_cfile(sel) ||
689 (sel >= V_SQ_ALU_SRC_0 &&
690 sel <= V_SQ_ALU_SRC_LITERAL);
691 }
692
693 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
694 struct alu_bank_swizzle *bs, int bank_swizzle)
695 {
696 int r, src, num_src, sel, elem, cycle;
697
698 num_src = r600_bc_get_num_operands(bc, alu);
699 for (src = 0; src < num_src; src++) {
700 sel = alu->src[src].sel;
701 elem = alu->src[src].chan;
702 if (is_gpr(sel)) {
703 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
704 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
705 // Nothing to do; special-case optimization,
706 // second source uses first source’s reservation
707 continue;
708 else {
709 r = reserve_gpr(bs, sel, elem, cycle);
710 if (r)
711 return r;
712 }
713 } else if (is_cfile(sel)) {
714 r = reserve_cfile(bc, bs, sel, elem);
715 if (r)
716 return r;
717 }
718 // No restrictions on PV, PS, literal or special constants
719 }
720 return 0;
721 }
722
723 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
724 struct alu_bank_swizzle *bs, int bank_swizzle)
725 {
726 int r, src, num_src, const_count, sel, elem, cycle;
727
728 num_src = r600_bc_get_num_operands(bc, alu);
729 for (const_count = 0, src = 0; src < num_src; ++src) {
730 sel = alu->src[src].sel;
731 elem = alu->src[src].chan;
732 if (is_const(sel)) { // Any constant, including literal and inline constants
733 if (const_count >= 2)
734 // More than two references to a constant in
735 // transcendental operation.
736 return -1;
737 else
738 const_count++;
739 }
740 if (is_cfile(sel)) {
741 r = reserve_cfile(bc, bs, sel, elem);
742 if (r)
743 return r;
744 }
745 }
746 for (src = 0; src < num_src; ++src) {
747 sel = alu->src[src].sel;
748 elem = alu->src[src].chan;
749 if (is_gpr(sel)) {
750 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
751 if (cycle < const_count)
752 // Cycle for GPR load conflicts with
753 // constant load in transcendental operation.
754 return -1;
755 r = reserve_gpr(bs, sel, elem, cycle);
756 if (r)
757 return r;
758 }
759 // Constants already processed
760 // No restrictions on PV, PS
761 }
762 return 0;
763 }
764
765 static int check_and_set_bank_swizzle(struct r600_bc *bc,
766 struct r600_bc_alu *slots[5])
767 {
768 struct alu_bank_swizzle bs;
769 int bank_swizzle[5];
770 int i, r = 0, forced = 0;
771
772 for (i = 0; i < 5; i++)
773 if (slots[i] && slots[i]->bank_swizzle_force) {
774 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
775 forced = 1;
776 }
777
778 if (forced)
779 return 0;
780
781 // just check every possible combination of bank swizzle
782 // not very efficent, but works on the first try in most of the cases
783 for (i = 0; i < 4; i++)
784 bank_swizzle[i] = SQ_ALU_VEC_012;
785 bank_swizzle[4] = SQ_ALU_SCL_210;
786 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
787 init_bank_swizzle(&bs);
788 for (i = 0; i < 4; i++) {
789 if (slots[i]) {
790 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
791 if (r)
792 break;
793 }
794 }
795 if (!r && slots[4]) {
796 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
797 }
798 if (!r) {
799 for (i = 0; i < 5; i++) {
800 if (slots[i])
801 slots[i]->bank_swizzle = bank_swizzle[i];
802 }
803 return 0;
804 }
805
806 for (i = 0; i < 5; i++) {
807 bank_swizzle[i]++;
808 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
809 break;
810 else
811 bank_swizzle[i] = SQ_ALU_VEC_012;
812 }
813 }
814
815 // couldn't find a working swizzle
816 return -1;
817 }
818
819 static int replace_gpr_with_pv_ps(struct r600_bc *bc,
820 struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
821 {
822 struct r600_bc_alu *prev[5];
823 int gpr[5], chan[5];
824 int i, j, r, src, num_src;
825
826 r = assign_alu_units(bc, alu_prev, prev);
827 if (r)
828 return r;
829
830 for (i = 0; i < 5; ++i) {
831 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
832 gpr[i] = prev[i]->dst.sel;
833 /* cube writes more than PV.X */
834 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
835 chan[i] = 0;
836 else
837 chan[i] = prev[i]->dst.chan;
838 } else
839 gpr[i] = -1;
840 }
841
842 for (i = 0; i < 5; ++i) {
843 struct r600_bc_alu *alu = slots[i];
844 if(!alu)
845 continue;
846
847 num_src = r600_bc_get_num_operands(bc, alu);
848 for (src = 0; src < num_src; ++src) {
849 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
850 continue;
851
852 if (alu->src[src].sel == gpr[4] &&
853 alu->src[src].chan == chan[4]) {
854 alu->src[src].sel = V_SQ_ALU_SRC_PS;
855 alu->src[src].chan = 0;
856 continue;
857 }
858
859 for (j = 0; j < 4; ++j) {
860 if (alu->src[src].sel == gpr[j] &&
861 alu->src[src].chan == j) {
862 alu->src[src].sel = V_SQ_ALU_SRC_PV;
863 alu->src[src].chan = chan[j];
864 break;
865 }
866 }
867 }
868 }
869
870 return 0;
871 }
872
873 void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
874 {
875 switch(value) {
876 case 0:
877 *sel = V_SQ_ALU_SRC_0;
878 break;
879 case 1:
880 *sel = V_SQ_ALU_SRC_1_INT;
881 break;
882 case -1:
883 *sel = V_SQ_ALU_SRC_M_1_INT;
884 break;
885 case 0x3F800000: // 1.0f
886 *sel = V_SQ_ALU_SRC_1;
887 break;
888 case 0x3F000000: // 0.5f
889 *sel = V_SQ_ALU_SRC_0_5;
890 break;
891 case 0xBF800000: // -1.0f
892 *sel = V_SQ_ALU_SRC_1;
893 *neg ^= 1;
894 break;
895 case 0xBF000000: // -0.5f
896 *sel = V_SQ_ALU_SRC_0_5;
897 *neg ^= 1;
898 break;
899 default:
900 *sel = V_SQ_ALU_SRC_LITERAL;
901 break;
902 }
903 }
904
905 /* compute how many literal are needed */
906 static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
907 uint32_t literal[4], unsigned *nliteral)
908 {
909 unsigned num_src = r600_bc_get_num_operands(bc, alu);
910 unsigned i, j;
911
912 for (i = 0; i < num_src; ++i) {
913 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
914 uint32_t value = alu->src[i].value;
915 unsigned found = 0;
916 for (j = 0; j < *nliteral; ++j) {
917 if (literal[j] == value) {
918 found = 1;
919 break;
920 }
921 }
922 if (!found) {
923 if (*nliteral >= 4)
924 return -EINVAL;
925 literal[(*nliteral)++] = value;
926 }
927 }
928 }
929 return 0;
930 }
931
932 static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
933 struct r600_bc_alu *alu,
934 uint32_t literal[4], unsigned nliteral)
935 {
936 unsigned num_src = r600_bc_get_num_operands(bc, alu);
937 unsigned i, j;
938
939 for (i = 0; i < num_src; ++i) {
940 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
941 uint32_t value = alu->src[i].value;
942 for (j = 0; j < nliteral; ++j) {
943 if (literal[j] == value) {
944 alu->src[i].chan = j;
945 break;
946 }
947 }
948 }
949 }
950 }
951
952 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
953 struct r600_bc_alu *alu_prev)
954 {
955 struct r600_bc_alu *prev[5];
956 struct r600_bc_alu *result[5] = { NULL };
957
958 uint32_t literal[4], prev_literal[4];
959 unsigned nliteral = 0, prev_nliteral = 0;
960
961 int i, j, r, src, num_src;
962 int num_once_inst = 0;
963 int have_mova = 0, have_rel = 0;
964
965 r = assign_alu_units(bc, alu_prev, prev);
966 if (r)
967 return r;
968
969 for (i = 0; i < 5; ++i) {
970 struct r600_bc_alu *alu;
971
972 /* check number of literals */
973 if (prev[i]) {
974 if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
975 return 0;
976 if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
977 return 0;
978 if (is_alu_mova_inst(bc, prev[i])) {
979 if (have_rel)
980 return 0;
981 have_mova = 1;
982 }
983 num_once_inst += is_alu_once_inst(bc, prev[i]);
984 }
985 if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
986 return 0;
987
988 // let's check used slots
989 if (prev[i] && !slots[i]) {
990 result[i] = prev[i];
991 continue;
992 } else if (prev[i] && slots[i]) {
993 if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
994 // trans unit is still free try to use it
995 if (is_alu_any_unit_inst(bc, slots[i])) {
996 result[i] = prev[i];
997 result[4] = slots[i];
998 } else if (is_alu_any_unit_inst(bc, prev[i])) {
999 result[i] = slots[i];
1000 result[4] = prev[i];
1001 } else
1002 return 0;
1003 } else
1004 return 0;
1005 } else if(!slots[i]) {
1006 continue;
1007 } else
1008 result[i] = slots[i];
1009
1010 // let's check source gprs
1011 alu = slots[i];
1012 num_once_inst += is_alu_once_inst(bc, alu);
1013
1014 num_src = r600_bc_get_num_operands(bc, alu);
1015 for (src = 0; src < num_src; ++src) {
1016 if (alu->src[src].rel) {
1017 if (have_mova)
1018 return 0;
1019 have_rel = 1;
1020 }
1021
1022 // constants doesn't matter
1023 if (!is_gpr(alu->src[src].sel))
1024 continue;
1025
1026 for (j = 0; j < 5; ++j) {
1027 if (!prev[j] || !prev[j]->dst.write)
1028 continue;
1029
1030 // if it's relative then we can't determin which gpr is really used
1031 if (prev[j]->dst.chan == alu->src[src].chan &&
1032 (prev[j]->dst.sel == alu->src[src].sel ||
1033 prev[j]->dst.rel || alu->src[src].rel))
1034 return 0;
1035 }
1036 }
1037 }
1038
1039 /* more than one PRED_ or KILL_ ? */
1040 if (num_once_inst > 1)
1041 return 0;
1042
1043 /* check if the result can still be swizzlet */
1044 r = check_and_set_bank_swizzle(bc, result);
1045 if (r)
1046 return 0;
1047
1048 /* looks like everything worked out right, apply the changes */
1049
1050 /* undo adding previus literals */
1051 bc->cf_last->ndw -= align(prev_nliteral, 2);
1052
1053 /* sort instructions */
1054 for (i = 0; i < 5; ++i) {
1055 slots[i] = result[i];
1056 if (result[i]) {
1057 LIST_DEL(&result[i]->list);
1058 result[i]->last = 0;
1059 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1060 }
1061 }
1062
1063 /* determine new last instruction */
1064 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
1065
1066 /* determine new first instruction */
1067 for (i = 0; i < 5; ++i) {
1068 if (result[i]) {
1069 bc->cf_last->curr_bs_head = result[i];
1070 break;
1071 }
1072 }
1073
1074 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1075 bc->cf_last->prev2_bs_head = NULL;
1076
1077 return 0;
1078 }
1079
1080 /* This code handles kcache lines as single blocks of 32 constants. We could
1081 * probably do slightly better by recognizing that we actually have two
1082 * consecutive lines of 16 constants, but the resulting code would also be
1083 * somewhat more complicated. */
1084 static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
1085 {
1086 struct r600_bc_kcache *kcache = bc->cf_last->kcache;
1087 unsigned int required_lines;
1088 unsigned int free_lines = 0;
1089 unsigned int cache_line[3];
1090 unsigned int count = 0;
1091 unsigned int i, j;
1092 int r;
1093
1094 /* Collect required cache lines. */
1095 for (i = 0; i < 3; ++i) {
1096 bool found = false;
1097 unsigned int line;
1098
1099 if (alu->src[i].sel < 512)
1100 continue;
1101
1102 line = ((alu->src[i].sel - 512) / 32) * 2;
1103
1104 for (j = 0; j < count; ++j) {
1105 if (cache_line[j] == line) {
1106 found = true;
1107 break;
1108 }
1109 }
1110
1111 if (!found)
1112 cache_line[count++] = line;
1113 }
1114
1115 /* This should never actually happen. */
1116 if (count >= 3) return -ENOMEM;
1117
1118 for (i = 0; i < 2; ++i) {
1119 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1120 ++free_lines;
1121 }
1122 }
1123
1124 /* Filter lines pulled in by previous intructions. Note that this is
1125 * only for the required_lines count, we can't remove these from the
1126 * cache_line array since we may have to start a new ALU clause. */
1127 for (i = 0, required_lines = count; i < count; ++i) {
1128 for (j = 0; j < 2; ++j) {
1129 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1130 kcache[j].addr == cache_line[i]) {
1131 --required_lines;
1132 break;
1133 }
1134 }
1135 }
1136
1137 /* Start a new ALU clause if needed. */
1138 if (required_lines > free_lines) {
1139 if ((r = r600_bc_add_cf(bc))) {
1140 return r;
1141 }
1142 bc->cf_last->inst = (type << 3);
1143 kcache = bc->cf_last->kcache;
1144 }
1145
1146 /* Setup the kcache lines. */
1147 for (i = 0; i < count; ++i) {
1148 bool found = false;
1149
1150 for (j = 0; j < 2; ++j) {
1151 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1152 kcache[j].addr == cache_line[i]) {
1153 found = true;
1154 break;
1155 }
1156 }
1157
1158 if (found) continue;
1159
1160 for (j = 0; j < 2; ++j) {
1161 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1162 kcache[j].bank = 0;
1163 kcache[j].addr = cache_line[i];
1164 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1165 break;
1166 }
1167 }
1168 }
1169
1170 /* Alter the src operands to refer to the kcache. */
1171 for (i = 0; i < 3; ++i) {
1172 static const unsigned int base[] = {128, 160, 256, 288};
1173 unsigned int line;
1174
1175 if (alu->src[i].sel < 512)
1176 continue;
1177
1178 alu->src[i].sel -= 512;
1179 line = (alu->src[i].sel / 32) * 2;
1180
1181 for (j = 0; j < 2; ++j) {
1182 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1183 kcache[j].addr == line) {
1184 alu->src[i].sel &= 0x1f;
1185 alu->src[i].sel += base[j];
1186 break;
1187 }
1188 }
1189 }
1190
1191 return 0;
1192 }
1193
1194 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
1195 {
1196 struct r600_bc_alu *nalu = r600_bc_alu();
1197 struct r600_bc_alu *lalu;
1198 int i, r;
1199
1200 if (nalu == NULL)
1201 return -ENOMEM;
1202 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
1203
1204 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1205 /* check if we could add it anyway */
1206 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1207 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1208 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1209 if (lalu->predicate) {
1210 bc->force_add_cf = 1;
1211 break;
1212 }
1213 }
1214 } else
1215 bc->force_add_cf = 1;
1216 }
1217
1218 /* cf can contains only alu or only vtx or only tex */
1219 if (bc->cf_last == NULL || bc->force_add_cf) {
1220 r = r600_bc_add_cf(bc);
1221 if (r) {
1222 free(nalu);
1223 return r;
1224 }
1225 }
1226 bc->cf_last->inst = (type << 3);
1227
1228 /* Setup the kcache for this ALU instruction. This will start a new
1229 * ALU clause if needed. */
1230 if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
1231 free(nalu);
1232 return r;
1233 }
1234
1235 if (!bc->cf_last->curr_bs_head) {
1236 bc->cf_last->curr_bs_head = nalu;
1237 }
1238 /* number of gpr == the last gpr used in any alu */
1239 for (i = 0; i < 3; i++) {
1240 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1241 bc->ngpr = nalu->src[i].sel + 1;
1242 }
1243 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1244 r600_bc_special_constants(nalu->src[i].value,
1245 &nalu->src[i].sel, &nalu->src[i].neg);
1246 }
1247 if (nalu->dst.sel >= bc->ngpr) {
1248 bc->ngpr = nalu->dst.sel + 1;
1249 }
1250 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1251 /* each alu use 2 dwords */
1252 bc->cf_last->ndw += 2;
1253 bc->ndw += 2;
1254
1255 /* process cur ALU instructions for bank swizzle */
1256 if (nalu->last) {
1257 uint32_t literal[4];
1258 unsigned nliteral;
1259 struct r600_bc_alu *slots[5];
1260 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1261 if (r)
1262 return r;
1263
1264 if (bc->cf_last->prev_bs_head) {
1265 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1266 if (r)
1267 return r;
1268 }
1269
1270 if (bc->cf_last->prev_bs_head) {
1271 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1272 if (r)
1273 return r;
1274 }
1275
1276 r = check_and_set_bank_swizzle(bc, slots);
1277 if (r)
1278 return r;
1279
1280 for (i = 0, nliteral = 0; i < 5; i++) {
1281 if (slots[i]) {
1282 r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
1283 if (r)
1284 return r;
1285 }
1286 }
1287 bc->cf_last->ndw += align(nliteral, 2);
1288
1289 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1290 * worst case */
1291 if ((bc->cf_last->ndw >> 1) >= 120) {
1292 bc->force_add_cf = 1;
1293 }
1294
1295 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1296 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1297 bc->cf_last->curr_bs_head = NULL;
1298 }
1299 return 0;
1300 }
1301
1302 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
1303 {
1304 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1305 }
1306
1307 static void r600_bc_remove_alu(struct r600_bc_cf *cf, struct r600_bc_alu *alu)
1308 {
1309 if (alu->last && alu->list.prev != &cf->alu) {
1310 PREV_ALU(alu)->last = 1;
1311 }
1312 LIST_DEL(&alu->list);
1313 free(alu);
1314 cf->ndw -= 2;
1315 }
1316
1317 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
1318 {
1319 struct r600_bc_vtx *nvtx = r600_bc_vtx();
1320 int r;
1321
1322 if (nvtx == NULL)
1323 return -ENOMEM;
1324 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
1325
1326 /* cf can contains only alu or only vtx or only tex */
1327 if (bc->cf_last == NULL ||
1328 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1329 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
1330 bc->force_add_cf) {
1331 r = r600_bc_add_cf(bc);
1332 if (r) {
1333 free(nvtx);
1334 return r;
1335 }
1336 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1337 }
1338 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1339 /* each fetch use 4 dwords */
1340 bc->cf_last->ndw += 4;
1341 bc->ndw += 4;
1342 if ((bc->cf_last->ndw / 4) > 7)
1343 bc->force_add_cf = 1;
1344 return 0;
1345 }
1346
1347 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
1348 {
1349 struct r600_bc_tex *ntex = r600_bc_tex();
1350 int r;
1351
1352 if (ntex == NULL)
1353 return -ENOMEM;
1354 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
1355
1356 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1357 if (bc->cf_last != NULL &&
1358 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
1359 struct r600_bc_tex *ttex;
1360 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1361 if (ttex->dst_gpr == ntex->src_gpr) {
1362 bc->force_add_cf = 1;
1363 break;
1364 }
1365 }
1366 }
1367
1368 /* cf can contains only alu or only vtx or only tex */
1369 if (bc->cf_last == NULL ||
1370 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1371 bc->force_add_cf) {
1372 r = r600_bc_add_cf(bc);
1373 if (r) {
1374 free(ntex);
1375 return r;
1376 }
1377 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1378 }
1379 if (ntex->src_gpr >= bc->ngpr) {
1380 bc->ngpr = ntex->src_gpr + 1;
1381 }
1382 if (ntex->dst_gpr >= bc->ngpr) {
1383 bc->ngpr = ntex->dst_gpr + 1;
1384 }
1385 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1386 /* each texture fetch use 4 dwords */
1387 bc->cf_last->ndw += 4;
1388 bc->ndw += 4;
1389 if ((bc->cf_last->ndw / 4) > 7)
1390 bc->force_add_cf = 1;
1391 return 0;
1392 }
1393
1394 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
1395 {
1396 int r;
1397 r = r600_bc_add_cf(bc);
1398 if (r)
1399 return r;
1400
1401 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1402 bc->cf_last->inst = inst;
1403 return 0;
1404 }
1405
1406 /* common to all 3 families */
1407 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
1408 {
1409 unsigned fetch_resource_start = 0;
1410
1411 /* check if we are fetch shader */
1412 /* fetch shader can also access vertex resource,
1413 * first fetch shader resource is at 160
1414 */
1415 if (bc->type == -1) {
1416 switch (bc->chiprev) {
1417 /* r600 */
1418 case CHIPREV_R600:
1419 /* r700 */
1420 case CHIPREV_R700:
1421 fetch_resource_start = 160;
1422 break;
1423 /* evergreen */
1424 case CHIPREV_EVERGREEN:
1425 fetch_resource_start = 0;
1426 break;
1427 default:
1428 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
1429 __FILE__, __func__, __LINE__, bc->chiprev);
1430 break;
1431 }
1432 }
1433 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
1434 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1435 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1436 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
1437 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1438 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1439 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1440 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1441 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1442 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1443 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1444 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1445 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1446 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1447 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1448 bc->bytecode[id++] = S_SQ_VTX_WORD2_OFFSET(vtx->offset) |
1449 S_SQ_VTX_WORD2_MEGA_FETCH(1);
1450 bc->bytecode[id++] = 0;
1451 return 0;
1452 }
1453
1454 /* common to all 3 families */
1455 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
1456 {
1457 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1458 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1459 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1460 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1461 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1462 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1463 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1464 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1465 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1466 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1467 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1468 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1469 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1470 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1471 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1472 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1473 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1474 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1475 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1476 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1477 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1478 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1479 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1480 bc->bytecode[id++] = 0;
1481 return 0;
1482 }
1483
1484 /* r600 only, r700/eg bits in r700_asm.c */
1485 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1486 {
1487 /* don't replace gpr by pv or ps for destination register */
1488 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1489 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1490 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1491 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1492 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1493 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1494 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1495 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1496 S_SQ_ALU_WORD0_LAST(alu->last);
1497
1498 if (alu->is_op3) {
1499 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1500 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1501 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1502 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1503 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1504 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1505 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1506 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1507 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1508 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1509 } else {
1510 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1511 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1512 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1513 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1514 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1515 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1516 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1517 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1518 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1519 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1520 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1521 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1522 }
1523 return 0;
1524 }
1525
1526 enum cf_class
1527 {
1528 CF_CLASS_ALU,
1529 CF_CLASS_TEXTURE,
1530 CF_CLASS_VERTEX,
1531 CF_CLASS_EXPORT,
1532 CF_CLASS_OTHER
1533 };
1534
1535 static enum cf_class r600_bc_cf_class(struct r600_bc_cf *cf)
1536 {
1537 switch (cf->inst) {
1538 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1539 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1540 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1541 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1542 return CF_CLASS_ALU;
1543
1544 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1545 return CF_CLASS_TEXTURE;
1546
1547 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1548 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1549 return CF_CLASS_VERTEX;
1550
1551 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1552 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1553 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1554 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1555 return CF_CLASS_EXPORT;
1556
1557 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1558 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1559 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1560 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1561 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1562 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1563 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1564 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1565 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1566 case V_SQ_CF_WORD1_SQ_CF_INST_NOP:
1567 return CF_CLASS_OTHER;
1568
1569 default:
1570 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1571 return -EINVAL;
1572 }
1573 }
1574
1575 /* common for r600/r700 - eg in eg_asm.c */
1576 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1577 {
1578 unsigned id = cf->id;
1579 unsigned end_of_program = bc->cf.prev == &cf->list;
1580
1581 switch (r600_bc_cf_class(cf)) {
1582 case CF_CLASS_ALU:
1583 assert(!end_of_program);
1584 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1585 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1586 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1587 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1588
1589 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1590 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1591 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1592 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1593 S_SQ_CF_ALU_WORD1_BARRIER(cf->barrier) |
1594 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
1595 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1596 break;
1597 case CF_CLASS_TEXTURE:
1598 case CF_CLASS_VERTEX:
1599 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1600 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1601 S_SQ_CF_WORD1_BARRIER(cf->barrier) |
1602 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1) |
1603 S_SQ_CF_WORD1_END_OF_PROGRAM(end_of_program);
1604 break;
1605 case CF_CLASS_EXPORT:
1606 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1607 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1608 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1609 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1610 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1611 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1612 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1613 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1614 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1615 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1616 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) |
1617 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(end_of_program);
1618 break;
1619 case CF_CLASS_OTHER:
1620 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1621 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1622 S_SQ_CF_WORD1_BARRIER(cf->barrier) |
1623 S_SQ_CF_WORD1_COND(cf->cond) |
1624 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1625 S_SQ_CF_WORD1_END_OF_PROGRAM(end_of_program);
1626
1627 break;
1628 default:
1629 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1630 return -EINVAL;
1631 }
1632 return 0;
1633 }
1634
1635 struct gpr_usage_range {
1636 int replacement;
1637 int rel_block;
1638 int start;
1639 int end;
1640 };
1641
1642 struct gpr_usage {
1643 unsigned channels:4;
1644 int first_write;
1645 int last_write[4];
1646 unsigned nranges;
1647 struct gpr_usage_range *ranges;
1648 };
1649
1650 static struct gpr_usage_range* last_gpr_usage_range(struct gpr_usage *usage)
1651 {
1652 if (usage->nranges)
1653 return usage->ranges + usage->nranges - 1;
1654 else
1655 return NULL;
1656 }
1657
1658 static struct gpr_usage_range* add_gpr_usage_range(struct gpr_usage *usage)
1659 {
1660 struct gpr_usage_range *range;
1661
1662 usage->nranges++;
1663 usage->ranges = realloc(usage->ranges, usage->nranges * sizeof(struct gpr_usage_range));
1664 if (!usage->ranges)
1665 return NULL;
1666
1667 range = last_gpr_usage_range(usage);
1668 range->replacement = -1; /* no prefered replacement */
1669 range->rel_block = -1;
1670 range->start = -1;
1671 range->end = -1;
1672
1673 return range;
1674 }
1675
1676 static void notice_gpr_read(struct gpr_usage *usage, int id, unsigned chan)
1677 {
1678 struct gpr_usage_range* range;
1679
1680 usage->channels |= 1 << chan;
1681 usage->first_write = -1;
1682 if (!usage->nranges) {
1683 range = add_gpr_usage_range(usage);
1684 } else
1685 range = last_gpr_usage_range(usage);
1686
1687 if (range && range->end < id)
1688 range->end = id;
1689 }
1690
1691 static void notice_gpr_rel_read(struct r600_bc *bc, struct gpr_usage usage[128],
1692 int id, unsigned gpr, unsigned chan)
1693 {
1694 unsigned i;
1695 for (i = gpr; i < bc->ngpr; ++i)
1696 notice_gpr_read(&usage[i], id, chan);
1697
1698 last_gpr_usage_range(&usage[gpr])->rel_block = bc->ngpr - gpr;
1699 }
1700
1701 static void notice_gpr_last_write(struct gpr_usage *usage, int id, unsigned chan)
1702 {
1703 usage->last_write[chan] = id;
1704 }
1705
1706 static void notice_gpr_write(struct gpr_usage *usage, int id, unsigned chan,
1707 int predicate, int prefered_replacement)
1708 {
1709 struct gpr_usage_range* last_range = last_gpr_usage_range(usage);
1710 int start = usage->first_write != -1 ? usage->first_write : id;
1711 usage->channels &= ~(1 << chan);
1712 if (usage->channels) {
1713 if (usage->first_write == -1)
1714 usage->first_write = id;
1715 } else if (!last_range || (last_range->start != start && !predicate)) {
1716 usage->first_write = start;
1717 struct gpr_usage_range* range = add_gpr_usage_range(usage);
1718 range->replacement = prefered_replacement;
1719 range->start = start;
1720 } else if (last_range->start == start && prefered_replacement != -1) {
1721 last_range->replacement = prefered_replacement;
1722 }
1723 notice_gpr_last_write(usage, id, chan);
1724 }
1725
1726 static void notice_gpr_rel_last_write(struct gpr_usage usage[128], int id, unsigned chan)
1727 {
1728 unsigned i;
1729 for (i = 0; i < 128; ++i)
1730 notice_gpr_last_write(&usage[i], id, chan);
1731 }
1732
1733 static void notice_gpr_rel_write(struct gpr_usage usage[128], int id, unsigned chan)
1734 {
1735 unsigned i;
1736 for (i = 0; i < 128; ++i)
1737 notice_gpr_write(&usage[i], id, chan, 1, -1);
1738 }
1739
1740 static void notice_alu_src_gprs(struct r600_bc *bc, struct r600_bc_alu *alu,
1741 struct gpr_usage usage[128], int id)
1742 {
1743 unsigned src, num_src;
1744
1745 num_src = r600_bc_get_num_operands(bc, alu);
1746 for (src = 0; src < num_src; ++src) {
1747 // constants doesn't matter
1748 if (!is_gpr(alu->src[src].sel))
1749 continue;
1750
1751 if (alu->src[src].rel)
1752 notice_gpr_rel_read(bc, usage, id, alu->src[src].sel, alu->src[src].chan);
1753 else
1754 notice_gpr_read(&usage[alu->src[src].sel], id, alu->src[src].chan);
1755 }
1756 }
1757
1758 static void notice_alu_dst_gprs(struct r600_bc_alu *alu_first, struct gpr_usage usage[128],
1759 int id, int predicate)
1760 {
1761 struct r600_bc_alu *alu;
1762 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
1763 if (alu->dst.write) {
1764 if (alu->dst.rel)
1765 notice_gpr_rel_write(usage, id, alu->dst.chan);
1766 else if (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV && is_gpr(alu->src[0].sel))
1767 notice_gpr_write(&usage[alu->dst.sel], id, alu->dst.chan,
1768 predicate, alu->src[0].sel);
1769 else
1770 notice_gpr_write(&usage[alu->dst.sel], id, alu->dst.chan, predicate, -1);
1771 }
1772
1773 if (alu->last)
1774 break;
1775 }
1776 }
1777
1778 static void notice_tex_gprs(struct r600_bc *bc, struct r600_bc_tex *tex,
1779 struct gpr_usage usage[128],
1780 int id, int predicate)
1781 {
1782 if (tex->src_rel) {
1783 if (tex->src_sel_x < 4)
1784 notice_gpr_rel_read(bc, usage, id, tex->src_gpr, tex->src_sel_x);
1785 if (tex->src_sel_y < 4)
1786 notice_gpr_rel_read(bc, usage, id, tex->src_gpr, tex->src_sel_y);
1787 if (tex->src_sel_z < 4)
1788 notice_gpr_rel_read(bc, usage, id, tex->src_gpr, tex->src_sel_z);
1789 if (tex->src_sel_w < 4)
1790 notice_gpr_rel_read(bc, usage, id, tex->src_gpr, tex->src_sel_w);
1791 } else {
1792 if (tex->src_sel_x < 4)
1793 notice_gpr_read(&usage[tex->src_gpr], id, tex->src_sel_x);
1794 if (tex->src_sel_y < 4)
1795 notice_gpr_read(&usage[tex->src_gpr], id, tex->src_sel_y);
1796 if (tex->src_sel_z < 4)
1797 notice_gpr_read(&usage[tex->src_gpr], id, tex->src_sel_z);
1798 if (tex->src_sel_w < 4)
1799 notice_gpr_read(&usage[tex->src_gpr], id, tex->src_sel_w);
1800 }
1801 if (tex->dst_rel) {
1802 if (tex->dst_sel_x != 7)
1803 notice_gpr_rel_write(usage, id, 0);
1804 if (tex->dst_sel_y != 7)
1805 notice_gpr_rel_write(usage, id, 1);
1806 if (tex->dst_sel_z != 7)
1807 notice_gpr_rel_write(usage, id, 2);
1808 if (tex->dst_sel_w != 7)
1809 notice_gpr_rel_write(usage, id, 3);
1810 } else {
1811 if (tex->dst_sel_x != 7)
1812 notice_gpr_write(&usage[tex->dst_gpr], id, 0, predicate, -1);
1813 if (tex->dst_sel_y != 7)
1814 notice_gpr_write(&usage[tex->dst_gpr], id, 1, predicate, -1);
1815 if (tex->dst_sel_z != 7)
1816 notice_gpr_write(&usage[tex->dst_gpr], id, 2, predicate, -1);
1817 if (tex->dst_sel_w != 7)
1818 notice_gpr_write(&usage[tex->dst_gpr], id, 3, predicate, -1);
1819 }
1820 }
1821
1822 static void notice_vtx_gprs(struct r600_bc_vtx *vtx, struct gpr_usage usage[128],
1823 int id, int predicate)
1824 {
1825 notice_gpr_read(&usage[vtx->src_gpr], id, vtx->src_sel_x);
1826
1827 if (vtx->dst_sel_x != 7)
1828 notice_gpr_write(&usage[vtx->dst_gpr], id, 0, predicate, -1);
1829 if (vtx->dst_sel_y != 7)
1830 notice_gpr_write(&usage[vtx->dst_gpr], id, 1, predicate, -1);
1831 if (vtx->dst_sel_z != 7)
1832 notice_gpr_write(&usage[vtx->dst_gpr], id, 2, predicate, -1);
1833 if (vtx->dst_sel_w != 7)
1834 notice_gpr_write(&usage[vtx->dst_gpr], id, 3, predicate, -1);
1835 }
1836
1837 static void notice_export_gprs(struct r600_bc_cf *cf, struct gpr_usage usage[128],
1838 struct r600_bc_cf *export_cf[128], int export_remap[128])
1839 {
1840 //TODO handle other memory operations
1841 struct gpr_usage *output = &usage[cf->output.gpr];
1842 int id = MAX4(output->last_write[0], output->last_write[1],
1843 output->last_write[2], output->last_write[3]);
1844 id += 0x100;
1845 id &= ~0xFF;
1846
1847 export_cf[cf->output.gpr] = cf;
1848 export_remap[cf->output.gpr] = id;
1849 if (cf->output.swizzle_x < 4)
1850 notice_gpr_read(output, id, cf->output.swizzle_x);
1851 if (cf->output.swizzle_y < 4)
1852 notice_gpr_read(output, id, cf->output.swizzle_y);
1853 if (cf->output.swizzle_z < 4)
1854 notice_gpr_read(output, id, cf->output.swizzle_z);
1855 if (cf->output.swizzle_w < 4)
1856 notice_gpr_read(output, id, cf->output.swizzle_w);
1857 }
1858
1859 static struct gpr_usage_range *find_src_range(struct gpr_usage *usage, int id)
1860 {
1861 unsigned i;
1862 for (i = 0; i < usage->nranges; ++i) {
1863 struct gpr_usage_range* range = &usage->ranges[i];
1864
1865 if (range->start < id && id <= range->end)
1866 return range;
1867 }
1868 return NULL;
1869 }
1870
1871 static struct gpr_usage_range *find_dst_range(struct gpr_usage *usage, int id)
1872 {
1873 unsigned i;
1874 for (i = 0; i < usage->nranges; ++i) {
1875 struct gpr_usage_range* range = &usage->ranges[i];
1876 int end = range->end;
1877
1878 if (range->start <= id && (id < end || end == -1))
1879 return range;
1880 }
1881 return NULL;
1882 }
1883
1884 static int is_barrier_needed(struct gpr_usage *usage, int id, unsigned chan, int last_barrier)
1885 {
1886 if (usage->last_write[chan] != (id & ~0xFF))
1887 return usage->last_write[chan] >= last_barrier;
1888 else
1889 return 0;
1890 }
1891
1892 static int is_intersection(struct gpr_usage_range* a, struct gpr_usage_range* b)
1893 {
1894 return a->start <= b->end && b->start < a->end;
1895 }
1896
1897 static int rate_replacement(struct gpr_usage usage[128], unsigned current, unsigned gpr,
1898 struct gpr_usage_range* range)
1899 {
1900 int max_gpr = gpr + MAX2(range->rel_block, 1);
1901 int best_start = 0x3FFFFFFF, best_end = 0x3FFFFFFF;
1902 unsigned i;
1903
1904 for (; gpr < max_gpr; ++gpr) {
1905
1906 if (gpr >= 128) /* relative gpr block won't fit into clause temporaries */
1907 return -1; /* forget it */
1908
1909 if (gpr == current) /* ignore ranges of to be replaced register */
1910 continue;
1911
1912 for (i = 0; i < usage[gpr].nranges; ++i) {
1913 if (usage[gpr].ranges[i].replacement < gpr)
1914 continue; /* ignore already remapped ranges */
1915
1916 if (is_intersection(&usage[gpr].ranges[i], range))
1917 return -1; /* forget it if usages overlap */
1918
1919 if (range->start >= usage[gpr].ranges[i].end)
1920 best_start = MIN2(best_start, range->start - usage[gpr].ranges[i].end);
1921
1922 if (range->end != -1 && range->end <= usage[gpr].ranges[i].start)
1923 best_end = MIN2(best_end, usage[gpr].ranges[i].start - range->end);
1924 }
1925 }
1926 return best_start + best_end;
1927 }
1928
1929 static void find_replacement(struct gpr_usage usage[128], unsigned current,
1930 struct gpr_usage_range *range)
1931 {
1932 unsigned i, j;
1933 int best_gpr = -1, best_rate = 0x7FFFFFFF;
1934
1935 if (range->replacement == current)
1936 return; /* register prefers to be not remapped */
1937
1938 if (range->replacement != -1 && range->replacement <= current) {
1939 struct gpr_usage_range *other = find_src_range(&usage[range->replacement], range->start);
1940 if (other && other->replacement != -1)
1941 range->replacement = other->replacement;
1942 }
1943
1944 if (range->replacement != -1 && range->replacement < current) {
1945 int rate = rate_replacement(usage, current, range->replacement, range);
1946
1947 /* check if prefered replacement can be used */
1948 if (rate != -1) {
1949 best_rate = rate;
1950 best_gpr = range->replacement;
1951 }
1952 }
1953
1954 if (best_gpr == -1 && (range->start & ~0xFF) == (range->end & ~0xFF)) {
1955 /* register is just used inside one ALU clause */
1956 /* try to use clause temporaries for it */
1957 for (i = 127; i > 123; --i) {
1958 int rate = rate_replacement(usage, current, i, range);
1959
1960 if (rate == -1) /* can't be used because ranges overlap */
1961 continue;
1962
1963 if (rate < best_rate) {
1964 best_rate = rate;
1965 best_gpr = i;
1966
1967 /* can't get better than this */
1968 if (rate == 0)
1969 break;
1970 }
1971 }
1972 }
1973
1974 if (best_gpr == -1) {
1975 for (i = 0; i < current; ++i) {
1976 int rate = rate_replacement(usage, current, i, range);
1977
1978 if (rate == -1) /* can't be used because ranges overlap */
1979 continue;
1980
1981 if (rate < best_rate) {
1982 best_rate = rate;
1983 best_gpr = i;
1984
1985 /* can't get better than this */
1986 if (rate == 0)
1987 break;
1988 }
1989 }
1990 }
1991
1992 if (best_gpr != -1) {
1993 struct gpr_usage_range *reservation = add_gpr_usage_range(&usage[best_gpr]);
1994 reservation->replacement = best_gpr;
1995 reservation->rel_block = -1;
1996 reservation->start = range->start;
1997 reservation->end = range->end;
1998 } else
1999 best_gpr = current;
2000
2001 range->replacement = best_gpr;
2002 if (range->rel_block == -1)
2003 return; /* no relative block to handle we are done here */
2004
2005 /* set prefered register for the whole relative register block */
2006 for (i = current + 1, ++best_gpr; i < current + range->rel_block; ++i, ++best_gpr) {
2007 for (j = 0; j < usage[i].nranges; ++j) {
2008 if (is_intersection(&usage[i].ranges[j], range))
2009 usage[i].ranges[j].replacement = best_gpr;
2010 }
2011 }
2012 }
2013
2014 static void replace_alu_gprs(struct r600_bc *bc, struct r600_bc_alu *alu, struct gpr_usage usage[128],
2015 int id, int last_barrier, unsigned *barrier)
2016 {
2017 struct gpr_usage *cur_usage;
2018 struct gpr_usage_range *range;
2019 unsigned src, num_src;
2020
2021 num_src = r600_bc_get_num_operands(bc, alu);
2022 for (src = 0; src < num_src; ++src) {
2023 // constants doesn't matter
2024 if (!is_gpr(alu->src[src].sel))
2025 continue;
2026
2027 cur_usage = &usage[alu->src[src].sel];
2028 range = find_src_range(cur_usage, id);
2029 alu->src[src].sel = range->replacement;
2030
2031 *barrier |= is_barrier_needed(cur_usage, id, alu->src[src].chan, last_barrier);
2032 }
2033
2034 if (alu->dst.write) {
2035 cur_usage = &usage[alu->dst.sel];
2036 range = find_dst_range(cur_usage, id);
2037 if (!range || range->replacement == -1) {
2038 if (!alu->is_op3)
2039 alu->dst.write = 0;
2040 else
2041 /*TODO: really check that register 123 is useable */
2042 alu->dst.sel = 123;
2043 } else {
2044 alu->dst.sel = range->replacement;
2045 *barrier |= is_barrier_needed(cur_usage, id, alu->dst.chan, last_barrier);
2046 }
2047 }
2048 if (alu->dst.write) {
2049 if (alu->dst.rel)
2050 notice_gpr_rel_last_write(usage, id, alu->dst.chan);
2051 else
2052 notice_gpr_last_write(cur_usage, id, alu->dst.chan);
2053 }
2054 }
2055
2056 static void replace_tex_gprs(struct r600_bc_tex *tex, struct gpr_usage usage[128],
2057 int id, int last_barrier, unsigned *barrier)
2058 {
2059 struct gpr_usage *cur_usage = &usage[tex->src_gpr];
2060 struct gpr_usage_range *range = find_src_range(cur_usage, id);
2061
2062 if (tex->src_rel) {
2063 *barrier = 1;
2064 } else {
2065 if (tex->src_sel_x < 4)
2066 *barrier |= is_barrier_needed(cur_usage, id, tex->src_sel_x, last_barrier);
2067 if (tex->src_sel_y < 4)
2068 *barrier |= is_barrier_needed(cur_usage, id, tex->src_sel_y, last_barrier);
2069 if (tex->src_sel_z < 4)
2070 *barrier |= is_barrier_needed(cur_usage, id, tex->src_sel_z, last_barrier);
2071 if (tex->src_sel_w < 4)
2072 *barrier |= is_barrier_needed(cur_usage, id, tex->src_sel_w, last_barrier);
2073 }
2074 tex->src_gpr = range->replacement;
2075
2076 cur_usage = &usage[tex->dst_gpr];
2077
2078 range = find_dst_range(cur_usage, id);
2079 if (range) {
2080 tex->dst_gpr = range->replacement;
2081
2082 if (tex->dst_rel) {
2083 if (tex->dst_sel_x != 7)
2084 notice_gpr_rel_last_write(usage, id, tex->dst_sel_x);
2085 if (tex->dst_sel_y != 7)
2086 notice_gpr_rel_last_write(usage, id, tex->dst_sel_y);
2087 if (tex->dst_sel_z != 7)
2088 notice_gpr_rel_last_write(usage, id, tex->dst_sel_z);
2089 if (tex->dst_sel_w != 7)
2090 notice_gpr_rel_last_write(usage, id, tex->dst_sel_w);
2091 } else {
2092 if (tex->dst_sel_x != 7)
2093 notice_gpr_last_write(cur_usage, id, tex->dst_sel_x);
2094 if (tex->dst_sel_y != 7)
2095 notice_gpr_last_write(cur_usage, id, tex->dst_sel_y);
2096 if (tex->dst_sel_z != 7)
2097 notice_gpr_last_write(cur_usage, id, tex->dst_sel_z);
2098 if (tex->dst_sel_w != 7)
2099 notice_gpr_last_write(cur_usage, id, tex->dst_sel_w);
2100 }
2101 } else {
2102 tex->dst_gpr = 123;
2103 }
2104 }
2105
2106 static void replace_vtx_gprs(struct r600_bc_vtx *vtx, struct gpr_usage usage[128],
2107 int id, int last_barrier, unsigned *barrier)
2108 {
2109 struct gpr_usage *cur_usage = &usage[vtx->src_gpr];
2110 struct gpr_usage_range *range = find_src_range(cur_usage, id);
2111
2112 *barrier |= is_barrier_needed(cur_usage, id, vtx->src_sel_x, last_barrier);
2113
2114 vtx->src_gpr = range->replacement;
2115
2116 cur_usage = &usage[vtx->dst_gpr];
2117 range = find_dst_range(cur_usage, id);
2118 if (range) {
2119 vtx->dst_gpr = range->replacement;
2120
2121 if (vtx->dst_sel_x != 7)
2122 notice_gpr_last_write(cur_usage, id, vtx->dst_sel_x);
2123 if (vtx->dst_sel_y != 7)
2124 notice_gpr_last_write(cur_usage, id, vtx->dst_sel_y);
2125 if (vtx->dst_sel_z != 7)
2126 notice_gpr_last_write(cur_usage, id, vtx->dst_sel_z);
2127 if (vtx->dst_sel_w != 7)
2128 notice_gpr_last_write(cur_usage, id, vtx->dst_sel_w);
2129 } else {
2130 vtx->dst_gpr = 123;
2131 }
2132 }
2133
2134 static void replace_export_gprs(struct r600_bc_cf *cf, struct gpr_usage usage[128],
2135 int id, int last_barrier)
2136 {
2137 //TODO handle other memory operations
2138 struct gpr_usage *cur_usage = &usage[cf->output.gpr];
2139 struct gpr_usage_range *range = find_src_range(cur_usage, id);
2140
2141 cf->barrier = 0;
2142 if (cf->output.swizzle_x < 4)
2143 cf->barrier |= is_barrier_needed(cur_usage, -1, cf->output.swizzle_x, last_barrier);
2144 if (cf->output.swizzle_y < 4)
2145 cf->barrier |= is_barrier_needed(cur_usage, -1, cf->output.swizzle_y, last_barrier);
2146 if (cf->output.swizzle_z < 4)
2147 cf->barrier |= is_barrier_needed(cur_usage, -1, cf->output.swizzle_z, last_barrier);
2148 if (cf->output.swizzle_w < 4)
2149 cf->barrier |= is_barrier_needed(cur_usage, -1, cf->output.swizzle_w, last_barrier);
2150
2151 cf->output.gpr = range->replacement;
2152 }
2153
2154 static void optimize_alu_inst(struct r600_bc *bc, struct r600_bc_cf *cf, struct r600_bc_alu *alu)
2155 {
2156 struct r600_bc_alu *alu_next;
2157 unsigned chan;
2158 unsigned src, num_src;
2159
2160 /* check if a MOV could be optimized away */
2161 if (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV) {
2162
2163 /* destination equals source? */
2164 if (alu->dst.sel != alu->src[0].sel ||
2165 alu->dst.chan != alu->src[0].chan)
2166 return;
2167
2168 /* any special handling for the source? */
2169 if (alu->src[0].rel || alu->src[0].neg || alu->src[0].abs)
2170 return;
2171
2172 /* any special handling for destination? */
2173 if (alu->dst.rel || alu->dst.clamp)
2174 return;
2175
2176 /* ok find next instruction group and check if ps/pv is used */
2177 for (alu_next = alu; !alu_next->last; alu_next = NEXT_ALU(alu_next));
2178
2179 if (alu_next->list.next != &cf->alu) {
2180 chan = is_alu_reduction_inst(bc, alu) ? 0 : alu->dst.chan;
2181 for (alu_next = NEXT_ALU(alu_next); alu_next; alu_next = NEXT_ALU(alu_next)) {
2182 num_src = r600_bc_get_num_operands(bc, alu_next);
2183 for (src = 0; src < num_src; ++src) {
2184 if (alu_next->src[src].sel == V_SQ_ALU_SRC_PV &&
2185 alu_next->src[src].chan == chan)
2186 return;
2187
2188 if (alu_next->src[src].sel == V_SQ_ALU_SRC_PS)
2189 return;
2190 }
2191
2192 if (alu_next->last)
2193 break;
2194 }
2195 }
2196
2197 r600_bc_remove_alu(cf, alu);
2198 }
2199 }
2200
2201 static void optimize_export_inst(struct r600_bc *bc, struct r600_bc_cf *cf)
2202 {
2203 struct r600_bc_cf *prev = LIST_ENTRY(struct r600_bc_cf, cf->list.prev, list);
2204 if (&prev->list == &bc->cf ||
2205 prev->inst != cf->inst ||
2206 prev->output.type != cf->output.type ||
2207 prev->output.elem_size != cf->output.elem_size ||
2208 prev->output.swizzle_x != cf->output.swizzle_x ||
2209 prev->output.swizzle_y != cf->output.swizzle_y ||
2210 prev->output.swizzle_z != cf->output.swizzle_z ||
2211 prev->output.swizzle_w != cf->output.swizzle_w)
2212 return;
2213
2214 if ((prev->output.burst_count + cf->output.burst_count) > 16)
2215 return;
2216
2217 if ((prev->output.gpr + prev->output.burst_count) == cf->output.gpr &&
2218 (prev->output.array_base + prev->output.burst_count) == cf->output.array_base) {
2219
2220 prev->output.burst_count += cf->output.burst_count;
2221 r600_bc_remove_cf(bc, cf);
2222
2223 } else if (prev->output.gpr == (cf->output.gpr + cf->output.burst_count) &&
2224 prev->output.array_base == (cf->output.array_base + cf->output.burst_count)) {
2225
2226 cf->output.burst_count += prev->output.burst_count;
2227 r600_bc_remove_cf(bc, prev);
2228 }
2229 }
2230
2231 static void r600_bc_optimize(struct r600_bc *bc)
2232 {
2233 struct r600_bc_cf *cf, *next_cf;
2234 struct r600_bc_alu *first, *next_alu;
2235 struct r600_bc_alu *alu;
2236 struct r600_bc_vtx *vtx;
2237 struct r600_bc_tex *tex;
2238 struct gpr_usage usage[128];
2239
2240 /* assume that each gpr is exported only once */
2241 struct r600_bc_cf *export_cf[128] = { NULL };
2242 int export_remap[128];
2243
2244 int id, cond_start, barrier[bc->nstack];
2245 unsigned i, j, stack, predicate, old_stack;
2246
2247 memset(&usage, 0, sizeof(usage));
2248 for (i = 0; i < 128; ++i) {
2249 usage[i].first_write = -1;
2250 usage[i].last_write[0] = -1;
2251 usage[i].last_write[1] = -1;
2252 usage[i].last_write[2] = -1;
2253 usage[i].last_write[3] = -1;
2254 }
2255
2256 /* first gather some informations about the gpr usage */
2257 id = 0; stack = 0;
2258 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2259 old_stack = stack;
2260 if (stack == 0)
2261 cond_start = stack;
2262
2263 switch (r600_bc_cf_class(cf)) {
2264 case CF_CLASS_ALU:
2265 predicate = 0;
2266 first = NULL;
2267 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2268 if (!first)
2269 first = alu;
2270 notice_alu_src_gprs(bc, alu, usage, id);
2271 if (alu->last) {
2272 notice_alu_dst_gprs(first, usage, id, predicate || stack > 0);
2273 first = NULL;
2274 ++id;
2275 }
2276 if (is_alu_pred_inst(bc, alu))
2277 predicate++;
2278 }
2279 if (cf->inst == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3)
2280 stack += predicate;
2281 else if (cf->inst == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3)
2282 stack -= 1;
2283 else if (cf->inst == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3)
2284 stack -= 2;
2285 break;
2286 case CF_CLASS_TEXTURE:
2287 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2288 notice_tex_gprs(bc, tex, usage, id++, stack > 0);
2289 }
2290 break;
2291 case CF_CLASS_VERTEX:
2292 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2293 notice_vtx_gprs(vtx, usage, id++, stack > 0);
2294 }
2295 break;
2296 case CF_CLASS_EXPORT:
2297 notice_export_gprs(cf, usage, export_cf, export_remap);
2298 continue; // don't increment id
2299 case CF_CLASS_OTHER:
2300 switch (cf->inst) {
2301 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2302 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2303 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2304 break;
2305
2306 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2307 stack -= cf->pop_count;
2308 break;
2309
2310 default:
2311 // TODO implement loop handling
2312 goto out;
2313 }
2314 }
2315
2316 /* extend last_write after conditional block */
2317 if (stack == 0 && old_stack != 0)
2318 for (i = 0; i < 128; ++i)
2319 for (j = 0; j < 4; ++j)
2320 if (usage[i].last_write[j] >= cond_start)
2321 usage[i].last_write[j] = id;
2322
2323 id += 0x100;
2324 id &= ~0xFF;
2325 }
2326 assert(stack == 0);
2327
2328 /* try to optimize gpr usage */
2329 for (i = 0; i < 124; ++i) {
2330 for (j = 0; j < usage[i].nranges; ++j) {
2331 struct gpr_usage_range *range = &usage[i].ranges[j];
2332 if (range->start == -1)
2333 /* can't rearange shader inputs */
2334 range->replacement = i;
2335 else if (range->end == -1)
2336 /* gpr isn't used any more after this instruction */
2337 range->replacement = -1;
2338 else
2339 find_replacement(usage, i, range);
2340
2341 if (range->replacement == i)
2342 bc->ngpr = i;
2343 else if (range->replacement < i && range->replacement > bc->ngpr)
2344 bc->ngpr = range->replacement;
2345 }
2346 }
2347 bc->ngpr++;
2348
2349 /* apply the changes */
2350 for (i = 0; i < 128; ++i) {
2351 usage[i].last_write[0] = -1;
2352 usage[i].last_write[1] = -1;
2353 usage[i].last_write[2] = -1;
2354 usage[i].last_write[3] = -1;
2355 }
2356 barrier[0] = 0;
2357 id = 0; stack = 0;
2358 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2359 old_stack = stack;
2360 switch (r600_bc_cf_class(cf)) {
2361 case CF_CLASS_ALU:
2362 predicate = 0;
2363 first = NULL;
2364 cf->barrier = 0;
2365 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2366 replace_alu_gprs(bc, alu, usage, id, barrier[stack], &cf->barrier);
2367 if (alu->last)
2368 ++id;
2369
2370 if (is_alu_pred_inst(bc, alu))
2371 predicate++;
2372
2373 if (cf->inst == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)
2374 optimize_alu_inst(bc, cf, alu);
2375 }
2376 if (cf->inst == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3)
2377 stack += predicate;
2378 else if (cf->inst == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3)
2379 stack -= 1;
2380 else if (cf->inst == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3)
2381 stack -= 2;
2382 if (LIST_IS_EMPTY(&cf->alu)) {
2383 r600_bc_remove_cf(bc, cf);
2384 cf = NULL;
2385 }
2386 break;
2387 case CF_CLASS_TEXTURE:
2388 cf->barrier = 0;
2389 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2390 replace_tex_gprs(tex, usage, id++, barrier[stack], &cf->barrier);
2391 }
2392 break;
2393 case CF_CLASS_VERTEX:
2394 cf->barrier = 0;
2395 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2396 replace_vtx_gprs(vtx, usage, id++, barrier[stack], &cf->barrier);
2397 }
2398 break;
2399 case CF_CLASS_EXPORT:
2400 continue; // don't increment id
2401 case CF_CLASS_OTHER:
2402 if (cf->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
2403 cf->barrier = 0;
2404 stack -= cf->pop_count;
2405 }
2406 break;
2407 }
2408
2409 id &= ~0xFF;
2410 if (cf && cf->barrier)
2411 barrier[old_stack] = id;
2412
2413 for (i = old_stack + 1; i <= stack; ++i)
2414 barrier[i] = barrier[old_stack];
2415
2416 id += 0x100;
2417 if (stack != 0) /* ensure exports are placed outside of conditional blocks */
2418 continue;
2419
2420 for (i = 0; i < 128; ++i) {
2421 if (!export_cf[i] || id < export_remap[i])
2422 continue;
2423
2424 r600_bc_move_cf(bc, export_cf[i], next_cf);
2425 replace_export_gprs(export_cf[i], usage, export_remap[i], barrier[stack]);
2426 if (export_cf[i]->barrier)
2427 barrier[stack] = id - 1;
2428 next_cf = LIST_ENTRY(struct r600_bc_cf, export_cf[i]->list.next, list);
2429 optimize_export_inst(bc, export_cf[i]);
2430 export_cf[i] = NULL;
2431 }
2432 }
2433 assert(stack == 0);
2434
2435 out:
2436 for (i = 0; i < 128; ++i) {
2437 free(usage[i].ranges);
2438 }
2439 }
2440
2441 int r600_bc_build(struct r600_bc *bc)
2442 {
2443 struct r600_bc_cf *cf;
2444 struct r600_bc_alu *alu;
2445 struct r600_bc_vtx *vtx;
2446 struct r600_bc_tex *tex;
2447 struct r600_bc_cf *exports[4] = { NULL };
2448 uint32_t literal[4];
2449 unsigned nliteral;
2450 unsigned addr;
2451 int i, r;
2452
2453 if (bc->callstack[0].max > 0)
2454 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
2455 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
2456 bc->nstack = 1;
2457 }
2458
2459 //r600_bc_optimize(bc);
2460
2461 /* first path compute addr of each CF block */
2462 /* addr start after all the CF instructions */
2463 addr = LIST_ENTRY(struct r600_bc_cf, bc->cf.prev, list)->id + 2;
2464 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2465 switch (r600_bc_cf_class(cf)) {
2466 case CF_CLASS_ALU:
2467 break;
2468 case CF_CLASS_TEXTURE:
2469 case CF_CLASS_VERTEX:
2470 /* fetch node need to be 16 bytes aligned*/
2471 addr += 3;
2472 addr &= 0xFFFFFFFCUL;
2473 break;
2474 case CF_CLASS_EXPORT:
2475 if (cf->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT))
2476 exports[cf->output.type] = cf;
2477 break;
2478 case CF_CLASS_OTHER:
2479 break;
2480 default:
2481 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2482 return -EINVAL;
2483 }
2484 cf->addr = addr;
2485 addr += cf->ndw;
2486 bc->ndw = cf->addr + cf->ndw;
2487 }
2488
2489 /* set export done on last export of each type */
2490 for (i = 0; i < 4; ++i) {
2491 if (exports[i]) {
2492 exports[i]->inst = BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
2493 }
2494 }
2495
2496 free(bc->bytecode);
2497 bc->bytecode = calloc(1, bc->ndw * 4);
2498 if (bc->bytecode == NULL)
2499 return -ENOMEM;
2500 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2501 addr = cf->addr;
2502 if (bc->chiprev == CHIPREV_EVERGREEN)
2503 r = eg_bc_cf_build(bc, cf);
2504 else
2505 r = r600_bc_cf_build(bc, cf);
2506 if (r)
2507 return r;
2508 switch (r600_bc_cf_class(cf)) {
2509 case CF_CLASS_ALU:
2510 nliteral = 0;
2511 memset(literal, 0, sizeof(literal));
2512 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2513 r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
2514 if (r)
2515 return r;
2516 r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
2517 switch(bc->chiprev) {
2518 case CHIPREV_R600:
2519 r = r600_bc_alu_build(bc, alu, addr);
2520 break;
2521 case CHIPREV_R700:
2522 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
2523 r = r700_bc_alu_build(bc, alu, addr);
2524 break;
2525 default:
2526 R600_ERR("unknown family %d\n", bc->family);
2527 return -EINVAL;
2528 }
2529 if (r)
2530 return r;
2531 addr += 2;
2532 if (alu->last) {
2533 for (i = 0; i < align(nliteral, 2); ++i) {
2534 bc->bytecode[addr++] = literal[i];
2535 }
2536 nliteral = 0;
2537 memset(literal, 0, sizeof(literal));
2538 }
2539 }
2540 break;
2541 case CF_CLASS_VERTEX:
2542 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2543 r = r600_bc_vtx_build(bc, vtx, addr);
2544 if (r)
2545 return r;
2546 addr += 4;
2547 }
2548 break;
2549 case CF_CLASS_TEXTURE:
2550 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2551 r = r600_bc_tex_build(bc, tex, addr);
2552 if (r)
2553 return r;
2554 addr += 4;
2555 }
2556 break;
2557 case CF_CLASS_EXPORT:
2558 case CF_CLASS_OTHER:
2559 break;
2560 default:
2561 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2562 return -EINVAL;
2563 }
2564 }
2565 return 0;
2566 }
2567
2568 void r600_bc_clear(struct r600_bc *bc)
2569 {
2570 struct r600_bc_cf *cf = NULL, *next_cf;
2571
2572 free(bc->bytecode);
2573 bc->bytecode = NULL;
2574
2575 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2576 struct r600_bc_alu *alu = NULL, *next_alu;
2577 struct r600_bc_tex *tex = NULL, *next_tex;
2578 struct r600_bc_tex *vtx = NULL, *next_vtx;
2579
2580 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2581 free(alu);
2582 }
2583
2584 LIST_INITHEAD(&cf->alu);
2585
2586 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2587 free(tex);
2588 }
2589
2590 LIST_INITHEAD(&cf->tex);
2591
2592 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2593 free(vtx);
2594 }
2595
2596 LIST_INITHEAD(&cf->vtx);
2597
2598 free(cf);
2599 }
2600
2601 LIST_INITHEAD(&cf->list);
2602 }
2603
2604 void r600_bc_dump(struct r600_bc *bc)
2605 {
2606 struct r600_bc_cf *cf = NULL;
2607 struct r600_bc_alu *alu = NULL;
2608 struct r600_bc_vtx *vtx = NULL;
2609 struct r600_bc_tex *tex = NULL;
2610
2611 unsigned i, id;
2612 uint32_t literal[4];
2613 unsigned nliteral;
2614 char chip = '6';
2615
2616 switch (bc->chiprev) {
2617 case 1:
2618 chip = '7';
2619 break;
2620 case 2:
2621 chip = 'E';
2622 break;
2623 case 0:
2624 default:
2625 chip = '6';
2626 break;
2627 }
2628 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2629 fprintf(stderr, " %c\n", chip);
2630
2631 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2632 id = cf->id;
2633
2634 switch (r600_bc_cf_class(cf)) {
2635 case CF_CLASS_ALU:
2636 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2637 fprintf(stderr, "ADDR:%04d ", cf->addr);
2638 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2639 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2640 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2641 id++;
2642 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2643 fprintf(stderr, "INST:%d ", cf->inst);
2644 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2645 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2646 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2647 fprintf(stderr, "BARRIER:%d ", cf->barrier);
2648 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2649 break;
2650 case CF_CLASS_TEXTURE:
2651 case CF_CLASS_VERTEX:
2652 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2653 fprintf(stderr, "ADDR:%04d\n", cf->addr);
2654 id++;
2655 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2656 fprintf(stderr, "INST:%d ", cf->inst);
2657 fprintf(stderr, "BARRIER:%d ", cf->barrier);
2658 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2659 break;
2660 case CF_CLASS_EXPORT:
2661 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2662 fprintf(stderr, "GPR:%d ", cf->output.gpr);
2663 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2664 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2665 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2666 id++;
2667 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2668 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2669 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2670 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2671 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2672 fprintf(stderr, "BARRIER:%d ", cf->barrier);
2673 fprintf(stderr, "INST:%d ", cf->inst);
2674 fprintf(stderr, "BURST_COUNT:%d\n", cf->output.burst_count);
2675 break;
2676 case CF_CLASS_OTHER:
2677 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2678 fprintf(stderr, "ADDR:%04d\n", cf->cf_addr);
2679 id++;
2680 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2681 fprintf(stderr, "INST:%d ", cf->inst);
2682 fprintf(stderr, "COND:%X ", cf->cond);
2683 fprintf(stderr, "BARRIER:%d ", cf->barrier);
2684 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2685 break;
2686 }
2687
2688 id = cf->addr;
2689 nliteral = 0;
2690 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2691 r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
2692
2693 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2694 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2695 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2696 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2697 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2698 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2699 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2700 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2701 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
2702 fprintf(stderr, "LAST:%d)\n", alu->last);
2703 id++;
2704 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2705 fprintf(stderr, "INST:%d ", alu->inst);
2706 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2707 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2708 fprintf(stderr, "REL:%d ", alu->dst.rel);
2709 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2710 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2711 if (alu->is_op3) {
2712 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2713 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2714 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2715 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2716 } else {
2717 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2718 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2719 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2720 fprintf(stderr, "OMOD:%d ", alu->omod);
2721 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
2722 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
2723 }
2724
2725 id++;
2726 if (alu->last) {
2727 for (i = 0; i < nliteral; i++, id++) {
2728 float *f = (float*)(bc->bytecode + id);
2729 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
2730 }
2731 id += nliteral & 1;
2732 nliteral = 0;
2733 }
2734 }
2735
2736 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2737 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2738 fprintf(stderr, "INST:%d ", tex->inst);
2739 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2740 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2741 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2742 id++;
2743 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2744 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2745 fprintf(stderr, "REL:%d ", tex->dst_rel);
2746 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2747 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2748 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2749 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2750 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2751 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2752 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2753 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2754 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2755 id++;
2756 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2757 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2758 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2759 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2760 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2761 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2762 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2763 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2764 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2765 id++;
2766 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2767 id++;
2768 }
2769
2770 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2771 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2772 fprintf(stderr, "INST:%d ", vtx->inst);
2773 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2774 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2775 id++;
2776 /* This assumes that no semantic fetches exist */
2777 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2778 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2779 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2780 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2781 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2782 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2783 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2784 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2785 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2786 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2787 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2788 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2789 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2790 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2791 id++;
2792 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2793 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2794 //TODO
2795 id++;
2796 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2797 id++;
2798 }
2799 }
2800
2801 fprintf(stderr, "--------------------------------------\n");
2802 }
2803
2804 static void r600_cf_vtx(struct r600_vertex_element *ve)
2805 {
2806 struct r600_pipe_state *rstate;
2807
2808 rstate = &ve->rstate;
2809 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2810 rstate->nregs = 0;
2811 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2812 0x00000000, 0xFFFFFFFF, NULL);
2813 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2814 0x00000000, 0xFFFFFFFF, NULL);
2815 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2816 r600_bo_offset(ve->fetch_shader) >> 8,
2817 0xFFFFFFFF, ve->fetch_shader);
2818 }
2819
2820 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
2821 unsigned *num_format, unsigned *format_comp)
2822 {
2823 const struct util_format_description *desc;
2824 unsigned i;
2825
2826 *format = 0;
2827 *num_format = 0;
2828 *format_comp = 0;
2829
2830 desc = util_format_description(pformat);
2831 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2832 goto out_unknown;
2833 }
2834
2835 /* Find the first non-VOID channel. */
2836 for (i = 0; i < 4; i++) {
2837 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2838 break;
2839 }
2840 }
2841
2842 switch (desc->channel[i].type) {
2843 /* Half-floats, floats, ints */
2844 case UTIL_FORMAT_TYPE_FLOAT:
2845 switch (desc->channel[i].size) {
2846 case 16:
2847 switch (desc->nr_channels) {
2848 case 1:
2849 *format = FMT_16_FLOAT;
2850 break;
2851 case 2:
2852 *format = FMT_16_16_FLOAT;
2853 break;
2854 case 3:
2855 case 4:
2856 *format = FMT_16_16_16_16_FLOAT;
2857 break;
2858 }
2859 break;
2860 case 32:
2861 switch (desc->nr_channels) {
2862 case 1:
2863 *format = FMT_32_FLOAT;
2864 break;
2865 case 2:
2866 *format = FMT_32_32_FLOAT;
2867 break;
2868 case 3:
2869 *format = FMT_32_32_32_FLOAT;
2870 break;
2871 case 4:
2872 *format = FMT_32_32_32_32_FLOAT;
2873 break;
2874 }
2875 break;
2876 default:
2877 goto out_unknown;
2878 }
2879 break;
2880 /* Unsigned ints */
2881 case UTIL_FORMAT_TYPE_UNSIGNED:
2882 /* Signed ints */
2883 case UTIL_FORMAT_TYPE_SIGNED:
2884 switch (desc->channel[i].size) {
2885 case 8:
2886 switch (desc->nr_channels) {
2887 case 1:
2888 *format = FMT_8;
2889 break;
2890 case 2:
2891 *format = FMT_8_8;
2892 break;
2893 case 3:
2894 case 4:
2895 *format = FMT_8_8_8_8;
2896 break;
2897 }
2898 break;
2899 case 16:
2900 switch (desc->nr_channels) {
2901 case 1:
2902 *format = FMT_16;
2903 break;
2904 case 2:
2905 *format = FMT_16_16;
2906 break;
2907 case 3:
2908 case 4:
2909 *format = FMT_16_16_16_16;
2910 break;
2911 }
2912 break;
2913 case 32:
2914 switch (desc->nr_channels) {
2915 case 1:
2916 *format = FMT_32;
2917 break;
2918 case 2:
2919 *format = FMT_32_32;
2920 break;
2921 case 3:
2922 *format = FMT_32_32_32;
2923 break;
2924 case 4:
2925 *format = FMT_32_32_32_32;
2926 break;
2927 }
2928 break;
2929 default:
2930 goto out_unknown;
2931 }
2932 break;
2933 default:
2934 goto out_unknown;
2935 }
2936
2937 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2938 *format_comp = 1;
2939 }
2940 if (desc->channel[i].normalized) {
2941 *num_format = 0;
2942 } else {
2943 *num_format = 2;
2944 }
2945 return;
2946 out_unknown:
2947 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2948 }
2949
2950 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2951 {
2952 static int dump_shaders = -1;
2953
2954 struct r600_bc bc;
2955 struct r600_bc_vtx vtx;
2956 struct pipe_vertex_element *elements = ve->elements;
2957 const struct util_format_description *desc;
2958 unsigned fetch_resource_start = rctx->family >= CHIP_CEDAR ? 0 : 160;
2959 unsigned format, num_format, format_comp;
2960 u32 *bytecode;
2961 int i, r;
2962
2963 /* vertex elements offset need special handling, if offset is bigger
2964 + * than what we can put in fetch instruction then we need to alterate
2965 * the vertex resource offset. In such case in order to simplify code
2966 * we will bound one resource per elements. It's a worst case scenario.
2967 */
2968 for (i = 0; i < ve->count; i++) {
2969 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2970 if (ve->vbuffer_offset[i]) {
2971 ve->vbuffer_need_offset = 1;
2972 }
2973 }
2974
2975 memset(&bc, 0, sizeof(bc));
2976 r = r600_bc_init(&bc, r600_get_family(rctx->radeon));
2977 if (r)
2978 return r;
2979
2980 for (i = 0; i < ve->count; i++) {
2981 if (elements[i].instance_divisor > 1) {
2982 struct r600_bc_alu alu;
2983
2984 memset(&alu, 0, sizeof(alu));
2985 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2986 alu.src[0].sel = 0;
2987 alu.src[0].chan = 3;
2988
2989 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2990 alu.src[1].value = (1l << 32) / elements[i].instance_divisor + 1;
2991
2992 alu.dst.sel = i + 1;
2993 alu.dst.chan = 3;
2994 alu.dst.write = 1;
2995 alu.last = 1;
2996
2997 if ((r = r600_bc_add_alu(&bc, &alu))) {
2998 r600_bc_clear(&bc);
2999 return r;
3000 }
3001 }
3002 }
3003
3004 for (i = 0; i < ve->count; i++) {
3005 unsigned vbuffer_index;
3006 r600_vertex_data_type(ve->elements[i].src_format, &format, &num_format, &format_comp);
3007 desc = util_format_description(ve->elements[i].src_format);
3008 if (desc == NULL) {
3009 r600_bc_clear(&bc);
3010 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
3011 return -EINVAL;
3012 }
3013
3014 /* see above for vbuffer_need_offset explanation */
3015 vbuffer_index = elements[i].vertex_buffer_index;
3016 memset(&vtx, 0, sizeof(vtx));
3017 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
3018 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
3019 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
3020 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
3021 vtx.mega_fetch_count = 0x1F;
3022 vtx.dst_gpr = i + 1;
3023 vtx.dst_sel_x = desc->swizzle[0];
3024 vtx.dst_sel_y = desc->swizzle[1];
3025 vtx.dst_sel_z = desc->swizzle[2];
3026 vtx.dst_sel_w = desc->swizzle[3];
3027 vtx.data_format = format;
3028 vtx.num_format_all = num_format;
3029 vtx.format_comp_all = format_comp;
3030 vtx.srf_mode_all = 1;
3031 vtx.offset = elements[i].src_offset;
3032
3033 if ((r = r600_bc_add_vtx(&bc, &vtx))) {
3034 r600_bc_clear(&bc);
3035 return r;
3036 }
3037 }
3038
3039 r600_bc_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
3040 r600_bc_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_NOP));
3041
3042 if ((r = r600_bc_build(&bc))) {
3043 r600_bc_clear(&bc);
3044 return r;
3045 }
3046
3047 if (dump_shaders == -1)
3048 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
3049
3050 if (dump_shaders) {
3051 fprintf(stderr, "--------------------------------------------------------------\n");
3052 r600_bc_dump(&bc);
3053 fprintf(stderr, "______________________________________________________________\n");
3054 }
3055
3056 ve->fs_size = bc.ndw*4;
3057
3058 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
3059 ve->fetch_shader = r600_bo(rctx->radeon, ve->fs_size, 256, PIPE_BIND_VERTEX_BUFFER, 0);
3060 if (ve->fetch_shader == NULL) {
3061 r600_bc_clear(&bc);
3062 return -ENOMEM;
3063 }
3064
3065 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
3066 if (bytecode == NULL) {
3067 r600_bc_clear(&bc);
3068 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
3069 return -ENOMEM;
3070 }
3071
3072 memcpy(bytecode, bc.bytecode, ve->fs_size);
3073
3074 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
3075 r600_bc_clear(&bc);
3076
3077 if (rctx->family >= CHIP_CEDAR)
3078 eg_cf_vtx(ve);
3079 else
3080 r600_cf_vtx(ve);
3081
3082 return 0;
3083 }