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r600g: merge alu groups
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
39 {
40 if(alu->is_op3)
41 return 3;
42
43 switch (alu->inst) {
44 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
45 return 0;
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
65 return 2;
66
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
80 return 1;
81 default: R600_ERR(
82 "Need instruction operand number for 0x%x.\n", alu->inst);
83 };
84
85 return 3;
86 }
87
88 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
89
90 static struct r600_bc_cf *r600_bc_cf(void)
91 {
92 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
93
94 if (cf == NULL)
95 return NULL;
96 LIST_INITHEAD(&cf->list);
97 LIST_INITHEAD(&cf->alu);
98 LIST_INITHEAD(&cf->vtx);
99 LIST_INITHEAD(&cf->tex);
100 return cf;
101 }
102
103 static struct r600_bc_alu *r600_bc_alu(void)
104 {
105 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
106
107 if (alu == NULL)
108 return NULL;
109 LIST_INITHEAD(&alu->list);
110 return alu;
111 }
112
113 static struct r600_bc_vtx *r600_bc_vtx(void)
114 {
115 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
116
117 if (vtx == NULL)
118 return NULL;
119 LIST_INITHEAD(&vtx->list);
120 return vtx;
121 }
122
123 static struct r600_bc_tex *r600_bc_tex(void)
124 {
125 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
126
127 if (tex == NULL)
128 return NULL;
129 LIST_INITHEAD(&tex->list);
130 return tex;
131 }
132
133 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
134 {
135 LIST_INITHEAD(&bc->cf);
136 bc->family = family;
137 switch (bc->family) {
138 case CHIP_R600:
139 case CHIP_RV610:
140 case CHIP_RV630:
141 case CHIP_RV670:
142 case CHIP_RV620:
143 case CHIP_RV635:
144 case CHIP_RS780:
145 case CHIP_RS880:
146 bc->chiprev = CHIPREV_R600;
147 break;
148 case CHIP_RV770:
149 case CHIP_RV730:
150 case CHIP_RV710:
151 case CHIP_RV740:
152 bc->chiprev = CHIPREV_R700;
153 break;
154 case CHIP_CEDAR:
155 case CHIP_REDWOOD:
156 case CHIP_JUNIPER:
157 case CHIP_CYPRESS:
158 case CHIP_HEMLOCK:
159 case CHIP_PALM:
160 bc->chiprev = CHIPREV_EVERGREEN;
161 break;
162 default:
163 R600_ERR("unknown family %d\n", bc->family);
164 return -EINVAL;
165 }
166 return 0;
167 }
168
169 static int r600_bc_add_cf(struct r600_bc *bc)
170 {
171 struct r600_bc_cf *cf = r600_bc_cf();
172
173 if (cf == NULL)
174 return -ENOMEM;
175 LIST_ADDTAIL(&cf->list, &bc->cf);
176 if (bc->cf_last)
177 cf->id = bc->cf_last->id + 2;
178 bc->cf_last = cf;
179 bc->ncf++;
180 bc->ndw += 2;
181 bc->force_add_cf = 0;
182 return 0;
183 }
184
185 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
186 {
187 int r;
188
189 r = r600_bc_add_cf(bc);
190 if (r)
191 return r;
192 bc->cf_last->inst = output->inst;
193 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
194 return 0;
195 }
196
197 /* alu instructions that can ony exits once per group */
198 static int is_alu_once_inst(struct r600_bc_alu *alu)
199 {
200 return !alu->is_op3 && (
201 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
202 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
203 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
204 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
205 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
206 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
207 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
208 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
209 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
210 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
211 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
212 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
213 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
214 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
215 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
216 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
217 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
218 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
219 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
220 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
221 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
222 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
223 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
224 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
225 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
226 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
227 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
228 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
229 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
230 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
231 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
232 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
233 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
234 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
235 }
236
237 static int is_alu_reduction_inst(struct r600_bc_alu *alu)
238 {
239 return !alu->is_op3 && (
240 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
241 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
242 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
243 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
244 }
245
246 static int is_alu_mova_inst(struct r600_bc_alu *alu)
247 {
248 return !alu->is_op3 && (
249 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
250 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
251 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
252 }
253
254 /* alu instructions that can only execute on the vector unit */
255 static int is_alu_vec_unit_inst(struct r600_bc_alu *alu)
256 {
257 return is_alu_reduction_inst(alu) ||
258 is_alu_mova_inst(alu);
259 }
260
261 /* alu instructions that can only execute on the trans unit */
262 static int is_alu_trans_unit_inst(struct r600_bc_alu *alu)
263 {
264 if(!alu->is_op3)
265 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
266 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
267 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
268 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
269 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
270 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
271 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
272 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
273 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
274 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
275 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
276 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
277 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
278 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
279 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
280 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
281 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
282 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
283 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
284 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
285 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
286 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
287 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
288 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
289 else
290 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
291 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
292 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
293 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
294 }
295
296 /* alu instructions that can execute on any unit */
297 static int is_alu_any_unit_inst(struct r600_bc_alu *alu)
298 {
299 return !is_alu_vec_unit_inst(alu) &&
300 !is_alu_trans_unit_inst(alu);
301 }
302
303 static int assign_alu_units(struct r600_bc_alu *alu_first, struct r600_bc_alu *assignment[5])
304 {
305 struct r600_bc_alu *alu;
306 unsigned i, chan, trans;
307
308 for (i = 0; i < 5; i++)
309 assignment[i] = NULL;
310
311 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
312 chan = alu->dst.chan;
313 if (is_alu_trans_unit_inst(alu))
314 trans = 1;
315 else if (is_alu_vec_unit_inst(alu))
316 trans = 0;
317 else if (assignment[chan])
318 trans = 1; // assume ALU_INST_PREFER_VECTOR
319 else
320 trans = 0;
321
322 if (trans) {
323 if (assignment[4]) {
324 assert(0); //ALU.Trans has already been allocated
325 return -1;
326 }
327 assignment[4] = alu;
328 } else {
329 if (assignment[chan]) {
330 assert(0); //ALU.chan has already been allocated
331 return -1;
332 }
333 assignment[chan] = alu;
334 }
335
336 if (alu->last)
337 break;
338 }
339 return 0;
340 }
341
342 struct alu_bank_swizzle {
343 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
344 int hw_cfile_addr[4];
345 int hw_cfile_elem[4];
346 };
347
348 const unsigned cycle_for_bank_swizzle_vec[][3] = {
349 [SQ_ALU_VEC_012] = { 0, 1, 2 },
350 [SQ_ALU_VEC_021] = { 0, 2, 1 },
351 [SQ_ALU_VEC_120] = { 1, 2, 0 },
352 [SQ_ALU_VEC_102] = { 1, 0, 2 },
353 [SQ_ALU_VEC_201] = { 2, 0, 1 },
354 [SQ_ALU_VEC_210] = { 2, 1, 0 }
355 };
356
357 const unsigned cycle_for_bank_swizzle_scl[][3] = {
358 [SQ_ALU_SCL_210] = { 2, 1, 0 },
359 [SQ_ALU_SCL_122] = { 1, 2, 2 },
360 [SQ_ALU_SCL_212] = { 2, 1, 2 },
361 [SQ_ALU_SCL_221] = { 2, 2, 1 }
362 };
363
364 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
365 {
366 int i, cycle, component;
367 /* set up gpr use */
368 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
369 for (component = 0; component < NUM_OF_COMPONENTS; component++)
370 bs->hw_gpr[cycle][component] = -1;
371 for (i = 0; i < 4; i++)
372 bs->hw_cfile_addr[i] = -1;
373 for (i = 0; i < 4; i++)
374 bs->hw_cfile_elem[i] = -1;
375 }
376
377 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
378 {
379 if (bs->hw_gpr[cycle][chan] == -1)
380 bs->hw_gpr[cycle][chan] = sel;
381 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
382 // Another scalar operation has already used GPR read port for channel
383 return -1;
384 }
385 return 0;
386 }
387
388 static int reserve_cfile(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
389 {
390 int res, resmatch = -1, resempty = -1;
391 for (res = 3; res >= 0; --res) {
392 if (bs->hw_cfile_addr[res] == -1)
393 resempty = res;
394 else if (bs->hw_cfile_addr[res] == sel &&
395 bs->hw_cfile_elem[res] == chan)
396 resmatch = res;
397 }
398 if (resmatch != -1)
399 return 0; // Read for this scalar element already reserved, nothing to do here.
400 else if (resempty != -1) {
401 bs->hw_cfile_addr[resempty] = sel;
402 bs->hw_cfile_elem[resempty] = chan;
403 } else {
404 // All cfile read ports are used, cannot reference vector element
405 return -1;
406 }
407 return 0;
408 }
409
410 static int is_gpr(unsigned sel)
411 {
412 return (sel >= 0 && sel <= 127);
413 }
414
415 static int is_cfile(unsigned sel)
416 {
417 return (sel > 255 && sel < 512);
418 }
419
420 static int is_const(int sel)
421 {
422 return is_cfile(sel) ||
423 (sel >= V_SQ_ALU_SRC_0 &&
424 sel <= V_SQ_ALU_SRC_LITERAL);
425 }
426
427 static int check_vector(struct r600_bc_alu *alu, struct alu_bank_swizzle *bs, int bank_swizzle)
428 {
429 int r, src, num_src, sel, elem, cycle;
430
431 num_src = r600_bc_get_num_operands(alu);
432 for (src = 0; src < num_src; src++) {
433 sel = alu->src[src].sel;
434 elem = alu->src[src].chan;
435 if (is_gpr(sel)) {
436 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
437 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
438 // Nothing to do; special-case optimization,
439 // second source uses first source’s reservation
440 continue;
441 else {
442 r = reserve_gpr(bs, sel, elem, cycle);
443 if (r)
444 return r;
445 }
446 } else if (is_cfile(sel)) {
447 r = reserve_cfile(bs, sel, elem);
448 if (r)
449 return r;
450 }
451 // No restrictions on PV, PS, literal or special constants
452 }
453 return 0;
454 }
455
456 static int check_scalar(struct r600_bc_alu *alu, struct alu_bank_swizzle *bs, int bank_swizzle)
457 {
458 int r, src, num_src, const_count, sel, elem, cycle;
459
460 num_src = r600_bc_get_num_operands(alu);
461 for (const_count = 0, src = 0; src < num_src; ++src) {
462 sel = alu->src[src].sel;
463 elem = alu->src[src].chan;
464 if (is_const(sel)) { // Any constant, including literal and inline constants
465 if (const_count >= 2)
466 // More than two references to a constant in
467 // transcendental operation.
468 return -1;
469 else
470 const_count++;
471 }
472 if (is_cfile(sel)) {
473 r = reserve_cfile(bs, sel, elem);
474 if (r)
475 return r;
476 }
477 }
478 for (src = 0; src < num_src; ++src) {
479 sel = alu->src[src].sel;
480 elem = alu->src[src].chan;
481 if (is_gpr(sel)) {
482 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
483 if (cycle < const_count)
484 // Cycle for GPR load conflicts with
485 // constant load in transcendental operation.
486 return -1;
487 r = reserve_gpr(bs, sel, elem, cycle);
488 if (r)
489 return r;
490 }
491 // Constants already processed
492 // No restrictions on PV, PS
493 }
494 return 0;
495 }
496
497 static int check_and_set_bank_swizzle(struct r600_bc_alu *slots[5])
498 {
499 struct alu_bank_swizzle bs;
500 int bank_swizzle[5];
501 int i, r = 0, forced = 0;
502
503 for (i = 0; i < 5; i++)
504 if (slots[i] && slots[i]->bank_swizzle_force) {
505 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
506 forced = 1;
507 }
508
509 if (forced)
510 return 0;
511
512 // just check every possible combination of bank swizzle
513 // not very efficent, but works on the first try in most of the cases
514 for (i = 0; i < 4; i++)
515 bank_swizzle[i] = SQ_ALU_VEC_012;
516 bank_swizzle[4] = SQ_ALU_SCL_210;
517 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
518 init_bank_swizzle(&bs);
519 for (i = 0; i < 4; i++) {
520 if (slots[i]) {
521 r = check_vector(slots[i], &bs, bank_swizzle[i]);
522 if (r)
523 break;
524 }
525 }
526 if (!r && slots[4]) {
527 r = check_scalar(slots[4], &bs, bank_swizzle[4]);
528 }
529 if (!r) {
530 for (i = 0; i < 5; i++) {
531 if (slots[i])
532 slots[i]->bank_swizzle = bank_swizzle[i];
533 }
534 return 0;
535 }
536
537 for (i = 0; i < 5; i++) {
538 bank_swizzle[i]++;
539 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
540 break;
541 else
542 bank_swizzle[i] = SQ_ALU_VEC_012;
543 }
544 }
545
546 // couldn't find a working swizzle
547 return -1;
548 }
549
550 static int replace_gpr_with_pv_ps(struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
551 {
552 struct r600_bc_alu *prev[5];
553 int gpr[5], chan[5];
554 int i, j, r, src, num_src;
555
556 r = assign_alu_units(alu_prev, prev);
557 if (r)
558 return r;
559
560 for (i = 0; i < 5; ++i) {
561 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
562 gpr[i] = prev[i]->dst.sel;
563 if (is_alu_reduction_inst(prev[i]))
564 chan[i] = 0;
565 else
566 chan[i] = prev[i]->dst.chan;
567 } else
568 gpr[i] = -1;
569 }
570
571 for (i = 0; i < 5; ++i) {
572 struct r600_bc_alu *alu = slots[i];
573 if(!alu)
574 continue;
575
576 num_src = r600_bc_get_num_operands(alu);
577 for (src = 0; src < num_src; ++src) {
578 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
579 continue;
580
581 if (alu->src[src].sel == gpr[4] &&
582 alu->src[src].chan == chan[4]) {
583 alu->src[src].sel = V_SQ_ALU_SRC_PS;
584 alu->src[src].chan = 0;
585 continue;
586 }
587
588 for (j = 0; j < 4; ++j) {
589 if (alu->src[src].sel == gpr[j] &&
590 alu->src[src].chan == j) {
591 alu->src[src].sel = V_SQ_ALU_SRC_PV;
592 alu->src[src].chan = chan[j];
593 break;
594 }
595 }
596 }
597 }
598
599 return 0;
600 }
601
602 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
603 {
604 struct r600_bc_alu *prev[5];
605 struct r600_bc_alu *result[5] = { NULL };
606 int i, j, r, src, num_src;
607 int num_once_inst = 0;
608
609 r = assign_alu_units(alu_prev, prev);
610 if (r)
611 return r;
612
613 for (i = 0; i < 5; ++i) {
614 // TODO: we have literals? forget it!
615 if (prev[i] && prev[i]->nliteral)
616 return 0;
617 if (slots[i] && slots[i]->nliteral)
618 return 0;
619
620
621 // let's check used slots
622 if (prev[i] && !slots[i]) {
623 result[i] = prev[i];
624 num_once_inst += is_alu_once_inst(prev[i]);
625 continue;
626 } else if (prev[i] && slots[i]) {
627 if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
628 // trans unit is still free try to use it
629 if (is_alu_any_unit_inst(slots[i])) {
630 result[i] = prev[i];
631 result[4] = slots[i];
632 } else if (is_alu_any_unit_inst(prev[i])) {
633 result[i] = slots[i];
634 result[4] = prev[i];
635 } else
636 return 0;
637 } else
638 return 0;
639 } else if(!slots[i]) {
640 continue;
641 } else
642 result[i] = slots[i];
643
644 // let's check source gprs
645 struct r600_bc_alu *alu = slots[i];
646 num_once_inst += is_alu_once_inst(alu);
647
648 num_src = r600_bc_get_num_operands(alu);
649 for (src = 0; src < num_src; ++src) {
650 // constants doesn't matter
651 if (!is_gpr(alu->src[src].sel))
652 continue;
653
654 for (j = 0; j < 5; ++j) {
655 if (!prev[j] || !prev[j]->dst.write)
656 continue;
657
658 // if it's relative then we can't determin which gpr is really used
659 if (prev[j]->dst.chan == alu->src[src].chan &&
660 (prev[j]->dst.sel == alu->src[src].sel ||
661 prev[j]->dst.rel || alu->src[src].rel))
662 return 0;
663 }
664 }
665 }
666
667 /* more than one PRED_ or KILL_ ? */
668 if (num_once_inst > 1)
669 return 0;
670
671 /* check if the result can still be swizzlet */
672 r = check_and_set_bank_swizzle(result);
673 if (r)
674 return 0;
675
676 /* looks like everything worked out right, apply the changes */
677
678 /* sort instructions */
679 for (i = 0; i < 5; ++i) {
680 slots[i] = result[i];
681 if (result[i]) {
682 LIST_DEL(&result[i]->list);
683 result[i]->last = 0;
684 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
685 }
686 }
687
688 /* determine new last instruction */
689 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
690
691 /* determine new first instruction */
692 for (i = 0; i < 5; ++i) {
693 if (result[i]) {
694 bc->cf_last->curr_bs_head = result[i];
695 break;
696 }
697 }
698
699 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
700 bc->cf_last->prev2_bs_head = NULL;
701
702 return 0;
703 }
704
705 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
706 {
707 struct r600_bc_alu *nalu = r600_bc_alu();
708 struct r600_bc_alu *lalu;
709 int i, r;
710
711 if (nalu == NULL)
712 return -ENOMEM;
713 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
714 nalu->nliteral = 0;
715
716 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
717 /* check if we could add it anyway */
718 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
719 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
720 LIST_FOR_EACH_ENTRY(alu, &bc->cf_last->alu, list) {
721 if (alu->predicate) {
722 bc->force_add_cf = 1;
723 break;
724 }
725 }
726 } else
727 bc->force_add_cf = 1;
728 }
729
730 /* cf can contains only alu or only vtx or only tex */
731 if (bc->cf_last == NULL || bc->force_add_cf) {
732 r = r600_bc_add_cf(bc);
733 if (r) {
734 free(nalu);
735 return r;
736 }
737 }
738 bc->cf_last->inst = (type << 3);
739 if (!bc->cf_last->curr_bs_head) {
740 bc->cf_last->curr_bs_head = nalu;
741 }
742 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
743 * worst case */
744 if (alu->last && (bc->cf_last->ndw >> 1) >= 120) {
745 bc->force_add_cf = 1;
746 }
747 /* number of gpr == the last gpr used in any alu */
748 for (i = 0; i < 3; i++) {
749 if (alu->src[i].sel >= bc->ngpr && alu->src[i].sel < 128) {
750 bc->ngpr = alu->src[i].sel + 1;
751 }
752 /* compute how many literal are needed
753 * either 2 or 4 literals
754 */
755 if (alu->src[i].sel == 253) {
756 if (((alu->src[i].chan + 2) & 0x6) > nalu->nliteral) {
757 nalu->nliteral = (alu->src[i].chan + 2) & 0x6;
758 }
759 }
760 }
761 if (!LIST_IS_EMPTY(&bc->cf_last->alu)) {
762 lalu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
763 if (!lalu->last && lalu->nliteral > nalu->nliteral) {
764 nalu->nliteral = lalu->nliteral;
765 }
766 }
767 if (alu->dst.sel >= bc->ngpr) {
768 bc->ngpr = alu->dst.sel + 1;
769 }
770 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
771 /* each alu use 2 dwords */
772 bc->cf_last->ndw += 2;
773 bc->ndw += 2;
774
775 bc->cf_last->kcache0_mode = 2;
776
777 /* process cur ALU instructions for bank swizzle */
778 if (alu->last) {
779 struct r600_bc_alu *slots[5];
780 r = assign_alu_units(bc->cf_last->curr_bs_head, slots);
781 if (r)
782 return r;
783
784 if (bc->cf_last->prev_bs_head) {
785 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
786 if (r)
787 return r;
788 }
789
790 if (bc->cf_last->prev_bs_head) {
791 r = replace_gpr_with_pv_ps(slots, bc->cf_last->prev_bs_head);
792 if (r)
793 return r;
794 }
795
796 r = check_and_set_bank_swizzle(slots);
797 if (r)
798 return r;
799
800 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
801 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
802 bc->cf_last->curr_bs_head = NULL;
803 }
804 return 0;
805 }
806
807 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
808 {
809 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
810 }
811
812 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
813 {
814 struct r600_bc_alu *alu;
815
816 if (bc->cf_last == NULL) {
817 return 0;
818 }
819 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
820 return 0;
821 }
822 /* all same on EG */
823 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
824 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
825 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
826 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK ||
827 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE ||
828 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END ||
829 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
830 return 0;
831 }
832 /* same on EG */
833 if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
834 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3)) &&
835 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3)) &&
836 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
837 LIST_IS_EMPTY(&bc->cf_last->alu)) {
838 R600_ERR("last CF is not ALU (%p)\n", bc->cf_last);
839 return -EINVAL;
840 }
841 alu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
842 if (!alu->last || !alu->nliteral || alu->literal_added) {
843 return 0;
844 }
845 memcpy(alu->value, value, 4 * 4);
846 bc->cf_last->ndw += alu->nliteral;
847 bc->ndw += alu->nliteral;
848 alu->literal_added = 1;
849 return 0;
850 }
851
852 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
853 {
854 struct r600_bc_vtx *nvtx = r600_bc_vtx();
855 int r;
856
857 if (nvtx == NULL)
858 return -ENOMEM;
859 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
860
861 /* cf can contains only alu or only vtx or only tex */
862 if (bc->cf_last == NULL ||
863 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
864 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
865 bc->force_add_cf) {
866 r = r600_bc_add_cf(bc);
867 if (r) {
868 free(nvtx);
869 return r;
870 }
871 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
872 }
873 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
874 /* each fetch use 4 dwords */
875 bc->cf_last->ndw += 4;
876 bc->ndw += 4;
877 if ((bc->cf_last->ndw / 4) > 7)
878 bc->force_add_cf = 1;
879 return 0;
880 }
881
882 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
883 {
884 struct r600_bc_tex *ntex = r600_bc_tex();
885 int r;
886
887 if (ntex == NULL)
888 return -ENOMEM;
889 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
890
891 /* cf can contains only alu or only vtx or only tex */
892 if (bc->cf_last == NULL ||
893 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
894 bc->force_add_cf) {
895 r = r600_bc_add_cf(bc);
896 if (r) {
897 free(ntex);
898 return r;
899 }
900 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
901 }
902 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
903 /* each texture fetch use 4 dwords */
904 bc->cf_last->ndw += 4;
905 bc->ndw += 4;
906 if ((bc->cf_last->ndw / 4) > 7)
907 bc->force_add_cf = 1;
908 return 0;
909 }
910
911 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
912 {
913 int r;
914 r = r600_bc_add_cf(bc);
915 if (r)
916 return r;
917
918 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
919 bc->cf_last->inst = inst;
920 return 0;
921 }
922
923 /* common to all 3 families */
924 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
925 {
926 unsigned fetch_resource_start = 0;
927
928 /* check if we are fetch shader */
929 /* fetch shader can also access vertex resource,
930 * first fetch shader resource is at 160
931 */
932 if (bc->type == -1) {
933 switch (bc->chiprev) {
934 /* r600 */
935 case CHIPREV_R600:
936 /* r700 */
937 case CHIPREV_R700:
938 fetch_resource_start = 160;
939 break;
940 /* evergreen */
941 case CHIPREV_EVERGREEN:
942 fetch_resource_start = 0;
943 break;
944 default:
945 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
946 __FILE__, __func__, __LINE__, bc->chiprev);
947 break;
948 }
949 }
950 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
951 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
952 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
953 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
954 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
955 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
956 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
957 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
958 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
959 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
960 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
961 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
962 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
963 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
964 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
965 bc->bytecode[id++] = 0;
966 return 0;
967 }
968
969 /* common to all 3 families */
970 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
971 {
972 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
973 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
974 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
975 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
976 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
977 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
978 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
979 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
980 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
981 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
982 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
983 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
984 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
985 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
986 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
987 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
988 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
989 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
990 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
991 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
992 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
993 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
994 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
995 bc->bytecode[id++] = 0;
996 return 0;
997 }
998
999 /* r600 only, r700/eg bits in r700_asm.c */
1000 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1001 {
1002 unsigned i;
1003
1004 /* don't replace gpr by pv or ps for destination register */
1005 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1006 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1007 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1008 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1009 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1010 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1011 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1012 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1013 S_SQ_ALU_WORD0_LAST(alu->last);
1014
1015 if (alu->is_op3) {
1016 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1017 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1018 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1019 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1020 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1021 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1022 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1023 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1024 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1025 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1026 } else {
1027 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1028 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1029 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1030 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1031 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1032 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1033 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1034 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1035 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1036 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1037 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1038 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1039 }
1040 if (alu->last) {
1041 if (alu->nliteral && !alu->literal_added) {
1042 R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst);
1043 }
1044 for (i = 0; i < alu->nliteral; i++) {
1045 bc->bytecode[id++] = alu->value[i];
1046 }
1047 }
1048 return 0;
1049 }
1050
1051 /* common for r600/r700 - eg in eg_asm.c */
1052 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1053 {
1054 unsigned id = cf->id;
1055
1056 switch (cf->inst) {
1057 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1058 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1059 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1060 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1061 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1062 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode) |
1063 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache0_bank) |
1064 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache1_bank);
1065
1066 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1067 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache1_mode) |
1068 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache0_addr) |
1069 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache1_addr) |
1070 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1071 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
1072 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1073 break;
1074 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1075 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1076 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1077 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1078 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1079 S_SQ_CF_WORD1_BARRIER(1) |
1080 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1081 break;
1082 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1083 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1084 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1085 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1086 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1087 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1088 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1089 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1090 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1091 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1092 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1093 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1094 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1095 break;
1096 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1097 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1098 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1099 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1100 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1101 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1102 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1103 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1104 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1105 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1106 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1107 S_SQ_CF_WORD1_BARRIER(1) |
1108 S_SQ_CF_WORD1_COND(cf->cond) |
1109 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1110
1111 break;
1112 default:
1113 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1114 return -EINVAL;
1115 }
1116 return 0;
1117 }
1118
1119 int r600_bc_build(struct r600_bc *bc)
1120 {
1121 struct r600_bc_cf *cf;
1122 struct r600_bc_alu *alu;
1123 struct r600_bc_vtx *vtx;
1124 struct r600_bc_tex *tex;
1125 unsigned addr;
1126 int r;
1127
1128 if (bc->callstack[0].max > 0)
1129 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1130 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1131 bc->nstack = 1;
1132 }
1133
1134 /* first path compute addr of each CF block */
1135 /* addr start after all the CF instructions */
1136 addr = bc->cf_last->id + 2;
1137 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1138 switch (cf->inst) {
1139 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1140 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1141 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1142 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1143 break;
1144 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1145 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1146 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1147 /* fetch node need to be 16 bytes aligned*/
1148 addr += 3;
1149 addr &= 0xFFFFFFFCUL;
1150 break;
1151 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1152 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1153 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1154 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1155 break;
1156 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1157 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1158 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1159 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1160 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1161 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1162 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1163 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1164 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1165 break;
1166 default:
1167 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1168 return -EINVAL;
1169 }
1170 cf->addr = addr;
1171 addr += cf->ndw;
1172 bc->ndw = cf->addr + cf->ndw;
1173 }
1174 free(bc->bytecode);
1175 bc->bytecode = calloc(1, bc->ndw * 4);
1176 if (bc->bytecode == NULL)
1177 return -ENOMEM;
1178 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1179 addr = cf->addr;
1180 if (bc->chiprev == CHIPREV_EVERGREEN)
1181 r = eg_bc_cf_build(bc, cf);
1182 else
1183 r = r600_bc_cf_build(bc, cf);
1184 if (r)
1185 return r;
1186 switch (cf->inst) {
1187 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1188 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1189 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1190 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1191 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1192 switch(bc->chiprev) {
1193 case CHIPREV_R600:
1194 r = r600_bc_alu_build(bc, alu, addr);
1195 break;
1196 case CHIPREV_R700:
1197 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
1198 r = r700_bc_alu_build(bc, alu, addr);
1199 break;
1200 default:
1201 R600_ERR("unknown family %d\n", bc->family);
1202 return -EINVAL;
1203 }
1204 if (r)
1205 return r;
1206 addr += 2;
1207 if (alu->last) {
1208 addr += alu->nliteral;
1209 }
1210 }
1211 break;
1212 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1213 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1214 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1215 r = r600_bc_vtx_build(bc, vtx, addr);
1216 if (r)
1217 return r;
1218 addr += 4;
1219 }
1220 break;
1221 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1222 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1223 r = r600_bc_tex_build(bc, tex, addr);
1224 if (r)
1225 return r;
1226 addr += 4;
1227 }
1228 break;
1229 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1230 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1231 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1232 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1233 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1234 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1235 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1236 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1237 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1238 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1239 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1240 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1241 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1242 break;
1243 default:
1244 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1245 return -EINVAL;
1246 }
1247 }
1248 return 0;
1249 }
1250
1251 void r600_bc_clear(struct r600_bc *bc)
1252 {
1253 struct r600_bc_cf *cf = NULL, *next_cf;
1254
1255 free(bc->bytecode);
1256 bc->bytecode = NULL;
1257
1258 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1259 struct r600_bc_alu *alu = NULL, *next_alu;
1260 struct r600_bc_tex *tex = NULL, *next_tex;
1261 struct r600_bc_tex *vtx = NULL, *next_vtx;
1262
1263 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1264 free(alu);
1265 }
1266
1267 LIST_INITHEAD(&cf->alu);
1268
1269 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1270 free(tex);
1271 }
1272
1273 LIST_INITHEAD(&cf->tex);
1274
1275 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1276 free(vtx);
1277 }
1278
1279 LIST_INITHEAD(&cf->vtx);
1280
1281 free(cf);
1282 }
1283
1284 LIST_INITHEAD(&cf->list);
1285 }
1286
1287 void r600_bc_dump(struct r600_bc *bc)
1288 {
1289 struct r600_bc_cf *cf;
1290 struct r600_bc_alu *alu;
1291 struct r600_bc_vtx *vtx;
1292 struct r600_bc_tex *tex;
1293
1294 unsigned i, id;
1295 char chip = '6';
1296
1297 switch (bc->chiprev) {
1298 case 1:
1299 chip = '7';
1300 break;
1301 case 2:
1302 chip = 'E';
1303 break;
1304 case 0:
1305 default:
1306 chip = '6';
1307 break;
1308 }
1309 fprintf(stderr, "bytecode %d dw -----------------------\n", bc->ndw);
1310 fprintf(stderr, " %c\n", chip);
1311
1312 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1313 id = cf->id;
1314
1315 switch (cf->inst) {
1316 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1317 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1318 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1319 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1320 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1321 fprintf(stderr, "ADDR:%d ", cf->addr);
1322 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache0_mode);
1323 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache0_bank);
1324 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache1_bank);
1325 id++;
1326 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1327 fprintf(stderr, "INST:%d ", cf->inst);
1328 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache1_mode);
1329 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache0_addr);
1330 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache1_addr);
1331 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1332 break;
1333 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1334 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1335 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1336 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1337 fprintf(stderr, "ADDR:%d\n", cf->addr);
1338 id++;
1339 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1340 fprintf(stderr, "INST:%d ", cf->inst);
1341 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1342 break;
1343 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1344 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1345 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1346 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1347 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1348 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1349 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1350 id++;
1351 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1352 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1353 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1354 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1355 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1356 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1357 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1358 fprintf(stderr, "INST:%d ", cf->output.inst);
1359 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1360 break;
1361 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1362 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1363 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1364 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1365 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1366 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1367 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1368 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1369 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1370 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1371 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1372 id++;
1373 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1374 fprintf(stderr, "INST:%d ", cf->inst);
1375 fprintf(stderr, "COND:%X ", cf->cond);
1376 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1377 break;
1378 }
1379
1380 id = cf->addr;
1381 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1382 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1383 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1384 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1385 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1386 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1387 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1388 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1389 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1390 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1391 fprintf(stderr, "LAST:%d)\n", alu->last);
1392 id++;
1393 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1394 fprintf(stderr, "INST:%d ", alu->inst);
1395 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1396 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1397 fprintf(stderr, "REL:%d ", alu->dst.rel);
1398 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1399 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1400 if (alu->is_op3) {
1401 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1402 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1403 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1404 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1405 } else {
1406 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1407 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1408 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1409 fprintf(stderr, "OMOD:%d ", alu->omod);
1410 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1411 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1412 }
1413
1414 id++;
1415 if (alu->last) {
1416 for (i = 0; i < alu->nliteral; i++, id++) {
1417 float *f = (float*)(bc->bytecode + id);
1418 fprintf(stderr, "%04d %08X %f\n", id, bc->bytecode[id], *f);
1419 }
1420 }
1421 }
1422
1423 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1424 //TODO
1425 }
1426
1427 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1428 //TODO
1429 }
1430 }
1431
1432 fprintf(stderr, "--------------------------------------\n");
1433 }
1434
1435 void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1436 {
1437 struct r600_pipe_state *rstate;
1438 unsigned i = 0;
1439
1440 if (count > 8) {
1441 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1442 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1443 S_SQ_CF_WORD1_BARRIER(1) |
1444 S_SQ_CF_WORD1_COUNT(8 - 1);
1445 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1446 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1447 S_SQ_CF_WORD1_BARRIER(1) |
1448 S_SQ_CF_WORD1_COUNT(count - 8 - 1);
1449 } else {
1450 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1451 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1452 S_SQ_CF_WORD1_BARRIER(1) |
1453 S_SQ_CF_WORD1_COUNT(count - 1);
1454 }
1455 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1456 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1457 S_SQ_CF_WORD1_BARRIER(1);
1458
1459 rstate = &ve->rstate;
1460 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1461 rstate->nregs = 0;
1462 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1463 0x00000000, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1465 0x00000000, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1467 r600_bo_offset(ve->fetch_shader) >> 8,
1468 0xFFFFFFFF, ve->fetch_shader);
1469 }
1470
1471 void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1472 {
1473 struct r600_pipe_state *rstate;
1474 unsigned i = 0;
1475
1476 if (count > 8) {
1477 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1478 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1479 S_SQ_CF_WORD1_BARRIER(1) |
1480 S_SQ_CF_WORD1_COUNT(8 - 1);
1481 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1482 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1483 S_SQ_CF_WORD1_BARRIER(1) |
1484 S_SQ_CF_WORD1_COUNT((count - 8) - 1);
1485 } else {
1486 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1487 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1488 S_SQ_CF_WORD1_BARRIER(1) |
1489 S_SQ_CF_WORD1_COUNT(count - 1);
1490 }
1491 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1492 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1493 S_SQ_CF_WORD1_BARRIER(1);
1494
1495 rstate = &ve->rstate;
1496 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1497 rstate->nregs = 0;
1498 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1499 0x00000000, 0xFFFFFFFF, NULL);
1500 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1501 0x00000000, 0xFFFFFFFF, NULL);
1502 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1503 r600_bo_offset(ve->fetch_shader) >> 8,
1504 0xFFFFFFFF, ve->fetch_shader);
1505 }
1506
1507 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1508 unsigned *num_format, unsigned *format_comp)
1509 {
1510 const struct util_format_description *desc;
1511 unsigned i;
1512
1513 *format = 0;
1514 *num_format = 0;
1515 *format_comp = 0;
1516
1517 desc = util_format_description(pformat);
1518 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1519 goto out_unknown;
1520 }
1521
1522 /* Find the first non-VOID channel. */
1523 for (i = 0; i < 4; i++) {
1524 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1525 break;
1526 }
1527 }
1528
1529 switch (desc->channel[i].type) {
1530 /* Half-floats, floats, doubles */
1531 case UTIL_FORMAT_TYPE_FLOAT:
1532 switch (desc->channel[i].size) {
1533 case 16:
1534 switch (desc->nr_channels) {
1535 case 1:
1536 *format = FMT_16_FLOAT;
1537 break;
1538 case 2:
1539 *format = FMT_16_16_FLOAT;
1540 break;
1541 case 3:
1542 *format = FMT_16_16_16_FLOAT;
1543 break;
1544 case 4:
1545 *format = FMT_16_16_16_16_FLOAT;
1546 break;
1547 }
1548 break;
1549 case 32:
1550 switch (desc->nr_channels) {
1551 case 1:
1552 *format = FMT_32_FLOAT;
1553 break;
1554 case 2:
1555 *format = FMT_32_32_FLOAT;
1556 break;
1557 case 3:
1558 *format = FMT_32_32_32_FLOAT;
1559 break;
1560 case 4:
1561 *format = FMT_32_32_32_32_FLOAT;
1562 break;
1563 }
1564 break;
1565 default:
1566 goto out_unknown;
1567 }
1568 break;
1569 /* Unsigned ints */
1570 case UTIL_FORMAT_TYPE_UNSIGNED:
1571 /* Signed ints */
1572 case UTIL_FORMAT_TYPE_SIGNED:
1573 switch (desc->channel[i].size) {
1574 case 8:
1575 switch (desc->nr_channels) {
1576 case 1:
1577 *format = FMT_8;
1578 break;
1579 case 2:
1580 *format = FMT_8_8;
1581 break;
1582 case 3:
1583 // *format = FMT_8_8_8; /* fails piglit draw-vertices test */
1584 // break;
1585 case 4:
1586 *format = FMT_8_8_8_8;
1587 break;
1588 }
1589 break;
1590 case 16:
1591 switch (desc->nr_channels) {
1592 case 1:
1593 *format = FMT_16;
1594 break;
1595 case 2:
1596 *format = FMT_16_16;
1597 break;
1598 case 3:
1599 // *format = FMT_16_16_16; /* fails piglit draw-vertices test */
1600 // break;
1601 case 4:
1602 *format = FMT_16_16_16_16;
1603 break;
1604 }
1605 break;
1606 case 32:
1607 switch (desc->nr_channels) {
1608 case 1:
1609 *format = FMT_32;
1610 break;
1611 case 2:
1612 *format = FMT_32_32;
1613 break;
1614 case 3:
1615 *format = FMT_32_32_32;
1616 break;
1617 case 4:
1618 *format = FMT_32_32_32_32;
1619 break;
1620 }
1621 break;
1622 default:
1623 goto out_unknown;
1624 }
1625 break;
1626 default:
1627 goto out_unknown;
1628 }
1629
1630 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1631 *format_comp = 1;
1632 }
1633 if (desc->channel[i].normalized) {
1634 *num_format = 0;
1635 } else {
1636 *num_format = 2;
1637 }
1638 return;
1639 out_unknown:
1640 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
1641 }
1642
1643 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
1644 {
1645 unsigned ndw, i;
1646 u32 *bytecode;
1647 unsigned fetch_resource_start = 0, format, num_format, format_comp;
1648 struct pipe_vertex_element *elements = ve->elements;
1649 const struct util_format_description *desc;
1650
1651 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
1652 ndw = 8 + ve->count * 4;
1653 ve->fs_size = ndw * 4;
1654
1655 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
1656 ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
1657 if (ve->fetch_shader == NULL) {
1658 return -ENOMEM;
1659 }
1660
1661 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
1662 if (bytecode == NULL) {
1663 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
1664 return -ENOMEM;
1665 }
1666
1667 if (rctx->family >= CHIP_CEDAR) {
1668 eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
1669 } else {
1670 r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
1671 fetch_resource_start = 160;
1672 }
1673
1674 /* vertex elements offset need special handling, if offset is bigger
1675 * than what we can put in fetch instruction then we need to alterate
1676 * the vertex resource offset. In such case in order to simplify code
1677 * we will bound one resource per elements. It's a worst case scenario.
1678 */
1679 for (i = 0; i < ve->count; i++) {
1680 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
1681 if (ve->vbuffer_offset[i]) {
1682 ve->vbuffer_need_offset = 1;
1683 }
1684 }
1685
1686 for (i = 0; i < ve->count; i++) {
1687 unsigned vbuffer_index;
1688 r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
1689 desc = util_format_description(ve->hw_format[i]);
1690 if (desc == NULL) {
1691 R600_ERR("unknown format %d\n", ve->hw_format[i]);
1692 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
1693 return -EINVAL;
1694 }
1695
1696 /* see above for vbuffer_need_offset explanation */
1697 vbuffer_index = elements[i].vertex_buffer_index;
1698 if (ve->vbuffer_need_offset) {
1699 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
1700 } else {
1701 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
1702 }
1703 bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
1704 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
1705 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
1706 bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
1707 S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
1708 S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
1709 S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
1710 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
1711 S_SQ_VTX_WORD1_DATA_FORMAT(format) |
1712 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
1713 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
1714 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
1715 S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
1716 bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
1717 S_SQ_VTX_WORD2_MEGA_FETCH(1);
1718 bytecode[8 + i * 4 + 3] = 0;
1719 }
1720 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
1721 return 0;
1722 }