2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "pipe/p_shader_tokens.h"
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
38 static inline unsigned int r600_bytecode_get_num_operands(
39 struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
41 return r600_isa_alu(alu
->op
)->src_count
;
44 int r700_bytecode_alu_build(struct r600_bytecode
*bc
,
45 struct r600_bytecode_alu
*alu
, unsigned id
);
47 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
49 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
53 LIST_INITHEAD(&cf
->list
);
54 LIST_INITHEAD(&cf
->alu
);
55 LIST_INITHEAD(&cf
->vtx
);
56 LIST_INITHEAD(&cf
->tex
);
60 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
62 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
66 LIST_INITHEAD(&alu
->list
);
70 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
72 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
76 LIST_INITHEAD(&vtx
->list
);
80 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
82 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
86 LIST_INITHEAD(&tex
->list
);
90 static unsigned stack_entry_size(enum radeon_family chip
) {
92 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
93 * Aruba/Sumo/Sumo2/redwood/juniper
94 * 32: R630/R730/R710/Palm/Cedar
98 * Wavefront Size 16 32 48 64
99 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
100 * Columns per Row (R9xx+) 8 4 4 4 */
103 /* FIXME: are some chips missing here? */
104 /* wavefront size 16 */
109 /* wavefront size 32 */
118 /* wavefront size 64 */
124 void r600_bytecode_init(struct r600_bytecode
*bc
,
125 enum chip_class chip_class
,
126 enum radeon_family family
,
127 enum r600_msaa_texture_mode msaa_texture_mode
)
129 if ((chip_class
== R600
) &&
130 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
131 bc
->ar_handling
= AR_HANDLE_RV6XX
;
132 bc
->r6xx_nop_after_rel_dst
= 1;
134 bc
->ar_handling
= AR_HANDLE_NORMAL
;
135 bc
->r6xx_nop_after_rel_dst
= 0;
138 LIST_INITHEAD(&bc
->cf
);
139 bc
->chip_class
= chip_class
;
140 bc
->msaa_texture_mode
= msaa_texture_mode
;
141 bc
->stack
.entry_size
= stack_entry_size(family
);
144 int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
146 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
150 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
152 cf
->id
= bc
->cf_last
->id
+ 2;
153 if (bc
->cf_last
->eg_alu_extended
) {
154 /* take into account extended alu size */
162 bc
->force_add_cf
= 0;
167 int r600_bytecode_add_output(struct r600_bytecode
*bc
,
168 const struct r600_bytecode_output
*output
)
172 if (output
->gpr
>= bc
->ngpr
)
173 bc
->ngpr
= output
->gpr
+ 1;
175 if (bc
->cf_last
&& (bc
->cf_last
->op
== output
->op
||
176 (bc
->cf_last
->op
== CF_OP_EXPORT
&&
177 output
->op
== CF_OP_EXPORT_DONE
)) &&
178 output
->type
== bc
->cf_last
->output
.type
&&
179 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
180 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
181 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
182 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
183 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
184 output
->comp_mask
== bc
->cf_last
->output
.comp_mask
&&
185 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
187 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
188 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
190 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
191 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
192 bc
->cf_last
->output
.gpr
= output
->gpr
;
193 bc
->cf_last
->output
.array_base
= output
->array_base
;
194 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
197 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
198 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
200 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
201 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
202 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
207 r
= r600_bytecode_add_cf(bc
);
210 bc
->cf_last
->op
= output
->op
;
211 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
215 /* alu instructions that can ony exits once per group */
216 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
218 return r600_isa_alu(alu
->op
)->flags
& (AF_KILL
| AF_PRED
);
221 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
223 return (r600_isa_alu(alu
->op
)->flags
& AF_REPL
) &&
224 (r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
) == AF_4V
);
227 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
229 return r600_isa_alu(alu
->op
)->flags
& AF_MOVA
;
232 static int alu_uses_rel(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
234 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
241 for (src
= 0; src
< num_src
; ++src
) {
242 if (alu
->src
[src
].rel
) {
249 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
251 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
252 return !(slots
& AF_S
);
255 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
257 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
258 return !(slots
& AF_V
);
261 /* alu instructions that can execute on any unit */
262 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
264 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
265 return slots
== AF_VS
;
268 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
270 return alu
->op
== ALU_OP0_NOP
;
273 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
274 struct r600_bytecode_alu
*assignment
[5])
276 struct r600_bytecode_alu
*alu
;
277 unsigned i
, chan
, trans
;
278 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
280 for (i
= 0; i
< max_slots
; i
++)
281 assignment
[i
] = NULL
;
283 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
284 chan
= alu
->dst
.chan
;
287 else if (is_alu_trans_unit_inst(bc
, alu
))
289 else if (is_alu_vec_unit_inst(bc
, alu
))
291 else if (assignment
[chan
])
292 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
298 assert(0); /* ALU.Trans has already been allocated. */
303 if (assignment
[chan
]) {
304 assert(0); /* ALU.chan has already been allocated. */
307 assignment
[chan
] = alu
;
316 struct alu_bank_swizzle
{
317 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
318 int hw_cfile_addr
[4];
319 int hw_cfile_elem
[4];
322 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
323 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
324 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
325 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
326 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
327 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
328 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
331 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
332 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
333 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
334 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
335 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
338 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
340 int i
, cycle
, component
;
342 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
343 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
344 bs
->hw_gpr
[cycle
][component
] = -1;
345 for (i
= 0; i
< 4; i
++)
346 bs
->hw_cfile_addr
[i
] = -1;
347 for (i
= 0; i
< 4; i
++)
348 bs
->hw_cfile_elem
[i
] = -1;
351 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
353 if (bs
->hw_gpr
[cycle
][chan
] == -1)
354 bs
->hw_gpr
[cycle
][chan
] = sel
;
355 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
356 /* Another scalar operation has already used the GPR read port for the channel. */
362 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
364 int res
, num_res
= 4;
365 if (bc
->chip_class
>= R700
) {
369 for (res
= 0; res
< num_res
; ++res
) {
370 if (bs
->hw_cfile_addr
[res
] == -1) {
371 bs
->hw_cfile_addr
[res
] = sel
;
372 bs
->hw_cfile_elem
[res
] = chan
;
374 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
375 bs
->hw_cfile_elem
[res
] == chan
)
376 return 0; /* Read for this scalar element already reserved, nothing to do here. */
378 /* All cfile read ports are used, cannot reference vector element. */
382 static int is_gpr(unsigned sel
)
384 return (sel
>= 0 && sel
<= 127);
387 /* CB constants start at 512, and get translated to a kcache index when ALU
388 * clauses are constructed. Note that we handle kcache constants the same way
389 * as (the now gone) cfile constants, is that really required? */
390 static int is_cfile(unsigned sel
)
392 return (sel
> 255 && sel
< 512) ||
393 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
394 (sel
> 127 && sel
< 192); /* Kcache after translation. */
397 static int is_const(int sel
)
399 return is_cfile(sel
) ||
400 (sel
>= V_SQ_ALU_SRC_0
&&
401 sel
<= V_SQ_ALU_SRC_LITERAL
);
404 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
405 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
407 int r
, src
, num_src
, sel
, elem
, cycle
;
409 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
410 for (src
= 0; src
< num_src
; src
++) {
411 sel
= alu
->src
[src
].sel
;
412 elem
= alu
->src
[src
].chan
;
414 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
415 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
416 /* Nothing to do; special-case optimization,
417 * second source uses first source’s reservation. */
420 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
424 } else if (is_cfile(sel
)) {
425 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
429 /* No restrictions on PV, PS, literal or special constants. */
434 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
435 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
437 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
439 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
440 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
441 sel
= alu
->src
[src
].sel
;
442 elem
= alu
->src
[src
].chan
;
443 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
444 if (const_count
>= 2)
445 /* More than two references to a constant in
446 * transcendental operation. */
452 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
457 for (src
= 0; src
< num_src
; ++src
) {
458 sel
= alu
->src
[src
].sel
;
459 elem
= alu
->src
[src
].chan
;
461 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
462 if (cycle
< const_count
)
463 /* Cycle for GPR load conflicts with
464 * constant load in transcendental operation. */
466 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
470 /* PV PS restrictions */
471 if (const_count
&& (sel
== 254 || sel
== 255)) {
472 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
473 if (cycle
< const_count
)
480 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
481 struct r600_bytecode_alu
*slots
[5])
483 struct alu_bank_swizzle bs
;
485 int i
, r
= 0, forced
= 1;
486 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
487 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
489 for (i
= 0; i
< max_slots
; i
++) {
491 if (slots
[i
]->bank_swizzle_force
) {
492 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
498 if (i
< 4 && slots
[i
])
504 /* Just check every possible combination of bank swizzle.
505 * Not very efficent, but works on the first try in most of the cases. */
506 for (i
= 0; i
< 4; i
++)
507 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
508 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
510 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
512 bank_swizzle
[4] = SQ_ALU_SCL_210
;
513 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
515 init_bank_swizzle(&bs
);
516 if (scalar_only
== false) {
517 for (i
= 0; i
< 4; i
++) {
519 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
527 if (!r
&& slots
[4] && max_slots
== 5) {
528 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
531 for (i
= 0; i
< max_slots
; i
++) {
533 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
541 for (i
= 0; i
< max_slots
; i
++) {
542 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
544 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
546 else if (i
< max_slots
- 1)
547 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
555 /* Couldn't find a working swizzle. */
559 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
560 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
562 struct r600_bytecode_alu
*prev
[5];
564 int i
, j
, r
, src
, num_src
;
565 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
567 r
= assign_alu_units(bc
, alu_prev
, prev
);
571 for (i
= 0; i
< max_slots
; ++i
) {
572 if (prev
[i
] && (prev
[i
]->dst
.write
|| prev
[i
]->is_op3
) && !prev
[i
]->dst
.rel
) {
573 gpr
[i
] = prev
[i
]->dst
.sel
;
574 /* cube writes more than PV.X */
575 if (is_alu_reduction_inst(bc
, prev
[i
]))
578 chan
[i
] = prev
[i
]->dst
.chan
;
583 for (i
= 0; i
< max_slots
; ++i
) {
584 struct r600_bytecode_alu
*alu
= slots
[i
];
588 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
589 for (src
= 0; src
< num_src
; ++src
) {
590 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
593 if (bc
->chip_class
< CAYMAN
) {
594 if (alu
->src
[src
].sel
== gpr
[4] &&
595 alu
->src
[src
].chan
== chan
[4] &&
596 alu_prev
->pred_sel
== alu
->pred_sel
) {
597 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
598 alu
->src
[src
].chan
= 0;
603 for (j
= 0; j
< 4; ++j
) {
604 if (alu
->src
[src
].sel
== gpr
[j
] &&
605 alu
->src
[src
].chan
== j
&&
606 alu_prev
->pred_sel
== alu
->pred_sel
) {
607 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
608 alu
->src
[src
].chan
= chan
[j
];
618 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
)
622 *sel
= V_SQ_ALU_SRC_0
;
625 *sel
= V_SQ_ALU_SRC_1_INT
;
628 *sel
= V_SQ_ALU_SRC_M_1_INT
;
630 case 0x3F800000: /* 1.0f */
631 *sel
= V_SQ_ALU_SRC_1
;
633 case 0x3F000000: /* 0.5f */
634 *sel
= V_SQ_ALU_SRC_0_5
;
636 case 0xBF800000: /* -1.0f */
637 *sel
= V_SQ_ALU_SRC_1
;
640 case 0xBF000000: /* -0.5f */
641 *sel
= V_SQ_ALU_SRC_0_5
;
645 *sel
= V_SQ_ALU_SRC_LITERAL
;
650 /* compute how many literal are needed */
651 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
652 uint32_t literal
[4], unsigned *nliteral
)
654 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
657 for (i
= 0; i
< num_src
; ++i
) {
658 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
659 uint32_t value
= alu
->src
[i
].value
;
661 for (j
= 0; j
< *nliteral
; ++j
) {
662 if (literal
[j
] == value
) {
670 literal
[(*nliteral
)++] = value
;
677 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
678 struct r600_bytecode_alu
*alu
,
679 uint32_t literal
[4], unsigned nliteral
)
681 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
684 for (i
= 0; i
< num_src
; ++i
) {
685 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
686 uint32_t value
= alu
->src
[i
].value
;
687 for (j
= 0; j
< nliteral
; ++j
) {
688 if (literal
[j
] == value
) {
689 alu
->src
[i
].chan
= j
;
697 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
698 struct r600_bytecode_alu
*alu_prev
)
700 struct r600_bytecode_alu
*prev
[5];
701 struct r600_bytecode_alu
*result
[5] = { NULL
};
703 uint32_t literal
[4], prev_literal
[4];
704 unsigned nliteral
= 0, prev_nliteral
= 0;
706 int i
, j
, r
, src
, num_src
;
707 int num_once_inst
= 0;
708 int have_mova
= 0, have_rel
= 0;
709 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
711 r
= assign_alu_units(bc
, alu_prev
, prev
);
715 for (i
= 0; i
< max_slots
; ++i
) {
717 if (prev
[i
]->pred_sel
)
719 if (is_alu_once_inst(bc
, prev
[i
]))
723 if (slots
[i
]->pred_sel
)
725 if (is_alu_once_inst(bc
, slots
[i
]))
730 for (i
= 0; i
< max_slots
; ++i
) {
731 struct r600_bytecode_alu
*alu
;
733 if (num_once_inst
> 0)
736 /* check number of literals */
738 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
740 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
742 if (is_alu_mova_inst(bc
, prev
[i
])) {
748 if (alu_uses_rel(bc
, prev
[i
])) {
755 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
757 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
760 /* Let's check used slots. */
761 if (prev
[i
] && !slots
[i
]) {
764 } else if (prev
[i
] && slots
[i
]) {
765 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
766 /* Trans unit is still free try to use it. */
767 if (is_alu_any_unit_inst(bc
, slots
[i
])) {
769 result
[4] = slots
[i
];
770 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
771 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
772 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
773 (prev
[i
]->dst
.write
== 1 || prev
[i
]->is_op3
))
776 result
[i
] = slots
[i
];
782 } else if(!slots
[i
]) {
785 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
786 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
787 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
788 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
789 (prev
[4]->dst
.write
== 1 || prev
[4]->is_op3
))
792 result
[i
] = slots
[i
];
796 num_once_inst
+= is_alu_once_inst(bc
, alu
);
798 /* don't reschedule NOPs */
799 if (is_nop_inst(bc
, alu
))
802 if (is_alu_mova_inst(bc
, alu
)) {
809 if (alu_uses_rel(bc
, alu
)) {
816 /* Let's check source gprs */
817 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
818 for (src
= 0; src
< num_src
; ++src
) {
820 /* Constants don't matter. */
821 if (!is_gpr(alu
->src
[src
].sel
))
824 for (j
= 0; j
< max_slots
; ++j
) {
825 if (!prev
[j
] || !(prev
[j
]->dst
.write
|| prev
[j
]->is_op3
))
828 /* If it's relative then we can't determin which gpr is really used. */
829 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
830 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
831 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
837 /* more than one PRED_ or KILL_ ? */
838 if (num_once_inst
> 1)
841 /* check if the result can still be swizzlet */
842 r
= check_and_set_bank_swizzle(bc
, result
);
846 /* looks like everything worked out right, apply the changes */
848 /* undo adding previus literals */
849 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
851 /* sort instructions */
852 for (i
= 0; i
< max_slots
; ++i
) {
853 slots
[i
] = result
[i
];
855 LIST_DEL(&result
[i
]->list
);
857 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
861 /* determine new last instruction */
862 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
864 /* determine new first instruction */
865 for (i
= 0; i
< max_slots
; ++i
) {
867 bc
->cf_last
->curr_bs_head
= result
[i
];
872 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
873 bc
->cf_last
->prev2_bs_head
= NULL
;
878 /* we'll keep kcache sets sorted by bank & addr */
879 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
880 struct r600_bytecode_kcache
*kcache
,
881 unsigned bank
, unsigned line
)
883 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
885 for (i
= 0; i
< kcache_banks
; i
++) {
886 if (kcache
[i
].mode
) {
889 if (kcache
[i
].bank
< bank
)
892 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
893 kcache
[i
].bank
> bank
) {
894 /* try to insert new line */
895 if (kcache
[kcache_banks
-1].mode
) {
896 /* all sets are in use */
900 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
901 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
902 kcache
[i
].bank
= bank
;
903 kcache
[i
].addr
= line
;
907 d
= line
- kcache
[i
].addr
;
911 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
912 /* we are prepending the line to the current set,
913 * discarding the existing second line,
914 * so we'll have to insert line+2 after it */
917 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
918 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
921 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
925 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
929 } else { /* free kcache set - use it */
930 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
931 kcache
[i
].bank
= bank
;
932 kcache
[i
].addr
= line
;
939 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
940 struct r600_bytecode_kcache
*kcache
,
941 struct r600_bytecode_alu
*alu
)
945 for (i
= 0; i
< 3; i
++) {
946 unsigned bank
, line
, sel
= alu
->src
[i
].sel
;
951 bank
= alu
->src
[i
].kc_bank
;
954 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
)))
960 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
961 struct r600_bytecode_alu
*alu
,
962 struct r600_bytecode_kcache
* kcache
)
966 /* Alter the src operands to refer to the kcache. */
967 for (i
= 0; i
< 3; ++i
) {
968 static const unsigned int base
[] = {128, 160, 256, 288};
969 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
977 for (j
= 0; j
< 4 && !found
; ++j
) {
978 switch (kcache
[j
].mode
) {
979 case V_SQ_CF_KCACHE_NOP
:
980 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
981 R600_ERR("unexpected kcache line mode\n");
984 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
985 kcache
[j
].addr
<= line
&&
986 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
987 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
988 alu
->src
[i
].sel
+= base
[j
];
997 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
,
998 struct r600_bytecode_alu
*alu
,
1001 struct r600_bytecode_kcache kcache_sets
[4];
1002 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1005 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1007 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1008 /* can't alloc, need to start new clause */
1009 if ((r
= r600_bytecode_add_cf(bc
))) {
1012 bc
->cf_last
->op
= type
;
1014 /* retry with the new clause */
1015 kcache
= bc
->cf_last
->kcache
;
1016 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1017 /* can't alloc again- should never happen */
1021 /* update kcache sets */
1022 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1025 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1026 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
) {
1027 if (bc
->chip_class
< EVERGREEN
)
1029 bc
->cf_last
->eg_alu_extended
= 1;
1035 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1037 struct r600_bytecode_alu alu
;
1040 for (i
= 0; i
< 4; i
++) {
1041 memset(&alu
, 0, sizeof(alu
));
1042 alu
.op
= ALU_OP0_NOP
;
1043 alu
.src
[0].chan
= i
;
1045 alu
.last
= (i
== 3);
1046 r
= r600_bytecode_add_alu(bc
, &alu
);
1053 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1054 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1056 struct r600_bytecode_alu alu
;
1062 /* hack to avoid making MOVA the last instruction in the clause */
1063 if ((bc
->cf_last
->ndw
>>1) >= 110)
1064 bc
->force_add_cf
= 1;
1066 memset(&alu
, 0, sizeof(alu
));
1067 alu
.op
= ALU_OP1_MOVA_GPR_INT
;
1068 alu
.src
[0].sel
= bc
->ar_reg
;
1069 alu
.src
[0].chan
= bc
->ar_chan
;
1071 alu
.index_mode
= INDEX_MODE_LOOP
;
1072 r
= r600_bytecode_add_alu(bc
, &alu
);
1076 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1081 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1082 static int load_ar(struct r600_bytecode
*bc
)
1084 struct r600_bytecode_alu alu
;
1087 if (bc
->ar_handling
)
1088 return load_ar_r6xx(bc
);
1093 /* hack to avoid making MOVA the last instruction in the clause */
1094 if ((bc
->cf_last
->ndw
>>1) >= 110)
1095 bc
->force_add_cf
= 1;
1097 memset(&alu
, 0, sizeof(alu
));
1098 alu
.op
= ALU_OP1_MOVA_INT
;
1099 alu
.src
[0].sel
= bc
->ar_reg
;
1100 alu
.src
[0].chan
= bc
->ar_chan
;
1102 r
= r600_bytecode_add_alu(bc
, &alu
);
1106 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1111 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
,
1112 const struct r600_bytecode_alu
*alu
, unsigned type
)
1114 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1115 struct r600_bytecode_alu
*lalu
;
1120 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1122 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->op
!= type
) {
1123 /* check if we could add it anyway */
1124 if (bc
->cf_last
->op
== CF_OP_ALU
&&
1125 type
== CF_OP_ALU_PUSH_BEFORE
) {
1126 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1127 if (lalu
->execute_mask
) {
1128 bc
->force_add_cf
= 1;
1133 bc
->force_add_cf
= 1;
1136 /* cf can contains only alu or only vtx or only tex */
1137 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1138 r
= r600_bytecode_add_cf(bc
);
1144 bc
->cf_last
->op
= type
;
1146 /* Check AR usage and load it if required */
1147 for (i
= 0; i
< 3; i
++)
1148 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1151 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1154 /* Setup the kcache for this ALU instruction. This will start a new
1155 * ALU clause if needed. */
1156 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1161 if (!bc
->cf_last
->curr_bs_head
) {
1162 bc
->cf_last
->curr_bs_head
= nalu
;
1164 /* number of gpr == the last gpr used in any alu */
1165 for (i
= 0; i
< 3; i
++) {
1166 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1167 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1169 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1170 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1171 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
);
1173 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1174 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1176 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1177 /* each alu use 2 dwords */
1178 bc
->cf_last
->ndw
+= 2;
1181 /* process cur ALU instructions for bank swizzle */
1183 uint32_t literal
[4];
1185 struct r600_bytecode_alu
*slots
[5];
1186 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1187 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1191 if (bc
->cf_last
->prev_bs_head
) {
1192 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1197 if (bc
->cf_last
->prev_bs_head
) {
1198 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1203 r
= check_and_set_bank_swizzle(bc
, slots
);
1207 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1209 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1214 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1216 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1218 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1219 bc
->force_add_cf
= 1;
1222 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1223 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1224 bc
->cf_last
->curr_bs_head
= NULL
;
1227 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1228 insert_nop_r6xx(bc
);
1233 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1235 return r600_bytecode_add_alu_type(bc
, alu
, CF_OP_ALU
);
1238 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1240 switch (bc
->chip_class
) {
1250 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1255 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1257 return !((r600_isa_cf(bc
->cf_last
->op
)->flags
& CF_FETCH
) &&
1258 (bc
->chip_class
== CAYMAN
||
1259 bc
->cf_last
->op
!= CF_OP_TEX
));
1262 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1264 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1269 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1271 /* cf can contains only alu or only vtx or only tex */
1272 if (bc
->cf_last
== NULL
||
1273 last_inst_was_not_vtx_fetch(bc
) ||
1275 r
= r600_bytecode_add_cf(bc
);
1280 switch (bc
->chip_class
) {
1284 bc
->cf_last
->op
= CF_OP_VTX
;
1287 bc
->cf_last
->op
= CF_OP_TEX
;
1290 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1295 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1296 /* each fetch use 4 dwords */
1297 bc
->cf_last
->ndw
+= 4;
1299 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1300 bc
->force_add_cf
= 1;
1302 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1303 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1308 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1310 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1315 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1317 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1318 if (bc
->cf_last
!= NULL
&&
1319 bc
->cf_last
->op
== CF_OP_TEX
) {
1320 struct r600_bytecode_tex
*ttex
;
1321 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1322 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1323 bc
->force_add_cf
= 1;
1327 /* slight hack to make gradients always go into same cf */
1328 if (ntex
->op
== FETCH_OP_SET_GRADIENTS_H
)
1329 bc
->force_add_cf
= 1;
1332 /* cf can contains only alu or only vtx or only tex */
1333 if (bc
->cf_last
== NULL
||
1334 bc
->cf_last
->op
!= CF_OP_TEX
||
1336 r
= r600_bytecode_add_cf(bc
);
1341 bc
->cf_last
->op
= CF_OP_TEX
;
1343 if (ntex
->src_gpr
>= bc
->ngpr
) {
1344 bc
->ngpr
= ntex
->src_gpr
+ 1;
1346 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1347 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1349 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1350 /* each texture fetch use 4 dwords */
1351 bc
->cf_last
->ndw
+= 4;
1353 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1354 bc
->force_add_cf
= 1;
1358 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, unsigned op
)
1361 r
= r600_bytecode_add_cf(bc
);
1365 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1366 bc
->cf_last
->op
= op
;
1370 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1372 return r600_bytecode_add_cfinst(bc
, CF_OP_CF_END
);
1375 /* common to all 3 families */
1376 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1378 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1379 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1380 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1381 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1382 if (bc
->chip_class
< CAYMAN
)
1383 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1385 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1386 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1387 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1388 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1389 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1390 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1391 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1392 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1393 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1394 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1395 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1396 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1397 if (bc
->chip_class
< CAYMAN
)
1398 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1400 bc
->bytecode
[id
++] = 0;
1404 /* common to all 3 families */
1405 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1407 bc
->bytecode
[id
++] = S_SQ_TEX_WORD0_TEX_INST(
1408 r600_isa_fetch_opcode(bc
->isa
->hw_class
, tex
->op
)) |
1409 EG_S_SQ_TEX_WORD0_INST_MOD(tex
->inst_mod
) |
1410 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1411 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1412 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1413 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1414 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1415 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1416 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1417 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1418 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1419 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1420 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1421 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1422 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1423 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1424 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1425 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1426 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1427 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1428 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1429 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1430 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1431 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1432 bc
->bytecode
[id
++] = 0;
1436 /* r600 only, r700/eg bits in r700_asm.c */
1437 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1439 unsigned opcode
= r600_isa_alu_opcode(bc
->isa
->hw_class
, alu
->op
);
1441 /* don't replace gpr by pv or ps for destination register */
1442 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1443 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1444 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1445 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1446 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1447 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1448 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1449 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1450 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1451 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1452 S_SQ_ALU_WORD0_LAST(alu
->last
);
1455 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1456 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1457 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1458 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1459 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1460 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1461 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1462 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1463 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode
) |
1464 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1466 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1467 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1468 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1469 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1470 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1471 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1472 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1473 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1474 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode
) |
1475 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1476 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1477 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1482 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1484 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1485 *bytecode
++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600
, cf
->op
)) |
1486 S_SQ_CF_WORD1_BARRIER(1) |
1487 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1490 /* common for r600/r700 - eg in eg_asm.c */
1491 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1493 unsigned id
= cf
->id
;
1494 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1495 unsigned opcode
= r600_isa_cf_opcode(bc
->isa
->hw_class
, cf
->op
);
1497 if (cfop
->flags
& CF_ALU
) {
1498 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1499 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1500 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1501 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1503 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode
) |
1504 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1505 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1506 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1507 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1508 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1509 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1510 } else if (cfop
->flags
& CF_FETCH
) {
1511 if (bc
->chip_class
== R700
)
1512 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1514 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1515 } else if (cfop
->flags
& CF_EXP
) {
1516 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1517 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1518 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1519 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1520 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1521 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1522 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1523 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1524 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1525 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1526 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1527 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
);
1528 } else if (cfop
->flags
& CF_STRM
) {
1529 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1530 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1531 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1532 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1533 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1534 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1535 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1536 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
) |
1537 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1538 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1540 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1541 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(opcode
) |
1542 S_SQ_CF_WORD1_BARRIER(1) |
1543 S_SQ_CF_WORD1_COND(cf
->cond
) |
1544 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
);
1549 int r600_bytecode_build(struct r600_bytecode
*bc
)
1551 struct r600_bytecode_cf
*cf
;
1552 struct r600_bytecode_alu
*alu
;
1553 struct r600_bytecode_vtx
*vtx
;
1554 struct r600_bytecode_tex
*tex
;
1555 uint32_t literal
[4];
1560 if (!bc
->nstack
) // If not 0, Stack_size already provided by llvm
1561 bc
->nstack
= bc
->stack
.max_entries
;
1563 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1567 /* first path compute addr of each CF block */
1568 /* addr start after all the CF instructions */
1569 addr
= bc
->cf_last
->id
+ 2;
1570 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1571 if (r600_isa_cf(cf
->op
)->flags
& CF_FETCH
) {
1573 addr
&= 0xFFFFFFFCUL
;
1577 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1580 bc
->bytecode
= calloc(1, bc
->ndw
* 4);
1581 if (bc
->bytecode
== NULL
)
1583 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1584 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1586 if (bc
->chip_class
>= EVERGREEN
)
1587 r
= eg_bytecode_cf_build(bc
, cf
);
1589 r
= r600_bytecode_cf_build(bc
, cf
);
1592 if (cfop
->flags
& CF_ALU
) {
1594 memset(literal
, 0, sizeof(literal
));
1595 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1596 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
1599 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
1600 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
1602 switch(bc
->chip_class
) {
1604 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
1607 case EVERGREEN
: /* eg alu is same encoding as r700 */
1609 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
1612 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
1619 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
1620 bc
->bytecode
[addr
++] = literal
[i
];
1623 memset(literal
, 0, sizeof(literal
));
1626 } else if (cf
->op
== CF_OP_VTX
) {
1627 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1628 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1633 } else if (cf
->op
== CF_OP_TEX
) {
1634 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1635 assert(bc
->chip_class
>= EVERGREEN
);
1636 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1641 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1642 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
1652 void r600_bytecode_clear(struct r600_bytecode
*bc
)
1654 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
1657 bc
->bytecode
= NULL
;
1659 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
1660 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
1661 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
1662 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
1664 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
1668 LIST_INITHEAD(&cf
->alu
);
1670 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
1674 LIST_INITHEAD(&cf
->tex
);
1676 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
1680 LIST_INITHEAD(&cf
->vtx
);
1685 LIST_INITHEAD(&cf
->list
);
1688 static int print_swizzle(unsigned swz
)
1690 const char * swzchars
= "xyzw01?_";
1691 assert(swz
<8 && swz
!= 6);
1692 return fprintf(stderr
, "%c", swzchars
[swz
]);
1695 static int print_sel(unsigned sel
, unsigned rel
, unsigned index_mode
,
1696 unsigned need_brackets
)
1699 if (rel
&& index_mode
>= 5 && sel
< 128)
1700 o
+= fprintf(stderr
, "G");
1701 if (rel
|| need_brackets
) {
1702 o
+= fprintf(stderr
, "[");
1704 o
+= fprintf(stderr
, "%d", sel
);
1706 if (index_mode
== 0 || index_mode
== 6)
1707 o
+= fprintf(stderr
, "+AR");
1708 else if (index_mode
== 4)
1709 o
+= fprintf(stderr
, "+AL");
1711 if (rel
|| need_brackets
) {
1712 o
+= fprintf(stderr
, "]");
1717 static int print_dst(struct r600_bytecode_alu
*alu
)
1720 unsigned sel
= alu
->dst
.sel
;
1721 char reg_char
= 'R';
1722 if (sel
> 128 - 4) { /* clause temporary gpr */
1727 if (alu
->dst
.write
|| alu
->is_op3
) {
1728 o
+= fprintf(stderr
, "%c", reg_char
);
1729 o
+= print_sel(alu
->dst
.sel
, alu
->dst
.rel
, alu
->index_mode
, 0);
1731 o
+= fprintf(stderr
, "__");
1733 o
+= fprintf(stderr
, ".");
1734 o
+= print_swizzle(alu
->dst
.chan
);
1738 static int print_src(struct r600_bytecode_alu
*alu
, unsigned idx
)
1741 struct r600_bytecode_alu_src
*src
= &alu
->src
[idx
];
1742 unsigned sel
= src
->sel
, need_sel
= 1, need_chan
= 1, need_brackets
= 0;
1745 o
+= fprintf(stderr
,"-");
1747 o
+= fprintf(stderr
,"|");
1749 if (sel
< 128 - 4) {
1750 o
+= fprintf(stderr
, "R");
1751 } else if (sel
< 128) {
1752 o
+= fprintf(stderr
, "T");
1754 } else if (sel
< 160) {
1755 o
+= fprintf(stderr
, "KC0");
1758 } else if (sel
< 192) {
1759 o
+= fprintf(stderr
, "KC1");
1762 } else if (sel
>= 512) {
1763 o
+= fprintf(stderr
, "C%d", src
->kc_bank
);
1766 } else if (sel
>= 448) {
1767 o
+= fprintf(stderr
, "Param");
1770 } else if (sel
>= 288) {
1771 o
+= fprintf(stderr
, "KC3");
1774 } else if (sel
>= 256) {
1775 o
+= fprintf(stderr
, "KC2");
1782 case V_SQ_ALU_SRC_PS
:
1783 o
+= fprintf(stderr
, "PS");
1785 case V_SQ_ALU_SRC_PV
:
1786 o
+= fprintf(stderr
, "PV");
1789 case V_SQ_ALU_SRC_LITERAL
:
1790 o
+= fprintf(stderr
, "[0x%08X %f]", src
->value
, *(float*)&src
->value
);
1792 case V_SQ_ALU_SRC_0_5
:
1793 o
+= fprintf(stderr
, "0.5");
1795 case V_SQ_ALU_SRC_M_1_INT
:
1796 o
+= fprintf(stderr
, "-1");
1798 case V_SQ_ALU_SRC_1_INT
:
1799 o
+= fprintf(stderr
, "1");
1801 case V_SQ_ALU_SRC_1
:
1802 o
+= fprintf(stderr
, "1.0");
1804 case V_SQ_ALU_SRC_0
:
1805 o
+= fprintf(stderr
, "0");
1808 o
+= fprintf(stderr
, "??IMM_%d", sel
);
1814 o
+= print_sel(sel
, src
->rel
, alu
->index_mode
, need_brackets
);
1817 o
+= fprintf(stderr
, ".");
1818 o
+= print_swizzle(src
->chan
);
1822 o
+= fprintf(stderr
,"|");
1827 static int print_indent(int p
, int c
)
1831 o
+= fprintf(stderr
, " ");
1835 void r600_bytecode_disasm(struct r600_bytecode
*bc
)
1837 static int index
= 0;
1838 struct r600_bytecode_cf
*cf
= NULL
;
1839 struct r600_bytecode_alu
*alu
= NULL
;
1840 struct r600_bytecode_vtx
*vtx
= NULL
;
1841 struct r600_bytecode_tex
*tex
= NULL
;
1843 unsigned i
, id
, ngr
= 0, last
;
1844 uint32_t literal
[4];
1848 switch (bc
->chip_class
) {
1863 fprintf(stderr
, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1864 bc
->ndw
, bc
->ngpr
, bc
->nstack
);
1865 fprintf(stderr
, "shader %d -- %c\n", index
++, chip
);
1867 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1869 if (cf
->op
== CF_NATIVE
) {
1870 fprintf(stderr
, "%04d %08X %08X CF_NATIVE\n", id
, bc
->bytecode
[id
],
1871 bc
->bytecode
[id
+ 1]);
1873 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1874 if (cfop
->flags
& CF_ALU
) {
1875 if (cf
->eg_alu_extended
) {
1876 fprintf(stderr
, "%04d %08X %08X %s\n", id
, bc
->bytecode
[id
],
1877 bc
->bytecode
[id
+ 1], "ALU_EXT");
1880 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
1881 bc
->bytecode
[id
+ 1], cfop
->name
);
1882 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 2, cf
->addr
);
1883 for (i
= 0; i
< 4; ++i
) {
1884 if (cf
->kcache
[i
].mode
) {
1885 int c_start
= (cf
->kcache
[i
].addr
<< 4);
1886 int c_end
= c_start
+ (cf
->kcache
[i
].mode
<< 4);
1887 fprintf(stderr
, "KC%d[CB%d:%d-%d] ",
1888 i
, cf
->kcache
[i
].bank
, c_start
, c_end
);
1891 fprintf(stderr
, "\n");
1892 } else if (cfop
->flags
& CF_FETCH
) {
1893 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
1894 bc
->bytecode
[id
+ 1], cfop
->name
);
1895 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 4, cf
->addr
);
1896 fprintf(stderr
, "\n");
1897 } else if (cfop
->flags
& CF_EXP
) {
1899 const char *exp_type
[] = {"PIXEL", "POS ", "PARAM"};
1900 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
1901 bc
->bytecode
[id
+ 1], cfop
->name
);
1902 o
+= print_indent(o
, 43);
1903 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
1904 if (cf
->output
.burst_count
> 1) {
1905 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
1906 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
1908 o
+= print_indent(o
, 55);
1909 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
1910 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
1912 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
1913 o
+= print_indent(o
, 55);
1914 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
1917 o
+= print_swizzle(cf
->output
.swizzle_x
);
1918 o
+= print_swizzle(cf
->output
.swizzle_y
);
1919 o
+= print_swizzle(cf
->output
.swizzle_z
);
1920 o
+= print_swizzle(cf
->output
.swizzle_w
);
1922 print_indent(o
, 67);
1924 fprintf(stderr
, " ES:%X ", cf
->output
.elem_size
);
1925 if (!cf
->output
.barrier
)
1926 fprintf(stderr
, "NO_BARRIER ");
1927 if (cf
->output
.end_of_program
)
1928 fprintf(stderr
, "EOP ");
1929 fprintf(stderr
, "\n");
1930 } else if (r600_isa_cf(cf
->op
)->flags
& CF_STRM
) {
1932 const char *exp_type
[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
1934 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
,
1935 bc
->bytecode
[id
], bc
->bytecode
[id
+ 1], cfop
->name
);
1936 o
+= print_indent(o
, 43);
1937 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
1938 if (cf
->output
.burst_count
> 1) {
1939 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
1940 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
1941 o
+= print_indent(o
, 55);
1942 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
1943 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
1945 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
1946 o
+= print_indent(o
, 55);
1947 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
1949 for (i
= 0; i
< 4; ++i
) {
1950 if (cf
->output
.comp_mask
& (1 << i
))
1951 o
+= print_swizzle(i
);
1953 o
+= print_swizzle(7);
1956 o
+= print_indent(o
, 67);
1958 fprintf(stderr
, " ES:%i ", cf
->output
.elem_size
);
1959 if (cf
->output
.array_size
!= 0xFFF)
1960 fprintf(stderr
, "AS:%i ", cf
->output
.array_size
);
1961 if (!cf
->output
.barrier
)
1962 fprintf(stderr
, "NO_BARRIER ");
1963 if (cf
->output
.end_of_program
)
1964 fprintf(stderr
, "EOP ");
1965 fprintf(stderr
, "\n");
1967 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
1968 bc
->bytecode
[id
+ 1], cfop
->name
);
1969 fprintf(stderr
, "@%d ", cf
->cf_addr
);
1971 fprintf(stderr
, "CND:%X ", cf
->cond
);
1973 fprintf(stderr
, "POP:%X ", cf
->pop_count
);
1974 fprintf(stderr
, "\n");
1981 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1982 const char *omod_str
[] = {"","*2","*4","/2"};
1983 const struct alu_op_info
*aop
= r600_isa_alu(alu
->op
);
1986 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
1987 o
+= fprintf(stderr
, " %04d %08X %08X ", id
, bc
->bytecode
[id
], bc
->bytecode
[id
+1]);
1989 o
+= fprintf(stderr
, "%4d ", ++ngr
);
1991 o
+= fprintf(stderr
, " ");
1992 o
+= fprintf(stderr
, "%c%c %c ", alu
->execute_mask
? 'M':' ',
1993 alu
->update_pred
? 'P':' ',
1994 alu
->pred_sel
? alu
->pred_sel
==2 ? '0':'1':' ');
1996 o
+= fprintf(stderr
, "%s%s%s ", aop
->name
,
1997 omod_str
[alu
->omod
], alu
->dst
.clamp
? "_sat":"");
1999 o
+= print_indent(o
,60);
2000 o
+= print_dst(alu
);
2001 for (i
= 0; i
< aop
->src_count
; ++i
) {
2002 o
+= fprintf(stderr
, i
== 0 ? ", ": ", ");
2003 o
+= print_src(alu
, i
);
2006 if (alu
->bank_swizzle
) {
2007 o
+= print_indent(o
,75);
2008 o
+= fprintf(stderr
, " BS:%d", alu
->bank_swizzle
);
2011 fprintf(stderr
, "\n");
2015 for (i
= 0; i
< nliteral
; i
++, id
++) {
2016 float *f
= (float*)(bc
->bytecode
+ id
);
2017 o
= fprintf(stderr
, " %04d %08X", id
, bc
->bytecode
[id
]);
2018 print_indent(o
, 60);
2019 fprintf(stderr
, " %f (%d)\n", *f
, *(bc
->bytecode
+ id
));
2027 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2029 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2030 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2032 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(tex
->op
)->name
);
2034 o
+= print_indent(o
, 50);
2036 o
+= fprintf(stderr
, "R%d.", tex
->dst_gpr
);
2037 o
+= print_swizzle(tex
->dst_sel_x
);
2038 o
+= print_swizzle(tex
->dst_sel_y
);
2039 o
+= print_swizzle(tex
->dst_sel_z
);
2040 o
+= print_swizzle(tex
->dst_sel_w
);
2042 o
+= fprintf(stderr
, ", R%d.", tex
->src_gpr
);
2043 o
+= print_swizzle(tex
->src_sel_x
);
2044 o
+= print_swizzle(tex
->src_sel_y
);
2045 o
+= print_swizzle(tex
->src_sel_z
);
2046 o
+= print_swizzle(tex
->src_sel_w
);
2048 o
+= fprintf(stderr
, ", RID:%d", tex
->resource_id
);
2049 o
+= fprintf(stderr
, ", SID:%d ", tex
->sampler_id
);
2052 fprintf(stderr
, "LB:%d ", tex
->lod_bias
);
2054 fprintf(stderr
, "CT:%c%c%c%c ",
2055 tex
->coord_type_x
? 'N' : 'U',
2056 tex
->coord_type_y
? 'N' : 'U',
2057 tex
->coord_type_z
? 'N' : 'U',
2058 tex
->coord_type_w
? 'N' : 'U');
2061 fprintf(stderr
, "OX:%d ", tex
->offset_x
);
2063 fprintf(stderr
, "OY:%d ", tex
->offset_y
);
2065 fprintf(stderr
, "OZ:%d ", tex
->offset_z
);
2068 fprintf(stderr
, "\n");
2071 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2073 const char * fetch_type
[] = {"VERTEX", "INSTANCE", ""};
2074 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2075 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2077 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(vtx
->op
)->name
);
2079 o
+= print_indent(o
, 50);
2081 o
+= fprintf(stderr
, "R%d.", vtx
->dst_gpr
);
2082 o
+= print_swizzle(vtx
->dst_sel_x
);
2083 o
+= print_swizzle(vtx
->dst_sel_y
);
2084 o
+= print_swizzle(vtx
->dst_sel_z
);
2085 o
+= print_swizzle(vtx
->dst_sel_w
);
2087 o
+= fprintf(stderr
, ", R%d.", vtx
->src_gpr
);
2088 o
+= print_swizzle(vtx
->src_sel_x
);
2091 fprintf(stderr
, " +%db", vtx
->offset
);
2093 o
+= print_indent(o
, 55);
2095 fprintf(stderr
, ", RID:%d ", vtx
->buffer_id
);
2097 fprintf(stderr
, "%s ", fetch_type
[vtx
->fetch_type
]);
2099 if (bc
->chip_class
< CAYMAN
&& vtx
->mega_fetch_count
)
2100 fprintf(stderr
, "MFC:%d ", vtx
->mega_fetch_count
);
2102 fprintf(stderr
, "UCF:%d ", vtx
->use_const_fields
);
2103 fprintf(stderr
, "FMT(DTA:%d ", vtx
->data_format
);
2104 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2105 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2106 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2112 fprintf(stderr
, "--------------------------------------\n");
2115 void r600_vertex_data_type(enum pipe_format pformat
,
2117 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2119 const struct util_format_description
*desc
;
2125 *endian
= ENDIAN_NONE
;
2127 desc
= util_format_description(pformat
);
2128 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2132 /* Find the first non-VOID channel. */
2133 for (i
= 0; i
< 4; i
++) {
2134 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2139 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2141 switch (desc
->channel
[i
].type
) {
2142 /* Half-floats, floats, ints */
2143 case UTIL_FORMAT_TYPE_FLOAT
:
2144 switch (desc
->channel
[i
].size
) {
2146 switch (desc
->nr_channels
) {
2148 *format
= FMT_16_FLOAT
;
2151 *format
= FMT_16_16_FLOAT
;
2155 *format
= FMT_16_16_16_16_FLOAT
;
2160 switch (desc
->nr_channels
) {
2162 *format
= FMT_32_FLOAT
;
2165 *format
= FMT_32_32_FLOAT
;
2168 *format
= FMT_32_32_32_FLOAT
;
2171 *format
= FMT_32_32_32_32_FLOAT
;
2180 case UTIL_FORMAT_TYPE_UNSIGNED
:
2182 case UTIL_FORMAT_TYPE_SIGNED
:
2183 switch (desc
->channel
[i
].size
) {
2185 switch (desc
->nr_channels
) {
2194 *format
= FMT_8_8_8_8
;
2199 if (desc
->nr_channels
!= 4)
2202 *format
= FMT_2_10_10_10
;
2205 switch (desc
->nr_channels
) {
2210 *format
= FMT_16_16
;
2214 *format
= FMT_16_16_16_16
;
2219 switch (desc
->nr_channels
) {
2224 *format
= FMT_32_32
;
2227 *format
= FMT_32_32_32
;
2230 *format
= FMT_32_32_32_32
;
2242 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2247 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2248 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2249 if (!desc
->channel
[i
].normalized
) {
2250 if (desc
->channel
[i
].pure_integer
)
2258 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2261 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2263 const struct pipe_vertex_element
*elements
)
2265 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2266 struct r600_bytecode bc
;
2267 struct r600_bytecode_vtx vtx
;
2268 const struct util_format_description
*desc
;
2269 unsigned fetch_resource_start
= rctx
->chip_class
>= EVERGREEN
? 0 : 160;
2270 unsigned format
, num_format
, format_comp
, endian
;
2272 int i
, j
, r
, fs_size
;
2273 struct r600_fetch_shader
*shader
;
2277 memset(&bc
, 0, sizeof(bc
));
2278 r600_bytecode_init(&bc
, rctx
->chip_class
, rctx
->family
,
2279 rctx
->screen
->msaa_texture_support
);
2283 for (i
= 0; i
< count
; i
++) {
2284 if (elements
[i
].instance_divisor
> 1) {
2285 if (rctx
->chip_class
== CAYMAN
) {
2286 for (j
= 0; j
< 4; j
++) {
2287 struct r600_bytecode_alu alu
;
2288 memset(&alu
, 0, sizeof(alu
));
2289 alu
.op
= ALU_OP2_MULHI_UINT
;
2291 alu
.src
[0].chan
= 3;
2292 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2293 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2294 alu
.dst
.sel
= i
+ 1;
2296 alu
.dst
.write
= j
== 3;
2298 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2299 r600_bytecode_clear(&bc
);
2304 struct r600_bytecode_alu alu
;
2305 memset(&alu
, 0, sizeof(alu
));
2306 alu
.op
= ALU_OP2_MULHI_UINT
;
2308 alu
.src
[0].chan
= 3;
2309 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2310 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2311 alu
.dst
.sel
= i
+ 1;
2315 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2316 r600_bytecode_clear(&bc
);
2323 for (i
= 0; i
< count
; i
++) {
2324 r600_vertex_data_type(elements
[i
].src_format
,
2325 &format
, &num_format
, &format_comp
, &endian
);
2327 desc
= util_format_description(elements
[i
].src_format
);
2329 r600_bytecode_clear(&bc
);
2330 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2334 if (elements
[i
].src_offset
> 65535) {
2335 r600_bytecode_clear(&bc
);
2336 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2340 memset(&vtx
, 0, sizeof(vtx
));
2341 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2342 vtx
.fetch_type
= elements
[i
].instance_divisor
? 1 : 0;
2343 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2344 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2345 vtx
.mega_fetch_count
= 0x1F;
2346 vtx
.dst_gpr
= i
+ 1;
2347 vtx
.dst_sel_x
= desc
->swizzle
[0];
2348 vtx
.dst_sel_y
= desc
->swizzle
[1];
2349 vtx
.dst_sel_z
= desc
->swizzle
[2];
2350 vtx
.dst_sel_w
= desc
->swizzle
[3];
2351 vtx
.data_format
= format
;
2352 vtx
.num_format_all
= num_format
;
2353 vtx
.format_comp_all
= format_comp
;
2354 vtx
.srf_mode_all
= 1;
2355 vtx
.offset
= elements
[i
].src_offset
;
2356 vtx
.endian
= endian
;
2358 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2359 r600_bytecode_clear(&bc
);
2364 r600_bytecode_add_cfinst(&bc
, CF_OP_RET
);
2366 if ((r
= r600_bytecode_build(&bc
))) {
2367 r600_bytecode_clear(&bc
);
2371 if (rctx
->screen
->debug_flags
& DBG_FS
) {
2372 fprintf(stderr
, "--------------------------------------------------------------\n");
2373 fprintf(stderr
, "Vertex elements state:\n");
2374 for (i
= 0; i
< count
; i
++) {
2375 fprintf(stderr
, " ");
2376 util_dump_vertex_element(stderr
, elements
+i
);
2377 fprintf(stderr
, "\n");
2380 r600_bytecode_disasm(&bc
);
2381 fprintf(stderr
, "______________________________________________________________\n");
2386 /* Allocate the CSO. */
2387 shader
= CALLOC_STRUCT(r600_fetch_shader
);
2389 r600_bytecode_clear(&bc
);
2393 u_suballocator_alloc(rctx
->allocator_fetch_shader
, fs_size
, &shader
->offset
,
2394 (struct pipe_resource
**)&shader
->buffer
);
2395 if (!shader
->buffer
) {
2396 r600_bytecode_clear(&bc
);
2401 bytecode
= r600_buffer_mmap_sync_with_rings(rctx
, shader
->buffer
, PIPE_TRANSFER_WRITE
| PIPE_TRANSFER_UNSYNCHRONIZED
);
2402 bytecode
+= shader
->offset
/ 4;
2404 if (R600_BIG_ENDIAN
) {
2405 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2406 bytecode
[i
] = bswap_32(bc
.bytecode
[i
]);
2409 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2411 rctx
->ws
->buffer_unmap(shader
->buffer
->cs_buf
);
2413 r600_bytecode_clear(&bc
);
2417 void r600_bytecode_alu_read(struct r600_bytecode
*bc
,
2418 struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2421 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2422 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2423 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2424 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2425 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2426 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2427 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2428 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2429 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2430 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2431 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2434 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2435 if (alu
->bank_swizzle
)
2436 alu
->bank_swizzle_force
= alu
->bank_swizzle
;
2437 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2438 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2439 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2440 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2441 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2444 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2445 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2446 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2447 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2448 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2449 G_SQ_ALU_WORD1_OP3_ALU_INST(word1
), /* is_op3 = */ 1);
2452 else /*ALU_DWORD1_OP2*/
2454 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2455 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2456 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2457 G_SQ_ALU_WORD1_OP2_ALU_INST(word1
), /* is_op3 = */ 0);
2458 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2459 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2460 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2462 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);
2466 void r600_bytecode_export_read(struct r600_bytecode
*bc
,
2467 struct r600_bytecode_output
*output
, uint32_t word0
, uint32_t word1
)
2469 output
->array_base
= G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0
);
2470 output
->type
= G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0
);
2471 output
->gpr
= G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0
);
2472 output
->elem_size
= G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0
);
2474 output
->swizzle_x
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1
);
2475 output
->swizzle_y
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1
);
2476 output
->swizzle_z
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1
);
2477 output
->swizzle_w
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1
);
2478 output
->burst_count
= G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1
);
2479 output
->end_of_program
= G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1
);
2480 output
->op
= r600_isa_cf_by_opcode(bc
->isa
,
2481 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1
), 0);
2482 output
->barrier
= G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1
);
2483 output
->array_size
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1
);
2484 output
->comp_mask
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1
);