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[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600d.h"
27
28 #include <errno.h>
29 #include <byteswap.h>
30 #include "util/u_memory.h"
31 #include "pipe/p_shader_tokens.h"
32
33 #define NUM_OF_CYCLES 3
34 #define NUM_OF_COMPONENTS 4
35
36 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
37 {
38 if(alu->is_op3)
39 return 3;
40
41 switch (bc->chip_class) {
42 case R600:
43 case R700:
44 switch (alu->inst) {
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
46 return 0;
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
90 return 2;
91
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
93 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
117 return 1;
118 default: R600_ERR(
119 "Need instruction operand number for 0x%x.\n", alu->inst);
120 }
121 break;
122 case EVERGREEN:
123 case CAYMAN:
124 switch (alu->inst) {
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
126 return 0;
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
173 return 2;
174
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
198 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
199 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
200 return 1;
201 default: R600_ERR(
202 "Need instruction operand number for 0x%x.\n", alu->inst);
203 }
204 break;
205 }
206
207 return 3;
208 }
209
210 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
211
212 static struct r600_bytecode_cf *r600_bytecode_cf(void)
213 {
214 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
215
216 if (cf == NULL)
217 return NULL;
218 LIST_INITHEAD(&cf->list);
219 LIST_INITHEAD(&cf->alu);
220 LIST_INITHEAD(&cf->vtx);
221 LIST_INITHEAD(&cf->tex);
222 return cf;
223 }
224
225 static struct r600_bytecode_alu *r600_bytecode_alu(void)
226 {
227 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
228
229 if (alu == NULL)
230 return NULL;
231 LIST_INITHEAD(&alu->list);
232 return alu;
233 }
234
235 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
236 {
237 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
238
239 if (vtx == NULL)
240 return NULL;
241 LIST_INITHEAD(&vtx->list);
242 return vtx;
243 }
244
245 static struct r600_bytecode_tex *r600_bytecode_tex(void)
246 {
247 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
248
249 if (tex == NULL)
250 return NULL;
251 LIST_INITHEAD(&tex->list);
252 return tex;
253 }
254
255 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
256 {
257 if ((chip_class == R600) && (family != CHIP_RV670))
258 bc->ar_handling = AR_HANDLE_RV6XX;
259 else
260 bc->ar_handling = AR_HANDLE_NORMAL;
261
262 if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
263 family != CHIP_RS880))
264 bc->r6xx_nop_after_rel_dst = 1;
265 else
266 bc->r6xx_nop_after_rel_dst = 0;
267 LIST_INITHEAD(&bc->cf);
268 bc->chip_class = chip_class;
269 }
270
271 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
272 {
273 struct r600_bytecode_cf *cf = r600_bytecode_cf();
274
275 if (cf == NULL)
276 return -ENOMEM;
277 LIST_ADDTAIL(&cf->list, &bc->cf);
278 if (bc->cf_last) {
279 cf->id = bc->cf_last->id + 2;
280 if (bc->cf_last->eg_alu_extended) {
281 /* take into account extended alu size */
282 cf->id += 2;
283 bc->ndw += 2;
284 }
285 }
286 bc->cf_last = cf;
287 bc->ncf++;
288 bc->ndw += 2;
289 bc->force_add_cf = 0;
290 bc->ar_loaded = 0;
291 return 0;
292 }
293
294 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
295 {
296 int r;
297
298 if (output->gpr >= bc->ngpr)
299 bc->ngpr = output->gpr + 1;
300
301 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
302 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
303 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
304 output->type == bc->cf_last->output.type &&
305 output->elem_size == bc->cf_last->output.elem_size &&
306 output->swizzle_x == bc->cf_last->output.swizzle_x &&
307 output->swizzle_y == bc->cf_last->output.swizzle_y &&
308 output->swizzle_z == bc->cf_last->output.swizzle_z &&
309 output->swizzle_w == bc->cf_last->output.swizzle_w &&
310 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
311
312 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
313 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
314
315 bc->cf_last->output.end_of_program |= output->end_of_program;
316 bc->cf_last->output.inst = output->inst;
317 bc->cf_last->output.gpr = output->gpr;
318 bc->cf_last->output.array_base = output->array_base;
319 bc->cf_last->output.burst_count += output->burst_count;
320 return 0;
321
322 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
323 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
324
325 bc->cf_last->output.end_of_program |= output->end_of_program;
326 bc->cf_last->output.inst = output->inst;
327 bc->cf_last->output.burst_count += output->burst_count;
328 return 0;
329 }
330 }
331
332 r = r600_bytecode_add_cf(bc);
333 if (r)
334 return r;
335 bc->cf_last->inst = output->inst;
336 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
337 return 0;
338 }
339
340 /* alu instructions that can ony exits once per group */
341 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
342 {
343 switch (bc->chip_class) {
344 case R600:
345 case R700:
346 return !alu->is_op3 && (
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
348 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
377 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
378 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
379 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
380 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
381 case EVERGREEN:
382 case CAYMAN:
383 default:
384 return !alu->is_op3 && (
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
415 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
416 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
417 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
418 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
419 }
420 }
421
422 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
423 {
424 switch (bc->chip_class) {
425 case R600:
426 case R700:
427 return !alu->is_op3 && (
428 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
429 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
430 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
431 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
432 case EVERGREEN:
433 case CAYMAN:
434 default:
435 return !alu->is_op3 && (
436 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
437 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
438 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
439 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
440 }
441 }
442
443 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
444 {
445 switch (bc->chip_class) {
446 case R600:
447 case R700:
448 return !alu->is_op3 &&
449 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
450 case EVERGREEN:
451 case CAYMAN:
452 default:
453 return !alu->is_op3 &&
454 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
455 }
456 }
457
458 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
459 {
460 switch (bc->chip_class) {
461 case R600:
462 case R700:
463 return !alu->is_op3 && (
464 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
465 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
466 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
467 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
468 case EVERGREEN:
469 case CAYMAN:
470 default:
471 return !alu->is_op3 && (
472 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
473 }
474 }
475
476 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
477 {
478 return min <= opcode && opcode <= max;
479 }
480
481 /* ALU instructions that can only execute on the vector unit:
482 *
483 * opcode ranges:
484 * R6xx/R7xx:
485 * op3 : [0x08 - 0x0B]
486 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
487 *
488 * EVERGREEN:
489 * op3: [0x04 - 0x11]
490 * op2: [0xA0 - 0xE2]
491 */
492 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
493 {
494 switch (bc->chip_class) {
495 case R600:
496 case R700:
497 if (alu->is_op3)
498 return is_opcode_in_range(alu->inst,
499 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
500 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
501 else
502 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
503 is_opcode_in_range(alu->inst,
504 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
505 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
506 is_opcode_in_range(alu->inst,
507 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
508 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
509 is_opcode_in_range(alu->inst,
510 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
511 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
512 is_opcode_in_range(alu->inst,
513 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
514 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
515
516 case EVERGREEN:
517 if (alu->is_op3)
518 return is_opcode_in_range(alu->inst,
519 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
520 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
521 else
522 return is_opcode_in_range(alu->inst,
523 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
524 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
525 case CAYMAN:
526 default:
527 assert(0);
528 return 0;
529 }
530 }
531
532 /* ALU instructions that can only execute on the trans unit:
533 *
534 * opcode ranges:
535 * R600:
536 * op3: 0x0C
537 * op2: [0x60 - 0x79]
538 *
539 * R700:
540 * op3: 0x0C
541 * op2: [0x60 - 0x6F], [0x73 - 0x79]
542 *
543 * EVERGREEN:
544 * op3: 0x1F
545 * op2: [0x81 - 0x9C]
546 */
547 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
548 {
549
550 switch (bc->chip_class) {
551 case R600:
552 if (alu->is_op3)
553 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
554 else
555 return is_opcode_in_range(alu->inst,
556 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
557 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
558 case R700:
559 if (alu->is_op3)
560 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
561 else
562 return is_opcode_in_range(alu->inst,
563 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
564 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
565 is_opcode_in_range(alu->inst,
566 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
567 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
568 case EVERGREEN:
569 if (alu->is_op3)
570 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
571 else
572 return is_opcode_in_range(alu->inst,
573 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
574 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
575 case CAYMAN:
576 default:
577 assert(0);
578 return 0;
579 }
580 }
581
582 /* alu instructions that can execute on any unit */
583 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
584 {
585 return !is_alu_vec_unit_inst(bc, alu) &&
586 !is_alu_trans_unit_inst(bc, alu);
587 }
588
589 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
590 {
591 switch (bc->chip_class) {
592 case R600:
593 case R700:
594 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
595 case EVERGREEN:
596 case CAYMAN:
597 default:
598 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
599 }
600 }
601
602 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
603 struct r600_bytecode_alu *assignment[5])
604 {
605 struct r600_bytecode_alu *alu;
606 unsigned i, chan, trans;
607 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
608
609 for (i = 0; i < max_slots; i++)
610 assignment[i] = NULL;
611
612 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
613 chan = alu->dst.chan;
614 if (max_slots == 4)
615 trans = 0;
616 else if (is_alu_trans_unit_inst(bc, alu))
617 trans = 1;
618 else if (is_alu_vec_unit_inst(bc, alu))
619 trans = 0;
620 else if (assignment[chan])
621 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
622 else
623 trans = 0;
624
625 if (trans) {
626 if (assignment[4]) {
627 assert(0); /* ALU.Trans has already been allocated. */
628 return -1;
629 }
630 assignment[4] = alu;
631 } else {
632 if (assignment[chan]) {
633 assert(0); /* ALU.chan has already been allocated. */
634 return -1;
635 }
636 assignment[chan] = alu;
637 }
638
639 if (alu->last)
640 break;
641 }
642 return 0;
643 }
644
645 struct alu_bank_swizzle {
646 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
647 int hw_cfile_addr[4];
648 int hw_cfile_elem[4];
649 };
650
651 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
652 [SQ_ALU_VEC_012] = { 0, 1, 2 },
653 [SQ_ALU_VEC_021] = { 0, 2, 1 },
654 [SQ_ALU_VEC_120] = { 1, 2, 0 },
655 [SQ_ALU_VEC_102] = { 1, 0, 2 },
656 [SQ_ALU_VEC_201] = { 2, 0, 1 },
657 [SQ_ALU_VEC_210] = { 2, 1, 0 }
658 };
659
660 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
661 [SQ_ALU_SCL_210] = { 2, 1, 0 },
662 [SQ_ALU_SCL_122] = { 1, 2, 2 },
663 [SQ_ALU_SCL_212] = { 2, 1, 2 },
664 [SQ_ALU_SCL_221] = { 2, 2, 1 }
665 };
666
667 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
668 {
669 int i, cycle, component;
670 /* set up gpr use */
671 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
672 for (component = 0; component < NUM_OF_COMPONENTS; component++)
673 bs->hw_gpr[cycle][component] = -1;
674 for (i = 0; i < 4; i++)
675 bs->hw_cfile_addr[i] = -1;
676 for (i = 0; i < 4; i++)
677 bs->hw_cfile_elem[i] = -1;
678 }
679
680 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
681 {
682 if (bs->hw_gpr[cycle][chan] == -1)
683 bs->hw_gpr[cycle][chan] = sel;
684 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
685 /* Another scalar operation has already used the GPR read port for the channel. */
686 return -1;
687 }
688 return 0;
689 }
690
691 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
692 {
693 int res, num_res = 4;
694 if (bc->chip_class >= R700) {
695 num_res = 2;
696 chan /= 2;
697 }
698 for (res = 0; res < num_res; ++res) {
699 if (bs->hw_cfile_addr[res] == -1) {
700 bs->hw_cfile_addr[res] = sel;
701 bs->hw_cfile_elem[res] = chan;
702 return 0;
703 } else if (bs->hw_cfile_addr[res] == sel &&
704 bs->hw_cfile_elem[res] == chan)
705 return 0; /* Read for this scalar element already reserved, nothing to do here. */
706 }
707 /* All cfile read ports are used, cannot reference vector element. */
708 return -1;
709 }
710
711 static int is_gpr(unsigned sel)
712 {
713 return (sel >= 0 && sel <= 127);
714 }
715
716 /* CB constants start at 512, and get translated to a kcache index when ALU
717 * clauses are constructed. Note that we handle kcache constants the same way
718 * as (the now gone) cfile constants, is that really required? */
719 static int is_cfile(unsigned sel)
720 {
721 return (sel > 255 && sel < 512) ||
722 (sel > 511 && sel < 4607) || /* Kcache before translation. */
723 (sel > 127 && sel < 192); /* Kcache after translation. */
724 }
725
726 static int is_const(int sel)
727 {
728 return is_cfile(sel) ||
729 (sel >= V_SQ_ALU_SRC_0 &&
730 sel <= V_SQ_ALU_SRC_LITERAL);
731 }
732
733 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
734 struct alu_bank_swizzle *bs, int bank_swizzle)
735 {
736 int r, src, num_src, sel, elem, cycle;
737
738 num_src = r600_bytecode_get_num_operands(bc, alu);
739 for (src = 0; src < num_src; src++) {
740 sel = alu->src[src].sel;
741 elem = alu->src[src].chan;
742 if (is_gpr(sel)) {
743 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
744 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
745 /* Nothing to do; special-case optimization,
746 * second source uses first source’s reservation. */
747 continue;
748 else {
749 r = reserve_gpr(bs, sel, elem, cycle);
750 if (r)
751 return r;
752 }
753 } else if (is_cfile(sel)) {
754 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
755 if (r)
756 return r;
757 }
758 /* No restrictions on PV, PS, literal or special constants. */
759 }
760 return 0;
761 }
762
763 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
764 struct alu_bank_swizzle *bs, int bank_swizzle)
765 {
766 int r, src, num_src, const_count, sel, elem, cycle;
767
768 num_src = r600_bytecode_get_num_operands(bc, alu);
769 for (const_count = 0, src = 0; src < num_src; ++src) {
770 sel = alu->src[src].sel;
771 elem = alu->src[src].chan;
772 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
773 if (const_count >= 2)
774 /* More than two references to a constant in
775 * transcendental operation. */
776 return -1;
777 else
778 const_count++;
779 }
780 if (is_cfile(sel)) {
781 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
782 if (r)
783 return r;
784 }
785 }
786 for (src = 0; src < num_src; ++src) {
787 sel = alu->src[src].sel;
788 elem = alu->src[src].chan;
789 if (is_gpr(sel)) {
790 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
791 if (cycle < const_count)
792 /* Cycle for GPR load conflicts with
793 * constant load in transcendental operation. */
794 return -1;
795 r = reserve_gpr(bs, sel, elem, cycle);
796 if (r)
797 return r;
798 }
799 /* PV PS restrictions */
800 if (const_count && (sel == 254 || sel == 255)) {
801 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
802 if (cycle < const_count)
803 return -1;
804 }
805 }
806 return 0;
807 }
808
809 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
810 struct r600_bytecode_alu *slots[5])
811 {
812 struct alu_bank_swizzle bs;
813 int bank_swizzle[5];
814 int i, r = 0, forced = 1;
815 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
816 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
817
818 for (i = 0; i < max_slots; i++) {
819 if (slots[i]) {
820 if (slots[i]->bank_swizzle_force) {
821 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
822 } else {
823 forced = 0;
824 }
825 }
826
827 if (i < 4 && slots[i])
828 scalar_only = false;
829 }
830 if (forced)
831 return 0;
832
833 /* Just check every possible combination of bank swizzle.
834 * Not very efficent, but works on the first try in most of the cases. */
835 for (i = 0; i < 4; i++)
836 if (!slots[i] || !slots[i]->bank_swizzle_force)
837 bank_swizzle[i] = SQ_ALU_VEC_012;
838 else
839 bank_swizzle[i] = slots[i]->bank_swizzle;
840
841 bank_swizzle[4] = SQ_ALU_SCL_210;
842 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
843
844 if (max_slots == 4) {
845 for (i = 0; i < max_slots; i++) {
846 if (bank_swizzle[i] == SQ_ALU_VEC_210)
847 return -1;
848 }
849 }
850 init_bank_swizzle(&bs);
851 if (scalar_only == false) {
852 for (i = 0; i < 4; i++) {
853 if (slots[i]) {
854 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
855 if (r)
856 break;
857 }
858 }
859 } else
860 r = 0;
861
862 if (!r && slots[4] && max_slots == 5) {
863 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
864 }
865 if (!r) {
866 for (i = 0; i < max_slots; i++) {
867 if (slots[i])
868 slots[i]->bank_swizzle = bank_swizzle[i];
869 }
870 return 0;
871 }
872
873 if (scalar_only) {
874 bank_swizzle[4]++;
875 } else {
876 for (i = 0; i < max_slots; i++) {
877 if (!slots[i] || !slots[i]->bank_swizzle_force) {
878 bank_swizzle[i]++;
879 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
880 break;
881 else
882 bank_swizzle[i] = SQ_ALU_VEC_012;
883 }
884 }
885 }
886 }
887
888 /* Couldn't find a working swizzle. */
889 return -1;
890 }
891
892 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
893 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
894 {
895 struct r600_bytecode_alu *prev[5];
896 int gpr[5], chan[5];
897 int i, j, r, src, num_src;
898 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
899
900 r = assign_alu_units(bc, alu_prev, prev);
901 if (r)
902 return r;
903
904 for (i = 0; i < max_slots; ++i) {
905 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
906 gpr[i] = prev[i]->dst.sel;
907 /* cube writes more than PV.X */
908 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
909 chan[i] = 0;
910 else
911 chan[i] = prev[i]->dst.chan;
912 } else
913 gpr[i] = -1;
914 }
915
916 for (i = 0; i < max_slots; ++i) {
917 struct r600_bytecode_alu *alu = slots[i];
918 if(!alu)
919 continue;
920
921 num_src = r600_bytecode_get_num_operands(bc, alu);
922 for (src = 0; src < num_src; ++src) {
923 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
924 continue;
925
926 if (bc->chip_class < CAYMAN) {
927 if (alu->src[src].sel == gpr[4] &&
928 alu->src[src].chan == chan[4]) {
929 alu->src[src].sel = V_SQ_ALU_SRC_PS;
930 alu->src[src].chan = 0;
931 continue;
932 }
933 }
934
935 for (j = 0; j < 4; ++j) {
936 if (alu->src[src].sel == gpr[j] &&
937 alu->src[src].chan == j) {
938 alu->src[src].sel = V_SQ_ALU_SRC_PV;
939 alu->src[src].chan = chan[j];
940 break;
941 }
942 }
943 }
944 }
945
946 return 0;
947 }
948
949 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
950 {
951 switch(value) {
952 case 0:
953 *sel = V_SQ_ALU_SRC_0;
954 break;
955 case 1:
956 *sel = V_SQ_ALU_SRC_1_INT;
957 break;
958 case -1:
959 *sel = V_SQ_ALU_SRC_M_1_INT;
960 break;
961 case 0x3F800000: /* 1.0f */
962 *sel = V_SQ_ALU_SRC_1;
963 break;
964 case 0x3F000000: /* 0.5f */
965 *sel = V_SQ_ALU_SRC_0_5;
966 break;
967 case 0xBF800000: /* -1.0f */
968 *sel = V_SQ_ALU_SRC_1;
969 *neg ^= 1;
970 break;
971 case 0xBF000000: /* -0.5f */
972 *sel = V_SQ_ALU_SRC_0_5;
973 *neg ^= 1;
974 break;
975 default:
976 *sel = V_SQ_ALU_SRC_LITERAL;
977 break;
978 }
979 }
980
981 /* compute how many literal are needed */
982 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
983 uint32_t literal[4], unsigned *nliteral)
984 {
985 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
986 unsigned i, j;
987
988 for (i = 0; i < num_src; ++i) {
989 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
990 uint32_t value = alu->src[i].value;
991 unsigned found = 0;
992 for (j = 0; j < *nliteral; ++j) {
993 if (literal[j] == value) {
994 found = 1;
995 break;
996 }
997 }
998 if (!found) {
999 if (*nliteral >= 4)
1000 return -EINVAL;
1001 literal[(*nliteral)++] = value;
1002 }
1003 }
1004 }
1005 return 0;
1006 }
1007
1008 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1009 struct r600_bytecode_alu *alu,
1010 uint32_t literal[4], unsigned nliteral)
1011 {
1012 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1013 unsigned i, j;
1014
1015 for (i = 0; i < num_src; ++i) {
1016 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1017 uint32_t value = alu->src[i].value;
1018 for (j = 0; j < nliteral; ++j) {
1019 if (literal[j] == value) {
1020 alu->src[i].chan = j;
1021 break;
1022 }
1023 }
1024 }
1025 }
1026 }
1027
1028 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1029 struct r600_bytecode_alu *alu_prev)
1030 {
1031 struct r600_bytecode_alu *prev[5];
1032 struct r600_bytecode_alu *result[5] = { NULL };
1033
1034 uint32_t literal[4], prev_literal[4];
1035 unsigned nliteral = 0, prev_nliteral = 0;
1036
1037 int i, j, r, src, num_src;
1038 int num_once_inst = 0;
1039 int have_mova = 0, have_rel = 0;
1040 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1041
1042 r = assign_alu_units(bc, alu_prev, prev);
1043 if (r)
1044 return r;
1045
1046 for (i = 0; i < max_slots; ++i) {
1047 struct r600_bytecode_alu *alu;
1048
1049 /* check number of literals */
1050 if (prev[i]) {
1051 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1052 return 0;
1053 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1054 return 0;
1055 if (is_alu_mova_inst(bc, prev[i])) {
1056 if (have_rel)
1057 return 0;
1058 have_mova = 1;
1059 }
1060 num_once_inst += is_alu_once_inst(bc, prev[i]);
1061 }
1062 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1063 return 0;
1064
1065 /* Let's check used slots. */
1066 if (prev[i] && !slots[i]) {
1067 result[i] = prev[i];
1068 continue;
1069 } else if (prev[i] && slots[i]) {
1070 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1071 /* Trans unit is still free try to use it. */
1072 if (is_alu_any_unit_inst(bc, slots[i])) {
1073 result[i] = prev[i];
1074 result[4] = slots[i];
1075 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1076 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1077 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1078 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1079 return 0;
1080
1081 result[i] = slots[i];
1082 result[4] = prev[i];
1083 } else
1084 return 0;
1085 } else
1086 return 0;
1087 } else if(!slots[i]) {
1088 continue;
1089 } else {
1090 if (max_slots == 5 && slots[i] && prev[4] &&
1091 slots[i]->dst.sel == prev[4]->dst.sel &&
1092 slots[i]->dst.chan == prev[4]->dst.chan &&
1093 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1094 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1095 return 0;
1096
1097 result[i] = slots[i];
1098 }
1099
1100 alu = slots[i];
1101 num_once_inst += is_alu_once_inst(bc, alu);
1102
1103 /* don't reschedule NOPs */
1104 if (is_nop_inst(bc, alu))
1105 return 0;
1106
1107 /* Let's check dst gpr. */
1108 if (alu->dst.rel) {
1109 if (have_mova)
1110 return 0;
1111 have_rel = 1;
1112 }
1113
1114 /* Let's check source gprs */
1115 num_src = r600_bytecode_get_num_operands(bc, alu);
1116 for (src = 0; src < num_src; ++src) {
1117 if (alu->src[src].rel) {
1118 if (have_mova)
1119 return 0;
1120 have_rel = 1;
1121 }
1122
1123 /* Constants don't matter. */
1124 if (!is_gpr(alu->src[src].sel))
1125 continue;
1126
1127 for (j = 0; j < max_slots; ++j) {
1128 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1129 continue;
1130
1131 /* If it's relative then we can't determin which gpr is really used. */
1132 if (prev[j]->dst.chan == alu->src[src].chan &&
1133 (prev[j]->dst.sel == alu->src[src].sel ||
1134 prev[j]->dst.rel || alu->src[src].rel))
1135 return 0;
1136 }
1137 }
1138 }
1139
1140 /* more than one PRED_ or KILL_ ? */
1141 if (num_once_inst > 1)
1142 return 0;
1143
1144 /* check if the result can still be swizzlet */
1145 r = check_and_set_bank_swizzle(bc, result);
1146 if (r)
1147 return 0;
1148
1149 /* looks like everything worked out right, apply the changes */
1150
1151 /* undo adding previus literals */
1152 bc->cf_last->ndw -= align(prev_nliteral, 2);
1153
1154 /* sort instructions */
1155 for (i = 0; i < max_slots; ++i) {
1156 slots[i] = result[i];
1157 if (result[i]) {
1158 LIST_DEL(&result[i]->list);
1159 result[i]->last = 0;
1160 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1161 }
1162 }
1163
1164 /* determine new last instruction */
1165 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1166
1167 /* determine new first instruction */
1168 for (i = 0; i < max_slots; ++i) {
1169 if (result[i]) {
1170 bc->cf_last->curr_bs_head = result[i];
1171 break;
1172 }
1173 }
1174
1175 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1176 bc->cf_last->prev2_bs_head = NULL;
1177
1178 return 0;
1179 }
1180
1181 /* we'll keep kcache sets sorted by bank & addr */
1182 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1183 struct r600_bytecode_kcache *kcache,
1184 unsigned bank, unsigned line)
1185 {
1186 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1187
1188 for (i = 0; i < kcache_banks; i++) {
1189 if (kcache[i].mode) {
1190 int d;
1191
1192 if (kcache[i].bank < bank)
1193 continue;
1194
1195 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1196 kcache[i].bank > bank) {
1197 /* try to insert new line */
1198 if (kcache[kcache_banks-1].mode) {
1199 /* all sets are in use */
1200 return -ENOMEM;
1201 }
1202
1203 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1204 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1205 kcache[i].bank = bank;
1206 kcache[i].addr = line;
1207 return 0;
1208 }
1209
1210 d = line - kcache[i].addr;
1211
1212 if (d == -1) {
1213 kcache[i].addr--;
1214 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1215 /* we are prepending the line to the current set,
1216 * discarding the existing second line,
1217 * so we'll have to insert line+2 after it */
1218 line += 2;
1219 continue;
1220 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1221 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1222 return 0;
1223 } else {
1224 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1225 return -ENOMEM;
1226 }
1227 } else if (d == 1) {
1228 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1229 return 0;
1230 } else if (d == 0)
1231 return 0;
1232 } else { /* free kcache set - use it */
1233 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1234 kcache[i].bank = bank;
1235 kcache[i].addr = line;
1236 return 0;
1237 }
1238 }
1239 return -ENOMEM;
1240 }
1241
1242 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1243 struct r600_bytecode_kcache *kcache,
1244 struct r600_bytecode_alu *alu)
1245 {
1246 int i, r;
1247
1248 for (i = 0; i < 3; i++) {
1249 unsigned bank, line, sel = alu->src[i].sel;
1250
1251 if (sel < 512)
1252 continue;
1253
1254 bank = alu->src[i].kc_bank;
1255 line = (sel-512)>>4;
1256
1257 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1258 return r;
1259 }
1260 return 0;
1261 }
1262
1263 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1264 struct r600_bytecode_alu *alu,
1265 struct r600_bytecode_kcache * kcache)
1266 {
1267 int i, j;
1268
1269 /* Alter the src operands to refer to the kcache. */
1270 for (i = 0; i < 3; ++i) {
1271 static const unsigned int base[] = {128, 160, 256, 288};
1272 unsigned int line, sel = alu->src[i].sel, found = 0;
1273
1274 if (sel < 512)
1275 continue;
1276
1277 sel -= 512;
1278 line = sel>>4;
1279
1280 for (j = 0; j < 4 && !found; ++j) {
1281 switch (kcache[j].mode) {
1282 case V_SQ_CF_KCACHE_NOP:
1283 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1284 R600_ERR("unexpected kcache line mode\n");
1285 return -ENOMEM;
1286 default:
1287 if (kcache[j].bank == alu->src[i].kc_bank &&
1288 kcache[j].addr <= line &&
1289 line < kcache[j].addr + kcache[j].mode) {
1290 alu->src[i].sel = sel - (kcache[j].addr<<4);
1291 alu->src[i].sel += base[j];
1292 found=1;
1293 }
1294 }
1295 }
1296 }
1297 return 0;
1298 }
1299
1300 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1301 {
1302 struct r600_bytecode_kcache kcache_sets[4];
1303 struct r600_bytecode_kcache *kcache = kcache_sets;
1304 int r;
1305
1306 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1307
1308 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1309 /* can't alloc, need to start new clause */
1310 if ((r = r600_bytecode_add_cf(bc))) {
1311 return r;
1312 }
1313 bc->cf_last->inst = type;
1314
1315 /* retry with the new clause */
1316 kcache = bc->cf_last->kcache;
1317 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1318 /* can't alloc again- should never happen */
1319 return r;
1320 }
1321 } else {
1322 /* update kcache sets */
1323 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1324 }
1325
1326 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1327 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1328 if (bc->chip_class < EVERGREEN)
1329 return -ENOMEM;
1330 bc->cf_last->eg_alu_extended = 1;
1331 }
1332
1333 return 0;
1334 }
1335
1336 static int insert_nop_r6xx(struct r600_bytecode *bc)
1337 {
1338 struct r600_bytecode_alu alu;
1339 int r, i;
1340
1341 for (i = 0; i < 4; i++) {
1342 memset(&alu, 0, sizeof(alu));
1343 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1344 alu.src[0].chan = i;
1345 alu.dst.chan = i;
1346 alu.last = (i == 3);
1347 r = r600_bytecode_add_alu(bc, &alu);
1348 if (r)
1349 return r;
1350 }
1351 return 0;
1352 }
1353
1354 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1355 static int load_ar_r6xx(struct r600_bytecode *bc)
1356 {
1357 struct r600_bytecode_alu alu;
1358 int r;
1359
1360 if (bc->ar_loaded)
1361 return 0;
1362
1363 /* hack to avoid making MOVA the last instruction in the clause */
1364 if ((bc->cf_last->ndw>>1) >= 110)
1365 bc->force_add_cf = 1;
1366
1367 memset(&alu, 0, sizeof(alu));
1368 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1369 alu.src[0].sel = bc->ar_reg;
1370 alu.last = 1;
1371 alu.index_mode = INDEX_MODE_LOOP;
1372 r = r600_bytecode_add_alu(bc, &alu);
1373 if (r)
1374 return r;
1375
1376 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1377 bc->ar_loaded = 1;
1378 return 0;
1379 }
1380
1381 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1382 static int load_ar(struct r600_bytecode *bc)
1383 {
1384 struct r600_bytecode_alu alu;
1385 int r;
1386
1387 if (bc->ar_handling)
1388 return load_ar_r6xx(bc);
1389
1390 if (bc->ar_loaded)
1391 return 0;
1392
1393 /* hack to avoid making MOVA the last instruction in the clause */
1394 if ((bc->cf_last->ndw>>1) >= 110)
1395 bc->force_add_cf = 1;
1396
1397 memset(&alu, 0, sizeof(alu));
1398 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1399 alu.src[0].sel = bc->ar_reg;
1400 alu.last = 1;
1401 r = r600_bytecode_add_alu(bc, &alu);
1402 if (r)
1403 return r;
1404
1405 bc->cf_last->r6xx_uses_waterfall = 1;
1406 bc->ar_loaded = 1;
1407 return 0;
1408 }
1409
1410 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1411 {
1412 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1413 struct r600_bytecode_alu *lalu;
1414 int i, r;
1415
1416 if (nalu == NULL)
1417 return -ENOMEM;
1418 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1419
1420 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1421 /* check if we could add it anyway */
1422 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1423 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1424 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1425 if (lalu->predicate) {
1426 bc->force_add_cf = 1;
1427 break;
1428 }
1429 }
1430 } else
1431 bc->force_add_cf = 1;
1432 }
1433
1434 /* cf can contains only alu or only vtx or only tex */
1435 if (bc->cf_last == NULL || bc->force_add_cf) {
1436 r = r600_bytecode_add_cf(bc);
1437 if (r) {
1438 free(nalu);
1439 return r;
1440 }
1441 }
1442 bc->cf_last->inst = type;
1443
1444 /* Check AR usage and load it if required */
1445 for (i = 0; i < 3; i++)
1446 if (nalu->src[i].rel && !bc->ar_loaded)
1447 load_ar(bc);
1448
1449 if (nalu->dst.rel && !bc->ar_loaded)
1450 load_ar(bc);
1451
1452 /* Setup the kcache for this ALU instruction. This will start a new
1453 * ALU clause if needed. */
1454 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1455 free(nalu);
1456 return r;
1457 }
1458
1459 if (!bc->cf_last->curr_bs_head) {
1460 bc->cf_last->curr_bs_head = nalu;
1461 }
1462 /* number of gpr == the last gpr used in any alu */
1463 for (i = 0; i < 3; i++) {
1464 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1465 bc->ngpr = nalu->src[i].sel + 1;
1466 }
1467 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1468 r600_bytecode_special_constants(nalu->src[i].value,
1469 &nalu->src[i].sel, &nalu->src[i].neg);
1470 }
1471 if (nalu->dst.sel >= bc->ngpr) {
1472 bc->ngpr = nalu->dst.sel + 1;
1473 }
1474 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1475 /* each alu use 2 dwords */
1476 bc->cf_last->ndw += 2;
1477 bc->ndw += 2;
1478
1479 /* process cur ALU instructions for bank swizzle */
1480 if (nalu->last) {
1481 uint32_t literal[4];
1482 unsigned nliteral;
1483 struct r600_bytecode_alu *slots[5];
1484 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1485 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1486 if (r)
1487 return r;
1488
1489 if (bc->cf_last->prev_bs_head) {
1490 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1491 if (r)
1492 return r;
1493 }
1494
1495 if (bc->cf_last->prev_bs_head) {
1496 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1497 if (r)
1498 return r;
1499 }
1500
1501 r = check_and_set_bank_swizzle(bc, slots);
1502 if (r)
1503 return r;
1504
1505 for (i = 0, nliteral = 0; i < max_slots; i++) {
1506 if (slots[i]) {
1507 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1508 if (r)
1509 return r;
1510 }
1511 }
1512 bc->cf_last->ndw += align(nliteral, 2);
1513
1514 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1515 * worst case */
1516 if ((bc->cf_last->ndw >> 1) >= 120) {
1517 bc->force_add_cf = 1;
1518 }
1519
1520 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1521 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1522 bc->cf_last->curr_bs_head = NULL;
1523 }
1524
1525 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1526 insert_nop_r6xx(bc);
1527
1528 return 0;
1529 }
1530
1531 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1532 {
1533 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1534 }
1535
1536 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1537 {
1538 switch (bc->chip_class) {
1539 case R600:
1540 return 8;
1541
1542 case R700:
1543 case EVERGREEN:
1544 case CAYMAN:
1545 return 16;
1546
1547 default:
1548 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1549 return 8;
1550 }
1551 }
1552
1553 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1554 {
1555 switch (bc->chip_class) {
1556 case R700:
1557 case R600:
1558 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1559 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1560 case EVERGREEN:
1561 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1562 case CAYMAN:
1563 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1564 default:
1565 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1566 return FALSE;
1567 }
1568 }
1569
1570 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1571 {
1572 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1573 int r;
1574
1575 if (nvtx == NULL)
1576 return -ENOMEM;
1577 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1578
1579 /* cf can contains only alu or only vtx or only tex */
1580 if (bc->cf_last == NULL ||
1581 last_inst_was_not_vtx_fetch(bc) ||
1582 bc->force_add_cf) {
1583 r = r600_bytecode_add_cf(bc);
1584 if (r) {
1585 free(nvtx);
1586 return r;
1587 }
1588 switch (bc->chip_class) {
1589 case R600:
1590 case R700:
1591 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1592 break;
1593 case EVERGREEN:
1594 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1595 break;
1596 case CAYMAN:
1597 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1598 break;
1599 default:
1600 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1601 return -EINVAL;
1602 }
1603 }
1604 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1605 /* each fetch use 4 dwords */
1606 bc->cf_last->ndw += 4;
1607 bc->ndw += 4;
1608 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1609 bc->force_add_cf = 1;
1610 return 0;
1611 }
1612
1613 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1614 {
1615 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1616 int r;
1617
1618 if (ntex == NULL)
1619 return -ENOMEM;
1620 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1621
1622 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1623 if (bc->cf_last != NULL &&
1624 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1625 struct r600_bytecode_tex *ttex;
1626 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1627 if (ttex->dst_gpr == ntex->src_gpr) {
1628 bc->force_add_cf = 1;
1629 break;
1630 }
1631 }
1632 /* slight hack to make gradients always go into same cf */
1633 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1634 bc->force_add_cf = 1;
1635 }
1636
1637 /* cf can contains only alu or only vtx or only tex */
1638 if (bc->cf_last == NULL ||
1639 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1640 bc->force_add_cf) {
1641 r = r600_bytecode_add_cf(bc);
1642 if (r) {
1643 free(ntex);
1644 return r;
1645 }
1646 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1647 }
1648 if (ntex->src_gpr >= bc->ngpr) {
1649 bc->ngpr = ntex->src_gpr + 1;
1650 }
1651 if (ntex->dst_gpr >= bc->ngpr) {
1652 bc->ngpr = ntex->dst_gpr + 1;
1653 }
1654 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1655 /* each texture fetch use 4 dwords */
1656 bc->cf_last->ndw += 4;
1657 bc->ndw += 4;
1658 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1659 bc->force_add_cf = 1;
1660 return 0;
1661 }
1662
1663 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1664 {
1665 int r;
1666 r = r600_bytecode_add_cf(bc);
1667 if (r)
1668 return r;
1669
1670 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1671 bc->cf_last->inst = inst;
1672 return 0;
1673 }
1674
1675 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1676 {
1677 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1678 }
1679
1680 /* common to all 3 families */
1681 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1682 {
1683 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1684 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1685 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1686 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1687 if (bc->chip_class < CAYMAN)
1688 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1689 id++;
1690 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1691 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1692 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1693 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1694 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1695 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1696 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1697 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1698 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1699 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1700 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1701 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1702 if (bc->chip_class < CAYMAN)
1703 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1704 id++;
1705 bc->bytecode[id++] = 0;
1706 return 0;
1707 }
1708
1709 /* common to all 3 families */
1710 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1711 {
1712 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1713 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1714 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1715 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1716 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1717 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1718 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1719 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1720 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1721 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1722 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1723 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1724 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1725 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1726 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1727 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1728 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1729 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1730 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1731 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1732 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1733 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1734 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1735 bc->bytecode[id++] = 0;
1736 return 0;
1737 }
1738
1739 /* r600 only, r700/eg bits in r700_asm.c */
1740 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1741 {
1742 /* don't replace gpr by pv or ps for destination register */
1743 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1744 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1745 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1746 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1747 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1748 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1749 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1750 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1751 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1752 S_SQ_ALU_WORD0_LAST(alu->last);
1753
1754 if (alu->is_op3) {
1755 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1756 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1757 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1758 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1759 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1760 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1761 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1762 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1763 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1764 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1765 } else {
1766 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1767 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1768 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1769 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1770 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1771 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1772 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1773 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1774 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1775 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1776 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1777 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1778 }
1779 return 0;
1780 }
1781
1782 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1783 {
1784 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1785 *bytecode++ = cf->inst |
1786 S_SQ_CF_WORD1_BARRIER(1) |
1787 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1788 }
1789
1790 /* common for r600/r700 - eg in eg_asm.c */
1791 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1792 {
1793 unsigned id = cf->id;
1794
1795 switch (cf->inst) {
1796 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1797 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1798 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1799 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1800 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1801 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1802 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1803 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1804
1805 bc->bytecode[id++] = cf->inst |
1806 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1807 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1808 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1809 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1810 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1811 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1812 break;
1813 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1814 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1815 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1816 if (bc->chip_class == R700)
1817 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1818 else
1819 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1820 break;
1821 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1822 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1823 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1824 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1825 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1826 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1827 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1828 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1829 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1830 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1831 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1832 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1833 cf->output.inst |
1834 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1835 break;
1836 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1837 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1838 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1839 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1840 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1841 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1842 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1843 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1844 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1845 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1846 cf->output.inst |
1847 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1848 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1849 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1850 break;
1851 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1852 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1853 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1854 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1855 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1856 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1857 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1858 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1859 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1860 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1861 bc->bytecode[id++] = cf->inst |
1862 S_SQ_CF_WORD1_BARRIER(1) |
1863 S_SQ_CF_WORD1_COND(cf->cond) |
1864 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1865
1866 break;
1867 default:
1868 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1869 return -EINVAL;
1870 }
1871 return 0;
1872 }
1873
1874 int r600_bytecode_build(struct r600_bytecode *bc)
1875 {
1876 struct r600_bytecode_cf *cf;
1877 struct r600_bytecode_alu *alu;
1878 struct r600_bytecode_vtx *vtx;
1879 struct r600_bytecode_tex *tex;
1880 uint32_t literal[4];
1881 unsigned nliteral;
1882 unsigned addr;
1883 int i, r;
1884
1885 if (bc->callstack[0].max > 0)
1886 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1887 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1888 bc->nstack = 1;
1889 }
1890
1891 /* first path compute addr of each CF block */
1892 /* addr start after all the CF instructions */
1893 addr = bc->cf_last->id + 2;
1894 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1895 if (bc->chip_class >= EVERGREEN) {
1896 switch (cf->inst) {
1897 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1898 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1899 /* fetch node need to be 16 bytes aligned*/
1900 addr += 3;
1901 addr &= 0xFFFFFFFCUL;
1902 break;
1903 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1904 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1905 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1906 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1907 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1908 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1909 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1910 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1911 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1912 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1913 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1914 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1915 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1916 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1917 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1918 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1919 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1920 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1921 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1922 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1923 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1924 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1925 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1926 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1927 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1928 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1929 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1930 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1931 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1932 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1933 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1934 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1935 case CF_NATIVE:
1936 break;
1937 default:
1938 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1939 return -EINVAL;
1940 }
1941 } else {
1942 switch (cf->inst) {
1943 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1944 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1945 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1946 /* fetch node need to be 16 bytes aligned*/
1947 addr += 3;
1948 addr &= 0xFFFFFFFCUL;
1949 break;
1950 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1951 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1952 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1953 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1954 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1955 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1956 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1957 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1958 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1959 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1960 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1961 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1962 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1963 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1964 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1965 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1966 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1967 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1968 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1969 break;
1970 default:
1971 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1972 return -EINVAL;
1973 }
1974 }
1975 cf->addr = addr;
1976 addr += cf->ndw;
1977 bc->ndw = cf->addr + cf->ndw;
1978 }
1979 free(bc->bytecode);
1980 bc->bytecode = calloc(1, bc->ndw * 4);
1981 if (bc->bytecode == NULL)
1982 return -ENOMEM;
1983 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1984 addr = cf->addr;
1985 if (bc->chip_class >= EVERGREEN) {
1986 r = eg_bytecode_cf_build(bc, cf);
1987 if (r)
1988 return r;
1989
1990 switch (cf->inst) {
1991 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1992 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1993 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1994 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1995 nliteral = 0;
1996 memset(literal, 0, sizeof(literal));
1997 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1998 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1999 if (r)
2000 return r;
2001 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2002 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2003
2004 switch(bc->chip_class) {
2005 case EVERGREEN: /* eg alu is same encoding as r700 */
2006 case CAYMAN:
2007 r = r700_bytecode_alu_build(bc, alu, addr);
2008 break;
2009 default:
2010 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2011 return -EINVAL;
2012 }
2013 if (r)
2014 return r;
2015 addr += 2;
2016 if (alu->last) {
2017 for (i = 0; i < align(nliteral, 2); ++i) {
2018 bc->bytecode[addr++] = literal[i];
2019 }
2020 nliteral = 0;
2021 memset(literal, 0, sizeof(literal));
2022 }
2023 }
2024 break;
2025 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2026 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2027 r = r600_bytecode_vtx_build(bc, vtx, addr);
2028 if (r)
2029 return r;
2030 addr += 4;
2031 }
2032 break;
2033 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2034 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2035 assert(bc->chip_class >= EVERGREEN);
2036 r = r600_bytecode_vtx_build(bc, vtx, addr);
2037 if (r)
2038 return r;
2039 addr += 4;
2040 }
2041 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2042 r = r600_bytecode_tex_build(bc, tex, addr);
2043 if (r)
2044 return r;
2045 addr += 4;
2046 }
2047 break;
2048 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2049 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2050 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2051 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2052 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2053 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2054 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2055 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2056 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2057 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2058 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2059 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2060 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2061 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2062 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2063 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2064 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2065 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2066 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2067 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2068 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2069 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2070 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2071 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2072 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2073 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2074 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2075 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2076 break;
2077 case CF_NATIVE:
2078 break;
2079 default:
2080 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2081 return -EINVAL;
2082 }
2083 } else {
2084 r = r600_bytecode_cf_build(bc, cf);
2085 if (r)
2086 return r;
2087
2088 switch (cf->inst) {
2089 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2090 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2091 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2092 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2093 nliteral = 0;
2094 memset(literal, 0, sizeof(literal));
2095 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2096 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2097 if (r)
2098 return r;
2099 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2100 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2101
2102 switch(bc->chip_class) {
2103 case R600:
2104 r = r600_bytecode_alu_build(bc, alu, addr);
2105 break;
2106 case R700:
2107 r = r700_bytecode_alu_build(bc, alu, addr);
2108 break;
2109 default:
2110 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2111 return -EINVAL;
2112 }
2113 if (r)
2114 return r;
2115 addr += 2;
2116 if (alu->last) {
2117 for (i = 0; i < align(nliteral, 2); ++i) {
2118 bc->bytecode[addr++] = literal[i];
2119 }
2120 nliteral = 0;
2121 memset(literal, 0, sizeof(literal));
2122 }
2123 }
2124 break;
2125 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2126 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2127 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2128 r = r600_bytecode_vtx_build(bc, vtx, addr);
2129 if (r)
2130 return r;
2131 addr += 4;
2132 }
2133 break;
2134 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2135 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2136 r = r600_bytecode_tex_build(bc, tex, addr);
2137 if (r)
2138 return r;
2139 addr += 4;
2140 }
2141 break;
2142 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2143 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2144 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2145 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2146 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2147 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2148 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2149 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2150 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2151 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2152 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2153 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2154 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2155 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2156 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2157 break;
2158 default:
2159 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2160 return -EINVAL;
2161 }
2162 }
2163 }
2164 return 0;
2165 }
2166
2167 void r600_bytecode_clear(struct r600_bytecode *bc)
2168 {
2169 struct r600_bytecode_cf *cf = NULL, *next_cf;
2170
2171 free(bc->bytecode);
2172 bc->bytecode = NULL;
2173
2174 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2175 struct r600_bytecode_alu *alu = NULL, *next_alu;
2176 struct r600_bytecode_tex *tex = NULL, *next_tex;
2177 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2178
2179 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2180 free(alu);
2181 }
2182
2183 LIST_INITHEAD(&cf->alu);
2184
2185 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2186 free(tex);
2187 }
2188
2189 LIST_INITHEAD(&cf->tex);
2190
2191 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2192 free(vtx);
2193 }
2194
2195 LIST_INITHEAD(&cf->vtx);
2196
2197 free(cf);
2198 }
2199
2200 LIST_INITHEAD(&cf->list);
2201 }
2202
2203 void r600_bytecode_dump(struct r600_bytecode *bc)
2204 {
2205 struct r600_bytecode_cf *cf = NULL;
2206 struct r600_bytecode_alu *alu = NULL;
2207 struct r600_bytecode_vtx *vtx = NULL;
2208 struct r600_bytecode_tex *tex = NULL;
2209
2210 unsigned i, id;
2211 uint32_t literal[4];
2212 unsigned nliteral;
2213 char chip = '6';
2214
2215 switch (bc->chip_class) {
2216 case R700:
2217 chip = '7';
2218 break;
2219 case EVERGREEN:
2220 chip = 'E';
2221 break;
2222 case CAYMAN:
2223 chip = 'C';
2224 break;
2225 case R600:
2226 default:
2227 chip = '6';
2228 break;
2229 }
2230 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2231 fprintf(stderr, " %c\n", chip);
2232
2233 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2234 id = cf->id;
2235
2236 if (bc->chip_class >= EVERGREEN) {
2237 switch (cf->inst) {
2238 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2239 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2240 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2241 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2242 if (cf->eg_alu_extended) {
2243 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2244 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2245 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2246 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2247 id++;
2248 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2249 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2250 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2251 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2252 id++;
2253 }
2254
2255 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2256 fprintf(stderr, "ADDR:%d ", cf->addr);
2257 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2258 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2259 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2260 id++;
2261 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2262 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2263 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2264 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2265 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2266 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2267 break;
2268 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2269 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2270 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2271 fprintf(stderr, "ADDR:%d\n", cf->addr);
2272 id++;
2273 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2274 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2275 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2276 break;
2277 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2278 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2279 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2280 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2281 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2282 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2283 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2284 id++;
2285 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2286 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2287 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2288 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2289 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2290 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2291 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2292 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2293 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2294 break;
2295 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2296 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2297 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2298 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2299 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2300 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2301 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2302 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2303 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2304 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2305 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2306 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2307 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2308 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2309 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2310 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2311 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2312 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2313 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2314 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2315 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2316 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2317 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2318 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2319 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2320 id++;
2321 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2322 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2323 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2324 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2325 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2326 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2327 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2328 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2329 fprintf(stderr, "INST:%d ", cf->output.inst);
2330 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2331 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2332 break;
2333 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2334 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2335 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2336 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2337 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2338 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2339 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2340 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2341 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2342 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2343 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2344 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2345 id++;
2346 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2347 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2348 fprintf(stderr, "COND:%X ", cf->cond);
2349 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2350 break;
2351 case CF_NATIVE:
2352 fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
2353 fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
2354 break;
2355 default:
2356 R600_ERR("Unknown instruction %0x\n", cf->inst);
2357 }
2358 } else {
2359 switch (cf->inst) {
2360 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2361 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2362 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2363 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2364 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2365 fprintf(stderr, "ADDR:%d ", cf->addr);
2366 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2367 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2368 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2369 id++;
2370 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2371 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2372 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2373 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2374 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2375 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2376 break;
2377 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2378 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2379 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2380 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2381 fprintf(stderr, "ADDR:%d\n", cf->addr);
2382 id++;
2383 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2384 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2385 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2386 break;
2387 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2388 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2389 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2390 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2391 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2392 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2393 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2394 id++;
2395 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2396 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2397 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2398 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2399 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2400 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2401 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2402 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2403 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2404 break;
2405 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2406 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2407 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2408 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2409 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2410 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2411 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2412 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2413 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2414 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2415 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2416 id++;
2417 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2418 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2419 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2420 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2421 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2422 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2423 fprintf(stderr, "INST:%d ", cf->output.inst);
2424 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2425 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2426 break;
2427 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2428 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2429 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2430 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2431 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2432 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2433 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2434 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2435 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2436 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2437 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2438 id++;
2439 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2440 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2441 fprintf(stderr, "COND:%X ", cf->cond);
2442 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2443 break;
2444 default:
2445 R600_ERR("Unknown instruction %0x\n", cf->inst);
2446 }
2447 }
2448
2449 id = cf->addr;
2450 nliteral = 0;
2451 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2452 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2453
2454 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2455 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2456 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2457 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2458 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2459 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2460 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2461 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2462 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2463 fprintf(stderr, "IM:%d) ", alu->index_mode);
2464 fprintf(stderr, "LAST:%d)\n", alu->last);
2465 id++;
2466 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2467 fprintf(stderr, "INST:0x%x ", alu->inst);
2468 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2469 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2470 fprintf(stderr, "REL:%d ", alu->dst.rel);
2471 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2472 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2473 if (alu->is_op3) {
2474 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2475 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2476 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2477 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2478 } else {
2479 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2480 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2481 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2482 fprintf(stderr, "OMOD:%d ", alu->omod);
2483 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
2484 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
2485 }
2486
2487 id++;
2488 if (alu->last) {
2489 for (i = 0; i < nliteral; i++, id++) {
2490 float *f = (float*)(bc->bytecode + id);
2491 fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
2492 *(bc->bytecode + id));
2493 }
2494 id += nliteral & 1;
2495 nliteral = 0;
2496 }
2497 }
2498
2499 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2500 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2501 fprintf(stderr, "INST:0x%x ", tex->inst);
2502 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2503 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2504 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2505 id++;
2506 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2507 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2508 fprintf(stderr, "REL:%d ", tex->dst_rel);
2509 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2510 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2511 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2512 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2513 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2514 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2515 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2516 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2517 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2518 id++;
2519 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2520 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2521 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2522 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2523 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2524 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2525 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2526 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2527 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2528 id++;
2529 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2530 id++;
2531 }
2532
2533 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2534 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2535 fprintf(stderr, "INST:%d ", vtx->inst);
2536 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2537 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2538 id++;
2539 /* This assumes that no semantic fetches exist */
2540 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2541 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2542 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2543 if (bc->chip_class < CAYMAN)
2544 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2545 else
2546 fprintf(stderr, "SEL_Y:%d) ", 0);
2547 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2548 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2549 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2550 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2551 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2552 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2553 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2554 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2555 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2556 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2557 id++;
2558 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2559 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2560 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2561 /* XXX */
2562 id++;
2563 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2564 id++;
2565 }
2566 }
2567
2568 fprintf(stderr, "--------------------------------------\n");
2569 }
2570
2571 static void r600_vertex_data_type(enum pipe_format pformat,
2572 unsigned *format,
2573 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2574 {
2575 const struct util_format_description *desc;
2576 unsigned i;
2577
2578 *format = 0;
2579 *num_format = 0;
2580 *format_comp = 0;
2581 *endian = ENDIAN_NONE;
2582
2583 desc = util_format_description(pformat);
2584 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2585 goto out_unknown;
2586 }
2587
2588 /* Find the first non-VOID channel. */
2589 for (i = 0; i < 4; i++) {
2590 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2591 break;
2592 }
2593 }
2594
2595 *endian = r600_endian_swap(desc->channel[i].size);
2596
2597 switch (desc->channel[i].type) {
2598 /* Half-floats, floats, ints */
2599 case UTIL_FORMAT_TYPE_FLOAT:
2600 switch (desc->channel[i].size) {
2601 case 16:
2602 switch (desc->nr_channels) {
2603 case 1:
2604 *format = FMT_16_FLOAT;
2605 break;
2606 case 2:
2607 *format = FMT_16_16_FLOAT;
2608 break;
2609 case 3:
2610 case 4:
2611 *format = FMT_16_16_16_16_FLOAT;
2612 break;
2613 }
2614 break;
2615 case 32:
2616 switch (desc->nr_channels) {
2617 case 1:
2618 *format = FMT_32_FLOAT;
2619 break;
2620 case 2:
2621 *format = FMT_32_32_FLOAT;
2622 break;
2623 case 3:
2624 *format = FMT_32_32_32_FLOAT;
2625 break;
2626 case 4:
2627 *format = FMT_32_32_32_32_FLOAT;
2628 break;
2629 }
2630 break;
2631 default:
2632 goto out_unknown;
2633 }
2634 break;
2635 /* Unsigned ints */
2636 case UTIL_FORMAT_TYPE_UNSIGNED:
2637 /* Signed ints */
2638 case UTIL_FORMAT_TYPE_SIGNED:
2639 switch (desc->channel[i].size) {
2640 case 8:
2641 switch (desc->nr_channels) {
2642 case 1:
2643 *format = FMT_8;
2644 break;
2645 case 2:
2646 *format = FMT_8_8;
2647 break;
2648 case 3:
2649 case 4:
2650 *format = FMT_8_8_8_8;
2651 break;
2652 }
2653 break;
2654 case 10:
2655 if (desc->nr_channels != 4)
2656 goto out_unknown;
2657
2658 *format = FMT_2_10_10_10;
2659 break;
2660 case 16:
2661 switch (desc->nr_channels) {
2662 case 1:
2663 *format = FMT_16;
2664 break;
2665 case 2:
2666 *format = FMT_16_16;
2667 break;
2668 case 3:
2669 case 4:
2670 *format = FMT_16_16_16_16;
2671 break;
2672 }
2673 break;
2674 case 32:
2675 switch (desc->nr_channels) {
2676 case 1:
2677 *format = FMT_32;
2678 break;
2679 case 2:
2680 *format = FMT_32_32;
2681 break;
2682 case 3:
2683 *format = FMT_32_32_32;
2684 break;
2685 case 4:
2686 *format = FMT_32_32_32_32;
2687 break;
2688 }
2689 break;
2690 default:
2691 goto out_unknown;
2692 }
2693 break;
2694 default:
2695 goto out_unknown;
2696 }
2697
2698 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2699 *format_comp = 1;
2700 }
2701
2702 *num_format = 0;
2703 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2704 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2705 if (!desc->channel[i].normalized) {
2706 if (desc->channel[i].pure_integer)
2707 *num_format = 1;
2708 else
2709 *num_format = 2;
2710 }
2711 }
2712 return;
2713 out_unknown:
2714 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2715 }
2716
2717 int r600_vertex_elements_build_fetch_shader(struct r600_context *rctx, struct r600_vertex_element *ve)
2718 {
2719 static int dump_shaders = -1;
2720
2721 struct r600_bytecode bc;
2722 struct r600_bytecode_vtx vtx;
2723 struct pipe_vertex_element *elements = ve->elements;
2724 const struct util_format_description *desc;
2725 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2726 unsigned format, num_format, format_comp, endian;
2727 uint32_t *bytecode;
2728 int i, r;
2729
2730 memset(&bc, 0, sizeof(bc));
2731 r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
2732
2733 for (i = 0; i < ve->count; i++) {
2734 if (elements[i].instance_divisor > 1) {
2735 struct r600_bytecode_alu alu;
2736
2737 memset(&alu, 0, sizeof(alu));
2738 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2739 alu.src[0].sel = 0;
2740 alu.src[0].chan = 3;
2741
2742 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2743 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2744
2745 alu.dst.sel = i + 1;
2746 alu.dst.chan = 3;
2747 alu.dst.write = 1;
2748 alu.last = 1;
2749
2750 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2751 r600_bytecode_clear(&bc);
2752 return r;
2753 }
2754 }
2755 }
2756
2757 for (i = 0; i < ve->count; i++) {
2758 r600_vertex_data_type(ve->elements[i].src_format,
2759 &format, &num_format, &format_comp, &endian);
2760
2761 desc = util_format_description(ve->elements[i].src_format);
2762 if (desc == NULL) {
2763 r600_bytecode_clear(&bc);
2764 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2765 return -EINVAL;
2766 }
2767
2768 if (elements[i].src_offset > 65535) {
2769 r600_bytecode_clear(&bc);
2770 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2771 return -EINVAL;
2772 }
2773
2774 memset(&vtx, 0, sizeof(vtx));
2775 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2776 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2777 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2778 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2779 vtx.mega_fetch_count = 0x1F;
2780 vtx.dst_gpr = i + 1;
2781 vtx.dst_sel_x = desc->swizzle[0];
2782 vtx.dst_sel_y = desc->swizzle[1];
2783 vtx.dst_sel_z = desc->swizzle[2];
2784 vtx.dst_sel_w = desc->swizzle[3];
2785 vtx.data_format = format;
2786 vtx.num_format_all = num_format;
2787 vtx.format_comp_all = format_comp;
2788 vtx.srf_mode_all = 1;
2789 vtx.offset = elements[i].src_offset;
2790 vtx.endian = endian;
2791
2792 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2793 r600_bytecode_clear(&bc);
2794 return r;
2795 }
2796 }
2797
2798 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2799
2800 if ((r = r600_bytecode_build(&bc))) {
2801 r600_bytecode_clear(&bc);
2802 return r;
2803 }
2804
2805 if (dump_shaders == -1)
2806 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2807
2808 if (dump_shaders) {
2809 fprintf(stderr, "--------------------------------------------------------------\n");
2810 r600_bytecode_dump(&bc);
2811 fprintf(stderr, "______________________________________________________________\n");
2812 }
2813
2814 ve->fs_size = bc.ndw*4;
2815
2816 ve->fetch_shader = (struct r600_resource*)
2817 pipe_buffer_create(rctx->context.screen,
2818 PIPE_BIND_CUSTOM,
2819 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2820 if (ve->fetch_shader == NULL) {
2821 r600_bytecode_clear(&bc);
2822 return -ENOMEM;
2823 }
2824
2825 bytecode = rctx->ws->buffer_map(ve->fetch_shader->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
2826 if (bytecode == NULL) {
2827 r600_bytecode_clear(&bc);
2828 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2829 return -ENOMEM;
2830 }
2831
2832 if (R600_BIG_ENDIAN) {
2833 for (i = 0; i < ve->fs_size / 4; ++i) {
2834 bytecode[i] = bswap_32(bc.bytecode[i]);
2835 }
2836 } else {
2837 memcpy(bytecode, bc.bytecode, ve->fs_size);
2838 }
2839
2840 rctx->ws->buffer_unmap(ve->fetch_shader->cs_buf);
2841 r600_bytecode_clear(&bc);
2842
2843 if (rctx->chip_class >= EVERGREEN)
2844 evergreen_fetch_shader(&rctx->context, ve);
2845 else
2846 r600_fetch_shader(&rctx->context, ve);
2847
2848 return 0;
2849 }