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r600g: fix reserve_cfile for R700+
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
39 {
40 if(alu->is_op3)
41 return 3;
42
43 switch (bc->chiprev) {
44 case CHIPREV_R600:
45 case CHIPREV_R700:
46 switch (alu->inst) {
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
48 return 0;
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
68 return 2;
69
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
87 return 1;
88 default: R600_ERR(
89 "Need instruction operand number for 0x%x.\n", alu->inst);
90 }
91 break;
92 case CHIPREV_EVERGREEN:
93 switch (alu->inst) {
94 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
95 return 0;
96 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
97 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
98 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
99 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
100 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
101 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
103 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
117 return 2;
118
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
135 return 1;
136 default: R600_ERR(
137 "Need instruction operand number for 0x%x.\n", alu->inst);
138 }
139 break;
140 }
141
142 return 3;
143 }
144
145 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
146
147 static struct r600_bc_cf *r600_bc_cf(void)
148 {
149 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
150
151 if (cf == NULL)
152 return NULL;
153 LIST_INITHEAD(&cf->list);
154 LIST_INITHEAD(&cf->alu);
155 LIST_INITHEAD(&cf->vtx);
156 LIST_INITHEAD(&cf->tex);
157 return cf;
158 }
159
160 static struct r600_bc_alu *r600_bc_alu(void)
161 {
162 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
163
164 if (alu == NULL)
165 return NULL;
166 LIST_INITHEAD(&alu->list);
167 return alu;
168 }
169
170 static struct r600_bc_vtx *r600_bc_vtx(void)
171 {
172 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
173
174 if (vtx == NULL)
175 return NULL;
176 LIST_INITHEAD(&vtx->list);
177 return vtx;
178 }
179
180 static struct r600_bc_tex *r600_bc_tex(void)
181 {
182 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
183
184 if (tex == NULL)
185 return NULL;
186 LIST_INITHEAD(&tex->list);
187 return tex;
188 }
189
190 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
191 {
192 LIST_INITHEAD(&bc->cf);
193 bc->family = family;
194 switch (bc->family) {
195 case CHIP_R600:
196 case CHIP_RV610:
197 case CHIP_RV630:
198 case CHIP_RV670:
199 case CHIP_RV620:
200 case CHIP_RV635:
201 case CHIP_RS780:
202 case CHIP_RS880:
203 bc->chiprev = CHIPREV_R600;
204 break;
205 case CHIP_RV770:
206 case CHIP_RV730:
207 case CHIP_RV710:
208 case CHIP_RV740:
209 bc->chiprev = CHIPREV_R700;
210 break;
211 case CHIP_CEDAR:
212 case CHIP_REDWOOD:
213 case CHIP_JUNIPER:
214 case CHIP_CYPRESS:
215 case CHIP_HEMLOCK:
216 case CHIP_PALM:
217 case CHIP_BARTS:
218 case CHIP_TURKS:
219 case CHIP_CAICOS:
220 bc->chiprev = CHIPREV_EVERGREEN;
221 break;
222 default:
223 R600_ERR("unknown family %d\n", bc->family);
224 return -EINVAL;
225 }
226 return 0;
227 }
228
229 static int r600_bc_add_cf(struct r600_bc *bc)
230 {
231 struct r600_bc_cf *cf = r600_bc_cf();
232
233 if (cf == NULL)
234 return -ENOMEM;
235 LIST_ADDTAIL(&cf->list, &bc->cf);
236 if (bc->cf_last)
237 cf->id = bc->cf_last->id + 2;
238 bc->cf_last = cf;
239 bc->ncf++;
240 bc->ndw += 2;
241 bc->force_add_cf = 0;
242 return 0;
243 }
244
245 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
246 {
247 int r;
248
249 r = r600_bc_add_cf(bc);
250 if (r)
251 return r;
252 bc->cf_last->inst = output->inst;
253 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
254 return 0;
255 }
256
257 /* alu instructions that can ony exits once per group */
258 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
259 {
260 switch (bc->chiprev) {
261 case CHIPREV_R600:
262 case CHIPREV_R700:
263 return !alu->is_op3 && (
264 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
265 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
266 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
267 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
268 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
269 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
270 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
271 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
272 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
273 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
274 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
275 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
276 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
277 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
278 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
279 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
280 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
281 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
282 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
283 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
284 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
285 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
286 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
287 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
288 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
289 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
290 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
291 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
292 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
293 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
294 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
295 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
296 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
297 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
298 case CHIPREV_EVERGREEN:
299 default:
300 return !alu->is_op3 && (
301 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
302 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
303 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
304 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
305 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
306 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
307 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
308 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
309 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
310 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
311 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
312 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
313 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
314 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
315 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
316 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
317 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
318 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
319 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
320 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
321 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
322 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
323 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
324 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
325 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
326 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
327 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
328 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
329 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
330 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
331 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
332 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
333 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
334 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
335 }
336 }
337
338 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
339 {
340 switch (bc->chiprev) {
341 case CHIPREV_R600:
342 case CHIPREV_R700:
343 return !alu->is_op3 && (
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
348 case CHIPREV_EVERGREEN:
349 default:
350 return !alu->is_op3 && (
351 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
352 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
353 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
354 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
355 }
356 }
357
358 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
359 {
360 switch (bc->chiprev) {
361 case CHIPREV_R600:
362 case CHIPREV_R700:
363 return !alu->is_op3 && (
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
367 case CHIPREV_EVERGREEN:
368 default:
369 return !alu->is_op3 && (
370 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
371 }
372 }
373
374 /* alu instructions that can only execute on the vector unit */
375 static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
376 {
377 return is_alu_reduction_inst(bc, alu) ||
378 is_alu_mova_inst(bc, alu);
379 }
380
381 /* alu instructions that can only execute on the trans unit */
382 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
383 {
384 switch (bc->chiprev) {
385 case CHIPREV_R600:
386 case CHIPREV_R700:
387 if (!alu->is_op3)
388 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
389 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
390 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
391 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
392 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
393 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
394 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
395 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
396 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
397 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
398 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
399 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
400 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
401 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
402 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
403 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
404 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
405 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
406 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
407 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
408 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
409 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
410 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
411 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
412 else
413 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
414 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
415 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
416 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
417 case CHIPREV_EVERGREEN:
418 default:
419 if (!alu->is_op3)
420 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
421 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
422 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
423 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
424 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
425 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
426 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
427 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
428 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
429 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
430 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
431 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
433 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
434 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
435 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
436 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
437 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
438 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
439 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
440 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
441 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
442 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
443 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
444 else
445 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
446 }
447 }
448
449 /* alu instructions that can execute on any unit */
450 static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
451 {
452 return !is_alu_vec_unit_inst(bc, alu) &&
453 !is_alu_trans_unit_inst(bc, alu);
454 }
455
456 static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
457 struct r600_bc_alu *assignment[5])
458 {
459 struct r600_bc_alu *alu;
460 unsigned i, chan, trans;
461
462 for (i = 0; i < 5; i++)
463 assignment[i] = NULL;
464
465 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
466 chan = alu->dst.chan;
467 if (is_alu_trans_unit_inst(bc, alu))
468 trans = 1;
469 else if (is_alu_vec_unit_inst(bc, alu))
470 trans = 0;
471 else if (assignment[chan])
472 trans = 1; // assume ALU_INST_PREFER_VECTOR
473 else
474 trans = 0;
475
476 if (trans) {
477 if (assignment[4]) {
478 assert(0); //ALU.Trans has already been allocated
479 return -1;
480 }
481 assignment[4] = alu;
482 } else {
483 if (assignment[chan]) {
484 assert(0); //ALU.chan has already been allocated
485 return -1;
486 }
487 assignment[chan] = alu;
488 }
489
490 if (alu->last)
491 break;
492 }
493 return 0;
494 }
495
496 struct alu_bank_swizzle {
497 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
498 int hw_cfile_addr[4];
499 int hw_cfile_elem[4];
500 };
501
502 const unsigned cycle_for_bank_swizzle_vec[][3] = {
503 [SQ_ALU_VEC_012] = { 0, 1, 2 },
504 [SQ_ALU_VEC_021] = { 0, 2, 1 },
505 [SQ_ALU_VEC_120] = { 1, 2, 0 },
506 [SQ_ALU_VEC_102] = { 1, 0, 2 },
507 [SQ_ALU_VEC_201] = { 2, 0, 1 },
508 [SQ_ALU_VEC_210] = { 2, 1, 0 }
509 };
510
511 const unsigned cycle_for_bank_swizzle_scl[][3] = {
512 [SQ_ALU_SCL_210] = { 2, 1, 0 },
513 [SQ_ALU_SCL_122] = { 1, 2, 2 },
514 [SQ_ALU_SCL_212] = { 2, 1, 2 },
515 [SQ_ALU_SCL_221] = { 2, 2, 1 }
516 };
517
518 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
519 {
520 int i, cycle, component;
521 /* set up gpr use */
522 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
523 for (component = 0; component < NUM_OF_COMPONENTS; component++)
524 bs->hw_gpr[cycle][component] = -1;
525 for (i = 0; i < 4; i++)
526 bs->hw_cfile_addr[i] = -1;
527 for (i = 0; i < 4; i++)
528 bs->hw_cfile_elem[i] = -1;
529 }
530
531 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
532 {
533 if (bs->hw_gpr[cycle][chan] == -1)
534 bs->hw_gpr[cycle][chan] = sel;
535 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
536 // Another scalar operation has already used GPR read port for channel
537 return -1;
538 }
539 return 0;
540 }
541
542 static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
543 {
544 int res, num_res = 4;
545 if (bc->chiprev >= CHIPREV_R700) {
546 num_res = 2;
547 chan /= 2;
548 }
549 for (res = 0; res < num_res; ++res) {
550 if (bs->hw_cfile_addr[res] == -1) {
551 bs->hw_cfile_addr[res] = sel;
552 bs->hw_cfile_elem[res] = chan;
553 return 0;
554 } else if (bs->hw_cfile_addr[res] == sel &&
555 bs->hw_cfile_elem[res] == chan)
556 return 0; // Read for this scalar element already reserved, nothing to do here.
557 }
558 // All cfile read ports are used, cannot reference vector element
559 return -1;
560 }
561
562 static int is_gpr(unsigned sel)
563 {
564 return (sel >= 0 && sel <= 127);
565 }
566
567 /* CB constants start at 512, and get translated to a kcache index when ALU
568 * clauses are constructed. Note that we handle kcache constants the same way
569 * as (the now gone) cfile constants, is that really required? */
570 static int is_cfile(unsigned sel)
571 {
572 return (sel > 255 && sel < 512) ||
573 (sel > 511 && sel < 4607) || // Kcache before translate
574 (sel > 127 && sel < 192); // Kcache after translate
575 }
576
577 static int is_const(int sel)
578 {
579 return is_cfile(sel) ||
580 (sel >= V_SQ_ALU_SRC_0 &&
581 sel <= V_SQ_ALU_SRC_LITERAL);
582 }
583
584 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
585 struct alu_bank_swizzle *bs, int bank_swizzle)
586 {
587 int r, src, num_src, sel, elem, cycle;
588
589 num_src = r600_bc_get_num_operands(bc, alu);
590 for (src = 0; src < num_src; src++) {
591 sel = alu->src[src].sel;
592 elem = alu->src[src].chan;
593 if (is_gpr(sel)) {
594 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
595 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
596 // Nothing to do; special-case optimization,
597 // second source uses first source’s reservation
598 continue;
599 else {
600 r = reserve_gpr(bs, sel, elem, cycle);
601 if (r)
602 return r;
603 }
604 } else if (is_cfile(sel)) {
605 r = reserve_cfile(bc, bs, sel, elem);
606 if (r)
607 return r;
608 }
609 // No restrictions on PV, PS, literal or special constants
610 }
611 return 0;
612 }
613
614 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
615 struct alu_bank_swizzle *bs, int bank_swizzle)
616 {
617 int r, src, num_src, const_count, sel, elem, cycle;
618
619 num_src = r600_bc_get_num_operands(bc, alu);
620 for (const_count = 0, src = 0; src < num_src; ++src) {
621 sel = alu->src[src].sel;
622 elem = alu->src[src].chan;
623 if (is_const(sel)) { // Any constant, including literal and inline constants
624 if (const_count >= 2)
625 // More than two references to a constant in
626 // transcendental operation.
627 return -1;
628 else
629 const_count++;
630 }
631 if (is_cfile(sel)) {
632 r = reserve_cfile(bc, bs, sel, elem);
633 if (r)
634 return r;
635 }
636 }
637 for (src = 0; src < num_src; ++src) {
638 sel = alu->src[src].sel;
639 elem = alu->src[src].chan;
640 if (is_gpr(sel)) {
641 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
642 if (cycle < const_count)
643 // Cycle for GPR load conflicts with
644 // constant load in transcendental operation.
645 return -1;
646 r = reserve_gpr(bs, sel, elem, cycle);
647 if (r)
648 return r;
649 }
650 // Constants already processed
651 // No restrictions on PV, PS
652 }
653 return 0;
654 }
655
656 static int check_and_set_bank_swizzle(struct r600_bc *bc,
657 struct r600_bc_alu *slots[5])
658 {
659 struct alu_bank_swizzle bs;
660 int bank_swizzle[5];
661 int i, r = 0, forced = 0;
662
663 for (i = 0; i < 5; i++)
664 if (slots[i] && slots[i]->bank_swizzle_force) {
665 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
666 forced = 1;
667 }
668
669 if (forced)
670 return 0;
671
672 // just check every possible combination of bank swizzle
673 // not very efficent, but works on the first try in most of the cases
674 for (i = 0; i < 4; i++)
675 bank_swizzle[i] = SQ_ALU_VEC_012;
676 bank_swizzle[4] = SQ_ALU_SCL_210;
677 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
678 init_bank_swizzle(&bs);
679 for (i = 0; i < 4; i++) {
680 if (slots[i]) {
681 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
682 if (r)
683 break;
684 }
685 }
686 if (!r && slots[4]) {
687 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
688 }
689 if (!r) {
690 for (i = 0; i < 5; i++) {
691 if (slots[i])
692 slots[i]->bank_swizzle = bank_swizzle[i];
693 }
694 return 0;
695 }
696
697 for (i = 0; i < 5; i++) {
698 bank_swizzle[i]++;
699 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
700 break;
701 else
702 bank_swizzle[i] = SQ_ALU_VEC_012;
703 }
704 }
705
706 // couldn't find a working swizzle
707 return -1;
708 }
709
710 static int replace_gpr_with_pv_ps(struct r600_bc *bc,
711 struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
712 {
713 struct r600_bc_alu *prev[5];
714 int gpr[5], chan[5];
715 int i, j, r, src, num_src;
716
717 r = assign_alu_units(bc, alu_prev, prev);
718 if (r)
719 return r;
720
721 for (i = 0; i < 5; ++i) {
722 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
723 gpr[i] = prev[i]->dst.sel;
724 if (is_alu_reduction_inst(bc, prev[i]))
725 chan[i] = 0;
726 else
727 chan[i] = prev[i]->dst.chan;
728 } else
729 gpr[i] = -1;
730 }
731
732 for (i = 0; i < 5; ++i) {
733 struct r600_bc_alu *alu = slots[i];
734 if(!alu)
735 continue;
736
737 num_src = r600_bc_get_num_operands(bc, alu);
738 for (src = 0; src < num_src; ++src) {
739 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
740 continue;
741
742 if (alu->src[src].sel == gpr[4] &&
743 alu->src[src].chan == chan[4]) {
744 alu->src[src].sel = V_SQ_ALU_SRC_PS;
745 alu->src[src].chan = 0;
746 continue;
747 }
748
749 for (j = 0; j < 4; ++j) {
750 if (alu->src[src].sel == gpr[j] &&
751 alu->src[src].chan == j) {
752 alu->src[src].sel = V_SQ_ALU_SRC_PV;
753 alu->src[src].chan = chan[j];
754 break;
755 }
756 }
757 }
758 }
759
760 return 0;
761 }
762
763 void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
764 {
765 switch(value) {
766 case 0:
767 *sel = V_SQ_ALU_SRC_0;
768 break;
769 case 1:
770 *sel = V_SQ_ALU_SRC_1_INT;
771 break;
772 case -1:
773 *sel = V_SQ_ALU_SRC_M_1_INT;
774 break;
775 case 0x3F800000: // 1.0f
776 *sel = V_SQ_ALU_SRC_1;
777 break;
778 case 0x3F000000: // 0.5f
779 *sel = V_SQ_ALU_SRC_0_5;
780 break;
781 case 0xBF800000: // -1.0f
782 *sel = V_SQ_ALU_SRC_1;
783 *neg ^= 1;
784 break;
785 case 0xBF000000: // -0.5f
786 *sel = V_SQ_ALU_SRC_0_5;
787 *neg ^= 1;
788 break;
789 default:
790 *sel = V_SQ_ALU_SRC_LITERAL;
791 break;
792 }
793 }
794
795 /* compute how many literal are needed */
796 static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
797 uint32_t literal[4], unsigned *nliteral)
798 {
799 unsigned num_src = r600_bc_get_num_operands(bc, alu);
800 unsigned i, j;
801
802 for (i = 0; i < num_src; ++i) {
803 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
804 uint32_t value = alu->src[i].value[alu->src[i].chan];
805 unsigned found = 0;
806 for (j = 0; j < *nliteral; ++j) {
807 if (literal[j] == value) {
808 found = 1;
809 break;
810 }
811 }
812 if (!found) {
813 if (*nliteral >= 4)
814 return -EINVAL;
815 literal[(*nliteral)++] = value;
816 }
817 }
818 }
819 return 0;
820 }
821
822 static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
823 struct r600_bc_alu *alu,
824 uint32_t literal[4], unsigned nliteral)
825 {
826 unsigned num_src = r600_bc_get_num_operands(bc, alu);
827 unsigned i, j;
828
829 for (i = 0; i < num_src; ++i) {
830 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
831 uint32_t value = alu->src[i].value[alu->src[i].chan];
832 for (j = 0; j < nliteral; ++j) {
833 if (literal[j] == value) {
834 alu->src[i].chan = j;
835 break;
836 }
837 }
838 }
839 }
840 }
841
842 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
843 struct r600_bc_alu *alu_prev)
844 {
845 struct r600_bc_alu *prev[5];
846 struct r600_bc_alu *result[5] = { NULL };
847
848 uint32_t literal[4], prev_literal[4];
849 unsigned nliteral = 0, prev_nliteral = 0;
850
851 int i, j, r, src, num_src;
852 int num_once_inst = 0;
853 int have_mova = 0, have_rel = 0;
854
855 r = assign_alu_units(bc, alu_prev, prev);
856 if (r)
857 return r;
858
859 for (i = 0; i < 5; ++i) {
860 struct r600_bc_alu *alu;
861
862 /* check number of literals */
863 if (prev[i]) {
864 if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
865 return 0;
866 if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
867 return 0;
868 if (is_alu_mova_inst(bc, prev[i])) {
869 if (have_rel)
870 return 0;
871 have_mova = 1;
872 }
873 num_once_inst += is_alu_once_inst(bc, prev[i]);
874 }
875 if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
876 return 0;
877
878 // let's check used slots
879 if (prev[i] && !slots[i]) {
880 result[i] = prev[i];
881 continue;
882 } else if (prev[i] && slots[i]) {
883 if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
884 // trans unit is still free try to use it
885 if (is_alu_any_unit_inst(bc, slots[i])) {
886 result[i] = prev[i];
887 result[4] = slots[i];
888 } else if (is_alu_any_unit_inst(bc, prev[i])) {
889 result[i] = slots[i];
890 result[4] = prev[i];
891 } else
892 return 0;
893 } else
894 return 0;
895 } else if(!slots[i]) {
896 continue;
897 } else
898 result[i] = slots[i];
899
900 // let's check source gprs
901 alu = slots[i];
902 num_once_inst += is_alu_once_inst(bc, alu);
903
904 num_src = r600_bc_get_num_operands(bc, alu);
905 for (src = 0; src < num_src; ++src) {
906 if (alu->src[src].rel) {
907 if (have_mova)
908 return 0;
909 have_rel = 1;
910 }
911
912 // constants doesn't matter
913 if (!is_gpr(alu->src[src].sel))
914 continue;
915
916 for (j = 0; j < 5; ++j) {
917 if (!prev[j] || !prev[j]->dst.write)
918 continue;
919
920 // if it's relative then we can't determin which gpr is really used
921 if (prev[j]->dst.chan == alu->src[src].chan &&
922 (prev[j]->dst.sel == alu->src[src].sel ||
923 prev[j]->dst.rel || alu->src[src].rel))
924 return 0;
925 }
926 }
927 }
928
929 /* more than one PRED_ or KILL_ ? */
930 if (num_once_inst > 1)
931 return 0;
932
933 /* check if the result can still be swizzlet */
934 r = check_and_set_bank_swizzle(bc, result);
935 if (r)
936 return 0;
937
938 /* looks like everything worked out right, apply the changes */
939
940 /* undo adding previus literals */
941 bc->cf_last->ndw -= align(prev_nliteral, 2);
942
943 /* sort instructions */
944 for (i = 0; i < 5; ++i) {
945 slots[i] = result[i];
946 if (result[i]) {
947 LIST_DEL(&result[i]->list);
948 result[i]->last = 0;
949 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
950 }
951 }
952
953 /* determine new last instruction */
954 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
955
956 /* determine new first instruction */
957 for (i = 0; i < 5; ++i) {
958 if (result[i]) {
959 bc->cf_last->curr_bs_head = result[i];
960 break;
961 }
962 }
963
964 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
965 bc->cf_last->prev2_bs_head = NULL;
966
967 return 0;
968 }
969
970 /* This code handles kcache lines as single blocks of 32 constants. We could
971 * probably do slightly better by recognizing that we actually have two
972 * consecutive lines of 16 constants, but the resulting code would also be
973 * somewhat more complicated. */
974 static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
975 {
976 struct r600_bc_kcache *kcache = bc->cf_last->kcache;
977 unsigned int required_lines;
978 unsigned int free_lines = 0;
979 unsigned int cache_line[3];
980 unsigned int count = 0;
981 unsigned int i, j;
982 int r;
983
984 /* Collect required cache lines. */
985 for (i = 0; i < 3; ++i) {
986 bool found = false;
987 unsigned int line;
988
989 if (alu->src[i].sel < 512)
990 continue;
991
992 line = ((alu->src[i].sel - 512) / 32) * 2;
993
994 for (j = 0; j < count; ++j) {
995 if (cache_line[j] == line) {
996 found = true;
997 break;
998 }
999 }
1000
1001 if (!found)
1002 cache_line[count++] = line;
1003 }
1004
1005 /* This should never actually happen. */
1006 if (count >= 3) return -ENOMEM;
1007
1008 for (i = 0; i < 2; ++i) {
1009 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1010 ++free_lines;
1011 }
1012 }
1013
1014 /* Filter lines pulled in by previous intructions. Note that this is
1015 * only for the required_lines count, we can't remove these from the
1016 * cache_line array since we may have to start a new ALU clause. */
1017 for (i = 0, required_lines = count; i < count; ++i) {
1018 for (j = 0; j < 2; ++j) {
1019 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1020 kcache[j].addr == cache_line[i]) {
1021 --required_lines;
1022 break;
1023 }
1024 }
1025 }
1026
1027 /* Start a new ALU clause if needed. */
1028 if (required_lines > free_lines) {
1029 if ((r = r600_bc_add_cf(bc))) {
1030 return r;
1031 }
1032 bc->cf_last->inst = (type << 3);
1033 kcache = bc->cf_last->kcache;
1034 }
1035
1036 /* Setup the kcache lines. */
1037 for (i = 0; i < count; ++i) {
1038 bool found = false;
1039
1040 for (j = 0; j < 2; ++j) {
1041 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1042 kcache[j].addr == cache_line[i]) {
1043 found = true;
1044 break;
1045 }
1046 }
1047
1048 if (found) continue;
1049
1050 for (j = 0; j < 2; ++j) {
1051 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1052 kcache[j].bank = 0;
1053 kcache[j].addr = cache_line[i];
1054 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1055 break;
1056 }
1057 }
1058 }
1059
1060 /* Alter the src operands to refer to the kcache. */
1061 for (i = 0; i < 3; ++i) {
1062 static const unsigned int base[] = {128, 160, 256, 288};
1063 unsigned int line;
1064
1065 if (alu->src[i].sel < 512)
1066 continue;
1067
1068 alu->src[i].sel -= 512;
1069 line = (alu->src[i].sel / 32) * 2;
1070
1071 for (j = 0; j < 2; ++j) {
1072 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1073 kcache[j].addr == line) {
1074 alu->src[i].sel &= 0x1f;
1075 alu->src[i].sel += base[j];
1076 break;
1077 }
1078 }
1079 }
1080
1081 return 0;
1082 }
1083
1084 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
1085 {
1086 struct r600_bc_alu *nalu = r600_bc_alu();
1087 struct r600_bc_alu *lalu;
1088 int i, r;
1089
1090 if (nalu == NULL)
1091 return -ENOMEM;
1092 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
1093
1094 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1095 /* check if we could add it anyway */
1096 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1097 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1098 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1099 if (lalu->predicate) {
1100 bc->force_add_cf = 1;
1101 break;
1102 }
1103 }
1104 } else
1105 bc->force_add_cf = 1;
1106 }
1107
1108 /* cf can contains only alu or only vtx or only tex */
1109 if (bc->cf_last == NULL || bc->force_add_cf) {
1110 r = r600_bc_add_cf(bc);
1111 if (r) {
1112 free(nalu);
1113 return r;
1114 }
1115 }
1116 bc->cf_last->inst = (type << 3);
1117
1118 /* Setup the kcache for this ALU instruction. This will start a new
1119 * ALU clause if needed. */
1120 if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
1121 free(nalu);
1122 return r;
1123 }
1124
1125 if (!bc->cf_last->curr_bs_head) {
1126 bc->cf_last->curr_bs_head = nalu;
1127 }
1128 /* number of gpr == the last gpr used in any alu */
1129 for (i = 0; i < 3; i++) {
1130 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1131 bc->ngpr = nalu->src[i].sel + 1;
1132 }
1133 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1134 r600_bc_special_constants(
1135 nalu->src[i].value[nalu->src[i].chan],
1136 &nalu->src[i].sel, &nalu->src[i].neg);
1137 }
1138 if (nalu->dst.sel >= bc->ngpr) {
1139 bc->ngpr = nalu->dst.sel + 1;
1140 }
1141 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1142 /* each alu use 2 dwords */
1143 bc->cf_last->ndw += 2;
1144 bc->ndw += 2;
1145
1146 /* process cur ALU instructions for bank swizzle */
1147 if (nalu->last) {
1148 uint32_t literal[4];
1149 unsigned nliteral;
1150 struct r600_bc_alu *slots[5];
1151 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1152 if (r)
1153 return r;
1154
1155 if (bc->cf_last->prev_bs_head) {
1156 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1157 if (r)
1158 return r;
1159 }
1160
1161 if (bc->cf_last->prev_bs_head) {
1162 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1163 if (r)
1164 return r;
1165 }
1166
1167 r = check_and_set_bank_swizzle(bc, slots);
1168 if (r)
1169 return r;
1170
1171 for (i = 0, nliteral = 0; i < 5; i++) {
1172 if (slots[i]) {
1173 r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
1174 if (r)
1175 return r;
1176 }
1177 }
1178 bc->cf_last->ndw += align(nliteral, 2);
1179
1180 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1181 * worst case */
1182 if ((bc->cf_last->ndw >> 1) >= 120) {
1183 bc->force_add_cf = 1;
1184 }
1185
1186 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1187 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1188 bc->cf_last->curr_bs_head = NULL;
1189 }
1190 return 0;
1191 }
1192
1193 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
1194 {
1195 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1196 }
1197
1198 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
1199 {
1200 struct r600_bc_vtx *nvtx = r600_bc_vtx();
1201 int r;
1202
1203 if (nvtx == NULL)
1204 return -ENOMEM;
1205 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
1206
1207 /* cf can contains only alu or only vtx or only tex */
1208 if (bc->cf_last == NULL ||
1209 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1210 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
1211 bc->force_add_cf) {
1212 r = r600_bc_add_cf(bc);
1213 if (r) {
1214 free(nvtx);
1215 return r;
1216 }
1217 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1218 }
1219 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1220 /* each fetch use 4 dwords */
1221 bc->cf_last->ndw += 4;
1222 bc->ndw += 4;
1223 if ((bc->cf_last->ndw / 4) > 7)
1224 bc->force_add_cf = 1;
1225 return 0;
1226 }
1227
1228 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
1229 {
1230 struct r600_bc_tex *ntex = r600_bc_tex();
1231 int r;
1232
1233 if (ntex == NULL)
1234 return -ENOMEM;
1235 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
1236
1237 /* cf can contains only alu or only vtx or only tex */
1238 if (bc->cf_last == NULL ||
1239 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1240 bc->force_add_cf) {
1241 r = r600_bc_add_cf(bc);
1242 if (r) {
1243 free(ntex);
1244 return r;
1245 }
1246 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1247 }
1248 if (ntex->src_gpr >= bc->ngpr) {
1249 bc->ngpr = ntex->src_gpr + 1;
1250 }
1251 if (ntex->dst_gpr >= bc->ngpr) {
1252 bc->ngpr = ntex->dst_gpr + 1;
1253 }
1254 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1255 /* each texture fetch use 4 dwords */
1256 bc->cf_last->ndw += 4;
1257 bc->ndw += 4;
1258 if ((bc->cf_last->ndw / 4) > 7)
1259 bc->force_add_cf = 1;
1260 return 0;
1261 }
1262
1263 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
1264 {
1265 int r;
1266 r = r600_bc_add_cf(bc);
1267 if (r)
1268 return r;
1269
1270 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1271 bc->cf_last->inst = inst;
1272 return 0;
1273 }
1274
1275 /* common to all 3 families */
1276 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
1277 {
1278 unsigned fetch_resource_start = 0;
1279
1280 /* check if we are fetch shader */
1281 /* fetch shader can also access vertex resource,
1282 * first fetch shader resource is at 160
1283 */
1284 if (bc->type == -1) {
1285 switch (bc->chiprev) {
1286 /* r600 */
1287 case CHIPREV_R600:
1288 /* r700 */
1289 case CHIPREV_R700:
1290 fetch_resource_start = 160;
1291 break;
1292 /* evergreen */
1293 case CHIPREV_EVERGREEN:
1294 fetch_resource_start = 0;
1295 break;
1296 default:
1297 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
1298 __FILE__, __func__, __LINE__, bc->chiprev);
1299 break;
1300 }
1301 }
1302 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
1303 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1304 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
1305 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1306 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1307 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1308 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1309 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1310 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1311 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1312 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1313 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1314 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1315 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1316 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
1317 bc->bytecode[id++] = 0;
1318 return 0;
1319 }
1320
1321 /* common to all 3 families */
1322 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
1323 {
1324 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1325 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1326 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1327 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1328 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1329 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1330 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1331 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1332 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1333 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1334 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1335 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1336 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1337 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1338 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1339 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1340 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1341 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1342 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1343 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1344 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1345 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1346 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1347 bc->bytecode[id++] = 0;
1348 return 0;
1349 }
1350
1351 /* r600 only, r700/eg bits in r700_asm.c */
1352 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1353 {
1354 /* don't replace gpr by pv or ps for destination register */
1355 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1356 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1357 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1358 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1359 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1360 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1361 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1362 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1363 S_SQ_ALU_WORD0_LAST(alu->last);
1364
1365 if (alu->is_op3) {
1366 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1367 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1368 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1369 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1370 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1371 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1372 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1373 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1374 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1375 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1376 } else {
1377 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1378 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1379 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1380 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1381 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1382 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1383 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1384 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1385 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1386 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1387 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1388 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1389 }
1390 return 0;
1391 }
1392
1393 /* common for r600/r700 - eg in eg_asm.c */
1394 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1395 {
1396 unsigned id = cf->id;
1397
1398 switch (cf->inst) {
1399 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1400 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1401 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1402 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1403 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1404 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1405 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1406 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1407
1408 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1409 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1410 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1411 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1412 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1413 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
1414 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1415 break;
1416 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1417 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1418 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1419 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1420 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1421 S_SQ_CF_WORD1_BARRIER(1) |
1422 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1423 break;
1424 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1425 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1426 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1427 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1428 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1429 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1430 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1431 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1432 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1433 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1434 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1435 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1436 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1437 break;
1438 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1439 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1440 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1441 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1442 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1443 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1444 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1445 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1446 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1447 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1448 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1449 S_SQ_CF_WORD1_BARRIER(1) |
1450 S_SQ_CF_WORD1_COND(cf->cond) |
1451 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1452
1453 break;
1454 default:
1455 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1456 return -EINVAL;
1457 }
1458 return 0;
1459 }
1460
1461 int r600_bc_build(struct r600_bc *bc)
1462 {
1463 struct r600_bc_cf *cf;
1464 struct r600_bc_alu *alu;
1465 struct r600_bc_vtx *vtx;
1466 struct r600_bc_tex *tex;
1467 uint32_t literal[4];
1468 unsigned nliteral;
1469 unsigned addr;
1470 int i, r;
1471
1472 if (bc->callstack[0].max > 0)
1473 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1474 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1475 bc->nstack = 1;
1476 }
1477
1478 /* first path compute addr of each CF block */
1479 /* addr start after all the CF instructions */
1480 addr = bc->cf_last->id + 2;
1481 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1482 switch (cf->inst) {
1483 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1484 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1485 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1486 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1487 break;
1488 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1489 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1490 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1491 /* fetch node need to be 16 bytes aligned*/
1492 addr += 3;
1493 addr &= 0xFFFFFFFCUL;
1494 break;
1495 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1496 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1497 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1498 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1499 break;
1500 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1501 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1502 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1503 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1504 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1505 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1506 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1507 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1508 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1509 break;
1510 default:
1511 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1512 return -EINVAL;
1513 }
1514 cf->addr = addr;
1515 addr += cf->ndw;
1516 bc->ndw = cf->addr + cf->ndw;
1517 }
1518 free(bc->bytecode);
1519 bc->bytecode = calloc(1, bc->ndw * 4);
1520 if (bc->bytecode == NULL)
1521 return -ENOMEM;
1522 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1523 addr = cf->addr;
1524 if (bc->chiprev == CHIPREV_EVERGREEN)
1525 r = eg_bc_cf_build(bc, cf);
1526 else
1527 r = r600_bc_cf_build(bc, cf);
1528 if (r)
1529 return r;
1530 switch (cf->inst) {
1531 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1532 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1533 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1534 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1535 nliteral = 0;
1536 memset(literal, 0, sizeof(literal));
1537 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1538 r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1539 if (r)
1540 return r;
1541 r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
1542 switch(bc->chiprev) {
1543 case CHIPREV_R600:
1544 r = r600_bc_alu_build(bc, alu, addr);
1545 break;
1546 case CHIPREV_R700:
1547 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
1548 r = r700_bc_alu_build(bc, alu, addr);
1549 break;
1550 default:
1551 R600_ERR("unknown family %d\n", bc->family);
1552 return -EINVAL;
1553 }
1554 if (r)
1555 return r;
1556 addr += 2;
1557 if (alu->last) {
1558 for (i = 0; i < align(nliteral, 2); ++i) {
1559 bc->bytecode[addr++] = literal[i];
1560 }
1561 nliteral = 0;
1562 memset(literal, 0, sizeof(literal));
1563 }
1564 }
1565 break;
1566 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1567 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1568 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1569 r = r600_bc_vtx_build(bc, vtx, addr);
1570 if (r)
1571 return r;
1572 addr += 4;
1573 }
1574 break;
1575 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1576 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1577 r = r600_bc_tex_build(bc, tex, addr);
1578 if (r)
1579 return r;
1580 addr += 4;
1581 }
1582 break;
1583 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1584 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1585 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1586 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1587 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1588 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1589 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1590 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1591 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1592 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1593 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1594 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1595 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1596 break;
1597 default:
1598 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1599 return -EINVAL;
1600 }
1601 }
1602 return 0;
1603 }
1604
1605 void r600_bc_clear(struct r600_bc *bc)
1606 {
1607 struct r600_bc_cf *cf = NULL, *next_cf;
1608
1609 free(bc->bytecode);
1610 bc->bytecode = NULL;
1611
1612 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1613 struct r600_bc_alu *alu = NULL, *next_alu;
1614 struct r600_bc_tex *tex = NULL, *next_tex;
1615 struct r600_bc_tex *vtx = NULL, *next_vtx;
1616
1617 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1618 free(alu);
1619 }
1620
1621 LIST_INITHEAD(&cf->alu);
1622
1623 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1624 free(tex);
1625 }
1626
1627 LIST_INITHEAD(&cf->tex);
1628
1629 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1630 free(vtx);
1631 }
1632
1633 LIST_INITHEAD(&cf->vtx);
1634
1635 free(cf);
1636 }
1637
1638 LIST_INITHEAD(&cf->list);
1639 }
1640
1641 void r600_bc_dump(struct r600_bc *bc)
1642 {
1643 struct r600_bc_cf *cf = NULL;
1644 struct r600_bc_alu *alu = NULL;
1645 struct r600_bc_vtx *vtx = NULL;
1646 struct r600_bc_tex *tex = NULL;
1647
1648 unsigned i, id;
1649 uint32_t literal[4];
1650 unsigned nliteral;
1651 char chip = '6';
1652
1653 switch (bc->chiprev) {
1654 case 1:
1655 chip = '7';
1656 break;
1657 case 2:
1658 chip = 'E';
1659 break;
1660 case 0:
1661 default:
1662 chip = '6';
1663 break;
1664 }
1665 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1666 fprintf(stderr, " %c\n", chip);
1667
1668 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1669 id = cf->id;
1670
1671 switch (cf->inst) {
1672 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1673 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1674 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1675 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1676 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1677 fprintf(stderr, "ADDR:%d ", cf->addr);
1678 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1679 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1680 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1681 id++;
1682 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1683 fprintf(stderr, "INST:%d ", cf->inst);
1684 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1685 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1686 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1687 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1688 break;
1689 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1690 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1691 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1692 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1693 fprintf(stderr, "ADDR:%d\n", cf->addr);
1694 id++;
1695 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1696 fprintf(stderr, "INST:%d ", cf->inst);
1697 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1698 break;
1699 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1700 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1701 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1702 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1703 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1704 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1705 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1706 id++;
1707 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1708 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1709 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1710 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1711 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1712 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1713 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1714 fprintf(stderr, "INST:%d ", cf->output.inst);
1715 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1716 break;
1717 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1718 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1719 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1720 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1721 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1722 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1723 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1724 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1725 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1726 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1727 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1728 id++;
1729 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1730 fprintf(stderr, "INST:%d ", cf->inst);
1731 fprintf(stderr, "COND:%X ", cf->cond);
1732 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1733 break;
1734 }
1735
1736 id = cf->addr;
1737 nliteral = 0;
1738 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1739 r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1740
1741 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1742 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1743 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1744 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1745 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1746 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1747 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1748 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1749 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1750 fprintf(stderr, "LAST:%d)\n", alu->last);
1751 id++;
1752 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1753 fprintf(stderr, "INST:%d ", alu->inst);
1754 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1755 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1756 fprintf(stderr, "REL:%d ", alu->dst.rel);
1757 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1758 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1759 if (alu->is_op3) {
1760 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1761 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1762 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1763 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1764 } else {
1765 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1766 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1767 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1768 fprintf(stderr, "OMOD:%d ", alu->omod);
1769 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1770 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1771 }
1772
1773 id++;
1774 if (alu->last) {
1775 for (i = 0; i < nliteral; i++, id++) {
1776 float *f = (float*)(bc->bytecode + id);
1777 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1778 }
1779 id += nliteral & 1;
1780 nliteral = 0;
1781 }
1782 }
1783
1784 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1785 //TODO
1786 }
1787
1788 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1789 //TODO
1790 }
1791 }
1792
1793 fprintf(stderr, "--------------------------------------\n");
1794 }
1795
1796 void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1797 {
1798 struct r600_pipe_state *rstate;
1799 unsigned i = 0;
1800
1801 if (count > 8) {
1802 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1803 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1804 S_SQ_CF_WORD1_BARRIER(1) |
1805 S_SQ_CF_WORD1_COUNT(8 - 1);
1806 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1807 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1808 S_SQ_CF_WORD1_BARRIER(1) |
1809 S_SQ_CF_WORD1_COUNT(count - 8 - 1);
1810 } else {
1811 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1812 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1813 S_SQ_CF_WORD1_BARRIER(1) |
1814 S_SQ_CF_WORD1_COUNT(count - 1);
1815 }
1816 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1817 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1818 S_SQ_CF_WORD1_BARRIER(1);
1819
1820 rstate = &ve->rstate;
1821 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1822 rstate->nregs = 0;
1823 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1824 0x00000000, 0xFFFFFFFF, NULL);
1825 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1826 0x00000000, 0xFFFFFFFF, NULL);
1827 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1828 r600_bo_offset(ve->fetch_shader) >> 8,
1829 0xFFFFFFFF, ve->fetch_shader);
1830 }
1831
1832 void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1833 {
1834 struct r600_pipe_state *rstate;
1835 unsigned i = 0;
1836
1837 if (count > 8) {
1838 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1839 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1840 S_SQ_CF_WORD1_BARRIER(1) |
1841 S_SQ_CF_WORD1_COUNT(8 - 1);
1842 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1843 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1844 S_SQ_CF_WORD1_BARRIER(1) |
1845 S_SQ_CF_WORD1_COUNT((count - 8) - 1);
1846 } else {
1847 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1848 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1849 S_SQ_CF_WORD1_BARRIER(1) |
1850 S_SQ_CF_WORD1_COUNT(count - 1);
1851 }
1852 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1853 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1854 S_SQ_CF_WORD1_BARRIER(1);
1855
1856 rstate = &ve->rstate;
1857 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1858 rstate->nregs = 0;
1859 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1860 0x00000000, 0xFFFFFFFF, NULL);
1861 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1862 0x00000000, 0xFFFFFFFF, NULL);
1863 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1864 r600_bo_offset(ve->fetch_shader) >> 8,
1865 0xFFFFFFFF, ve->fetch_shader);
1866 }
1867
1868 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1869 unsigned *num_format, unsigned *format_comp)
1870 {
1871 const struct util_format_description *desc;
1872 unsigned i;
1873
1874 *format = 0;
1875 *num_format = 0;
1876 *format_comp = 0;
1877
1878 desc = util_format_description(pformat);
1879 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1880 goto out_unknown;
1881 }
1882
1883 /* Find the first non-VOID channel. */
1884 for (i = 0; i < 4; i++) {
1885 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1886 break;
1887 }
1888 }
1889
1890 switch (desc->channel[i].type) {
1891 /* Half-floats, floats, doubles */
1892 case UTIL_FORMAT_TYPE_FLOAT:
1893 switch (desc->channel[i].size) {
1894 case 16:
1895 switch (desc->nr_channels) {
1896 case 1:
1897 *format = FMT_16_FLOAT;
1898 break;
1899 case 2:
1900 *format = FMT_16_16_FLOAT;
1901 break;
1902 case 3:
1903 *format = FMT_16_16_16_FLOAT;
1904 break;
1905 case 4:
1906 *format = FMT_16_16_16_16_FLOAT;
1907 break;
1908 }
1909 break;
1910 case 32:
1911 switch (desc->nr_channels) {
1912 case 1:
1913 *format = FMT_32_FLOAT;
1914 break;
1915 case 2:
1916 *format = FMT_32_32_FLOAT;
1917 break;
1918 case 3:
1919 *format = FMT_32_32_32_FLOAT;
1920 break;
1921 case 4:
1922 *format = FMT_32_32_32_32_FLOAT;
1923 break;
1924 }
1925 break;
1926 default:
1927 goto out_unknown;
1928 }
1929 break;
1930 /* Unsigned ints */
1931 case UTIL_FORMAT_TYPE_UNSIGNED:
1932 /* Signed ints */
1933 case UTIL_FORMAT_TYPE_SIGNED:
1934 switch (desc->channel[i].size) {
1935 case 8:
1936 switch (desc->nr_channels) {
1937 case 1:
1938 *format = FMT_8;
1939 break;
1940 case 2:
1941 *format = FMT_8_8;
1942 break;
1943 case 3:
1944 // *format = FMT_8_8_8; /* fails piglit draw-vertices test */
1945 // break;
1946 case 4:
1947 *format = FMT_8_8_8_8;
1948 break;
1949 }
1950 break;
1951 case 16:
1952 switch (desc->nr_channels) {
1953 case 1:
1954 *format = FMT_16;
1955 break;
1956 case 2:
1957 *format = FMT_16_16;
1958 break;
1959 case 3:
1960 // *format = FMT_16_16_16; /* fails piglit draw-vertices test */
1961 // break;
1962 case 4:
1963 *format = FMT_16_16_16_16;
1964 break;
1965 }
1966 break;
1967 case 32:
1968 switch (desc->nr_channels) {
1969 case 1:
1970 *format = FMT_32;
1971 break;
1972 case 2:
1973 *format = FMT_32_32;
1974 break;
1975 case 3:
1976 *format = FMT_32_32_32;
1977 break;
1978 case 4:
1979 *format = FMT_32_32_32_32;
1980 break;
1981 }
1982 break;
1983 default:
1984 goto out_unknown;
1985 }
1986 break;
1987 default:
1988 goto out_unknown;
1989 }
1990
1991 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1992 *format_comp = 1;
1993 }
1994 if (desc->channel[i].normalized) {
1995 *num_format = 0;
1996 } else {
1997 *num_format = 2;
1998 }
1999 return;
2000 out_unknown:
2001 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2002 }
2003
2004 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2005 {
2006 unsigned ndw, i;
2007 u32 *bytecode;
2008 unsigned fetch_resource_start = 0, format, num_format, format_comp;
2009 struct pipe_vertex_element *elements = ve->elements;
2010 const struct util_format_description *desc;
2011
2012 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
2013 ndw = 8 + ve->count * 4;
2014 ve->fs_size = ndw * 4;
2015
2016 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
2017 ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
2018 if (ve->fetch_shader == NULL) {
2019 return -ENOMEM;
2020 }
2021
2022 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
2023 if (bytecode == NULL) {
2024 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2025 return -ENOMEM;
2026 }
2027
2028 if (rctx->family >= CHIP_CEDAR) {
2029 eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2030 } else {
2031 r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2032 fetch_resource_start = 160;
2033 }
2034
2035 /* vertex elements offset need special handling, if offset is bigger
2036 * than what we can put in fetch instruction then we need to alterate
2037 * the vertex resource offset. In such case in order to simplify code
2038 * we will bound one resource per elements. It's a worst case scenario.
2039 */
2040 for (i = 0; i < ve->count; i++) {
2041 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2042 if (ve->vbuffer_offset[i]) {
2043 ve->vbuffer_need_offset = 1;
2044 }
2045 }
2046
2047 for (i = 0; i < ve->count; i++) {
2048 unsigned vbuffer_index;
2049 r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
2050 desc = util_format_description(ve->hw_format[i]);
2051 if (desc == NULL) {
2052 R600_ERR("unknown format %d\n", ve->hw_format[i]);
2053 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2054 return -EINVAL;
2055 }
2056
2057 /* see above for vbuffer_need_offset explanation */
2058 vbuffer_index = elements[i].vertex_buffer_index;
2059 if (ve->vbuffer_need_offset) {
2060 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
2061 } else {
2062 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
2063 }
2064 bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
2065 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
2066 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
2067 bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
2068 S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
2069 S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
2070 S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
2071 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
2072 S_SQ_VTX_WORD1_DATA_FORMAT(format) |
2073 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
2074 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
2075 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
2076 S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
2077 bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
2078 S_SQ_VTX_WORD2_MEGA_FETCH(1);
2079 bytecode[8 + i * 4 + 3] = 0;
2080 }
2081 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
2082 return 0;
2083 }