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r600g: implement replacing gpr with pv and ps
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
39 {
40 if(alu->is_op3)
41 return 3;
42
43 switch (alu->inst) {
44 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
45 return 0;
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
65 return 2;
66
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
80 return 1;
81 default: R600_ERR(
82 "Need instruction operand number for 0x%x.\n", alu->inst);
83 };
84
85 return 3;
86 }
87
88 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
89
90 static struct r600_bc_cf *r600_bc_cf(void)
91 {
92 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
93
94 if (cf == NULL)
95 return NULL;
96 LIST_INITHEAD(&cf->list);
97 LIST_INITHEAD(&cf->alu);
98 LIST_INITHEAD(&cf->vtx);
99 LIST_INITHEAD(&cf->tex);
100 return cf;
101 }
102
103 static struct r600_bc_alu *r600_bc_alu(void)
104 {
105 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
106
107 if (alu == NULL)
108 return NULL;
109 LIST_INITHEAD(&alu->list);
110 return alu;
111 }
112
113 static struct r600_bc_vtx *r600_bc_vtx(void)
114 {
115 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
116
117 if (vtx == NULL)
118 return NULL;
119 LIST_INITHEAD(&vtx->list);
120 return vtx;
121 }
122
123 static struct r600_bc_tex *r600_bc_tex(void)
124 {
125 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
126
127 if (tex == NULL)
128 return NULL;
129 LIST_INITHEAD(&tex->list);
130 return tex;
131 }
132
133 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
134 {
135 LIST_INITHEAD(&bc->cf);
136 bc->family = family;
137 switch (bc->family) {
138 case CHIP_R600:
139 case CHIP_RV610:
140 case CHIP_RV630:
141 case CHIP_RV670:
142 case CHIP_RV620:
143 case CHIP_RV635:
144 case CHIP_RS780:
145 case CHIP_RS880:
146 bc->chiprev = CHIPREV_R600;
147 break;
148 case CHIP_RV770:
149 case CHIP_RV730:
150 case CHIP_RV710:
151 case CHIP_RV740:
152 bc->chiprev = CHIPREV_R700;
153 break;
154 case CHIP_CEDAR:
155 case CHIP_REDWOOD:
156 case CHIP_JUNIPER:
157 case CHIP_CYPRESS:
158 case CHIP_HEMLOCK:
159 case CHIP_PALM:
160 bc->chiprev = CHIPREV_EVERGREEN;
161 break;
162 default:
163 R600_ERR("unknown family %d\n", bc->family);
164 return -EINVAL;
165 }
166 return 0;
167 }
168
169 static int r600_bc_add_cf(struct r600_bc *bc)
170 {
171 struct r600_bc_cf *cf = r600_bc_cf();
172
173 if (cf == NULL)
174 return -ENOMEM;
175 LIST_ADDTAIL(&cf->list, &bc->cf);
176 if (bc->cf_last)
177 cf->id = bc->cf_last->id + 2;
178 bc->cf_last = cf;
179 bc->ncf++;
180 bc->ndw += 2;
181 bc->force_add_cf = 0;
182 return 0;
183 }
184
185 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
186 {
187 int r;
188
189 r = r600_bc_add_cf(bc);
190 if (r)
191 return r;
192 bc->cf_last->inst = output->inst;
193 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
194 return 0;
195 }
196
197 /* alu instructions that can ony exits once per group */
198 static int is_alu_once_inst(struct r600_bc_alu *alu)
199 {
200 return !alu->is_op3 && (
201 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
202 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
203 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
204 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
205 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
206 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
207 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
208 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
209 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
210 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
211 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
212 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
213 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
214 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
215 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
216 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
217 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
218 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
219 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
220 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
221 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
222 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
223 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
224 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
225 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
226 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
227 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
228 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
229 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
230 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
231 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
232 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
233 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
234 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
235 }
236
237 static int is_alu_reduction_inst(struct r600_bc_alu *alu)
238 {
239 return !alu->is_op3 && (
240 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
241 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
242 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
243 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
244 }
245
246 static int is_alu_mova_inst(struct r600_bc_alu *alu)
247 {
248 return !alu->is_op3 && (
249 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
250 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
251 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
252 }
253
254 /* alu instructions that can only execute on the vector unit */
255 static int is_alu_vec_unit_inst(struct r600_bc_alu *alu)
256 {
257 return is_alu_reduction_inst(alu) ||
258 is_alu_mova_inst(alu);
259 }
260
261 /* alu instructions that can only execute on the trans unit */
262 static int is_alu_trans_unit_inst(struct r600_bc_alu *alu)
263 {
264 if(!alu->is_op3)
265 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
266 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
267 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
268 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
269 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
270 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
271 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
272 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
273 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
274 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
275 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
276 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
277 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
278 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
279 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
280 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
281 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
282 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
283 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
284 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
285 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
286 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
287 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
288 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
289 else
290 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
291 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
292 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
293 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
294 }
295
296 /* alu instructions that can execute on any unit */
297 static int is_alu_any_unit_inst(struct r600_bc_alu *alu)
298 {
299 return !is_alu_vec_unit_inst(alu) &&
300 !is_alu_trans_unit_inst(alu);
301 }
302
303 static int assign_alu_units(struct r600_bc_alu *alu_first, struct r600_bc_alu *assignment[5])
304 {
305 struct r600_bc_alu *alu;
306 unsigned i, chan, trans;
307
308 for (i = 0; i < 5; i++)
309 assignment[i] = NULL;
310
311 for (alu = alu_first; alu; alu = container_of(alu->list.next, alu, list)) {
312 chan = alu->dst.chan;
313 if (is_alu_trans_unit_inst(alu))
314 trans = 1;
315 else if (is_alu_vec_unit_inst(alu))
316 trans = 0;
317 else if (assignment[chan])
318 trans = 1; // assume ALU_INST_PREFER_VECTOR
319 else
320 trans = 0;
321
322 if (trans) {
323 if (assignment[4]) {
324 assert(0); //ALU.Trans has already been allocated
325 return -1;
326 }
327 assignment[4] = alu;
328 } else {
329 if (assignment[chan]) {
330 assert(0); //ALU.chan has already been allocated
331 return -1;
332 }
333 assignment[chan] = alu;
334 }
335
336 if (alu->last)
337 break;
338 }
339 return 0;
340 }
341
342 struct alu_bank_swizzle {
343 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
344 int hw_cfile_addr[4];
345 int hw_cfile_elem[4];
346 };
347
348 const unsigned cycle_for_bank_swizzle_vec[][3] = {
349 [SQ_ALU_VEC_012] = { 0, 1, 2 },
350 [SQ_ALU_VEC_021] = { 0, 2, 1 },
351 [SQ_ALU_VEC_120] = { 1, 2, 0 },
352 [SQ_ALU_VEC_102] = { 1, 0, 2 },
353 [SQ_ALU_VEC_201] = { 2, 0, 1 },
354 [SQ_ALU_VEC_210] = { 2, 1, 0 }
355 };
356
357 const unsigned cycle_for_bank_swizzle_scl[][3] = {
358 [SQ_ALU_SCL_210] = { 2, 1, 0 },
359 [SQ_ALU_SCL_122] = { 1, 2, 2 },
360 [SQ_ALU_SCL_212] = { 2, 1, 2 },
361 [SQ_ALU_SCL_221] = { 2, 2, 1 }
362 };
363
364 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
365 {
366 int i, cycle, component;
367 /* set up gpr use */
368 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
369 for (component = 0; component < NUM_OF_COMPONENTS; component++)
370 bs->hw_gpr[cycle][component] = -1;
371 for (i = 0; i < 4; i++)
372 bs->hw_cfile_addr[i] = -1;
373 for (i = 0; i < 4; i++)
374 bs->hw_cfile_elem[i] = -1;
375 }
376
377 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
378 {
379 if (bs->hw_gpr[cycle][chan] == -1)
380 bs->hw_gpr[cycle][chan] = sel;
381 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
382 // Another scalar operation has already used GPR read port for channel
383 return -1;
384 }
385 return 0;
386 }
387
388 static int reserve_cfile(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
389 {
390 int res, resmatch = -1, resempty = -1;
391 for (res = 3; res >= 0; --res) {
392 if (bs->hw_cfile_addr[res] == -1)
393 resempty = res;
394 else if (bs->hw_cfile_addr[res] == sel &&
395 bs->hw_cfile_elem[res] == chan)
396 resmatch = res;
397 }
398 if (resmatch != -1)
399 return 0; // Read for this scalar element already reserved, nothing to do here.
400 else if (resempty != -1) {
401 bs->hw_cfile_addr[resempty] = sel;
402 bs->hw_cfile_elem[resempty] = chan;
403 } else {
404 // All cfile read ports are used, cannot reference vector element
405 return -1;
406 }
407 return 0;
408 }
409
410 static int is_gpr(unsigned sel)
411 {
412 return (sel >= 0 && sel <= 127);
413 }
414
415 static int is_cfile(unsigned sel)
416 {
417 return (sel > 255 && sel < 512);
418 }
419
420 static int is_const(int sel)
421 {
422 return is_cfile(sel) ||
423 (sel >= V_SQ_ALU_SRC_0 &&
424 sel <= V_SQ_ALU_SRC_LITERAL);
425 }
426
427 static int check_vector(struct r600_bc_alu *alu, struct alu_bank_swizzle *bs, int bank_swizzle)
428 {
429 int r, src, num_src, sel, elem, cycle;
430
431 num_src = r600_bc_get_num_operands(alu);
432 for (src = 0; src < num_src; src++) {
433 sel = alu->src[src].sel;
434 elem = alu->src[src].chan;
435 if (is_gpr(sel)) {
436 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
437 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
438 // Nothing to do; special-case optimization,
439 // second source uses first source’s reservation
440 continue;
441 else {
442 r = reserve_gpr(bs, sel, elem, cycle);
443 if (r)
444 return r;
445 }
446 } else if (is_cfile(sel)) {
447 r = reserve_cfile(bs, sel, elem);
448 if (r)
449 return r;
450 }
451 // No restrictions on PV, PS, literal or special constants
452 }
453 return 0;
454 }
455
456 static int check_scalar(struct r600_bc_alu *alu, struct alu_bank_swizzle *bs, int bank_swizzle)
457 {
458 int r, src, num_src, const_count, sel, elem, cycle;
459
460 num_src = r600_bc_get_num_operands(alu);
461 for (const_count = 0, src = 0; src < num_src; ++src) {
462 sel = alu->src[src].sel;
463 elem = alu->src[src].chan;
464 if (is_const(sel)) { // Any constant, including literal and inline constants
465 if (const_count >= 2)
466 // More than two references to a constant in
467 // transcendental operation.
468 return -1;
469 else
470 const_count++;
471 }
472 if (is_cfile(sel)) {
473 r = reserve_cfile(bs, sel, elem);
474 if (r)
475 return r;
476 }
477 }
478 for (src = 0; src < num_src; ++src) {
479 sel = alu->src[src].sel;
480 elem = alu->src[src].chan;
481 if (is_gpr(sel)) {
482 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
483 if (cycle < const_count)
484 // Cycle for GPR load conflicts with
485 // constant load in transcendental operation.
486 return -1;
487 r = reserve_gpr(bs, sel, elem, cycle);
488 if (r)
489 return r;
490 }
491 // Constants already processed
492 // No restrictions on PV, PS
493 }
494 return 0;
495 }
496
497 static int check_and_set_bank_swizzle(struct r600_bc *bc, struct r600_bc_alu *alu_first)
498 {
499 struct r600_bc_alu *assignment[5];
500 struct alu_bank_swizzle bs;
501 int bank_swizzle[5];
502 int i, r;
503
504 r = assign_alu_units(alu_first, assignment);
505 if (r)
506 return r;
507
508 if(alu_first->bank_swizzle_force) {
509 for (i = 0; i < 5; i++)
510 if (assignment[i])
511 assignment[i]->bank_swizzle = assignment[i]->bank_swizzle_force;
512 return 0;
513 }
514
515 // just check every possible combination of bank swizzle
516 // not very efficent, but works on the first try in most of the cases
517 for (i = 0; i < 4; i++)
518 bank_swizzle[i] = SQ_ALU_VEC_012;
519 bank_swizzle[4] = SQ_ALU_SCL_210;
520 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
521 init_bank_swizzle(&bs);
522 for (i = 0; i < 4; i++) {
523 if (assignment[i]) {
524 r = check_vector(assignment[i], &bs, bank_swizzle[i]);
525 if (r)
526 break;
527 }
528 }
529 if (!r && assignment[4]) {
530 r = check_scalar(assignment[4], &bs, bank_swizzle[4]);
531 }
532 if (!r) {
533 for (i = 0; i < 5; i++) {
534 if (assignment[i])
535 assignment[i]->bank_swizzle = bank_swizzle[i];
536 }
537 return 0;
538 }
539
540 for (i = 0; i < 5; i++) {
541 bank_swizzle[i]++;
542 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
543 break;
544 else
545 bank_swizzle[i] = SQ_ALU_VEC_012;
546 }
547 }
548
549 // couldn't find a working swizzle
550 return -1;
551 }
552
553 static int replace_gpr_with_pv_ps(struct r600_bc_alu *alu_first, struct r600_bc_alu *alu_prev)
554 {
555 struct r600_bc_alu *slots[5];
556 int gpr[5], chan[5];
557 int i, j, r, src, num_src;
558
559 r = assign_alu_units(alu_prev, slots);
560 if (r)
561 return r;
562
563 for (i = 0; i < 5; ++i) {
564 if(slots[i] && slots[i]->dst.write && !slots[i]->dst.rel) {
565 gpr[i] = slots[i]->dst.sel;
566 if (is_alu_reduction_inst(slots[i]))
567 chan[i] = 0;
568 else
569 chan[i] = slots[i]->dst.chan;
570 } else
571 gpr[i] = -1;
572
573 }
574
575 r = assign_alu_units(alu_first, slots);
576 if (r)
577 return r;
578
579 for (i = 0; i < 5; ++i) {
580 struct r600_bc_alu *alu = slots[i];
581 if(!alu)
582 continue;
583
584 num_src = r600_bc_get_num_operands(alu);
585 for (src = 0; src < num_src; ++src) {
586 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
587 continue;
588
589 if (alu->src[src].sel == gpr[4] &&
590 alu->src[src].chan == chan[4]) {
591 alu->src[src].sel = V_SQ_ALU_SRC_PS;
592 alu->src[src].chan = 0;
593 continue;
594 }
595
596 for (j = 0; j < 4; ++j) {
597 if (alu->src[src].sel == gpr[j] &&
598 alu->src[src].chan == j) {
599 alu->src[src].sel = V_SQ_ALU_SRC_PV;
600 alu->src[src].chan = chan[j];
601 break;
602 }
603 }
604 }
605 }
606
607 return 0;
608 }
609
610 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
611 {
612 struct r600_bc_alu *nalu = r600_bc_alu();
613 struct r600_bc_alu *lalu;
614 int i, r;
615
616 if (nalu == NULL)
617 return -ENOMEM;
618 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
619 nalu->nliteral = 0;
620
621 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
622 /* check if we could add it anyway */
623 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
624 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
625 LIST_FOR_EACH_ENTRY(alu, &bc->cf_last->alu, list) {
626 if (alu->predicate) {
627 bc->force_add_cf = 1;
628 break;
629 }
630 }
631 } else
632 bc->force_add_cf = 1;
633 }
634
635 /* cf can contains only alu or only vtx or only tex */
636 if (bc->cf_last == NULL || bc->force_add_cf) {
637 r = r600_bc_add_cf(bc);
638 if (r) {
639 free(nalu);
640 return r;
641 }
642 }
643 bc->cf_last->inst = (type << 3);
644 if (!bc->cf_last->curr_bs_head) {
645 bc->cf_last->curr_bs_head = nalu;
646 }
647 /* at most 128 slots, one add alu can add 4 slots + 4 constants(2 slots)
648 * worst case */
649 if (alu->last && (bc->cf_last->ndw >> 1) >= 120) {
650 bc->force_add_cf = 1;
651 }
652 /* number of gpr == the last gpr used in any alu */
653 for (i = 0; i < 3; i++) {
654 if (alu->src[i].sel >= bc->ngpr && alu->src[i].sel < 128) {
655 bc->ngpr = alu->src[i].sel + 1;
656 }
657 /* compute how many literal are needed
658 * either 2 or 4 literals
659 */
660 if (alu->src[i].sel == 253) {
661 if (((alu->src[i].chan + 2) & 0x6) > nalu->nliteral) {
662 nalu->nliteral = (alu->src[i].chan + 2) & 0x6;
663 }
664 }
665 }
666 if (!LIST_IS_EMPTY(&bc->cf_last->alu)) {
667 lalu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
668 if (!lalu->last && lalu->nliteral > nalu->nliteral) {
669 nalu->nliteral = lalu->nliteral;
670 }
671 }
672 if (alu->dst.sel >= bc->ngpr) {
673 bc->ngpr = alu->dst.sel + 1;
674 }
675 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
676 /* each alu use 2 dwords */
677 bc->cf_last->ndw += 2;
678 bc->ndw += 2;
679
680 bc->cf_last->kcache0_mode = 2;
681
682 /* process cur ALU instructions for bank swizzle */
683 if (alu->last) {
684 if (bc->cf_last->prev_bs_head)
685 replace_gpr_with_pv_ps(bc->cf_last->curr_bs_head, bc->cf_last->prev_bs_head);
686 r = check_and_set_bank_swizzle(bc, bc->cf_last->curr_bs_head);
687 if (r)
688 return r;
689 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
690 bc->cf_last->curr_bs_head = NULL;
691 }
692 return 0;
693 }
694
695 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
696 {
697 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
698 }
699
700 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
701 {
702 struct r600_bc_alu *alu;
703
704 if (bc->cf_last == NULL) {
705 return 0;
706 }
707 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
708 return 0;
709 }
710 /* all same on EG */
711 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
712 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
713 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
714 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK ||
715 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE ||
716 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END ||
717 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
718 return 0;
719 }
720 /* same on EG */
721 if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
722 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3)) &&
723 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3)) &&
724 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
725 LIST_IS_EMPTY(&bc->cf_last->alu)) {
726 R600_ERR("last CF is not ALU (%p)\n", bc->cf_last);
727 return -EINVAL;
728 }
729 alu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
730 if (!alu->last || !alu->nliteral || alu->literal_added) {
731 return 0;
732 }
733 memcpy(alu->value, value, 4 * 4);
734 bc->cf_last->ndw += alu->nliteral;
735 bc->ndw += alu->nliteral;
736 alu->literal_added = 1;
737 return 0;
738 }
739
740 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
741 {
742 struct r600_bc_vtx *nvtx = r600_bc_vtx();
743 int r;
744
745 if (nvtx == NULL)
746 return -ENOMEM;
747 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
748
749 /* cf can contains only alu or only vtx or only tex */
750 if (bc->cf_last == NULL ||
751 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
752 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
753 bc->force_add_cf) {
754 r = r600_bc_add_cf(bc);
755 if (r) {
756 free(nvtx);
757 return r;
758 }
759 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
760 }
761 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
762 /* each fetch use 4 dwords */
763 bc->cf_last->ndw += 4;
764 bc->ndw += 4;
765 if ((bc->cf_last->ndw / 4) > 7)
766 bc->force_add_cf = 1;
767 return 0;
768 }
769
770 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
771 {
772 struct r600_bc_tex *ntex = r600_bc_tex();
773 int r;
774
775 if (ntex == NULL)
776 return -ENOMEM;
777 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
778
779 /* cf can contains only alu or only vtx or only tex */
780 if (bc->cf_last == NULL ||
781 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
782 bc->force_add_cf) {
783 r = r600_bc_add_cf(bc);
784 if (r) {
785 free(ntex);
786 return r;
787 }
788 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
789 }
790 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
791 /* each texture fetch use 4 dwords */
792 bc->cf_last->ndw += 4;
793 bc->ndw += 4;
794 if ((bc->cf_last->ndw / 4) > 7)
795 bc->force_add_cf = 1;
796 return 0;
797 }
798
799 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
800 {
801 int r;
802 r = r600_bc_add_cf(bc);
803 if (r)
804 return r;
805
806 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
807 bc->cf_last->inst = inst;
808 return 0;
809 }
810
811 /* common to all 3 families */
812 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
813 {
814 unsigned fetch_resource_start = 0;
815
816 /* check if we are fetch shader */
817 /* fetch shader can also access vertex resource,
818 * first fetch shader resource is at 160
819 */
820 if (bc->type == -1) {
821 switch (bc->chiprev) {
822 /* r600 */
823 case CHIPREV_R600:
824 /* r700 */
825 case CHIPREV_R700:
826 fetch_resource_start = 160;
827 break;
828 /* evergreen */
829 case CHIPREV_EVERGREEN:
830 fetch_resource_start = 0;
831 break;
832 default:
833 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
834 __FILE__, __func__, __LINE__, bc->chiprev);
835 break;
836 }
837 }
838 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
839 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
840 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
841 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
842 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
843 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
844 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
845 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
846 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
847 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
848 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
849 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
850 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
851 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
852 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
853 bc->bytecode[id++] = 0;
854 return 0;
855 }
856
857 /* common to all 3 families */
858 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
859 {
860 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
861 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
862 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
863 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
864 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
865 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
866 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
867 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
868 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
869 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
870 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
871 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
872 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
873 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
874 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
875 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
876 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
877 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
878 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
879 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
880 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
881 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
882 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
883 bc->bytecode[id++] = 0;
884 return 0;
885 }
886
887 /* r600 only, r700/eg bits in r700_asm.c */
888 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
889 {
890 unsigned i;
891
892 /* don't replace gpr by pv or ps for destination register */
893 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
894 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
895 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
896 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
897 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
898 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
899 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
900 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
901 S_SQ_ALU_WORD0_LAST(alu->last);
902
903 if (alu->is_op3) {
904 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
905 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
906 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
907 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
908 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
909 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
910 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
911 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
912 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
913 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
914 } else {
915 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
916 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
917 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
918 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
919 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
920 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
921 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
922 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
923 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
924 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
925 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
926 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
927 }
928 if (alu->last) {
929 if (alu->nliteral && !alu->literal_added) {
930 R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst);
931 }
932 for (i = 0; i < alu->nliteral; i++) {
933 bc->bytecode[id++] = alu->value[i];
934 }
935 }
936 return 0;
937 }
938
939 /* common for r600/r700 - eg in eg_asm.c */
940 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
941 {
942 unsigned id = cf->id;
943
944 switch (cf->inst) {
945 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
946 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
947 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
948 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
949 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
950 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode) |
951 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache0_bank) |
952 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache1_bank);
953
954 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
955 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache1_mode) |
956 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache0_addr) |
957 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache1_addr) |
958 S_SQ_CF_ALU_WORD1_BARRIER(1) |
959 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
960 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
961 break;
962 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
963 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
964 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
965 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
966 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
967 S_SQ_CF_WORD1_BARRIER(1) |
968 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
969 break;
970 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
971 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
972 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
973 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
974 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
975 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
976 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
977 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
978 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
979 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
980 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
981 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
982 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
983 break;
984 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
985 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
986 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
987 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
988 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
989 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
990 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
991 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
992 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
993 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
994 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
995 S_SQ_CF_WORD1_BARRIER(1) |
996 S_SQ_CF_WORD1_COND(cf->cond) |
997 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
998
999 break;
1000 default:
1001 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1002 return -EINVAL;
1003 }
1004 return 0;
1005 }
1006
1007 int r600_bc_build(struct r600_bc *bc)
1008 {
1009 struct r600_bc_cf *cf;
1010 struct r600_bc_alu *alu;
1011 struct r600_bc_vtx *vtx;
1012 struct r600_bc_tex *tex;
1013 unsigned addr;
1014 int r;
1015
1016 if (bc->callstack[0].max > 0)
1017 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1018 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1019 bc->nstack = 1;
1020 }
1021
1022 /* first path compute addr of each CF block */
1023 /* addr start after all the CF instructions */
1024 addr = bc->cf_last->id + 2;
1025 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1026 switch (cf->inst) {
1027 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1028 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1029 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1030 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1031 break;
1032 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1033 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1034 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1035 /* fetch node need to be 16 bytes aligned*/
1036 addr += 3;
1037 addr &= 0xFFFFFFFCUL;
1038 break;
1039 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1040 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1041 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1042 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1043 break;
1044 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1045 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1046 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1047 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1048 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1049 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1050 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1051 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1052 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1053 break;
1054 default:
1055 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1056 return -EINVAL;
1057 }
1058 cf->addr = addr;
1059 addr += cf->ndw;
1060 bc->ndw = cf->addr + cf->ndw;
1061 }
1062 free(bc->bytecode);
1063 bc->bytecode = calloc(1, bc->ndw * 4);
1064 if (bc->bytecode == NULL)
1065 return -ENOMEM;
1066 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1067 addr = cf->addr;
1068 if (bc->chiprev == CHIPREV_EVERGREEN)
1069 r = eg_bc_cf_build(bc, cf);
1070 else
1071 r = r600_bc_cf_build(bc, cf);
1072 if (r)
1073 return r;
1074 switch (cf->inst) {
1075 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1076 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1077 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1078 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1079 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1080 switch(bc->chiprev) {
1081 case CHIPREV_R600:
1082 r = r600_bc_alu_build(bc, alu, addr);
1083 break;
1084 case CHIPREV_R700:
1085 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
1086 r = r700_bc_alu_build(bc, alu, addr);
1087 break;
1088 default:
1089 R600_ERR("unknown family %d\n", bc->family);
1090 return -EINVAL;
1091 }
1092 if (r)
1093 return r;
1094 addr += 2;
1095 if (alu->last) {
1096 addr += alu->nliteral;
1097 }
1098 }
1099 break;
1100 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1101 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1102 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1103 r = r600_bc_vtx_build(bc, vtx, addr);
1104 if (r)
1105 return r;
1106 addr += 4;
1107 }
1108 break;
1109 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1110 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1111 r = r600_bc_tex_build(bc, tex, addr);
1112 if (r)
1113 return r;
1114 addr += 4;
1115 }
1116 break;
1117 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1118 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1119 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1120 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1121 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1122 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1123 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1124 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1125 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1126 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1127 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1128 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1129 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1130 break;
1131 default:
1132 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1133 return -EINVAL;
1134 }
1135 }
1136 return 0;
1137 }
1138
1139 void r600_bc_clear(struct r600_bc *bc)
1140 {
1141 struct r600_bc_cf *cf = NULL, *next_cf;
1142
1143 free(bc->bytecode);
1144 bc->bytecode = NULL;
1145
1146 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1147 struct r600_bc_alu *alu = NULL, *next_alu;
1148 struct r600_bc_tex *tex = NULL, *next_tex;
1149 struct r600_bc_tex *vtx = NULL, *next_vtx;
1150
1151 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1152 free(alu);
1153 }
1154
1155 LIST_INITHEAD(&cf->alu);
1156
1157 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1158 free(tex);
1159 }
1160
1161 LIST_INITHEAD(&cf->tex);
1162
1163 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1164 free(vtx);
1165 }
1166
1167 LIST_INITHEAD(&cf->vtx);
1168
1169 free(cf);
1170 }
1171
1172 LIST_INITHEAD(&cf->list);
1173 }
1174
1175 void r600_bc_dump(struct r600_bc *bc)
1176 {
1177 struct r600_bc_cf *cf;
1178 struct r600_bc_alu *alu;
1179 struct r600_bc_vtx *vtx;
1180 struct r600_bc_tex *tex;
1181
1182 unsigned i, id;
1183 char chip = '6';
1184
1185 switch (bc->chiprev) {
1186 case 1:
1187 chip = '7';
1188 break;
1189 case 2:
1190 chip = 'E';
1191 break;
1192 case 0:
1193 default:
1194 chip = '6';
1195 break;
1196 }
1197 fprintf(stderr, "bytecode %d dw -----------------------\n", bc->ndw);
1198 fprintf(stderr, " %c\n", chip);
1199
1200 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1201 id = cf->id;
1202
1203 switch (cf->inst) {
1204 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1205 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1206 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1207 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1208 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1209 fprintf(stderr, "ADDR:%d ", cf->addr);
1210 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache0_mode);
1211 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache0_bank);
1212 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache1_bank);
1213 id++;
1214 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1215 fprintf(stderr, "INST:%d ", cf->inst);
1216 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache1_mode);
1217 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache0_addr);
1218 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache1_addr);
1219 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1220 break;
1221 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1222 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1223 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1224 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1225 fprintf(stderr, "ADDR:%d\n", cf->addr);
1226 id++;
1227 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1228 fprintf(stderr, "INST:%d ", cf->inst);
1229 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1230 break;
1231 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1232 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1233 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1234 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1235 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1236 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1237 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1238 id++;
1239 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1240 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1241 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1242 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1243 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1244 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1245 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1246 fprintf(stderr, "INST:%d ", cf->output.inst);
1247 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1248 break;
1249 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1250 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1251 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1252 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1253 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1254 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1255 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1256 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1257 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1258 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1259 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1260 id++;
1261 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1262 fprintf(stderr, "INST:%d ", cf->inst);
1263 fprintf(stderr, "COND:%X ", cf->cond);
1264 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1265 break;
1266 }
1267
1268 id = cf->addr;
1269 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1270 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1271 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1272 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1273 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1274 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1275 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1276 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1277 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1278 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1279 fprintf(stderr, "LAST:%d)\n", alu->last);
1280 id++;
1281 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1282 fprintf(stderr, "INST:%d ", alu->inst);
1283 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1284 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1285 fprintf(stderr, "REL:%d ", alu->dst.rel);
1286 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1287 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1288 if (alu->is_op3) {
1289 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1290 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1291 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1292 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1293 } else {
1294 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1295 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1296 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1297 fprintf(stderr, "OMOD:%d ", alu->omod);
1298 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1299 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1300 }
1301
1302 id++;
1303 if (alu->last) {
1304 for (i = 0; i < alu->nliteral; i++, id++) {
1305 float *f = (float*)(bc->bytecode + id);
1306 fprintf(stderr, "%04d %08X %f\n", id, bc->bytecode[id], *f);
1307 }
1308 }
1309 }
1310
1311 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1312 //TODO
1313 }
1314
1315 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1316 //TODO
1317 }
1318 }
1319
1320 fprintf(stderr, "--------------------------------------\n");
1321 }
1322
1323 void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1324 {
1325 struct r600_pipe_state *rstate;
1326 unsigned i = 0;
1327
1328 if (count > 8) {
1329 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1330 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1331 S_SQ_CF_WORD1_BARRIER(1) |
1332 S_SQ_CF_WORD1_COUNT(8 - 1);
1333 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1334 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1335 S_SQ_CF_WORD1_BARRIER(1) |
1336 S_SQ_CF_WORD1_COUNT(count - 8 - 1);
1337 } else {
1338 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1339 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1340 S_SQ_CF_WORD1_BARRIER(1) |
1341 S_SQ_CF_WORD1_COUNT(count - 1);
1342 }
1343 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1344 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1345 S_SQ_CF_WORD1_BARRIER(1);
1346
1347 rstate = &ve->rstate;
1348 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1349 rstate->nregs = 0;
1350 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1351 0x00000000, 0xFFFFFFFF, NULL);
1352 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1353 0x00000000, 0xFFFFFFFF, NULL);
1354 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1355 r600_bo_offset(ve->fetch_shader) >> 8,
1356 0xFFFFFFFF, ve->fetch_shader);
1357 }
1358
1359 void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1360 {
1361 struct r600_pipe_state *rstate;
1362 unsigned i = 0;
1363
1364 if (count > 8) {
1365 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1366 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1367 S_SQ_CF_WORD1_BARRIER(1) |
1368 S_SQ_CF_WORD1_COUNT(8 - 1);
1369 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1370 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1371 S_SQ_CF_WORD1_BARRIER(1) |
1372 S_SQ_CF_WORD1_COUNT((count - 8) - 1);
1373 } else {
1374 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1375 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1376 S_SQ_CF_WORD1_BARRIER(1) |
1377 S_SQ_CF_WORD1_COUNT(count - 1);
1378 }
1379 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1380 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1381 S_SQ_CF_WORD1_BARRIER(1);
1382
1383 rstate = &ve->rstate;
1384 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1385 rstate->nregs = 0;
1386 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1387 0x00000000, 0xFFFFFFFF, NULL);
1388 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1389 0x00000000, 0xFFFFFFFF, NULL);
1390 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1391 r600_bo_offset(ve->fetch_shader) >> 8,
1392 0xFFFFFFFF, ve->fetch_shader);
1393 }
1394
1395 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1396 unsigned *num_format, unsigned *format_comp)
1397 {
1398 const struct util_format_description *desc;
1399 unsigned i;
1400
1401 *format = 0;
1402 *num_format = 0;
1403 *format_comp = 0;
1404
1405 desc = util_format_description(pformat);
1406 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1407 goto out_unknown;
1408 }
1409
1410 /* Find the first non-VOID channel. */
1411 for (i = 0; i < 4; i++) {
1412 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1413 break;
1414 }
1415 }
1416
1417 switch (desc->channel[i].type) {
1418 /* Half-floats, floats, doubles */
1419 case UTIL_FORMAT_TYPE_FLOAT:
1420 switch (desc->channel[i].size) {
1421 case 16:
1422 switch (desc->nr_channels) {
1423 case 1:
1424 *format = FMT_16_FLOAT;
1425 break;
1426 case 2:
1427 *format = FMT_16_16_FLOAT;
1428 break;
1429 case 3:
1430 *format = FMT_16_16_16_FLOAT;
1431 break;
1432 case 4:
1433 *format = FMT_16_16_16_16_FLOAT;
1434 break;
1435 }
1436 break;
1437 case 32:
1438 switch (desc->nr_channels) {
1439 case 1:
1440 *format = FMT_32_FLOAT;
1441 break;
1442 case 2:
1443 *format = FMT_32_32_FLOAT;
1444 break;
1445 case 3:
1446 *format = FMT_32_32_32_FLOAT;
1447 break;
1448 case 4:
1449 *format = FMT_32_32_32_32_FLOAT;
1450 break;
1451 }
1452 break;
1453 default:
1454 goto out_unknown;
1455 }
1456 break;
1457 /* Unsigned ints */
1458 case UTIL_FORMAT_TYPE_UNSIGNED:
1459 /* Signed ints */
1460 case UTIL_FORMAT_TYPE_SIGNED:
1461 switch (desc->channel[i].size) {
1462 case 8:
1463 switch (desc->nr_channels) {
1464 case 1:
1465 *format = FMT_8;
1466 break;
1467 case 2:
1468 *format = FMT_8_8;
1469 break;
1470 case 3:
1471 // *format = FMT_8_8_8; /* fails piglit draw-vertices test */
1472 // break;
1473 case 4:
1474 *format = FMT_8_8_8_8;
1475 break;
1476 }
1477 break;
1478 case 16:
1479 switch (desc->nr_channels) {
1480 case 1:
1481 *format = FMT_16;
1482 break;
1483 case 2:
1484 *format = FMT_16_16;
1485 break;
1486 case 3:
1487 // *format = FMT_16_16_16; /* fails piglit draw-vertices test */
1488 // break;
1489 case 4:
1490 *format = FMT_16_16_16_16;
1491 break;
1492 }
1493 break;
1494 case 32:
1495 switch (desc->nr_channels) {
1496 case 1:
1497 *format = FMT_32;
1498 break;
1499 case 2:
1500 *format = FMT_32_32;
1501 break;
1502 case 3:
1503 *format = FMT_32_32_32;
1504 break;
1505 case 4:
1506 *format = FMT_32_32_32_32;
1507 break;
1508 }
1509 break;
1510 default:
1511 goto out_unknown;
1512 }
1513 break;
1514 default:
1515 goto out_unknown;
1516 }
1517
1518 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1519 *format_comp = 1;
1520 }
1521 if (desc->channel[i].normalized) {
1522 *num_format = 0;
1523 } else {
1524 *num_format = 2;
1525 }
1526 return;
1527 out_unknown:
1528 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
1529 }
1530
1531 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
1532 {
1533 unsigned ndw, i;
1534 u32 *bytecode;
1535 unsigned fetch_resource_start = 0, format, num_format, format_comp;
1536 struct pipe_vertex_element *elements = ve->elements;
1537 const struct util_format_description *desc;
1538
1539 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
1540 ndw = 8 + ve->count * 4;
1541 ve->fs_size = ndw * 4;
1542
1543 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
1544 ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
1545 if (ve->fetch_shader == NULL) {
1546 return -ENOMEM;
1547 }
1548
1549 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
1550 if (bytecode == NULL) {
1551 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
1552 return -ENOMEM;
1553 }
1554
1555 if (rctx->family >= CHIP_CEDAR) {
1556 eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
1557 } else {
1558 r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
1559 fetch_resource_start = 160;
1560 }
1561
1562 /* vertex elements offset need special handling, if offset is bigger
1563 * than what we can put in fetch instruction then we need to alterate
1564 * the vertex resource offset. In such case in order to simplify code
1565 * we will bound one resource per elements. It's a worst case scenario.
1566 */
1567 for (i = 0; i < ve->count; i++) {
1568 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
1569 if (ve->vbuffer_offset[i]) {
1570 ve->vbuffer_need_offset = 1;
1571 }
1572 }
1573
1574 for (i = 0; i < ve->count; i++) {
1575 unsigned vbuffer_index;
1576 r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
1577 desc = util_format_description(ve->hw_format[i]);
1578 if (desc == NULL) {
1579 R600_ERR("unknown format %d\n", ve->hw_format[i]);
1580 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
1581 return -EINVAL;
1582 }
1583
1584 /* see above for vbuffer_need_offset explanation */
1585 vbuffer_index = elements[i].vertex_buffer_index;
1586 if (ve->vbuffer_need_offset) {
1587 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
1588 } else {
1589 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
1590 }
1591 bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
1592 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
1593 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
1594 bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
1595 S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
1596 S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
1597 S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
1598 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
1599 S_SQ_VTX_WORD1_DATA_FORMAT(format) |
1600 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
1601 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
1602 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
1603 S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
1604 bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
1605 S_SQ_VTX_WORD2_MEGA_FETCH(1);
1606 bytecode[8 + i * 4 + 3] = 0;
1607 }
1608 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
1609 return 0;
1610 }