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r600g: build fetch shader from vertex elements
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
36 {
37 if(alu->is_op3)
38 return 3;
39
40 switch (alu->inst) {
41 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
42 return 0;
43 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
44 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
62 return 2;
63
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
77 return 1;
78 default: R600_ERR(
79 "Need instruction operand number for 0x%x.\n", alu->inst);
80 };
81
82 return 3;
83 }
84
85 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
86
87 static struct r600_bc_cf *r600_bc_cf(void)
88 {
89 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
90
91 if (cf == NULL)
92 return NULL;
93 LIST_INITHEAD(&cf->list);
94 LIST_INITHEAD(&cf->alu);
95 LIST_INITHEAD(&cf->vtx);
96 LIST_INITHEAD(&cf->tex);
97 return cf;
98 }
99
100 static struct r600_bc_alu *r600_bc_alu(void)
101 {
102 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
103
104 if (alu == NULL)
105 return NULL;
106 LIST_INITHEAD(&alu->list);
107 LIST_INITHEAD(&alu->bs_list);
108 return alu;
109 }
110
111 static struct r600_bc_vtx *r600_bc_vtx(void)
112 {
113 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
114
115 if (vtx == NULL)
116 return NULL;
117 LIST_INITHEAD(&vtx->list);
118 return vtx;
119 }
120
121 static struct r600_bc_tex *r600_bc_tex(void)
122 {
123 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
124
125 if (tex == NULL)
126 return NULL;
127 LIST_INITHEAD(&tex->list);
128 return tex;
129 }
130
131 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
132 {
133 LIST_INITHEAD(&bc->cf);
134 bc->family = family;
135 switch (bc->family) {
136 case CHIP_R600:
137 case CHIP_RV610:
138 case CHIP_RV630:
139 case CHIP_RV670:
140 case CHIP_RV620:
141 case CHIP_RV635:
142 case CHIP_RS780:
143 case CHIP_RS880:
144 bc->chiprev = CHIPREV_R600;
145 break;
146 case CHIP_RV770:
147 case CHIP_RV730:
148 case CHIP_RV710:
149 case CHIP_RV740:
150 bc->chiprev = CHIPREV_R700;
151 break;
152 case CHIP_CEDAR:
153 case CHIP_REDWOOD:
154 case CHIP_JUNIPER:
155 case CHIP_CYPRESS:
156 case CHIP_HEMLOCK:
157 case CHIP_PALM:
158 bc->chiprev = CHIPREV_EVERGREEN;
159 break;
160 default:
161 R600_ERR("unknown family %d\n", bc->family);
162 return -EINVAL;
163 }
164 return 0;
165 }
166
167 static int r600_bc_add_cf(struct r600_bc *bc)
168 {
169 struct r600_bc_cf *cf = r600_bc_cf();
170
171 if (cf == NULL)
172 return -ENOMEM;
173 LIST_ADDTAIL(&cf->list, &bc->cf);
174 if (bc->cf_last)
175 cf->id = bc->cf_last->id + 2;
176 bc->cf_last = cf;
177 bc->ncf++;
178 bc->ndw += 2;
179 bc->force_add_cf = 0;
180 return 0;
181 }
182
183 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
184 {
185 int r;
186
187 r = r600_bc_add_cf(bc);
188 if (r)
189 return r;
190 bc->cf_last->inst = output->inst;
191 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
192 return 0;
193 }
194
195 const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
196 SQ_ALU_VEC_120, //001
197 SQ_ALU_VEC_102, //010
198
199 SQ_ALU_VEC_201, //011
200 SQ_ALU_VEC_012, //100
201 SQ_ALU_VEC_021, //101
202
203 SQ_ALU_VEC_012, //110
204 SQ_ALU_VEC_012}; //111
205
206 const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
207 SQ_ALU_SCL_122, //001
208 SQ_ALU_SCL_122, //010
209
210 SQ_ALU_SCL_221, //011
211 SQ_ALU_SCL_212, //100
212 SQ_ALU_SCL_122, //101
213
214 SQ_ALU_SCL_122, //110
215 SQ_ALU_SCL_122}; //111
216
217 static int init_gpr(struct r600_bc_alu *alu)
218 {
219 int cycle, component;
220 /* set up gpr use */
221 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
222 for (component = 0; component < NUM_OF_COMPONENTS; component++)
223 alu->hw_gpr[cycle][component] = -1;
224 return 0;
225 }
226
227 #if 0
228 static int reserve_gpr(struct r600_bc_alu *alu, unsigned sel, unsigned chan, unsigned cycle)
229 {
230 if (alu->hw_gpr[cycle][chan] < 0)
231 alu->hw_gpr[cycle][chan] = sel;
232 else if (alu->hw_gpr[cycle][chan] != (int)sel) {
233 R600_ERR("Another scalar operation has already used GPR read port for channel\n");
234 return -1;
235 }
236 return 0;
237 }
238
239 static int cycle_for_scalar_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
240 {
241 int table[3];
242 int ret = 0;
243 switch (swiz) {
244 case SQ_ALU_SCL_210:
245 table[0] = 2; table[1] = 1; table[2] = 0;
246 *p_cycle = table[sel];
247 break;
248 case SQ_ALU_SCL_122:
249 table[0] = 1; table[1] = 2; table[2] = 2;
250 *p_cycle = table[sel];
251 break;
252 case SQ_ALU_SCL_212:
253 table[0] = 2; table[1] = 1; table[2] = 2;
254 *p_cycle = table[sel];
255 break;
256 case SQ_ALU_SCL_221:
257 table[0] = 2; table[1] = 2; table[2] = 1;
258 *p_cycle = table[sel];
259 break;
260 break;
261 default:
262 R600_ERR("bad scalar bank swizzle value\n");
263 ret = -1;
264 break;
265 }
266 return ret;
267 }
268
269 static int cycle_for_vector_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
270 {
271 int table[3];
272 int ret;
273
274 switch (swiz) {
275 case SQ_ALU_VEC_012:
276 table[0] = 0; table[1] = 1; table[2] = 2;
277 *p_cycle = table[sel];
278 break;
279 case SQ_ALU_VEC_021:
280 table[0] = 0; table[1] = 2; table[2] = 1;
281 *p_cycle = table[sel];
282 break;
283 case SQ_ALU_VEC_120:
284 table[0] = 1; table[1] = 2; table[2] = 0;
285 *p_cycle = table[sel];
286 break;
287 case SQ_ALU_VEC_102:
288 table[0] = 1; table[1] = 0; table[2] = 2;
289 *p_cycle = table[sel];
290 break;
291 case SQ_ALU_VEC_201:
292 table[0] = 2; table[1] = 0; table[2] = 1;
293 *p_cycle = table[sel];
294 break;
295 case SQ_ALU_VEC_210:
296 table[0] = 2; table[1] = 1; table[2] = 0;
297 *p_cycle = table[sel];
298 break;
299 default:
300 R600_ERR("bad vector bank swizzle value\n");
301 ret = -1;
302 break;
303 }
304 return ret;
305 }
306
307
308
309 static void update_chan_counter(struct r600_bc_alu *alu, int *chan_counter)
310 {
311 int num_src;
312 int i;
313 int channel_swizzle;
314
315 num_src = r600_bc_get_num_operands(alu);
316
317 for (i = 0; i < num_src; i++) {
318 channel_swizzle = alu->src[i].chan;
319 if ((alu->src[i].sel > 0 && alu->src[i].sel < 128) && channel_swizzle <= 3)
320 chan_counter[channel_swizzle]++;
321 }
322 }
323
324 /* we need something like this I think - but this is bogus */
325 int check_read_slots(struct r600_bc *bc, struct r600_bc_alu *alu_first)
326 {
327 struct r600_bc_alu *alu;
328 int chan_counter[4] = { 0 };
329
330 update_chan_counter(alu_first, chan_counter);
331
332 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
333 update_chan_counter(alu, chan_counter);
334 }
335
336 if (chan_counter[0] > 3 ||
337 chan_counter[1] > 3 ||
338 chan_counter[2] > 3 ||
339 chan_counter[3] > 3) {
340 R600_ERR("needed to split instruction for input ran out of banks %x %d %d %d %d\n",
341 alu_first->inst, chan_counter[0], chan_counter[1], chan_counter[2], chan_counter[3]);
342 return -1;
343 }
344 return 0;
345 }
346 #endif
347
348 static int is_const(int sel)
349 {
350 if (sel > 255 && sel < 512)
351 return 1;
352 if (sel >= V_SQ_ALU_SRC_0 && sel <= V_SQ_ALU_SRC_LITERAL)
353 return 1;
354 return 0;
355 }
356
357 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu)
358 {
359 unsigned swizzle_key;
360
361 if (alu->bank_swizzle_force) {
362 alu->bank_swizzle = alu->bank_swizzle_force;
363 return 0;
364 }
365 swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
366 (is_const(alu->src[1].sel) ? 2 : 0 ) +
367 (is_const(alu->src[2].sel) ? 1 : 0 );
368
369 alu->bank_swizzle = bank_swizzle_scl[swizzle_key];
370 return 0;
371 }
372
373 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu)
374 {
375 unsigned swizzle_key;
376
377 if (alu->bank_swizzle_force) {
378 alu->bank_swizzle = alu->bank_swizzle_force;
379 return 0;
380 }
381 swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
382 (is_const(alu->src[1].sel) ? 2 : 0 ) +
383 (is_const(alu->src[2].sel) ? 1 : 0 );
384
385 alu->bank_swizzle = bank_swizzle_vec[swizzle_key];
386 return 0;
387 }
388
389 static int check_and_set_bank_swizzle(struct r600_bc *bc, struct r600_bc_alu *alu_first)
390 {
391 struct r600_bc_alu *alu = NULL;
392 int num_instr = 1;
393
394 init_gpr(alu_first);
395
396 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
397 num_instr++;
398 }
399
400 if (num_instr == 1) {
401 check_scalar(bc, alu_first);
402
403 } else {
404 /* check_read_slots(bc, bc->cf_last->curr_bs_head);*/
405 check_vector(bc, alu_first);
406 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
407 check_vector(bc, alu);
408 }
409 }
410 return 0;
411 }
412
413 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
414 {
415 struct r600_bc_alu *nalu = r600_bc_alu();
416 struct r600_bc_alu *lalu;
417 int i, r;
418
419 if (nalu == NULL)
420 return -ENOMEM;
421 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
422 nalu->nliteral = 0;
423
424 /* cf can contains only alu or only vtx or only tex */
425 if (bc->cf_last == NULL || bc->cf_last->inst != (type << 3) ||
426 bc->force_add_cf) {
427 r = r600_bc_add_cf(bc);
428 if (r) {
429 free(nalu);
430 return r;
431 }
432 bc->cf_last->inst = (type << 3);
433 }
434 if (!bc->cf_last->curr_bs_head) {
435 bc->cf_last->curr_bs_head = nalu;
436 LIST_INITHEAD(&nalu->bs_list);
437 } else {
438 LIST_ADDTAIL(&nalu->bs_list, &bc->cf_last->curr_bs_head->bs_list);
439 }
440 /* at most 128 slots, one add alu can add 4 slots + 4 constants(2 slots)
441 * worst case */
442 if (alu->last && (bc->cf_last->ndw >> 1) >= 120) {
443 bc->force_add_cf = 1;
444 }
445 /* number of gpr == the last gpr used in any alu */
446 for (i = 0; i < 3; i++) {
447 if (alu->src[i].sel >= bc->ngpr && alu->src[i].sel < 128) {
448 bc->ngpr = alu->src[i].sel + 1;
449 }
450 /* compute how many literal are needed
451 * either 2 or 4 literals
452 */
453 if (alu->src[i].sel == 253) {
454 if (((alu->src[i].chan + 2) & 0x6) > nalu->nliteral) {
455 nalu->nliteral = (alu->src[i].chan + 2) & 0x6;
456 }
457 }
458 }
459 if (!LIST_IS_EMPTY(&bc->cf_last->alu)) {
460 lalu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
461 if (!lalu->last && lalu->nliteral > nalu->nliteral) {
462 nalu->nliteral = lalu->nliteral;
463 }
464 }
465 if (alu->dst.sel >= bc->ngpr) {
466 bc->ngpr = alu->dst.sel + 1;
467 }
468 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
469 /* each alu use 2 dwords */
470 bc->cf_last->ndw += 2;
471 bc->ndw += 2;
472
473 bc->cf_last->kcache0_mode = 2;
474
475 /* process cur ALU instructions for bank swizzle */
476 if (alu->last) {
477 check_and_set_bank_swizzle(bc, bc->cf_last->curr_bs_head);
478 bc->cf_last->curr_bs_head = NULL;
479 }
480 return 0;
481 }
482
483 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
484 {
485 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
486 }
487
488 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
489 {
490 struct r600_bc_alu *alu;
491
492 if (bc->cf_last == NULL) {
493 return 0;
494 }
495 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
496 return 0;
497 }
498 /* all same on EG */
499 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
500 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
501 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
502 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK ||
503 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE ||
504 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END ||
505 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
506 return 0;
507 }
508 /* same on EG */
509 if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
510 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
511 LIST_IS_EMPTY(&bc->cf_last->alu)) {
512 R600_ERR("last CF is not ALU (%p)\n", bc->cf_last);
513 return -EINVAL;
514 }
515 alu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
516 if (!alu->last || !alu->nliteral || alu->literal_added) {
517 return 0;
518 }
519 memcpy(alu->value, value, 4 * 4);
520 bc->cf_last->ndw += alu->nliteral;
521 bc->ndw += alu->nliteral;
522 alu->literal_added = 1;
523 return 0;
524 }
525
526 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
527 {
528 struct r600_bc_vtx *nvtx = r600_bc_vtx();
529 int r;
530
531 if (nvtx == NULL)
532 return -ENOMEM;
533 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
534
535 /* cf can contains only alu or only vtx or only tex */
536 if (bc->cf_last == NULL ||
537 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
538 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
539 bc->force_add_cf) {
540 r = r600_bc_add_cf(bc);
541 if (r) {
542 free(nvtx);
543 return r;
544 }
545 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
546 }
547 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
548 /* each fetch use 4 dwords */
549 bc->cf_last->ndw += 4;
550 bc->ndw += 4;
551 if ((bc->ndw / 4) > 7)
552 bc->force_add_cf = 1;
553 return 0;
554 }
555
556 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
557 {
558 struct r600_bc_tex *ntex = r600_bc_tex();
559 int r;
560
561 if (ntex == NULL)
562 return -ENOMEM;
563 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
564
565 /* cf can contains only alu or only vtx or only tex */
566 if (bc->cf_last == NULL ||
567 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
568 bc->force_add_cf) {
569 r = r600_bc_add_cf(bc);
570 if (r) {
571 free(ntex);
572 return r;
573 }
574 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
575 }
576 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
577 /* each texture fetch use 4 dwords */
578 bc->cf_last->ndw += 4;
579 bc->ndw += 4;
580 if ((bc->ndw / 4) > 7)
581 bc->force_add_cf = 1;
582 return 0;
583 }
584
585 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
586 {
587 int r;
588 r = r600_bc_add_cf(bc);
589 if (r)
590 return r;
591
592 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
593 bc->cf_last->inst = inst;
594 return 0;
595 }
596
597 /* common to all 3 families */
598 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
599 {
600 unsigned fetch_resource_start = 0;
601
602 /* check if we are fetch shader */
603 /* fetch shader can also access vertex resource,
604 * first fetch shader resource is at 160
605 */
606 if (bc->type == -1) {
607 switch (bc->chiprev) {
608 /* r600 */
609 case CHIPREV_R600:
610 /* r700 */
611 case CHIPREV_R700:
612 fetch_resource_start = 160;
613 break;
614 /* evergreen */
615 case CHIPREV_EVERGREEN:
616 fetch_resource_start = 0;
617 break;
618 default:
619 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
620 __FILE__, __func__, __LINE__, bc->chiprev);
621 break;
622 }
623 }
624 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
625 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
626 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
627 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
628 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
629 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
630 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
631 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
632 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
633 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
634 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
635 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
636 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
637 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
638 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
639 bc->bytecode[id++] = 0;
640 return 0;
641 }
642
643 /* common to all 3 families */
644 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
645 {
646 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
647 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
648 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
649 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
650 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
651 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
652 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
653 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
654 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
655 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
656 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
657 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
658 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
659 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
660 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
661 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
662 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
663 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
664 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
665 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
666 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
667 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
668 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
669 bc->bytecode[id++] = 0;
670 return 0;
671 }
672
673 /* r600 only, r700/eg bits in r700_asm.c */
674 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
675 {
676 unsigned i;
677
678 /* don't replace gpr by pv or ps for destination register */
679 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
680 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
681 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
682 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
683 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
684 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
685 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
686 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
687 S_SQ_ALU_WORD0_LAST(alu->last);
688
689 if (alu->is_op3) {
690 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
691 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
692 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
693 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
694 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
695 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
696 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
697 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
698 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
699 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
700 } else {
701 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
702 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
703 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
704 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
705 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
706 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
707 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
708 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
709 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
710 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
711 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
712 }
713 if (alu->last) {
714 if (alu->nliteral && !alu->literal_added) {
715 R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst);
716 }
717 for (i = 0; i < alu->nliteral; i++) {
718 bc->bytecode[id++] = alu->value[i];
719 }
720 }
721 return 0;
722 }
723
724 /* common for r600/r700 - eg in eg_asm.c */
725 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
726 {
727 unsigned id = cf->id;
728
729 switch (cf->inst) {
730 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
731 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
732 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
733 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode) |
734 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache0_bank) |
735 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache1_bank);
736
737 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
738 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache1_mode) |
739 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache0_addr) |
740 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache1_addr) |
741 S_SQ_CF_ALU_WORD1_BARRIER(1) |
742 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
743 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
744 break;
745 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
746 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
747 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
748 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
749 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
750 S_SQ_CF_WORD1_BARRIER(1) |
751 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
752 break;
753 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
754 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
755 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
756 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
757 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
758 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
759 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
760 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
761 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
762 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
763 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
764 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
765 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
766 break;
767 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
768 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
769 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
770 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
771 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
772 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
773 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
774 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
775 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
776 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
777 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
778 S_SQ_CF_WORD1_BARRIER(1) |
779 S_SQ_CF_WORD1_COND(cf->cond) |
780 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
781
782 break;
783 default:
784 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
785 return -EINVAL;
786 }
787 return 0;
788 }
789
790 int r600_bc_build(struct r600_bc *bc)
791 {
792 struct r600_bc_cf *cf;
793 struct r600_bc_alu *alu;
794 struct r600_bc_vtx *vtx;
795 struct r600_bc_tex *tex;
796 unsigned addr;
797 int r;
798
799 if (bc->callstack[0].max > 0)
800 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
801 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
802 bc->nstack = 1;
803 }
804
805 /* first path compute addr of each CF block */
806 /* addr start after all the CF instructions */
807 addr = bc->cf_last->id + 2;
808 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
809 switch (cf->inst) {
810 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
811 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
812 break;
813 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
814 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
815 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
816 /* fetch node need to be 16 bytes aligned*/
817 addr += 3;
818 addr &= 0xFFFFFFFCUL;
819 break;
820 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
821 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
822 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
823 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
824 break;
825 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
826 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
827 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
828 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
829 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
830 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
831 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
832 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
833 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
834 break;
835 default:
836 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
837 return -EINVAL;
838 }
839 cf->addr = addr;
840 addr += cf->ndw;
841 bc->ndw = cf->addr + cf->ndw;
842 }
843 free(bc->bytecode);
844 bc->bytecode = calloc(1, bc->ndw * 4);
845 if (bc->bytecode == NULL)
846 return -ENOMEM;
847 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
848 addr = cf->addr;
849 if (bc->chiprev == CHIPREV_EVERGREEN)
850 r = eg_bc_cf_build(bc, cf);
851 else
852 r = r600_bc_cf_build(bc, cf);
853 if (r)
854 return r;
855 switch (cf->inst) {
856 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
857 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
858 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
859 switch(bc->chiprev) {
860 case CHIPREV_R600:
861 r = r600_bc_alu_build(bc, alu, addr);
862 break;
863 case CHIPREV_R700:
864 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
865 r = r700_bc_alu_build(bc, alu, addr);
866 break;
867 default:
868 R600_ERR("unknown family %d\n", bc->family);
869 return -EINVAL;
870 }
871 if (r)
872 return r;
873 addr += 2;
874 if (alu->last) {
875 addr += alu->nliteral;
876 }
877 }
878 break;
879 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
880 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
881 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
882 r = r600_bc_vtx_build(bc, vtx, addr);
883 if (r)
884 return r;
885 addr += 4;
886 }
887 break;
888 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
889 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
890 r = r600_bc_tex_build(bc, tex, addr);
891 if (r)
892 return r;
893 addr += 4;
894 }
895 break;
896 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
897 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
898 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
899 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
900 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
901 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
902 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
903 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
904 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
905 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
906 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
907 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
908 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
909 break;
910 default:
911 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
912 return -EINVAL;
913 }
914 }
915 return 0;
916 }
917
918 void r600_bc_clear(struct r600_bc *bc)
919 {
920 struct r600_bc_cf *cf = NULL, *next_cf;
921
922 free(bc->bytecode);
923 bc->bytecode = NULL;
924
925 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
926 struct r600_bc_alu *alu = NULL, *next_alu;
927 struct r600_bc_tex *tex = NULL, *next_tex;
928 struct r600_bc_tex *vtx = NULL, *next_vtx;
929
930 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
931 free(alu);
932 }
933
934 LIST_INITHEAD(&cf->alu);
935
936 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
937 free(tex);
938 }
939
940 LIST_INITHEAD(&cf->tex);
941
942 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
943 free(vtx);
944 }
945
946 LIST_INITHEAD(&cf->vtx);
947
948 free(cf);
949 }
950
951 LIST_INITHEAD(&cf->list);
952 }
953
954 void r600_bc_dump(struct r600_bc *bc)
955 {
956 unsigned i;
957 char chip = '6';
958
959 switch (bc->chiprev) {
960 case 1:
961 chip = '7';
962 break;
963 case 2:
964 chip = 'E';
965 break;
966 case 0:
967 default:
968 chip = '6';
969 break;
970 }
971 fprintf(stderr, "bytecode %d dw -----------------------\n", bc->ndw);
972 fprintf(stderr, " %c\n", chip);
973 for (i = 0; i < bc->ndw; i++) {
974 fprintf(stderr, "0x%08X\n", bc->bytecode[i]);
975 }
976 fprintf(stderr, "--------------------------------------\n");
977 }
978
979 void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
980 {
981 struct r600_pipe_state *rstate;
982 unsigned i = 0;
983
984 if (count > 8) {
985 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
986 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
987 S_SQ_CF_WORD1_BARRIER(1) |
988 S_SQ_CF_WORD1_COUNT(8 - 1);
989 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
990 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
991 S_SQ_CF_WORD1_BARRIER(1) |
992 S_SQ_CF_WORD1_COUNT(count - 8 - 1);
993 } else {
994 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
995 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
996 S_SQ_CF_WORD1_BARRIER(1) |
997 S_SQ_CF_WORD1_COUNT(count - 1);
998 }
999 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1000 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1001 S_SQ_CF_WORD1_BARRIER(1);
1002
1003 rstate = &ve->rstate;
1004 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1005 rstate->nregs = 0;
1006 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1007 0x00000000, 0xFFFFFFFF, NULL);
1008 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1009 0x00000000, 0xFFFFFFFF, NULL);
1010 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1011 r600_bo_offset(ve->fetch_shader) >> 8,
1012 0xFFFFFFFF, ve->fetch_shader);
1013 }
1014
1015 void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1016 {
1017 struct r600_pipe_state *rstate;
1018 unsigned i = 0;
1019
1020 if (count > 8) {
1021 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1022 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1023 S_SQ_CF_WORD1_BARRIER(1) |
1024 S_SQ_CF_WORD1_COUNT(8 - 1);
1025 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1026 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1027 S_SQ_CF_WORD1_BARRIER(1) |
1028 S_SQ_CF_WORD1_COUNT((count - 8) - 1);
1029 } else {
1030 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1031 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1032 S_SQ_CF_WORD1_BARRIER(1) |
1033 S_SQ_CF_WORD1_COUNT(count - 1);
1034 }
1035 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1036 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1037 S_SQ_CF_WORD1_BARRIER(1);
1038
1039 rstate = &ve->rstate;
1040 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1041 rstate->nregs = 0;
1042 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1043 0x00000000, 0xFFFFFFFF, NULL);
1044 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1045 0x00000000, 0xFFFFFFFF, NULL);
1046 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1047 r600_bo_offset(ve->fetch_shader) >> 8,
1048 0xFFFFFFFF, ve->fetch_shader);
1049 }
1050
1051 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1052 unsigned *num_format, unsigned *format_comp)
1053 {
1054 const struct util_format_description *desc;
1055 unsigned i;
1056
1057 *format = 0;
1058 *num_format = 0;
1059 *format_comp = 0;
1060
1061 desc = util_format_description(pformat);
1062 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1063 goto out_unknown;
1064 }
1065
1066 /* Find the first non-VOID channel. */
1067 for (i = 0; i < 4; i++) {
1068 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1069 break;
1070 }
1071 }
1072
1073 switch (desc->channel[i].type) {
1074 /* Half-floats, floats, doubles */
1075 case UTIL_FORMAT_TYPE_FLOAT:
1076 switch (desc->channel[i].size) {
1077 case 16:
1078 switch (desc->nr_channels) {
1079 case 1:
1080 *format = FMT_16_FLOAT;
1081 break;
1082 case 2:
1083 *format = FMT_16_16_FLOAT;
1084 break;
1085 case 3:
1086 *format = FMT_16_16_16_FLOAT;
1087 break;
1088 case 4:
1089 *format = FMT_16_16_16_16_FLOAT;
1090 break;
1091 }
1092 break;
1093 case 32:
1094 switch (desc->nr_channels) {
1095 case 1:
1096 *format = FMT_32_FLOAT;
1097 break;
1098 case 2:
1099 *format = FMT_32_32_FLOAT;
1100 break;
1101 case 3:
1102 *format = FMT_32_32_32_FLOAT;
1103 break;
1104 case 4:
1105 *format = FMT_32_32_32_32_FLOAT;
1106 break;
1107 }
1108 break;
1109 default:
1110 goto out_unknown;
1111 }
1112 break;
1113 /* Unsigned ints */
1114 case UTIL_FORMAT_TYPE_UNSIGNED:
1115 /* Signed ints */
1116 case UTIL_FORMAT_TYPE_SIGNED:
1117 switch (desc->channel[i].size) {
1118 case 8:
1119 switch (desc->nr_channels) {
1120 case 1:
1121 *format = FMT_8;
1122 break;
1123 case 2:
1124 *format = FMT_8_8;
1125 break;
1126 case 3:
1127 // *format = FMT_8_8_8; /* fails piglit draw-vertices test */
1128 // break;
1129 case 4:
1130 *format = FMT_8_8_8_8;
1131 break;
1132 }
1133 break;
1134 case 16:
1135 switch (desc->nr_channels) {
1136 case 1:
1137 *format = FMT_16;
1138 break;
1139 case 2:
1140 *format = FMT_16_16;
1141 break;
1142 case 3:
1143 // *format = FMT_16_16_16; /* fails piglit draw-vertices test */
1144 // break;
1145 case 4:
1146 *format = FMT_16_16_16_16;
1147 break;
1148 }
1149 break;
1150 case 32:
1151 switch (desc->nr_channels) {
1152 case 1:
1153 *format = FMT_32;
1154 break;
1155 case 2:
1156 *format = FMT_32_32;
1157 break;
1158 case 3:
1159 *format = FMT_32_32_32;
1160 break;
1161 case 4:
1162 *format = FMT_32_32_32_32;
1163 break;
1164 }
1165 break;
1166 default:
1167 goto out_unknown;
1168 }
1169 break;
1170 default:
1171 goto out_unknown;
1172 }
1173
1174 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1175 *format_comp = 1;
1176 }
1177 if (desc->channel[i].normalized) {
1178 *num_format = 0;
1179 } else {
1180 *num_format = 2;
1181 }
1182 return;
1183 out_unknown:
1184 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
1185 }
1186
1187 void r600_bc(unsigned ndw, unsigned chiprev, u32 *bytecode)
1188 {
1189 unsigned i;
1190 char chip = '6';
1191
1192 switch (chiprev) {
1193 case 1:
1194 chip = '7';
1195 break;
1196 case 2:
1197 chip = 'E';
1198 break;
1199 case 0:
1200 default:
1201 chip = '6';
1202 break;
1203 }
1204 fprintf(stderr, "bytecode %d dw -----------------------\n", ndw);
1205 fprintf(stderr, " %c\n", chip);
1206 for (i = 0; i < ndw; i++) {
1207 fprintf(stderr, "0x%08X\n", bytecode[i]);
1208 }
1209 fprintf(stderr, "--------------------------------------\n");
1210 }
1211
1212 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
1213 {
1214 unsigned ndw, i;
1215 u32 *bytecode;
1216 unsigned fetch_resource_start = 0, format, num_format, format_comp;
1217 struct pipe_vertex_element *elements = ve->elements;
1218 const struct util_format_description *desc;
1219
1220 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
1221 ndw = 8 + ve->count * 4;
1222 ve->fs_size = ndw * 4;
1223
1224 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
1225 ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
1226 if (ve->fetch_shader == NULL) {
1227 return -ENOMEM;
1228 }
1229
1230 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
1231 if (bytecode == NULL) {
1232 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
1233 return -ENOMEM;
1234 }
1235
1236 if (rctx->family >= CHIP_CEDAR) {
1237 eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
1238 } else {
1239 r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
1240 fetch_resource_start = 160;
1241 }
1242
1243 /* vertex elements offset need special handling, if offset is bigger
1244 * than what we can put in fetch instruction then we need to alterate
1245 * the vertex resource offset. In such case in order to simplify code
1246 * we will bound one resource per elements. It's a worst case scenario.
1247 */
1248 for (i = 0; i < ve->count; i++) {
1249 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
1250 if (ve->vbuffer_offset[i]) {
1251 ve->vbuffer_need_offset = 1;
1252 }
1253 }
1254
1255 for (i = 0; i < ve->count; i++) {
1256 unsigned vbuffer_index;
1257 r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
1258 desc = util_format_description(ve->hw_format[i]);
1259 if (desc == NULL) {
1260 R600_ERR("unknown format %d\n", ve->hw_format[i]);
1261 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
1262 return -EINVAL;
1263 }
1264
1265 /* see above for vbuffer_need_offset explanation */
1266 vbuffer_index = elements[i].vertex_buffer_index;
1267 if (ve->vbuffer_need_offset) {
1268 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
1269 } else {
1270 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
1271 }
1272 bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
1273 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
1274 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
1275 bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
1276 S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
1277 S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
1278 S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
1279 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
1280 S_SQ_VTX_WORD1_DATA_FORMAT(format) |
1281 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
1282 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
1283 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
1284 S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
1285 bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
1286 S_SQ_VTX_WORD2_MEGA_FETCH(1);
1287 bytecode[8 + i * 4 + 3] = 0;
1288 }
1289 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
1290 return 0;
1291 }