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r600g: only set depth bit for hw accessible depth buffers.
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
29 #include "r600_sq.h"
30 #include "r600_opcodes.h"
31 #include "r600_asm.h"
32 #include "r600_formats.h"
33 #include "r600d.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
39 {
40 if(alu->is_op3)
41 return 3;
42
43 switch (bc->chiprev) {
44 case CHIPREV_R600:
45 case CHIPREV_R700:
46 switch (alu->inst) {
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
48 return 0;
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
68 return 2;
69
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
87 return 1;
88 default: R600_ERR(
89 "Need instruction operand number for 0x%x.\n", alu->inst);
90 }
91 break;
92 case CHIPREV_EVERGREEN:
93 switch (alu->inst) {
94 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
95 return 0;
96 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
97 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
98 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
99 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
100 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
101 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
103 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
117 return 2;
118
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
135 return 1;
136 default: R600_ERR(
137 "Need instruction operand number for 0x%x.\n", alu->inst);
138 }
139 break;
140 }
141
142 return 3;
143 }
144
145 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
146
147 static struct r600_bc_cf *r600_bc_cf(void)
148 {
149 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
150
151 if (cf == NULL)
152 return NULL;
153 LIST_INITHEAD(&cf->list);
154 LIST_INITHEAD(&cf->alu);
155 LIST_INITHEAD(&cf->vtx);
156 LIST_INITHEAD(&cf->tex);
157 return cf;
158 }
159
160 static struct r600_bc_alu *r600_bc_alu(void)
161 {
162 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
163
164 if (alu == NULL)
165 return NULL;
166 LIST_INITHEAD(&alu->list);
167 return alu;
168 }
169
170 static struct r600_bc_vtx *r600_bc_vtx(void)
171 {
172 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
173
174 if (vtx == NULL)
175 return NULL;
176 LIST_INITHEAD(&vtx->list);
177 return vtx;
178 }
179
180 static struct r600_bc_tex *r600_bc_tex(void)
181 {
182 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
183
184 if (tex == NULL)
185 return NULL;
186 LIST_INITHEAD(&tex->list);
187 return tex;
188 }
189
190 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
191 {
192 LIST_INITHEAD(&bc->cf);
193 bc->family = family;
194 switch (bc->family) {
195 case CHIP_R600:
196 case CHIP_RV610:
197 case CHIP_RV630:
198 case CHIP_RV670:
199 case CHIP_RV620:
200 case CHIP_RV635:
201 case CHIP_RS780:
202 case CHIP_RS880:
203 bc->chiprev = CHIPREV_R600;
204 break;
205 case CHIP_RV770:
206 case CHIP_RV730:
207 case CHIP_RV710:
208 case CHIP_RV740:
209 bc->chiprev = CHIPREV_R700;
210 break;
211 case CHIP_CEDAR:
212 case CHIP_REDWOOD:
213 case CHIP_JUNIPER:
214 case CHIP_CYPRESS:
215 case CHIP_HEMLOCK:
216 case CHIP_PALM:
217 case CHIP_BARTS:
218 case CHIP_TURKS:
219 case CHIP_CAICOS:
220 bc->chiprev = CHIPREV_EVERGREEN;
221 break;
222 default:
223 R600_ERR("unknown family %d\n", bc->family);
224 return -EINVAL;
225 }
226 return 0;
227 }
228
229 static int r600_bc_add_cf(struct r600_bc *bc)
230 {
231 struct r600_bc_cf *cf = r600_bc_cf();
232
233 if (cf == NULL)
234 return -ENOMEM;
235 LIST_ADDTAIL(&cf->list, &bc->cf);
236 if (bc->cf_last)
237 cf->id = bc->cf_last->id + 2;
238 bc->cf_last = cf;
239 bc->ncf++;
240 bc->ndw += 2;
241 bc->force_add_cf = 0;
242 return 0;
243 }
244
245 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
246 {
247 int r;
248
249 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
250 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
251 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
252 output->type == bc->cf_last->output.type &&
253 output->elem_size == bc->cf_last->output.elem_size &&
254 output->swizzle_x == bc->cf_last->output.swizzle_x &&
255 output->swizzle_y == bc->cf_last->output.swizzle_y &&
256 output->swizzle_z == bc->cf_last->output.swizzle_z &&
257 output->swizzle_w == bc->cf_last->output.swizzle_w &&
258 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
259
260 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
261 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
262
263 bc->cf_last->output.end_of_program |= output->end_of_program;
264 bc->cf_last->output.inst = output->inst;
265 bc->cf_last->output.gpr = output->gpr;
266 bc->cf_last->output.array_base = output->array_base;
267 bc->cf_last->output.burst_count += output->burst_count;
268 return 0;
269
270 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
271 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
272
273 bc->cf_last->output.end_of_program |= output->end_of_program;
274 bc->cf_last->output.inst = output->inst;
275 bc->cf_last->output.burst_count += output->burst_count;
276 return 0;
277 }
278 }
279
280 r = r600_bc_add_cf(bc);
281 if (r)
282 return r;
283 bc->cf_last->inst = output->inst;
284 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
285 return 0;
286 }
287
288 /* alu instructions that can ony exits once per group */
289 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
290 {
291 switch (bc->chiprev) {
292 case CHIPREV_R600:
293 case CHIPREV_R700:
294 return !alu->is_op3 && (
295 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
296 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
297 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
298 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
299 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
300 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
301 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
302 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
303 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
304 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
305 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
306 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
307 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
308 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
309 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
310 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
311 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
312 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
313 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
314 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
315 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
316 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
317 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
318 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
319 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
320 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
321 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
322 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
323 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
324 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
325 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
326 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
327 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
328 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
329 case CHIPREV_EVERGREEN:
330 default:
331 return !alu->is_op3 && (
332 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
333 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
334 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
335 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
336 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
337 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
338 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
339 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
340 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
341 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
342 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
343 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
344 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
345 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
346 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
347 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
348 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
349 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
350 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
351 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
352 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
353 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
354 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
355 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
356 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
357 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
358 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
359 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
360 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
361 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
362 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
363 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
364 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
365 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
366 }
367 }
368
369 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
370 {
371 switch (bc->chiprev) {
372 case CHIPREV_R600:
373 case CHIPREV_R700:
374 return !alu->is_op3 && (
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
377 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
378 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
379 case CHIPREV_EVERGREEN:
380 default:
381 return !alu->is_op3 && (
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
386 }
387 }
388
389 static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
390 {
391 switch (bc->chiprev) {
392 case CHIPREV_R600:
393 case CHIPREV_R700:
394 return !alu->is_op3 &&
395 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
396 case CHIPREV_EVERGREEN:
397 default:
398 return !alu->is_op3 &&
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
400 }
401 }
402
403 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
404 {
405 switch (bc->chiprev) {
406 case CHIPREV_R600:
407 case CHIPREV_R700:
408 return !alu->is_op3 && (
409 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
410 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
411 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
412 case CHIPREV_EVERGREEN:
413 default:
414 return !alu->is_op3 && (
415 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
416 }
417 }
418
419 /* alu instructions that can only execute on the vector unit */
420 static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
421 {
422 return is_alu_reduction_inst(bc, alu) ||
423 is_alu_mova_inst(bc, alu);
424 }
425
426 /* alu instructions that can only execute on the trans unit */
427 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
428 {
429 switch (bc->chiprev) {
430 case CHIPREV_R600:
431 case CHIPREV_R700:
432 if (!alu->is_op3)
433 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
434 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
435 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
436 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
437 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
438 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
439 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
440 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
441 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
442 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
443 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
444 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
445 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
446 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
447 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
448 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
449 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
450 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
451 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
452 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
453 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
454 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
455 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
456 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
457 else
458 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
459 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
460 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
461 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
462 case CHIPREV_EVERGREEN:
463 default:
464 if (!alu->is_op3)
465 /* Note that FLT_TO_INT* instructions are vector instructions
466 * on Evergreen, despite what the documentation says. */
467 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
468 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
469 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
470 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
471 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
472 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
473 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
474 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
475 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
476 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
477 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
478 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
479 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
480 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
481 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
482 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
483 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
484 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
485 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
486 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
487 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
488 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
489 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
490 else
491 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
492 }
493 }
494
495 /* alu instructions that can execute on any unit */
496 static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
497 {
498 return !is_alu_vec_unit_inst(bc, alu) &&
499 !is_alu_trans_unit_inst(bc, alu);
500 }
501
502 static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
503 struct r600_bc_alu *assignment[5])
504 {
505 struct r600_bc_alu *alu;
506 unsigned i, chan, trans;
507
508 for (i = 0; i < 5; i++)
509 assignment[i] = NULL;
510
511 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
512 chan = alu->dst.chan;
513 if (is_alu_trans_unit_inst(bc, alu))
514 trans = 1;
515 else if (is_alu_vec_unit_inst(bc, alu))
516 trans = 0;
517 else if (assignment[chan])
518 trans = 1; // assume ALU_INST_PREFER_VECTOR
519 else
520 trans = 0;
521
522 if (trans) {
523 if (assignment[4]) {
524 assert(0); //ALU.Trans has already been allocated
525 return -1;
526 }
527 assignment[4] = alu;
528 } else {
529 if (assignment[chan]) {
530 assert(0); //ALU.chan has already been allocated
531 return -1;
532 }
533 assignment[chan] = alu;
534 }
535
536 if (alu->last)
537 break;
538 }
539 return 0;
540 }
541
542 struct alu_bank_swizzle {
543 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
544 int hw_cfile_addr[4];
545 int hw_cfile_elem[4];
546 };
547
548 const unsigned cycle_for_bank_swizzle_vec[][3] = {
549 [SQ_ALU_VEC_012] = { 0, 1, 2 },
550 [SQ_ALU_VEC_021] = { 0, 2, 1 },
551 [SQ_ALU_VEC_120] = { 1, 2, 0 },
552 [SQ_ALU_VEC_102] = { 1, 0, 2 },
553 [SQ_ALU_VEC_201] = { 2, 0, 1 },
554 [SQ_ALU_VEC_210] = { 2, 1, 0 }
555 };
556
557 const unsigned cycle_for_bank_swizzle_scl[][3] = {
558 [SQ_ALU_SCL_210] = { 2, 1, 0 },
559 [SQ_ALU_SCL_122] = { 1, 2, 2 },
560 [SQ_ALU_SCL_212] = { 2, 1, 2 },
561 [SQ_ALU_SCL_221] = { 2, 2, 1 }
562 };
563
564 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
565 {
566 int i, cycle, component;
567 /* set up gpr use */
568 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
569 for (component = 0; component < NUM_OF_COMPONENTS; component++)
570 bs->hw_gpr[cycle][component] = -1;
571 for (i = 0; i < 4; i++)
572 bs->hw_cfile_addr[i] = -1;
573 for (i = 0; i < 4; i++)
574 bs->hw_cfile_elem[i] = -1;
575 }
576
577 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
578 {
579 if (bs->hw_gpr[cycle][chan] == -1)
580 bs->hw_gpr[cycle][chan] = sel;
581 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
582 // Another scalar operation has already used GPR read port for channel
583 return -1;
584 }
585 return 0;
586 }
587
588 static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
589 {
590 int res, num_res = 4;
591 if (bc->chiprev >= CHIPREV_R700) {
592 num_res = 2;
593 chan /= 2;
594 }
595 for (res = 0; res < num_res; ++res) {
596 if (bs->hw_cfile_addr[res] == -1) {
597 bs->hw_cfile_addr[res] = sel;
598 bs->hw_cfile_elem[res] = chan;
599 return 0;
600 } else if (bs->hw_cfile_addr[res] == sel &&
601 bs->hw_cfile_elem[res] == chan)
602 return 0; // Read for this scalar element already reserved, nothing to do here.
603 }
604 // All cfile read ports are used, cannot reference vector element
605 return -1;
606 }
607
608 static int is_gpr(unsigned sel)
609 {
610 return (sel >= 0 && sel <= 127);
611 }
612
613 /* CB constants start at 512, and get translated to a kcache index when ALU
614 * clauses are constructed. Note that we handle kcache constants the same way
615 * as (the now gone) cfile constants, is that really required? */
616 static int is_cfile(unsigned sel)
617 {
618 return (sel > 255 && sel < 512) ||
619 (sel > 511 && sel < 4607) || // Kcache before translate
620 (sel > 127 && sel < 192); // Kcache after translate
621 }
622
623 static int is_const(int sel)
624 {
625 return is_cfile(sel) ||
626 (sel >= V_SQ_ALU_SRC_0 &&
627 sel <= V_SQ_ALU_SRC_LITERAL);
628 }
629
630 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
631 struct alu_bank_swizzle *bs, int bank_swizzle)
632 {
633 int r, src, num_src, sel, elem, cycle;
634
635 num_src = r600_bc_get_num_operands(bc, alu);
636 for (src = 0; src < num_src; src++) {
637 sel = alu->src[src].sel;
638 elem = alu->src[src].chan;
639 if (is_gpr(sel)) {
640 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
641 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
642 // Nothing to do; special-case optimization,
643 // second source uses first source’s reservation
644 continue;
645 else {
646 r = reserve_gpr(bs, sel, elem, cycle);
647 if (r)
648 return r;
649 }
650 } else if (is_cfile(sel)) {
651 r = reserve_cfile(bc, bs, sel, elem);
652 if (r)
653 return r;
654 }
655 // No restrictions on PV, PS, literal or special constants
656 }
657 return 0;
658 }
659
660 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
661 struct alu_bank_swizzle *bs, int bank_swizzle)
662 {
663 int r, src, num_src, const_count, sel, elem, cycle;
664
665 num_src = r600_bc_get_num_operands(bc, alu);
666 for (const_count = 0, src = 0; src < num_src; ++src) {
667 sel = alu->src[src].sel;
668 elem = alu->src[src].chan;
669 if (is_const(sel)) { // Any constant, including literal and inline constants
670 if (const_count >= 2)
671 // More than two references to a constant in
672 // transcendental operation.
673 return -1;
674 else
675 const_count++;
676 }
677 if (is_cfile(sel)) {
678 r = reserve_cfile(bc, bs, sel, elem);
679 if (r)
680 return r;
681 }
682 }
683 for (src = 0; src < num_src; ++src) {
684 sel = alu->src[src].sel;
685 elem = alu->src[src].chan;
686 if (is_gpr(sel)) {
687 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
688 if (cycle < const_count)
689 // Cycle for GPR load conflicts with
690 // constant load in transcendental operation.
691 return -1;
692 r = reserve_gpr(bs, sel, elem, cycle);
693 if (r)
694 return r;
695 }
696 // Constants already processed
697 // No restrictions on PV, PS
698 }
699 return 0;
700 }
701
702 static int check_and_set_bank_swizzle(struct r600_bc *bc,
703 struct r600_bc_alu *slots[5])
704 {
705 struct alu_bank_swizzle bs;
706 int bank_swizzle[5];
707 int i, r = 0, forced = 0;
708
709 for (i = 0; i < 5; i++)
710 if (slots[i] && slots[i]->bank_swizzle_force) {
711 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
712 forced = 1;
713 }
714
715 if (forced)
716 return 0;
717
718 // just check every possible combination of bank swizzle
719 // not very efficent, but works on the first try in most of the cases
720 for (i = 0; i < 4; i++)
721 bank_swizzle[i] = SQ_ALU_VEC_012;
722 bank_swizzle[4] = SQ_ALU_SCL_210;
723 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
724 init_bank_swizzle(&bs);
725 for (i = 0; i < 4; i++) {
726 if (slots[i]) {
727 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
728 if (r)
729 break;
730 }
731 }
732 if (!r && slots[4]) {
733 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
734 }
735 if (!r) {
736 for (i = 0; i < 5; i++) {
737 if (slots[i])
738 slots[i]->bank_swizzle = bank_swizzle[i];
739 }
740 return 0;
741 }
742
743 for (i = 0; i < 5; i++) {
744 bank_swizzle[i]++;
745 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
746 break;
747 else
748 bank_swizzle[i] = SQ_ALU_VEC_012;
749 }
750 }
751
752 // couldn't find a working swizzle
753 return -1;
754 }
755
756 static int replace_gpr_with_pv_ps(struct r600_bc *bc,
757 struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
758 {
759 struct r600_bc_alu *prev[5];
760 int gpr[5], chan[5];
761 int i, j, r, src, num_src;
762
763 r = assign_alu_units(bc, alu_prev, prev);
764 if (r)
765 return r;
766
767 for (i = 0; i < 5; ++i) {
768 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
769 gpr[i] = prev[i]->dst.sel;
770 /* cube writes more than PV.X */
771 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
772 chan[i] = 0;
773 else
774 chan[i] = prev[i]->dst.chan;
775 } else
776 gpr[i] = -1;
777 }
778
779 for (i = 0; i < 5; ++i) {
780 struct r600_bc_alu *alu = slots[i];
781 if(!alu)
782 continue;
783
784 num_src = r600_bc_get_num_operands(bc, alu);
785 for (src = 0; src < num_src; ++src) {
786 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
787 continue;
788
789 if (alu->src[src].sel == gpr[4] &&
790 alu->src[src].chan == chan[4]) {
791 alu->src[src].sel = V_SQ_ALU_SRC_PS;
792 alu->src[src].chan = 0;
793 continue;
794 }
795
796 for (j = 0; j < 4; ++j) {
797 if (alu->src[src].sel == gpr[j] &&
798 alu->src[src].chan == j) {
799 alu->src[src].sel = V_SQ_ALU_SRC_PV;
800 alu->src[src].chan = chan[j];
801 break;
802 }
803 }
804 }
805 }
806
807 return 0;
808 }
809
810 void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
811 {
812 switch(value) {
813 case 0:
814 *sel = V_SQ_ALU_SRC_0;
815 break;
816 case 1:
817 *sel = V_SQ_ALU_SRC_1_INT;
818 break;
819 case -1:
820 *sel = V_SQ_ALU_SRC_M_1_INT;
821 break;
822 case 0x3F800000: // 1.0f
823 *sel = V_SQ_ALU_SRC_1;
824 break;
825 case 0x3F000000: // 0.5f
826 *sel = V_SQ_ALU_SRC_0_5;
827 break;
828 case 0xBF800000: // -1.0f
829 *sel = V_SQ_ALU_SRC_1;
830 *neg ^= 1;
831 break;
832 case 0xBF000000: // -0.5f
833 *sel = V_SQ_ALU_SRC_0_5;
834 *neg ^= 1;
835 break;
836 default:
837 *sel = V_SQ_ALU_SRC_LITERAL;
838 break;
839 }
840 }
841
842 /* compute how many literal are needed */
843 static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
844 uint32_t literal[4], unsigned *nliteral)
845 {
846 unsigned num_src = r600_bc_get_num_operands(bc, alu);
847 unsigned i, j;
848
849 for (i = 0; i < num_src; ++i) {
850 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
851 uint32_t value = alu->src[i].value[alu->src[i].chan];
852 unsigned found = 0;
853 for (j = 0; j < *nliteral; ++j) {
854 if (literal[j] == value) {
855 found = 1;
856 break;
857 }
858 }
859 if (!found) {
860 if (*nliteral >= 4)
861 return -EINVAL;
862 literal[(*nliteral)++] = value;
863 }
864 }
865 }
866 return 0;
867 }
868
869 static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
870 struct r600_bc_alu *alu,
871 uint32_t literal[4], unsigned nliteral)
872 {
873 unsigned num_src = r600_bc_get_num_operands(bc, alu);
874 unsigned i, j;
875
876 for (i = 0; i < num_src; ++i) {
877 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
878 uint32_t value = alu->src[i].value[alu->src[i].chan];
879 for (j = 0; j < nliteral; ++j) {
880 if (literal[j] == value) {
881 alu->src[i].chan = j;
882 break;
883 }
884 }
885 }
886 }
887 }
888
889 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
890 struct r600_bc_alu *alu_prev)
891 {
892 struct r600_bc_alu *prev[5];
893 struct r600_bc_alu *result[5] = { NULL };
894
895 uint32_t literal[4], prev_literal[4];
896 unsigned nliteral = 0, prev_nliteral = 0;
897
898 int i, j, r, src, num_src;
899 int num_once_inst = 0;
900 int have_mova = 0, have_rel = 0;
901
902 r = assign_alu_units(bc, alu_prev, prev);
903 if (r)
904 return r;
905
906 for (i = 0; i < 5; ++i) {
907 struct r600_bc_alu *alu;
908
909 /* check number of literals */
910 if (prev[i]) {
911 if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
912 return 0;
913 if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
914 return 0;
915 if (is_alu_mova_inst(bc, prev[i])) {
916 if (have_rel)
917 return 0;
918 have_mova = 1;
919 }
920 num_once_inst += is_alu_once_inst(bc, prev[i]);
921 }
922 if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
923 return 0;
924
925 // let's check used slots
926 if (prev[i] && !slots[i]) {
927 result[i] = prev[i];
928 continue;
929 } else if (prev[i] && slots[i]) {
930 if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
931 // trans unit is still free try to use it
932 if (is_alu_any_unit_inst(bc, slots[i])) {
933 result[i] = prev[i];
934 result[4] = slots[i];
935 } else if (is_alu_any_unit_inst(bc, prev[i])) {
936 result[i] = slots[i];
937 result[4] = prev[i];
938 } else
939 return 0;
940 } else
941 return 0;
942 } else if(!slots[i]) {
943 continue;
944 } else
945 result[i] = slots[i];
946
947 // let's check source gprs
948 alu = slots[i];
949 num_once_inst += is_alu_once_inst(bc, alu);
950
951 num_src = r600_bc_get_num_operands(bc, alu);
952 for (src = 0; src < num_src; ++src) {
953 if (alu->src[src].rel) {
954 if (have_mova)
955 return 0;
956 have_rel = 1;
957 }
958
959 // constants doesn't matter
960 if (!is_gpr(alu->src[src].sel))
961 continue;
962
963 for (j = 0; j < 5; ++j) {
964 if (!prev[j] || !prev[j]->dst.write)
965 continue;
966
967 // if it's relative then we can't determin which gpr is really used
968 if (prev[j]->dst.chan == alu->src[src].chan &&
969 (prev[j]->dst.sel == alu->src[src].sel ||
970 prev[j]->dst.rel || alu->src[src].rel))
971 return 0;
972 }
973 }
974 }
975
976 /* more than one PRED_ or KILL_ ? */
977 if (num_once_inst > 1)
978 return 0;
979
980 /* check if the result can still be swizzlet */
981 r = check_and_set_bank_swizzle(bc, result);
982 if (r)
983 return 0;
984
985 /* looks like everything worked out right, apply the changes */
986
987 /* undo adding previus literals */
988 bc->cf_last->ndw -= align(prev_nliteral, 2);
989
990 /* sort instructions */
991 for (i = 0; i < 5; ++i) {
992 slots[i] = result[i];
993 if (result[i]) {
994 LIST_DEL(&result[i]->list);
995 result[i]->last = 0;
996 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
997 }
998 }
999
1000 /* determine new last instruction */
1001 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
1002
1003 /* determine new first instruction */
1004 for (i = 0; i < 5; ++i) {
1005 if (result[i]) {
1006 bc->cf_last->curr_bs_head = result[i];
1007 break;
1008 }
1009 }
1010
1011 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1012 bc->cf_last->prev2_bs_head = NULL;
1013
1014 return 0;
1015 }
1016
1017 /* This code handles kcache lines as single blocks of 32 constants. We could
1018 * probably do slightly better by recognizing that we actually have two
1019 * consecutive lines of 16 constants, but the resulting code would also be
1020 * somewhat more complicated. */
1021 static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
1022 {
1023 struct r600_bc_kcache *kcache = bc->cf_last->kcache;
1024 unsigned int required_lines;
1025 unsigned int free_lines = 0;
1026 unsigned int cache_line[3];
1027 unsigned int count = 0;
1028 unsigned int i, j;
1029 int r;
1030
1031 /* Collect required cache lines. */
1032 for (i = 0; i < 3; ++i) {
1033 bool found = false;
1034 unsigned int line;
1035
1036 if (alu->src[i].sel < 512)
1037 continue;
1038
1039 line = ((alu->src[i].sel - 512) / 32) * 2;
1040
1041 for (j = 0; j < count; ++j) {
1042 if (cache_line[j] == line) {
1043 found = true;
1044 break;
1045 }
1046 }
1047
1048 if (!found)
1049 cache_line[count++] = line;
1050 }
1051
1052 /* This should never actually happen. */
1053 if (count >= 3) return -ENOMEM;
1054
1055 for (i = 0; i < 2; ++i) {
1056 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1057 ++free_lines;
1058 }
1059 }
1060
1061 /* Filter lines pulled in by previous intructions. Note that this is
1062 * only for the required_lines count, we can't remove these from the
1063 * cache_line array since we may have to start a new ALU clause. */
1064 for (i = 0, required_lines = count; i < count; ++i) {
1065 for (j = 0; j < 2; ++j) {
1066 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1067 kcache[j].addr == cache_line[i]) {
1068 --required_lines;
1069 break;
1070 }
1071 }
1072 }
1073
1074 /* Start a new ALU clause if needed. */
1075 if (required_lines > free_lines) {
1076 if ((r = r600_bc_add_cf(bc))) {
1077 return r;
1078 }
1079 bc->cf_last->inst = (type << 3);
1080 kcache = bc->cf_last->kcache;
1081 }
1082
1083 /* Setup the kcache lines. */
1084 for (i = 0; i < count; ++i) {
1085 bool found = false;
1086
1087 for (j = 0; j < 2; ++j) {
1088 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1089 kcache[j].addr == cache_line[i]) {
1090 found = true;
1091 break;
1092 }
1093 }
1094
1095 if (found) continue;
1096
1097 for (j = 0; j < 2; ++j) {
1098 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1099 kcache[j].bank = 0;
1100 kcache[j].addr = cache_line[i];
1101 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1102 break;
1103 }
1104 }
1105 }
1106
1107 /* Alter the src operands to refer to the kcache. */
1108 for (i = 0; i < 3; ++i) {
1109 static const unsigned int base[] = {128, 160, 256, 288};
1110 unsigned int line;
1111
1112 if (alu->src[i].sel < 512)
1113 continue;
1114
1115 alu->src[i].sel -= 512;
1116 line = (alu->src[i].sel / 32) * 2;
1117
1118 for (j = 0; j < 2; ++j) {
1119 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1120 kcache[j].addr == line) {
1121 alu->src[i].sel &= 0x1f;
1122 alu->src[i].sel += base[j];
1123 break;
1124 }
1125 }
1126 }
1127
1128 return 0;
1129 }
1130
1131 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
1132 {
1133 struct r600_bc_alu *nalu = r600_bc_alu();
1134 struct r600_bc_alu *lalu;
1135 int i, r;
1136
1137 if (nalu == NULL)
1138 return -ENOMEM;
1139 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
1140
1141 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1142 /* check if we could add it anyway */
1143 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1144 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1145 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1146 if (lalu->predicate) {
1147 bc->force_add_cf = 1;
1148 break;
1149 }
1150 }
1151 } else
1152 bc->force_add_cf = 1;
1153 }
1154
1155 /* cf can contains only alu or only vtx or only tex */
1156 if (bc->cf_last == NULL || bc->force_add_cf) {
1157 r = r600_bc_add_cf(bc);
1158 if (r) {
1159 free(nalu);
1160 return r;
1161 }
1162 }
1163 bc->cf_last->inst = (type << 3);
1164
1165 /* Setup the kcache for this ALU instruction. This will start a new
1166 * ALU clause if needed. */
1167 if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
1168 free(nalu);
1169 return r;
1170 }
1171
1172 if (!bc->cf_last->curr_bs_head) {
1173 bc->cf_last->curr_bs_head = nalu;
1174 }
1175 /* number of gpr == the last gpr used in any alu */
1176 for (i = 0; i < 3; i++) {
1177 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1178 bc->ngpr = nalu->src[i].sel + 1;
1179 }
1180 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1181 r600_bc_special_constants(
1182 nalu->src[i].value[nalu->src[i].chan],
1183 &nalu->src[i].sel, &nalu->src[i].neg);
1184 }
1185 if (nalu->dst.sel >= bc->ngpr) {
1186 bc->ngpr = nalu->dst.sel + 1;
1187 }
1188 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1189 /* each alu use 2 dwords */
1190 bc->cf_last->ndw += 2;
1191 bc->ndw += 2;
1192
1193 /* process cur ALU instructions for bank swizzle */
1194 if (nalu->last) {
1195 uint32_t literal[4];
1196 unsigned nliteral;
1197 struct r600_bc_alu *slots[5];
1198 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1199 if (r)
1200 return r;
1201
1202 if (bc->cf_last->prev_bs_head) {
1203 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1204 if (r)
1205 return r;
1206 }
1207
1208 if (bc->cf_last->prev_bs_head) {
1209 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1210 if (r)
1211 return r;
1212 }
1213
1214 r = check_and_set_bank_swizzle(bc, slots);
1215 if (r)
1216 return r;
1217
1218 for (i = 0, nliteral = 0; i < 5; i++) {
1219 if (slots[i]) {
1220 r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
1221 if (r)
1222 return r;
1223 }
1224 }
1225 bc->cf_last->ndw += align(nliteral, 2);
1226
1227 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1228 * worst case */
1229 if ((bc->cf_last->ndw >> 1) >= 120) {
1230 bc->force_add_cf = 1;
1231 }
1232
1233 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1234 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1235 bc->cf_last->curr_bs_head = NULL;
1236 }
1237 return 0;
1238 }
1239
1240 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
1241 {
1242 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1243 }
1244
1245 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
1246 {
1247 struct r600_bc_vtx *nvtx = r600_bc_vtx();
1248 int r;
1249
1250 if (nvtx == NULL)
1251 return -ENOMEM;
1252 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
1253
1254 /* cf can contains only alu or only vtx or only tex */
1255 if (bc->cf_last == NULL ||
1256 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1257 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
1258 bc->force_add_cf) {
1259 r = r600_bc_add_cf(bc);
1260 if (r) {
1261 free(nvtx);
1262 return r;
1263 }
1264 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1265 }
1266 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1267 /* each fetch use 4 dwords */
1268 bc->cf_last->ndw += 4;
1269 bc->ndw += 4;
1270 if ((bc->cf_last->ndw / 4) > 7)
1271 bc->force_add_cf = 1;
1272 return 0;
1273 }
1274
1275 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
1276 {
1277 struct r600_bc_tex *ntex = r600_bc_tex();
1278 int r;
1279
1280 if (ntex == NULL)
1281 return -ENOMEM;
1282 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
1283
1284 /* cf can contains only alu or only vtx or only tex */
1285 if (bc->cf_last == NULL ||
1286 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1287 bc->force_add_cf) {
1288 r = r600_bc_add_cf(bc);
1289 if (r) {
1290 free(ntex);
1291 return r;
1292 }
1293 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1294 }
1295 if (ntex->src_gpr >= bc->ngpr) {
1296 bc->ngpr = ntex->src_gpr + 1;
1297 }
1298 if (ntex->dst_gpr >= bc->ngpr) {
1299 bc->ngpr = ntex->dst_gpr + 1;
1300 }
1301 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1302 /* each texture fetch use 4 dwords */
1303 bc->cf_last->ndw += 4;
1304 bc->ndw += 4;
1305 if ((bc->cf_last->ndw / 4) > 7)
1306 bc->force_add_cf = 1;
1307 return 0;
1308 }
1309
1310 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
1311 {
1312 int r;
1313 r = r600_bc_add_cf(bc);
1314 if (r)
1315 return r;
1316
1317 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1318 bc->cf_last->inst = inst;
1319 return 0;
1320 }
1321
1322 /* common to all 3 families */
1323 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
1324 {
1325 unsigned fetch_resource_start = 0;
1326
1327 /* check if we are fetch shader */
1328 /* fetch shader can also access vertex resource,
1329 * first fetch shader resource is at 160
1330 */
1331 if (bc->type == -1) {
1332 switch (bc->chiprev) {
1333 /* r600 */
1334 case CHIPREV_R600:
1335 /* r700 */
1336 case CHIPREV_R700:
1337 fetch_resource_start = 160;
1338 break;
1339 /* evergreen */
1340 case CHIPREV_EVERGREEN:
1341 fetch_resource_start = 0;
1342 break;
1343 default:
1344 fprintf(stderr, "%s:%s:%d unknown chiprev %d\n",
1345 __FILE__, __func__, __LINE__, bc->chiprev);
1346 break;
1347 }
1348 }
1349 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
1350 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1351 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
1352 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1353 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1354 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1355 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1356 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1357 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1358 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1359 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1360 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1361 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1362 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1363 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
1364 bc->bytecode[id++] = 0;
1365 return 0;
1366 }
1367
1368 /* common to all 3 families */
1369 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
1370 {
1371 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1372 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1373 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1374 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1375 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1376 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1377 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1378 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1379 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1380 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1381 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1382 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1383 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1384 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1385 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1386 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1387 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1388 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1389 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1390 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1391 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1392 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1393 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1394 bc->bytecode[id++] = 0;
1395 return 0;
1396 }
1397
1398 /* r600 only, r700/eg bits in r700_asm.c */
1399 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1400 {
1401 /* don't replace gpr by pv or ps for destination register */
1402 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1403 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1404 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1405 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1406 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1407 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1408 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1409 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1410 S_SQ_ALU_WORD0_LAST(alu->last);
1411
1412 if (alu->is_op3) {
1413 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1414 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1415 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1416 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1417 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1418 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1419 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1420 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1421 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1422 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1423 } else {
1424 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1425 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1426 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1427 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1428 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1429 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1430 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1431 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1432 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1433 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1434 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1435 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1436 }
1437 return 0;
1438 }
1439
1440 /* common for r600/r700 - eg in eg_asm.c */
1441 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1442 {
1443 unsigned id = cf->id;
1444
1445 switch (cf->inst) {
1446 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1447 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1448 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1449 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1450 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1451 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1452 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1453 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1454
1455 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1456 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1457 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1458 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1459 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1460 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
1461 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1462 break;
1463 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1464 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1465 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1466 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1467 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1468 S_SQ_CF_WORD1_BARRIER(1) |
1469 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1470 break;
1471 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1472 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1473 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1474 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1475 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1476 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1477 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1478 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1479 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1480 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1481 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1482 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1483 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1484 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1485 break;
1486 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1487 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1488 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1489 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1490 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1491 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1492 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1493 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1494 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1495 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1496 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1497 S_SQ_CF_WORD1_BARRIER(1) |
1498 S_SQ_CF_WORD1_COND(cf->cond) |
1499 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1500
1501 break;
1502 default:
1503 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1504 return -EINVAL;
1505 }
1506 return 0;
1507 }
1508
1509 int r600_bc_build(struct r600_bc *bc)
1510 {
1511 struct r600_bc_cf *cf;
1512 struct r600_bc_alu *alu;
1513 struct r600_bc_vtx *vtx;
1514 struct r600_bc_tex *tex;
1515 uint32_t literal[4];
1516 unsigned nliteral;
1517 unsigned addr;
1518 int i, r;
1519
1520 if (bc->callstack[0].max > 0)
1521 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1522 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1523 bc->nstack = 1;
1524 }
1525
1526 /* first path compute addr of each CF block */
1527 /* addr start after all the CF instructions */
1528 addr = bc->cf_last->id + 2;
1529 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1530 switch (cf->inst) {
1531 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1532 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1533 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1534 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1535 break;
1536 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1537 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1538 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1539 /* fetch node need to be 16 bytes aligned*/
1540 addr += 3;
1541 addr &= 0xFFFFFFFCUL;
1542 break;
1543 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1544 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1545 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1546 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1547 break;
1548 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1549 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1550 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1551 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1552 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1553 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1554 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1555 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1556 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1557 break;
1558 default:
1559 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1560 return -EINVAL;
1561 }
1562 cf->addr = addr;
1563 addr += cf->ndw;
1564 bc->ndw = cf->addr + cf->ndw;
1565 }
1566 free(bc->bytecode);
1567 bc->bytecode = calloc(1, bc->ndw * 4);
1568 if (bc->bytecode == NULL)
1569 return -ENOMEM;
1570 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1571 addr = cf->addr;
1572 if (bc->chiprev == CHIPREV_EVERGREEN)
1573 r = eg_bc_cf_build(bc, cf);
1574 else
1575 r = r600_bc_cf_build(bc, cf);
1576 if (r)
1577 return r;
1578 switch (cf->inst) {
1579 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1580 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1581 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1582 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1583 nliteral = 0;
1584 memset(literal, 0, sizeof(literal));
1585 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1586 r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1587 if (r)
1588 return r;
1589 r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
1590 switch(bc->chiprev) {
1591 case CHIPREV_R600:
1592 r = r600_bc_alu_build(bc, alu, addr);
1593 break;
1594 case CHIPREV_R700:
1595 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
1596 r = r700_bc_alu_build(bc, alu, addr);
1597 break;
1598 default:
1599 R600_ERR("unknown family %d\n", bc->family);
1600 return -EINVAL;
1601 }
1602 if (r)
1603 return r;
1604 addr += 2;
1605 if (alu->last) {
1606 for (i = 0; i < align(nliteral, 2); ++i) {
1607 bc->bytecode[addr++] = literal[i];
1608 }
1609 nliteral = 0;
1610 memset(literal, 0, sizeof(literal));
1611 }
1612 }
1613 break;
1614 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1615 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1616 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1617 r = r600_bc_vtx_build(bc, vtx, addr);
1618 if (r)
1619 return r;
1620 addr += 4;
1621 }
1622 break;
1623 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1624 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1625 r = r600_bc_tex_build(bc, tex, addr);
1626 if (r)
1627 return r;
1628 addr += 4;
1629 }
1630 break;
1631 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1632 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1633 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1634 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1635 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1636 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1637 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1638 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1639 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1640 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1641 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1642 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1643 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1644 break;
1645 default:
1646 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1647 return -EINVAL;
1648 }
1649 }
1650 return 0;
1651 }
1652
1653 void r600_bc_clear(struct r600_bc *bc)
1654 {
1655 struct r600_bc_cf *cf = NULL, *next_cf;
1656
1657 free(bc->bytecode);
1658 bc->bytecode = NULL;
1659
1660 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1661 struct r600_bc_alu *alu = NULL, *next_alu;
1662 struct r600_bc_tex *tex = NULL, *next_tex;
1663 struct r600_bc_tex *vtx = NULL, *next_vtx;
1664
1665 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1666 free(alu);
1667 }
1668
1669 LIST_INITHEAD(&cf->alu);
1670
1671 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1672 free(tex);
1673 }
1674
1675 LIST_INITHEAD(&cf->tex);
1676
1677 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1678 free(vtx);
1679 }
1680
1681 LIST_INITHEAD(&cf->vtx);
1682
1683 free(cf);
1684 }
1685
1686 LIST_INITHEAD(&cf->list);
1687 }
1688
1689 void r600_bc_dump(struct r600_bc *bc)
1690 {
1691 struct r600_bc_cf *cf = NULL;
1692 struct r600_bc_alu *alu = NULL;
1693 struct r600_bc_vtx *vtx = NULL;
1694 struct r600_bc_tex *tex = NULL;
1695
1696 unsigned i, id;
1697 uint32_t literal[4];
1698 unsigned nliteral;
1699 char chip = '6';
1700
1701 switch (bc->chiprev) {
1702 case 1:
1703 chip = '7';
1704 break;
1705 case 2:
1706 chip = 'E';
1707 break;
1708 case 0:
1709 default:
1710 chip = '6';
1711 break;
1712 }
1713 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1714 fprintf(stderr, " %c\n", chip);
1715
1716 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1717 id = cf->id;
1718
1719 switch (cf->inst) {
1720 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1721 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1722 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1723 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1724 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1725 fprintf(stderr, "ADDR:%d ", cf->addr);
1726 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1727 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1728 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1729 id++;
1730 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1731 fprintf(stderr, "INST:%d ", cf->inst);
1732 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1733 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1734 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1735 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1736 break;
1737 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1738 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1739 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1740 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1741 fprintf(stderr, "ADDR:%d\n", cf->addr);
1742 id++;
1743 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1744 fprintf(stderr, "INST:%d ", cf->inst);
1745 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1746 break;
1747 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1748 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1749 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1750 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1751 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1752 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1753 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1754 id++;
1755 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1756 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1757 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1758 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1759 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1760 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1761 fprintf(stderr, "INST:%d ", cf->output.inst);
1762 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
1763 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1764 break;
1765 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1766 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1767 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1768 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1769 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1770 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1771 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1772 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1773 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1774 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1775 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1776 id++;
1777 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1778 fprintf(stderr, "INST:%d ", cf->inst);
1779 fprintf(stderr, "COND:%X ", cf->cond);
1780 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1781 break;
1782 }
1783
1784 id = cf->addr;
1785 nliteral = 0;
1786 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1787 r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1788
1789 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1790 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1791 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1792 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1793 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1794 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1795 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1796 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1797 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1798 fprintf(stderr, "LAST:%d)\n", alu->last);
1799 id++;
1800 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1801 fprintf(stderr, "INST:%d ", alu->inst);
1802 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1803 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1804 fprintf(stderr, "REL:%d ", alu->dst.rel);
1805 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1806 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1807 if (alu->is_op3) {
1808 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1809 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1810 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1811 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1812 } else {
1813 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1814 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1815 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1816 fprintf(stderr, "OMOD:%d ", alu->omod);
1817 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1818 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1819 }
1820
1821 id++;
1822 if (alu->last) {
1823 for (i = 0; i < nliteral; i++, id++) {
1824 float *f = (float*)(bc->bytecode + id);
1825 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1826 }
1827 id += nliteral & 1;
1828 nliteral = 0;
1829 }
1830 }
1831
1832 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1833 //TODO
1834 }
1835
1836 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1837 //TODO
1838 }
1839 }
1840
1841 fprintf(stderr, "--------------------------------------\n");
1842 }
1843
1844 void r600_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1845 {
1846 struct r600_pipe_state *rstate;
1847 unsigned i = 0;
1848
1849 if (count > 8) {
1850 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1851 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1852 S_SQ_CF_WORD1_BARRIER(1) |
1853 S_SQ_CF_WORD1_COUNT(8 - 1);
1854 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1855 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1856 S_SQ_CF_WORD1_BARRIER(1) |
1857 S_SQ_CF_WORD1_COUNT(count - 8 - 1);
1858 } else {
1859 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1860 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
1861 S_SQ_CF_WORD1_BARRIER(1) |
1862 S_SQ_CF_WORD1_COUNT(count - 1);
1863 }
1864 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1865 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1866 S_SQ_CF_WORD1_BARRIER(1);
1867
1868 rstate = &ve->rstate;
1869 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1870 rstate->nregs = 0;
1871 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1872 0x00000000, 0xFFFFFFFF, NULL);
1873 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1874 0x00000000, 0xFFFFFFFF, NULL);
1875 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1876 r600_bo_offset(ve->fetch_shader) >> 8,
1877 0xFFFFFFFF, ve->fetch_shader);
1878 }
1879
1880 void r600_cf_vtx_tc(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
1881 {
1882 struct r600_pipe_state *rstate;
1883 unsigned i = 0;
1884
1885 if (count > 8) {
1886 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1887 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1888 S_SQ_CF_WORD1_BARRIER(1) |
1889 S_SQ_CF_WORD1_COUNT(8 - 1);
1890 bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1891 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1892 S_SQ_CF_WORD1_BARRIER(1) |
1893 S_SQ_CF_WORD1_COUNT((count - 8) - 1);
1894 } else {
1895 bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1896 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) |
1897 S_SQ_CF_WORD1_BARRIER(1) |
1898 S_SQ_CF_WORD1_COUNT(count - 1);
1899 }
1900 bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
1901 bytecode[i++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
1902 S_SQ_CF_WORD1_BARRIER(1);
1903
1904 rstate = &ve->rstate;
1905 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1906 rstate->nregs = 0;
1907 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1908 0x00000000, 0xFFFFFFFF, NULL);
1909 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1910 0x00000000, 0xFFFFFFFF, NULL);
1911 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1912 r600_bo_offset(ve->fetch_shader) >> 8,
1913 0xFFFFFFFF, ve->fetch_shader);
1914 }
1915
1916 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1917 unsigned *num_format, unsigned *format_comp)
1918 {
1919 const struct util_format_description *desc;
1920 unsigned i;
1921
1922 *format = 0;
1923 *num_format = 0;
1924 *format_comp = 0;
1925
1926 desc = util_format_description(pformat);
1927 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1928 goto out_unknown;
1929 }
1930
1931 /* Find the first non-VOID channel. */
1932 for (i = 0; i < 4; i++) {
1933 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1934 break;
1935 }
1936 }
1937
1938 switch (desc->channel[i].type) {
1939 /* Half-floats, floats, ints */
1940 case UTIL_FORMAT_TYPE_FLOAT:
1941 switch (desc->channel[i].size) {
1942 case 16:
1943 switch (desc->nr_channels) {
1944 case 1:
1945 *format = FMT_16_FLOAT;
1946 break;
1947 case 2:
1948 *format = FMT_16_16_FLOAT;
1949 break;
1950 case 3:
1951 case 4:
1952 *format = FMT_16_16_16_16_FLOAT;
1953 break;
1954 }
1955 break;
1956 case 32:
1957 switch (desc->nr_channels) {
1958 case 1:
1959 *format = FMT_32_FLOAT;
1960 break;
1961 case 2:
1962 *format = FMT_32_32_FLOAT;
1963 break;
1964 case 3:
1965 *format = FMT_32_32_32_FLOAT;
1966 break;
1967 case 4:
1968 *format = FMT_32_32_32_32_FLOAT;
1969 break;
1970 }
1971 break;
1972 default:
1973 goto out_unknown;
1974 }
1975 break;
1976 /* Unsigned ints */
1977 case UTIL_FORMAT_TYPE_UNSIGNED:
1978 /* Signed ints */
1979 case UTIL_FORMAT_TYPE_SIGNED:
1980 switch (desc->channel[i].size) {
1981 case 8:
1982 switch (desc->nr_channels) {
1983 case 1:
1984 *format = FMT_8;
1985 break;
1986 case 2:
1987 *format = FMT_8_8;
1988 break;
1989 case 3:
1990 case 4:
1991 *format = FMT_8_8_8_8;
1992 break;
1993 }
1994 break;
1995 case 16:
1996 switch (desc->nr_channels) {
1997 case 1:
1998 *format = FMT_16;
1999 break;
2000 case 2:
2001 *format = FMT_16_16;
2002 break;
2003 case 3:
2004 case 4:
2005 *format = FMT_16_16_16_16;
2006 break;
2007 }
2008 break;
2009 case 32:
2010 switch (desc->nr_channels) {
2011 case 1:
2012 *format = FMT_32;
2013 break;
2014 case 2:
2015 *format = FMT_32_32;
2016 break;
2017 case 3:
2018 *format = FMT_32_32_32;
2019 break;
2020 case 4:
2021 *format = FMT_32_32_32_32;
2022 break;
2023 }
2024 break;
2025 default:
2026 goto out_unknown;
2027 }
2028 break;
2029 default:
2030 goto out_unknown;
2031 }
2032
2033 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2034 *format_comp = 1;
2035 }
2036 if (desc->channel[i].normalized) {
2037 *num_format = 0;
2038 } else {
2039 *num_format = 2;
2040 }
2041 return;
2042 out_unknown:
2043 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2044 }
2045
2046 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2047 {
2048 unsigned ndw, i;
2049 u32 *bytecode;
2050 unsigned fetch_resource_start = 0, format, num_format, format_comp;
2051 struct pipe_vertex_element *elements = ve->elements;
2052 const struct util_format_description *desc;
2053
2054 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
2055 ndw = 8 + ve->count * 4;
2056 ve->fs_size = ndw * 4;
2057
2058 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
2059 ve->fetch_shader = r600_bo(rctx->radeon, ndw*4, 256, PIPE_BIND_VERTEX_BUFFER, 0);
2060 if (ve->fetch_shader == NULL) {
2061 return -ENOMEM;
2062 }
2063
2064 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
2065 if (bytecode == NULL) {
2066 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2067 return -ENOMEM;
2068 }
2069
2070 if (rctx->family >= CHIP_CEDAR) {
2071 eg_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2072 } else {
2073 r600_cf_vtx(ve, &bytecode[0], (ndw - 8) / 4);
2074 fetch_resource_start = 160;
2075 }
2076
2077 /* vertex elements offset need special handling, if offset is bigger
2078 * than what we can put in fetch instruction then we need to alterate
2079 * the vertex resource offset. In such case in order to simplify code
2080 * we will bound one resource per elements. It's a worst case scenario.
2081 */
2082 for (i = 0; i < ve->count; i++) {
2083 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2084 if (ve->vbuffer_offset[i]) {
2085 ve->vbuffer_need_offset = 1;
2086 }
2087 }
2088
2089 for (i = 0; i < ve->count; i++) {
2090 unsigned vbuffer_index;
2091 r600_vertex_data_type(ve->hw_format[i], &format, &num_format, &format_comp);
2092 desc = util_format_description(ve->hw_format[i]);
2093 if (desc == NULL) {
2094 R600_ERR("unknown format %d\n", ve->hw_format[i]);
2095 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2096 return -EINVAL;
2097 }
2098
2099 /* see above for vbuffer_need_offset explanation */
2100 vbuffer_index = elements[i].vertex_buffer_index;
2101 if (ve->vbuffer_need_offset) {
2102 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i + fetch_resource_start);
2103 } else {
2104 bytecode[8 + i * 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index + fetch_resource_start);
2105 }
2106 bytecode[8 + i * 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
2107 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
2108 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
2109 bytecode[8 + i * 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]) |
2110 S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]) |
2111 S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]) |
2112 S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]) |
2113 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
2114 S_SQ_VTX_WORD1_DATA_FORMAT(format) |
2115 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format) |
2116 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp) |
2117 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
2118 S_SQ_VTX_WORD1_GPR_DST_GPR(i + 1);
2119 bytecode[8 + i * 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements[i].src_offset) |
2120 S_SQ_VTX_WORD2_MEGA_FETCH(1);
2121 bytecode[8 + i * 4 + 3] = 0;
2122 }
2123 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
2124 return 0;
2125 }