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[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600d.h"
27
28 #include <errno.h>
29 #include <byteswap.h>
30 #include "util/u_memory.h"
31 #include "pipe/p_shader_tokens.h"
32
33 #define NUM_OF_CYCLES 3
34 #define NUM_OF_COMPONENTS 4
35
36 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
37 {
38 if(alu->is_op3)
39 return 3;
40
41 switch (bc->chip_class) {
42 case R600:
43 case R700:
44 switch (alu->inst) {
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
46 return 0;
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
91 return 2;
92
93 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
118 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
119 return 1;
120 default: R600_ERR(
121 "Need instruction operand number for 0x%x.\n", alu->inst);
122 }
123 break;
124 case EVERGREEN:
125 case CAYMAN:
126 switch (alu->inst) {
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
128 return 0;
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
175 return 2;
176
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
198 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
199 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
200 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
201 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
202 return 1;
203 default: R600_ERR(
204 "Need instruction operand number for 0x%x.\n", alu->inst);
205 }
206 break;
207 }
208
209 return 3;
210 }
211
212 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
213
214 static struct r600_bytecode_cf *r600_bytecode_cf(void)
215 {
216 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
217
218 if (cf == NULL)
219 return NULL;
220 LIST_INITHEAD(&cf->list);
221 LIST_INITHEAD(&cf->alu);
222 LIST_INITHEAD(&cf->vtx);
223 LIST_INITHEAD(&cf->tex);
224 return cf;
225 }
226
227 static struct r600_bytecode_alu *r600_bytecode_alu(void)
228 {
229 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
230
231 if (alu == NULL)
232 return NULL;
233 LIST_INITHEAD(&alu->list);
234 return alu;
235 }
236
237 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
238 {
239 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
240
241 if (vtx == NULL)
242 return NULL;
243 LIST_INITHEAD(&vtx->list);
244 return vtx;
245 }
246
247 static struct r600_bytecode_tex *r600_bytecode_tex(void)
248 {
249 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
250
251 if (tex == NULL)
252 return NULL;
253 LIST_INITHEAD(&tex->list);
254 return tex;
255 }
256
257 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
258 {
259 if ((chip_class == R600) && (family != CHIP_RV670))
260 bc->ar_handling = AR_HANDLE_RV6XX;
261 else
262 bc->ar_handling = AR_HANDLE_NORMAL;
263
264 if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
265 family != CHIP_RS880))
266 bc->r6xx_nop_after_rel_dst = 1;
267 else
268 bc->r6xx_nop_after_rel_dst = 0;
269 LIST_INITHEAD(&bc->cf);
270 bc->chip_class = chip_class;
271 }
272
273 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
274 {
275 struct r600_bytecode_cf *cf = r600_bytecode_cf();
276
277 if (cf == NULL)
278 return -ENOMEM;
279 LIST_ADDTAIL(&cf->list, &bc->cf);
280 if (bc->cf_last) {
281 cf->id = bc->cf_last->id + 2;
282 if (bc->cf_last->eg_alu_extended) {
283 /* take into account extended alu size */
284 cf->id += 2;
285 bc->ndw += 2;
286 }
287 }
288 bc->cf_last = cf;
289 bc->ncf++;
290 bc->ndw += 2;
291 bc->force_add_cf = 0;
292 bc->ar_loaded = 0;
293 return 0;
294 }
295
296 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
297 {
298 int r;
299
300 if (output->gpr >= bc->ngpr)
301 bc->ngpr = output->gpr + 1;
302
303 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
304 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
305 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
306 output->type == bc->cf_last->output.type &&
307 output->elem_size == bc->cf_last->output.elem_size &&
308 output->swizzle_x == bc->cf_last->output.swizzle_x &&
309 output->swizzle_y == bc->cf_last->output.swizzle_y &&
310 output->swizzle_z == bc->cf_last->output.swizzle_z &&
311 output->swizzle_w == bc->cf_last->output.swizzle_w &&
312 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
313
314 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
315 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
316
317 bc->cf_last->output.end_of_program |= output->end_of_program;
318 bc->cf_last->output.inst = output->inst;
319 bc->cf_last->output.gpr = output->gpr;
320 bc->cf_last->output.array_base = output->array_base;
321 bc->cf_last->output.burst_count += output->burst_count;
322 return 0;
323
324 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
325 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
326
327 bc->cf_last->output.end_of_program |= output->end_of_program;
328 bc->cf_last->output.inst = output->inst;
329 bc->cf_last->output.burst_count += output->burst_count;
330 return 0;
331 }
332 }
333
334 r = r600_bytecode_add_cf(bc);
335 if (r)
336 return r;
337 bc->cf_last->inst = output->inst;
338 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
339 return 0;
340 }
341
342 /* alu instructions that can ony exits once per group */
343 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
344 {
345 switch (bc->chip_class) {
346 case R600:
347 case R700:
348 return !alu->is_op3 && (
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
377 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
378 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
379 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
380 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
381 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
382 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
383 case EVERGREEN:
384 case CAYMAN:
385 default:
386 return !alu->is_op3 && (
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
415 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
416 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
417 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
418 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
419 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
420 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
421 }
422 }
423
424 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
425 {
426 switch (bc->chip_class) {
427 case R600:
428 case R700:
429 return !alu->is_op3 && (
430 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
431 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
432 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
433 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
434 case EVERGREEN:
435 case CAYMAN:
436 default:
437 return !alu->is_op3 && (
438 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
439 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
440 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
441 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
442 }
443 }
444
445 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
446 {
447 switch (bc->chip_class) {
448 case R600:
449 case R700:
450 return !alu->is_op3 &&
451 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
452 case EVERGREEN:
453 case CAYMAN:
454 default:
455 return !alu->is_op3 &&
456 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
457 }
458 }
459
460 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
461 {
462 switch (bc->chip_class) {
463 case R600:
464 case R700:
465 return !alu->is_op3 && (
466 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
467 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
468 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
469 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
470 case EVERGREEN:
471 case CAYMAN:
472 default:
473 return !alu->is_op3 && (
474 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
475 }
476 }
477
478 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
479 {
480 return min <= opcode && opcode <= max;
481 }
482
483 /* ALU instructions that can only execute on the vector unit:
484 *
485 * opcode ranges:
486 * R6xx/R7xx:
487 * op3 : [0x08 - 0x0B]
488 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
489 *
490 * EVERGREEN:
491 * op3: [0x04 - 0x11]
492 * op2: [0xA0 - 0xE2]
493 */
494 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
495 {
496 switch (bc->chip_class) {
497 case R600:
498 case R700:
499 if (alu->is_op3)
500 return is_opcode_in_range(alu->inst,
501 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
502 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
503 else
504 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
505 is_opcode_in_range(alu->inst,
506 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
507 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
508 is_opcode_in_range(alu->inst,
509 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
510 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
511 is_opcode_in_range(alu->inst,
512 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
513 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
514 is_opcode_in_range(alu->inst,
515 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
516 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
517
518 case EVERGREEN:
519 if (alu->is_op3)
520 return is_opcode_in_range(alu->inst,
521 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
522 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
523 else
524 return is_opcode_in_range(alu->inst,
525 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
526 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
527 case CAYMAN:
528 default:
529 assert(0);
530 return 0;
531 }
532 }
533
534 /* ALU instructions that can only execute on the trans unit:
535 *
536 * opcode ranges:
537 * R600:
538 * op3: 0x0C
539 * op2: [0x60 - 0x79]
540 *
541 * R700:
542 * op3: 0x0C
543 * op2: [0x60 - 0x6F], [0x73 - 0x79]
544 *
545 * EVERGREEN:
546 * op3: 0x1F
547 * op2: [0x81 - 0x9C]
548 */
549 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
550 {
551
552 switch (bc->chip_class) {
553 case R600:
554 if (alu->is_op3)
555 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
556 else
557 return is_opcode_in_range(alu->inst,
558 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
559 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
560 case R700:
561 if (alu->is_op3)
562 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
563 else
564 return is_opcode_in_range(alu->inst,
565 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
566 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
567 is_opcode_in_range(alu->inst,
568 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
569 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
570 case EVERGREEN:
571 if (alu->is_op3)
572 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
573 else
574 return is_opcode_in_range(alu->inst,
575 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
576 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
577 case CAYMAN:
578 default:
579 assert(0);
580 return 0;
581 }
582 }
583
584 /* alu instructions that can execute on any unit */
585 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
586 {
587 return !is_alu_vec_unit_inst(bc, alu) &&
588 !is_alu_trans_unit_inst(bc, alu);
589 }
590
591 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
592 {
593 switch (bc->chip_class) {
594 case R600:
595 case R700:
596 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
597 case EVERGREEN:
598 case CAYMAN:
599 default:
600 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
601 }
602 }
603
604 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
605 struct r600_bytecode_alu *assignment[5])
606 {
607 struct r600_bytecode_alu *alu;
608 unsigned i, chan, trans;
609 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
610
611 for (i = 0; i < max_slots; i++)
612 assignment[i] = NULL;
613
614 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
615 chan = alu->dst.chan;
616 if (max_slots == 4)
617 trans = 0;
618 else if (is_alu_trans_unit_inst(bc, alu))
619 trans = 1;
620 else if (is_alu_vec_unit_inst(bc, alu))
621 trans = 0;
622 else if (assignment[chan])
623 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
624 else
625 trans = 0;
626
627 if (trans) {
628 if (assignment[4]) {
629 assert(0); /* ALU.Trans has already been allocated. */
630 return -1;
631 }
632 assignment[4] = alu;
633 } else {
634 if (assignment[chan]) {
635 assert(0); /* ALU.chan has already been allocated. */
636 return -1;
637 }
638 assignment[chan] = alu;
639 }
640
641 if (alu->last)
642 break;
643 }
644 return 0;
645 }
646
647 struct alu_bank_swizzle {
648 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
649 int hw_cfile_addr[4];
650 int hw_cfile_elem[4];
651 };
652
653 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
654 [SQ_ALU_VEC_012] = { 0, 1, 2 },
655 [SQ_ALU_VEC_021] = { 0, 2, 1 },
656 [SQ_ALU_VEC_120] = { 1, 2, 0 },
657 [SQ_ALU_VEC_102] = { 1, 0, 2 },
658 [SQ_ALU_VEC_201] = { 2, 0, 1 },
659 [SQ_ALU_VEC_210] = { 2, 1, 0 }
660 };
661
662 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
663 [SQ_ALU_SCL_210] = { 2, 1, 0 },
664 [SQ_ALU_SCL_122] = { 1, 2, 2 },
665 [SQ_ALU_SCL_212] = { 2, 1, 2 },
666 [SQ_ALU_SCL_221] = { 2, 2, 1 }
667 };
668
669 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
670 {
671 int i, cycle, component;
672 /* set up gpr use */
673 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
674 for (component = 0; component < NUM_OF_COMPONENTS; component++)
675 bs->hw_gpr[cycle][component] = -1;
676 for (i = 0; i < 4; i++)
677 bs->hw_cfile_addr[i] = -1;
678 for (i = 0; i < 4; i++)
679 bs->hw_cfile_elem[i] = -1;
680 }
681
682 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
683 {
684 if (bs->hw_gpr[cycle][chan] == -1)
685 bs->hw_gpr[cycle][chan] = sel;
686 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
687 /* Another scalar operation has already used the GPR read port for the channel. */
688 return -1;
689 }
690 return 0;
691 }
692
693 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
694 {
695 int res, num_res = 4;
696 if (bc->chip_class >= R700) {
697 num_res = 2;
698 chan /= 2;
699 }
700 for (res = 0; res < num_res; ++res) {
701 if (bs->hw_cfile_addr[res] == -1) {
702 bs->hw_cfile_addr[res] = sel;
703 bs->hw_cfile_elem[res] = chan;
704 return 0;
705 } else if (bs->hw_cfile_addr[res] == sel &&
706 bs->hw_cfile_elem[res] == chan)
707 return 0; /* Read for this scalar element already reserved, nothing to do here. */
708 }
709 /* All cfile read ports are used, cannot reference vector element. */
710 return -1;
711 }
712
713 static int is_gpr(unsigned sel)
714 {
715 return (sel >= 0 && sel <= 127);
716 }
717
718 /* CB constants start at 512, and get translated to a kcache index when ALU
719 * clauses are constructed. Note that we handle kcache constants the same way
720 * as (the now gone) cfile constants, is that really required? */
721 static int is_cfile(unsigned sel)
722 {
723 return (sel > 255 && sel < 512) ||
724 (sel > 511 && sel < 4607) || /* Kcache before translation. */
725 (sel > 127 && sel < 192); /* Kcache after translation. */
726 }
727
728 static int is_const(int sel)
729 {
730 return is_cfile(sel) ||
731 (sel >= V_SQ_ALU_SRC_0 &&
732 sel <= V_SQ_ALU_SRC_LITERAL);
733 }
734
735 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
736 struct alu_bank_swizzle *bs, int bank_swizzle)
737 {
738 int r, src, num_src, sel, elem, cycle;
739
740 num_src = r600_bytecode_get_num_operands(bc, alu);
741 for (src = 0; src < num_src; src++) {
742 sel = alu->src[src].sel;
743 elem = alu->src[src].chan;
744 if (is_gpr(sel)) {
745 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
746 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
747 /* Nothing to do; special-case optimization,
748 * second source uses first source’s reservation. */
749 continue;
750 else {
751 r = reserve_gpr(bs, sel, elem, cycle);
752 if (r)
753 return r;
754 }
755 } else if (is_cfile(sel)) {
756 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
757 if (r)
758 return r;
759 }
760 /* No restrictions on PV, PS, literal or special constants. */
761 }
762 return 0;
763 }
764
765 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
766 struct alu_bank_swizzle *bs, int bank_swizzle)
767 {
768 int r, src, num_src, const_count, sel, elem, cycle;
769
770 num_src = r600_bytecode_get_num_operands(bc, alu);
771 for (const_count = 0, src = 0; src < num_src; ++src) {
772 sel = alu->src[src].sel;
773 elem = alu->src[src].chan;
774 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
775 if (const_count >= 2)
776 /* More than two references to a constant in
777 * transcendental operation. */
778 return -1;
779 else
780 const_count++;
781 }
782 if (is_cfile(sel)) {
783 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
784 if (r)
785 return r;
786 }
787 }
788 for (src = 0; src < num_src; ++src) {
789 sel = alu->src[src].sel;
790 elem = alu->src[src].chan;
791 if (is_gpr(sel)) {
792 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
793 if (cycle < const_count)
794 /* Cycle for GPR load conflicts with
795 * constant load in transcendental operation. */
796 return -1;
797 r = reserve_gpr(bs, sel, elem, cycle);
798 if (r)
799 return r;
800 }
801 /* PV PS restrictions */
802 if (const_count && (sel == 254 || sel == 255)) {
803 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
804 if (cycle < const_count)
805 return -1;
806 }
807 }
808 return 0;
809 }
810
811 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
812 struct r600_bytecode_alu *slots[5])
813 {
814 struct alu_bank_swizzle bs;
815 int bank_swizzle[5];
816 int i, r = 0, forced = 1;
817 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
818 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
819
820 for (i = 0; i < max_slots; i++) {
821 if (slots[i]) {
822 if (slots[i]->bank_swizzle_force) {
823 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
824 } else {
825 forced = 0;
826 }
827 }
828
829 if (i < 4 && slots[i])
830 scalar_only = false;
831 }
832 if (forced)
833 return 0;
834
835 /* Just check every possible combination of bank swizzle.
836 * Not very efficent, but works on the first try in most of the cases. */
837 for (i = 0; i < 4; i++)
838 if (!slots[i] || !slots[i]->bank_swizzle_force)
839 bank_swizzle[i] = SQ_ALU_VEC_012;
840 else
841 bank_swizzle[i] = slots[i]->bank_swizzle;
842
843 bank_swizzle[4] = SQ_ALU_SCL_210;
844 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
845
846 if (max_slots == 4) {
847 for (i = 0; i < max_slots; i++) {
848 if (bank_swizzle[i] == SQ_ALU_VEC_210)
849 return -1;
850 }
851 }
852 init_bank_swizzle(&bs);
853 if (scalar_only == false) {
854 for (i = 0; i < 4; i++) {
855 if (slots[i]) {
856 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
857 if (r)
858 break;
859 }
860 }
861 } else
862 r = 0;
863
864 if (!r && slots[4] && max_slots == 5) {
865 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
866 }
867 if (!r) {
868 for (i = 0; i < max_slots; i++) {
869 if (slots[i])
870 slots[i]->bank_swizzle = bank_swizzle[i];
871 }
872 return 0;
873 }
874
875 if (scalar_only) {
876 bank_swizzle[4]++;
877 } else {
878 for (i = 0; i < max_slots; i++) {
879 if (!slots[i] || !slots[i]->bank_swizzle_force) {
880 bank_swizzle[i]++;
881 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
882 break;
883 else
884 bank_swizzle[i] = SQ_ALU_VEC_012;
885 }
886 }
887 }
888 }
889
890 /* Couldn't find a working swizzle. */
891 return -1;
892 }
893
894 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
895 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
896 {
897 struct r600_bytecode_alu *prev[5];
898 int gpr[5], chan[5];
899 int i, j, r, src, num_src;
900 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
901
902 r = assign_alu_units(bc, alu_prev, prev);
903 if (r)
904 return r;
905
906 for (i = 0; i < max_slots; ++i) {
907 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
908 gpr[i] = prev[i]->dst.sel;
909 /* cube writes more than PV.X */
910 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
911 chan[i] = 0;
912 else
913 chan[i] = prev[i]->dst.chan;
914 } else
915 gpr[i] = -1;
916 }
917
918 for (i = 0; i < max_slots; ++i) {
919 struct r600_bytecode_alu *alu = slots[i];
920 if(!alu)
921 continue;
922
923 num_src = r600_bytecode_get_num_operands(bc, alu);
924 for (src = 0; src < num_src; ++src) {
925 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
926 continue;
927
928 if (bc->chip_class < CAYMAN) {
929 if (alu->src[src].sel == gpr[4] &&
930 alu->src[src].chan == chan[4] &&
931 alu_prev->pred_sel == alu->pred_sel) {
932 alu->src[src].sel = V_SQ_ALU_SRC_PS;
933 alu->src[src].chan = 0;
934 continue;
935 }
936 }
937
938 for (j = 0; j < 4; ++j) {
939 if (alu->src[src].sel == gpr[j] &&
940 alu->src[src].chan == j &&
941 alu_prev->pred_sel == alu->pred_sel) {
942 alu->src[src].sel = V_SQ_ALU_SRC_PV;
943 alu->src[src].chan = chan[j];
944 break;
945 }
946 }
947 }
948 }
949
950 return 0;
951 }
952
953 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
954 {
955 switch(value) {
956 case 0:
957 *sel = V_SQ_ALU_SRC_0;
958 break;
959 case 1:
960 *sel = V_SQ_ALU_SRC_1_INT;
961 break;
962 case -1:
963 *sel = V_SQ_ALU_SRC_M_1_INT;
964 break;
965 case 0x3F800000: /* 1.0f */
966 *sel = V_SQ_ALU_SRC_1;
967 break;
968 case 0x3F000000: /* 0.5f */
969 *sel = V_SQ_ALU_SRC_0_5;
970 break;
971 case 0xBF800000: /* -1.0f */
972 *sel = V_SQ_ALU_SRC_1;
973 *neg ^= 1;
974 break;
975 case 0xBF000000: /* -0.5f */
976 *sel = V_SQ_ALU_SRC_0_5;
977 *neg ^= 1;
978 break;
979 default:
980 *sel = V_SQ_ALU_SRC_LITERAL;
981 break;
982 }
983 }
984
985 /* compute how many literal are needed */
986 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
987 uint32_t literal[4], unsigned *nliteral)
988 {
989 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
990 unsigned i, j;
991
992 for (i = 0; i < num_src; ++i) {
993 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
994 uint32_t value = alu->src[i].value;
995 unsigned found = 0;
996 for (j = 0; j < *nliteral; ++j) {
997 if (literal[j] == value) {
998 found = 1;
999 break;
1000 }
1001 }
1002 if (!found) {
1003 if (*nliteral >= 4)
1004 return -EINVAL;
1005 literal[(*nliteral)++] = value;
1006 }
1007 }
1008 }
1009 return 0;
1010 }
1011
1012 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1013 struct r600_bytecode_alu *alu,
1014 uint32_t literal[4], unsigned nliteral)
1015 {
1016 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1017 unsigned i, j;
1018
1019 for (i = 0; i < num_src; ++i) {
1020 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1021 uint32_t value = alu->src[i].value;
1022 for (j = 0; j < nliteral; ++j) {
1023 if (literal[j] == value) {
1024 alu->src[i].chan = j;
1025 break;
1026 }
1027 }
1028 }
1029 }
1030 }
1031
1032 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1033 struct r600_bytecode_alu *alu_prev)
1034 {
1035 struct r600_bytecode_alu *prev[5];
1036 struct r600_bytecode_alu *result[5] = { NULL };
1037
1038 uint32_t literal[4], prev_literal[4];
1039 unsigned nliteral = 0, prev_nliteral = 0;
1040
1041 int i, j, r, src, num_src;
1042 int num_once_inst = 0;
1043 int have_mova = 0, have_rel = 0;
1044 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1045
1046 r = assign_alu_units(bc, alu_prev, prev);
1047 if (r)
1048 return r;
1049
1050 for (i = 0; i < max_slots; ++i) {
1051 if (prev[i]) {
1052 if (prev[i]->pred_sel)
1053 return 0;
1054 if (is_alu_once_inst(bc, prev[i]))
1055 return 0;
1056 }
1057 if (slots[i]) {
1058 if (slots[i]->pred_sel)
1059 return 0;
1060 if (is_alu_once_inst(bc, slots[i]))
1061 return 0;
1062 }
1063 }
1064
1065 for (i = 0; i < max_slots; ++i) {
1066 struct r600_bytecode_alu *alu;
1067
1068 if (num_once_inst > 0)
1069 return 0;
1070
1071 /* check number of literals */
1072 if (prev[i]) {
1073 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1074 return 0;
1075 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1076 return 0;
1077 if (is_alu_mova_inst(bc, prev[i])) {
1078 if (have_rel)
1079 return 0;
1080 have_mova = 1;
1081 }
1082 num_once_inst += is_alu_once_inst(bc, prev[i]);
1083 }
1084 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1085 return 0;
1086
1087 /* Let's check used slots. */
1088 if (prev[i] && !slots[i]) {
1089 result[i] = prev[i];
1090 continue;
1091 } else if (prev[i] && slots[i]) {
1092 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1093 /* Trans unit is still free try to use it. */
1094 if (is_alu_any_unit_inst(bc, slots[i])) {
1095 result[i] = prev[i];
1096 result[4] = slots[i];
1097 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1098 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1099 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1100 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1101 return 0;
1102
1103 result[i] = slots[i];
1104 result[4] = prev[i];
1105 } else
1106 return 0;
1107 } else
1108 return 0;
1109 } else if(!slots[i]) {
1110 continue;
1111 } else {
1112 if (max_slots == 5 && slots[i] && prev[4] &&
1113 slots[i]->dst.sel == prev[4]->dst.sel &&
1114 slots[i]->dst.chan == prev[4]->dst.chan &&
1115 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1116 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1117 return 0;
1118
1119 result[i] = slots[i];
1120 }
1121
1122 alu = slots[i];
1123 num_once_inst += is_alu_once_inst(bc, alu);
1124
1125 /* don't reschedule NOPs */
1126 if (is_nop_inst(bc, alu))
1127 return 0;
1128
1129 /* Let's check dst gpr. */
1130 if (alu->dst.rel) {
1131 if (have_mova)
1132 return 0;
1133 have_rel = 1;
1134 }
1135
1136 /* Let's check source gprs */
1137 num_src = r600_bytecode_get_num_operands(bc, alu);
1138 for (src = 0; src < num_src; ++src) {
1139 if (alu->src[src].rel) {
1140 if (have_mova)
1141 return 0;
1142 have_rel = 1;
1143 }
1144
1145 /* Constants don't matter. */
1146 if (!is_gpr(alu->src[src].sel))
1147 continue;
1148
1149 for (j = 0; j < max_slots; ++j) {
1150 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1151 continue;
1152
1153 /* If it's relative then we can't determin which gpr is really used. */
1154 if (prev[j]->dst.chan == alu->src[src].chan &&
1155 (prev[j]->dst.sel == alu->src[src].sel ||
1156 prev[j]->dst.rel || alu->src[src].rel))
1157 return 0;
1158 }
1159 }
1160 }
1161
1162 /* more than one PRED_ or KILL_ ? */
1163 if (num_once_inst > 1)
1164 return 0;
1165
1166 /* check if the result can still be swizzlet */
1167 r = check_and_set_bank_swizzle(bc, result);
1168 if (r)
1169 return 0;
1170
1171 /* looks like everything worked out right, apply the changes */
1172
1173 /* undo adding previus literals */
1174 bc->cf_last->ndw -= align(prev_nliteral, 2);
1175
1176 /* sort instructions */
1177 for (i = 0; i < max_slots; ++i) {
1178 slots[i] = result[i];
1179 if (result[i]) {
1180 LIST_DEL(&result[i]->list);
1181 result[i]->last = 0;
1182 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1183 }
1184 }
1185
1186 /* determine new last instruction */
1187 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1188
1189 /* determine new first instruction */
1190 for (i = 0; i < max_slots; ++i) {
1191 if (result[i]) {
1192 bc->cf_last->curr_bs_head = result[i];
1193 break;
1194 }
1195 }
1196
1197 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1198 bc->cf_last->prev2_bs_head = NULL;
1199
1200 return 0;
1201 }
1202
1203 /* we'll keep kcache sets sorted by bank & addr */
1204 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1205 struct r600_bytecode_kcache *kcache,
1206 unsigned bank, unsigned line)
1207 {
1208 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1209
1210 for (i = 0; i < kcache_banks; i++) {
1211 if (kcache[i].mode) {
1212 int d;
1213
1214 if (kcache[i].bank < bank)
1215 continue;
1216
1217 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1218 kcache[i].bank > bank) {
1219 /* try to insert new line */
1220 if (kcache[kcache_banks-1].mode) {
1221 /* all sets are in use */
1222 return -ENOMEM;
1223 }
1224
1225 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1226 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1227 kcache[i].bank = bank;
1228 kcache[i].addr = line;
1229 return 0;
1230 }
1231
1232 d = line - kcache[i].addr;
1233
1234 if (d == -1) {
1235 kcache[i].addr--;
1236 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1237 /* we are prepending the line to the current set,
1238 * discarding the existing second line,
1239 * so we'll have to insert line+2 after it */
1240 line += 2;
1241 continue;
1242 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1243 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1244 return 0;
1245 } else {
1246 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1247 return -ENOMEM;
1248 }
1249 } else if (d == 1) {
1250 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1251 return 0;
1252 } else if (d == 0)
1253 return 0;
1254 } else { /* free kcache set - use it */
1255 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1256 kcache[i].bank = bank;
1257 kcache[i].addr = line;
1258 return 0;
1259 }
1260 }
1261 return -ENOMEM;
1262 }
1263
1264 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1265 struct r600_bytecode_kcache *kcache,
1266 struct r600_bytecode_alu *alu)
1267 {
1268 int i, r;
1269
1270 for (i = 0; i < 3; i++) {
1271 unsigned bank, line, sel = alu->src[i].sel;
1272
1273 if (sel < 512)
1274 continue;
1275
1276 bank = alu->src[i].kc_bank;
1277 line = (sel-512)>>4;
1278
1279 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1280 return r;
1281 }
1282 return 0;
1283 }
1284
1285 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1286 struct r600_bytecode_alu *alu,
1287 struct r600_bytecode_kcache * kcache)
1288 {
1289 int i, j;
1290
1291 /* Alter the src operands to refer to the kcache. */
1292 for (i = 0; i < 3; ++i) {
1293 static const unsigned int base[] = {128, 160, 256, 288};
1294 unsigned int line, sel = alu->src[i].sel, found = 0;
1295
1296 if (sel < 512)
1297 continue;
1298
1299 sel -= 512;
1300 line = sel>>4;
1301
1302 for (j = 0; j < 4 && !found; ++j) {
1303 switch (kcache[j].mode) {
1304 case V_SQ_CF_KCACHE_NOP:
1305 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1306 R600_ERR("unexpected kcache line mode\n");
1307 return -ENOMEM;
1308 default:
1309 if (kcache[j].bank == alu->src[i].kc_bank &&
1310 kcache[j].addr <= line &&
1311 line < kcache[j].addr + kcache[j].mode) {
1312 alu->src[i].sel = sel - (kcache[j].addr<<4);
1313 alu->src[i].sel += base[j];
1314 found=1;
1315 }
1316 }
1317 }
1318 }
1319 return 0;
1320 }
1321
1322 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1323 {
1324 struct r600_bytecode_kcache kcache_sets[4];
1325 struct r600_bytecode_kcache *kcache = kcache_sets;
1326 int r;
1327
1328 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1329
1330 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1331 /* can't alloc, need to start new clause */
1332 if ((r = r600_bytecode_add_cf(bc))) {
1333 return r;
1334 }
1335 bc->cf_last->inst = type;
1336
1337 /* retry with the new clause */
1338 kcache = bc->cf_last->kcache;
1339 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1340 /* can't alloc again- should never happen */
1341 return r;
1342 }
1343 } else {
1344 /* update kcache sets */
1345 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1346 }
1347
1348 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1349 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1350 if (bc->chip_class < EVERGREEN)
1351 return -ENOMEM;
1352 bc->cf_last->eg_alu_extended = 1;
1353 }
1354
1355 return 0;
1356 }
1357
1358 static int insert_nop_r6xx(struct r600_bytecode *bc)
1359 {
1360 struct r600_bytecode_alu alu;
1361 int r, i;
1362
1363 for (i = 0; i < 4; i++) {
1364 memset(&alu, 0, sizeof(alu));
1365 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1366 alu.src[0].chan = i;
1367 alu.dst.chan = i;
1368 alu.last = (i == 3);
1369 r = r600_bytecode_add_alu(bc, &alu);
1370 if (r)
1371 return r;
1372 }
1373 return 0;
1374 }
1375
1376 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1377 static int load_ar_r6xx(struct r600_bytecode *bc)
1378 {
1379 struct r600_bytecode_alu alu;
1380 int r;
1381
1382 if (bc->ar_loaded)
1383 return 0;
1384
1385 /* hack to avoid making MOVA the last instruction in the clause */
1386 if ((bc->cf_last->ndw>>1) >= 110)
1387 bc->force_add_cf = 1;
1388
1389 memset(&alu, 0, sizeof(alu));
1390 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1391 alu.src[0].sel = bc->ar_reg;
1392 alu.last = 1;
1393 alu.index_mode = INDEX_MODE_LOOP;
1394 r = r600_bytecode_add_alu(bc, &alu);
1395 if (r)
1396 return r;
1397
1398 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1399 bc->ar_loaded = 1;
1400 return 0;
1401 }
1402
1403 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1404 static int load_ar(struct r600_bytecode *bc)
1405 {
1406 struct r600_bytecode_alu alu;
1407 int r;
1408
1409 if (bc->ar_handling)
1410 return load_ar_r6xx(bc);
1411
1412 if (bc->ar_loaded)
1413 return 0;
1414
1415 /* hack to avoid making MOVA the last instruction in the clause */
1416 if ((bc->cf_last->ndw>>1) >= 110)
1417 bc->force_add_cf = 1;
1418
1419 memset(&alu, 0, sizeof(alu));
1420 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1421 alu.src[0].sel = bc->ar_reg;
1422 alu.last = 1;
1423 r = r600_bytecode_add_alu(bc, &alu);
1424 if (r)
1425 return r;
1426
1427 bc->cf_last->r6xx_uses_waterfall = 1;
1428 bc->ar_loaded = 1;
1429 return 0;
1430 }
1431
1432 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1433 {
1434 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1435 struct r600_bytecode_alu *lalu;
1436 int i, r;
1437
1438 if (nalu == NULL)
1439 return -ENOMEM;
1440 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1441
1442 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1443 /* check if we could add it anyway */
1444 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1445 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1446 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1447 if (lalu->execute_mask) {
1448 bc->force_add_cf = 1;
1449 break;
1450 }
1451 }
1452 } else
1453 bc->force_add_cf = 1;
1454 }
1455
1456 /* cf can contains only alu or only vtx or only tex */
1457 if (bc->cf_last == NULL || bc->force_add_cf) {
1458 r = r600_bytecode_add_cf(bc);
1459 if (r) {
1460 free(nalu);
1461 return r;
1462 }
1463 }
1464 bc->cf_last->inst = type;
1465
1466 /* Check AR usage and load it if required */
1467 for (i = 0; i < 3; i++)
1468 if (nalu->src[i].rel && !bc->ar_loaded)
1469 load_ar(bc);
1470
1471 if (nalu->dst.rel && !bc->ar_loaded)
1472 load_ar(bc);
1473
1474 /* Setup the kcache for this ALU instruction. This will start a new
1475 * ALU clause if needed. */
1476 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1477 free(nalu);
1478 return r;
1479 }
1480
1481 if (!bc->cf_last->curr_bs_head) {
1482 bc->cf_last->curr_bs_head = nalu;
1483 }
1484 /* number of gpr == the last gpr used in any alu */
1485 for (i = 0; i < 3; i++) {
1486 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1487 bc->ngpr = nalu->src[i].sel + 1;
1488 }
1489 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1490 r600_bytecode_special_constants(nalu->src[i].value,
1491 &nalu->src[i].sel, &nalu->src[i].neg);
1492 }
1493 if (nalu->dst.sel >= bc->ngpr) {
1494 bc->ngpr = nalu->dst.sel + 1;
1495 }
1496 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1497 /* each alu use 2 dwords */
1498 bc->cf_last->ndw += 2;
1499 bc->ndw += 2;
1500
1501 /* process cur ALU instructions for bank swizzle */
1502 if (nalu->last) {
1503 uint32_t literal[4];
1504 unsigned nliteral;
1505 struct r600_bytecode_alu *slots[5];
1506 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1507 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1508 if (r)
1509 return r;
1510
1511 if (bc->cf_last->prev_bs_head) {
1512 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1513 if (r)
1514 return r;
1515 }
1516
1517 if (bc->cf_last->prev_bs_head) {
1518 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1519 if (r)
1520 return r;
1521 }
1522
1523 r = check_and_set_bank_swizzle(bc, slots);
1524 if (r)
1525 return r;
1526
1527 for (i = 0, nliteral = 0; i < max_slots; i++) {
1528 if (slots[i]) {
1529 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1530 if (r)
1531 return r;
1532 }
1533 }
1534 bc->cf_last->ndw += align(nliteral, 2);
1535
1536 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1537 * worst case */
1538 if ((bc->cf_last->ndw >> 1) >= 120) {
1539 bc->force_add_cf = 1;
1540 }
1541
1542 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1543 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1544 bc->cf_last->curr_bs_head = NULL;
1545 }
1546
1547 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1548 insert_nop_r6xx(bc);
1549
1550 return 0;
1551 }
1552
1553 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1554 {
1555 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1556 }
1557
1558 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1559 {
1560 switch (bc->chip_class) {
1561 case R600:
1562 return 8;
1563
1564 case R700:
1565 case EVERGREEN:
1566 case CAYMAN:
1567 return 16;
1568
1569 default:
1570 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1571 return 8;
1572 }
1573 }
1574
1575 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1576 {
1577 switch (bc->chip_class) {
1578 case R700:
1579 case R600:
1580 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1581 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1582 case EVERGREEN:
1583 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1584 case CAYMAN:
1585 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1586 default:
1587 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1588 return FALSE;
1589 }
1590 }
1591
1592 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1593 {
1594 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1595 int r;
1596
1597 if (nvtx == NULL)
1598 return -ENOMEM;
1599 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1600
1601 /* cf can contains only alu or only vtx or only tex */
1602 if (bc->cf_last == NULL ||
1603 last_inst_was_not_vtx_fetch(bc) ||
1604 bc->force_add_cf) {
1605 r = r600_bytecode_add_cf(bc);
1606 if (r) {
1607 free(nvtx);
1608 return r;
1609 }
1610 switch (bc->chip_class) {
1611 case R600:
1612 case R700:
1613 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1614 break;
1615 case EVERGREEN:
1616 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1617 break;
1618 case CAYMAN:
1619 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1620 break;
1621 default:
1622 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1623 return -EINVAL;
1624 }
1625 }
1626 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1627 /* each fetch use 4 dwords */
1628 bc->cf_last->ndw += 4;
1629 bc->ndw += 4;
1630 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1631 bc->force_add_cf = 1;
1632
1633 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1634 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1635
1636 return 0;
1637 }
1638
1639 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1640 {
1641 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1642 int r;
1643
1644 if (ntex == NULL)
1645 return -ENOMEM;
1646 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1647
1648 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1649 if (bc->cf_last != NULL &&
1650 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1651 struct r600_bytecode_tex *ttex;
1652 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1653 if (ttex->dst_gpr == ntex->src_gpr) {
1654 bc->force_add_cf = 1;
1655 break;
1656 }
1657 }
1658 /* slight hack to make gradients always go into same cf */
1659 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1660 bc->force_add_cf = 1;
1661 }
1662
1663 /* cf can contains only alu or only vtx or only tex */
1664 if (bc->cf_last == NULL ||
1665 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1666 bc->force_add_cf) {
1667 r = r600_bytecode_add_cf(bc);
1668 if (r) {
1669 free(ntex);
1670 return r;
1671 }
1672 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1673 }
1674 if (ntex->src_gpr >= bc->ngpr) {
1675 bc->ngpr = ntex->src_gpr + 1;
1676 }
1677 if (ntex->dst_gpr >= bc->ngpr) {
1678 bc->ngpr = ntex->dst_gpr + 1;
1679 }
1680 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1681 /* each texture fetch use 4 dwords */
1682 bc->cf_last->ndw += 4;
1683 bc->ndw += 4;
1684 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1685 bc->force_add_cf = 1;
1686 return 0;
1687 }
1688
1689 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1690 {
1691 int r;
1692 r = r600_bytecode_add_cf(bc);
1693 if (r)
1694 return r;
1695
1696 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1697 bc->cf_last->inst = inst;
1698 return 0;
1699 }
1700
1701 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1702 {
1703 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1704 }
1705
1706 /* common to all 3 families */
1707 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1708 {
1709 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1710 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1711 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1712 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1713 if (bc->chip_class < CAYMAN)
1714 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1715 id++;
1716 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1717 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1718 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1719 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1720 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1721 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1722 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1723 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1724 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1725 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1726 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1727 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1728 if (bc->chip_class < CAYMAN)
1729 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1730 id++;
1731 bc->bytecode[id++] = 0;
1732 return 0;
1733 }
1734
1735 /* common to all 3 families */
1736 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1737 {
1738 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1739 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1740 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1741 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1742 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1743 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1744 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1745 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1746 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1747 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1748 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1749 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1750 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1751 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1752 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1753 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1754 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1755 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1756 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1757 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1758 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1759 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1760 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1761 bc->bytecode[id++] = 0;
1762 return 0;
1763 }
1764
1765 /* r600 only, r700/eg bits in r700_asm.c */
1766 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1767 {
1768 /* don't replace gpr by pv or ps for destination register */
1769 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1770 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1771 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1772 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1773 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1774 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1775 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1776 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1777 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1778 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1779 S_SQ_ALU_WORD0_LAST(alu->last);
1780
1781 if (alu->is_op3) {
1782 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1783 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1784 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1785 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1786 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1787 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1788 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1789 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1790 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1791 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1792 } else {
1793 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1794 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1795 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1796 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1797 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1798 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1799 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1800 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1801 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1802 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1803 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1804 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1805 }
1806 return 0;
1807 }
1808
1809 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1810 {
1811 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1812 *bytecode++ = cf->inst |
1813 S_SQ_CF_WORD1_BARRIER(1) |
1814 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1815 }
1816
1817 /* common for r600/r700 - eg in eg_asm.c */
1818 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1819 {
1820 unsigned id = cf->id;
1821
1822 switch (cf->inst) {
1823 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1824 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1825 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1826 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1827 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1828 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1829 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1830 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1831
1832 bc->bytecode[id++] = cf->inst |
1833 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1834 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1835 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1836 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1837 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1838 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1839 break;
1840 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1841 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1842 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1843 if (bc->chip_class == R700)
1844 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1845 else
1846 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1847 break;
1848 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1849 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1850 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1851 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1852 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1853 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1854 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1855 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1856 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1857 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1858 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1859 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1860 cf->output.inst |
1861 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1862 break;
1863 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1864 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1865 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1866 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1867 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1868 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1869 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1870 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1871 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1872 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1873 cf->output.inst |
1874 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1875 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1876 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1877 break;
1878 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1879 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1880 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1881 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1882 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1883 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1884 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1885 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1886 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1887 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1888 bc->bytecode[id++] = cf->inst |
1889 S_SQ_CF_WORD1_BARRIER(1) |
1890 S_SQ_CF_WORD1_COND(cf->cond) |
1891 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1892
1893 break;
1894 default:
1895 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1896 return -EINVAL;
1897 }
1898 return 0;
1899 }
1900
1901 int r600_bytecode_build(struct r600_bytecode *bc)
1902 {
1903 struct r600_bytecode_cf *cf;
1904 struct r600_bytecode_alu *alu;
1905 struct r600_bytecode_vtx *vtx;
1906 struct r600_bytecode_tex *tex;
1907 uint32_t literal[4];
1908 unsigned nliteral;
1909 unsigned addr;
1910 int i, r;
1911
1912 if (bc->callstack[0].max > 0)
1913 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1914 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1915 bc->nstack = 1;
1916 }
1917
1918 /* first path compute addr of each CF block */
1919 /* addr start after all the CF instructions */
1920 addr = bc->cf_last->id + 2;
1921 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1922 if (bc->chip_class >= EVERGREEN) {
1923 switch (cf->inst) {
1924 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1925 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1926 /* fetch node need to be 16 bytes aligned*/
1927 addr += 3;
1928 addr &= 0xFFFFFFFCUL;
1929 break;
1930 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1931 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1932 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1933 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1934 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1935 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1936 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1937 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1938 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1939 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1940 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1941 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1942 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1943 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1944 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1945 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1946 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1947 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1948 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1949 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1950 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1951 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1952 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1953 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1954 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1955 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1956 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1957 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1958 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1959 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1960 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1961 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1962 case CF_NATIVE:
1963 break;
1964 default:
1965 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1966 return -EINVAL;
1967 }
1968 } else {
1969 switch (cf->inst) {
1970 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1971 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1972 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1973 /* fetch node need to be 16 bytes aligned*/
1974 addr += 3;
1975 addr &= 0xFFFFFFFCUL;
1976 break;
1977 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1978 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1979 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1980 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1981 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1982 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1983 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1984 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1985 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1986 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1987 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1988 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1989 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1990 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1991 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1992 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1993 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1994 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1995 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1996 break;
1997 default:
1998 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1999 return -EINVAL;
2000 }
2001 }
2002 cf->addr = addr;
2003 addr += cf->ndw;
2004 bc->ndw = cf->addr + cf->ndw;
2005 }
2006 free(bc->bytecode);
2007 bc->bytecode = calloc(1, bc->ndw * 4);
2008 if (bc->bytecode == NULL)
2009 return -ENOMEM;
2010 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2011 addr = cf->addr;
2012 if (bc->chip_class >= EVERGREEN) {
2013 r = eg_bytecode_cf_build(bc, cf);
2014 if (r)
2015 return r;
2016
2017 switch (cf->inst) {
2018 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2019 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2020 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2021 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2022 nliteral = 0;
2023 memset(literal, 0, sizeof(literal));
2024 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2025 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2026 if (r)
2027 return r;
2028 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2029 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2030
2031 switch(bc->chip_class) {
2032 case EVERGREEN: /* eg alu is same encoding as r700 */
2033 case CAYMAN:
2034 r = r700_bytecode_alu_build(bc, alu, addr);
2035 break;
2036 default:
2037 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2038 return -EINVAL;
2039 }
2040 if (r)
2041 return r;
2042 addr += 2;
2043 if (alu->last) {
2044 for (i = 0; i < align(nliteral, 2); ++i) {
2045 bc->bytecode[addr++] = literal[i];
2046 }
2047 nliteral = 0;
2048 memset(literal, 0, sizeof(literal));
2049 }
2050 }
2051 break;
2052 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2053 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2054 r = r600_bytecode_vtx_build(bc, vtx, addr);
2055 if (r)
2056 return r;
2057 addr += 4;
2058 }
2059 break;
2060 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2061 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2062 assert(bc->chip_class >= EVERGREEN);
2063 r = r600_bytecode_vtx_build(bc, vtx, addr);
2064 if (r)
2065 return r;
2066 addr += 4;
2067 }
2068 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2069 r = r600_bytecode_tex_build(bc, tex, addr);
2070 if (r)
2071 return r;
2072 addr += 4;
2073 }
2074 break;
2075 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2076 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2077 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2078 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2079 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2080 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2081 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2082 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2083 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2084 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2085 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2086 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2087 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2088 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2089 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2090 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2091 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2092 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2093 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2094 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2095 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2096 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2097 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2098 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2099 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2100 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2101 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2102 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2103 break;
2104 case CF_NATIVE:
2105 break;
2106 default:
2107 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2108 return -EINVAL;
2109 }
2110 } else {
2111 r = r600_bytecode_cf_build(bc, cf);
2112 if (r)
2113 return r;
2114
2115 switch (cf->inst) {
2116 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2117 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2118 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2119 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2120 nliteral = 0;
2121 memset(literal, 0, sizeof(literal));
2122 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2123 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2124 if (r)
2125 return r;
2126 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2127 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2128
2129 switch(bc->chip_class) {
2130 case R600:
2131 r = r600_bytecode_alu_build(bc, alu, addr);
2132 break;
2133 case R700:
2134 r = r700_bytecode_alu_build(bc, alu, addr);
2135 break;
2136 default:
2137 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2138 return -EINVAL;
2139 }
2140 if (r)
2141 return r;
2142 addr += 2;
2143 if (alu->last) {
2144 for (i = 0; i < align(nliteral, 2); ++i) {
2145 bc->bytecode[addr++] = literal[i];
2146 }
2147 nliteral = 0;
2148 memset(literal, 0, sizeof(literal));
2149 }
2150 }
2151 break;
2152 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2153 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2154 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2155 r = r600_bytecode_vtx_build(bc, vtx, addr);
2156 if (r)
2157 return r;
2158 addr += 4;
2159 }
2160 break;
2161 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2162 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2163 r = r600_bytecode_tex_build(bc, tex, addr);
2164 if (r)
2165 return r;
2166 addr += 4;
2167 }
2168 break;
2169 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2170 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2171 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2172 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2173 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2174 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2175 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2176 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2177 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2178 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2179 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2180 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2181 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2182 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2183 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2184 break;
2185 default:
2186 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2187 return -EINVAL;
2188 }
2189 }
2190 }
2191 return 0;
2192 }
2193
2194 void r600_bytecode_clear(struct r600_bytecode *bc)
2195 {
2196 struct r600_bytecode_cf *cf = NULL, *next_cf;
2197
2198 free(bc->bytecode);
2199 bc->bytecode = NULL;
2200
2201 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2202 struct r600_bytecode_alu *alu = NULL, *next_alu;
2203 struct r600_bytecode_tex *tex = NULL, *next_tex;
2204 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2205
2206 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2207 free(alu);
2208 }
2209
2210 LIST_INITHEAD(&cf->alu);
2211
2212 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2213 free(tex);
2214 }
2215
2216 LIST_INITHEAD(&cf->tex);
2217
2218 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2219 free(vtx);
2220 }
2221
2222 LIST_INITHEAD(&cf->vtx);
2223
2224 free(cf);
2225 }
2226
2227 LIST_INITHEAD(&cf->list);
2228 }
2229
2230 void r600_bytecode_dump(struct r600_bytecode *bc)
2231 {
2232 struct r600_bytecode_cf *cf = NULL;
2233 struct r600_bytecode_alu *alu = NULL;
2234 struct r600_bytecode_vtx *vtx = NULL;
2235 struct r600_bytecode_tex *tex = NULL;
2236
2237 unsigned i, id;
2238 uint32_t literal[4];
2239 unsigned nliteral;
2240 char chip = '6';
2241
2242 switch (bc->chip_class) {
2243 case R700:
2244 chip = '7';
2245 break;
2246 case EVERGREEN:
2247 chip = 'E';
2248 break;
2249 case CAYMAN:
2250 chip = 'C';
2251 break;
2252 case R600:
2253 default:
2254 chip = '6';
2255 break;
2256 }
2257 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2258 fprintf(stderr, " %c\n", chip);
2259
2260 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2261 id = cf->id;
2262
2263 if (bc->chip_class >= EVERGREEN) {
2264 switch (cf->inst) {
2265 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2266 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2267 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2268 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2269 if (cf->eg_alu_extended) {
2270 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2271 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2272 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2273 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2274 id++;
2275 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2276 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2277 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2278 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2279 id++;
2280 }
2281
2282 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2283 fprintf(stderr, "ADDR:%d ", cf->addr);
2284 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2285 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2286 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2287 id++;
2288 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2289 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2290 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2291 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2292 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2293 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2294 break;
2295 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2296 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2297 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2298 fprintf(stderr, "ADDR:%d\n", cf->addr);
2299 id++;
2300 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2301 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2302 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2303 break;
2304 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2305 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2306 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2307 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2308 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2309 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2310 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2311 id++;
2312 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2313 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2314 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2315 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2316 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2317 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2318 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2319 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2320 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2321 break;
2322 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2323 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2324 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2325 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2326 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2327 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2328 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2329 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2330 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2331 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2332 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2333 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2334 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2335 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2336 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2337 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2338 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2339 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2340 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2341 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2342 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2343 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2344 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2345 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2346 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2347 id++;
2348 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2349 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2350 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2351 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2352 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2353 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2354 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2355 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2356 fprintf(stderr, "INST:%d ", cf->output.inst);
2357 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2358 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2359 break;
2360 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2361 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2362 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2363 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2364 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2365 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2366 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2367 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2368 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2369 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2370 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2371 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2372 id++;
2373 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2374 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2375 fprintf(stderr, "COND:%X ", cf->cond);
2376 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2377 break;
2378 case CF_NATIVE:
2379 fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
2380 fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
2381 break;
2382 default:
2383 R600_ERR("Unknown instruction %0x\n", cf->inst);
2384 }
2385 } else {
2386 switch (cf->inst) {
2387 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2388 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2389 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2390 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2391 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2392 fprintf(stderr, "ADDR:%d ", cf->addr);
2393 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2394 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2395 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2396 id++;
2397 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2398 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2399 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2400 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2401 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2402 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2403 break;
2404 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2405 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2406 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2407 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2408 fprintf(stderr, "ADDR:%d\n", cf->addr);
2409 id++;
2410 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2411 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2412 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2413 break;
2414 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2415 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2416 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2417 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2418 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2419 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2420 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2421 id++;
2422 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2423 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2424 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2425 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2426 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2427 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2428 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2429 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2430 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2431 break;
2432 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2433 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2434 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2435 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2436 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2437 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2438 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2439 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2440 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2441 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2442 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2443 id++;
2444 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2445 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2446 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2447 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2448 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2449 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2450 fprintf(stderr, "INST:%d ", cf->output.inst);
2451 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2452 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2453 break;
2454 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2455 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2456 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2457 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2458 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2459 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2460 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2461 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2462 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2463 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2464 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2465 id++;
2466 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2467 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2468 fprintf(stderr, "COND:%X ", cf->cond);
2469 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2470 break;
2471 default:
2472 R600_ERR("Unknown instruction %0x\n", cf->inst);
2473 }
2474 }
2475
2476 id = cf->addr;
2477 nliteral = 0;
2478 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2479 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2480
2481 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2482 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2483 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2484 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2485 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2486 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2487 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2488 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2489 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2490 fprintf(stderr, "IM:%d) ", alu->index_mode);
2491 fprintf(stderr, "PRED_SEL:%d ", alu->pred_sel);
2492 fprintf(stderr, "LAST:%d)\n", alu->last);
2493 id++;
2494 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2495 fprintf(stderr, "INST:0x%x ", alu->inst);
2496 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2497 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2498 fprintf(stderr, "REL:%d ", alu->dst.rel);
2499 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2500 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2501 if (alu->is_op3) {
2502 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2503 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2504 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2505 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2506 } else {
2507 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2508 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2509 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2510 fprintf(stderr, "OMOD:%d ", alu->omod);
2511 fprintf(stderr, "EXECUTE_MASK:%d ", alu->execute_mask);
2512 fprintf(stderr, "UPDATE_PRED:%d\n", alu->update_pred);
2513 }
2514
2515 id++;
2516 if (alu->last) {
2517 for (i = 0; i < nliteral; i++, id++) {
2518 float *f = (float*)(bc->bytecode + id);
2519 fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
2520 *(bc->bytecode + id));
2521 }
2522 id += nliteral & 1;
2523 nliteral = 0;
2524 }
2525 }
2526
2527 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2528 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2529 fprintf(stderr, "INST:0x%x ", tex->inst);
2530 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2531 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2532 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2533 id++;
2534 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2535 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2536 fprintf(stderr, "REL:%d ", tex->dst_rel);
2537 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2538 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2539 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2540 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2541 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2542 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2543 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2544 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2545 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2546 id++;
2547 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2548 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2549 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2550 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2551 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2552 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2553 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2554 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2555 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2556 id++;
2557 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2558 id++;
2559 }
2560
2561 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2562 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2563 fprintf(stderr, "INST:%d ", vtx->inst);
2564 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2565 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2566 id++;
2567 /* This assumes that no semantic fetches exist */
2568 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2569 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2570 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2571 if (bc->chip_class < CAYMAN)
2572 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2573 else
2574 fprintf(stderr, "SEL_Y:%d) ", 0);
2575 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2576 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2577 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2578 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2579 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2580 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2581 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2582 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2583 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2584 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2585 id++;
2586 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2587 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2588 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2589 /* XXX */
2590 id++;
2591 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2592 id++;
2593 }
2594 }
2595
2596 fprintf(stderr, "--------------------------------------\n");
2597 }
2598
2599 static void r600_vertex_data_type(enum pipe_format pformat,
2600 unsigned *format,
2601 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2602 {
2603 const struct util_format_description *desc;
2604 unsigned i;
2605
2606 *format = 0;
2607 *num_format = 0;
2608 *format_comp = 0;
2609 *endian = ENDIAN_NONE;
2610
2611 desc = util_format_description(pformat);
2612 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2613 goto out_unknown;
2614 }
2615
2616 /* Find the first non-VOID channel. */
2617 for (i = 0; i < 4; i++) {
2618 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2619 break;
2620 }
2621 }
2622
2623 *endian = r600_endian_swap(desc->channel[i].size);
2624
2625 switch (desc->channel[i].type) {
2626 /* Half-floats, floats, ints */
2627 case UTIL_FORMAT_TYPE_FLOAT:
2628 switch (desc->channel[i].size) {
2629 case 16:
2630 switch (desc->nr_channels) {
2631 case 1:
2632 *format = FMT_16_FLOAT;
2633 break;
2634 case 2:
2635 *format = FMT_16_16_FLOAT;
2636 break;
2637 case 3:
2638 case 4:
2639 *format = FMT_16_16_16_16_FLOAT;
2640 break;
2641 }
2642 break;
2643 case 32:
2644 switch (desc->nr_channels) {
2645 case 1:
2646 *format = FMT_32_FLOAT;
2647 break;
2648 case 2:
2649 *format = FMT_32_32_FLOAT;
2650 break;
2651 case 3:
2652 *format = FMT_32_32_32_FLOAT;
2653 break;
2654 case 4:
2655 *format = FMT_32_32_32_32_FLOAT;
2656 break;
2657 }
2658 break;
2659 default:
2660 goto out_unknown;
2661 }
2662 break;
2663 /* Unsigned ints */
2664 case UTIL_FORMAT_TYPE_UNSIGNED:
2665 /* Signed ints */
2666 case UTIL_FORMAT_TYPE_SIGNED:
2667 switch (desc->channel[i].size) {
2668 case 8:
2669 switch (desc->nr_channels) {
2670 case 1:
2671 *format = FMT_8;
2672 break;
2673 case 2:
2674 *format = FMT_8_8;
2675 break;
2676 case 3:
2677 case 4:
2678 *format = FMT_8_8_8_8;
2679 break;
2680 }
2681 break;
2682 case 10:
2683 if (desc->nr_channels != 4)
2684 goto out_unknown;
2685
2686 *format = FMT_2_10_10_10;
2687 break;
2688 case 16:
2689 switch (desc->nr_channels) {
2690 case 1:
2691 *format = FMT_16;
2692 break;
2693 case 2:
2694 *format = FMT_16_16;
2695 break;
2696 case 3:
2697 case 4:
2698 *format = FMT_16_16_16_16;
2699 break;
2700 }
2701 break;
2702 case 32:
2703 switch (desc->nr_channels) {
2704 case 1:
2705 *format = FMT_32;
2706 break;
2707 case 2:
2708 *format = FMT_32_32;
2709 break;
2710 case 3:
2711 *format = FMT_32_32_32;
2712 break;
2713 case 4:
2714 *format = FMT_32_32_32_32;
2715 break;
2716 }
2717 break;
2718 default:
2719 goto out_unknown;
2720 }
2721 break;
2722 default:
2723 goto out_unknown;
2724 }
2725
2726 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2727 *format_comp = 1;
2728 }
2729
2730 *num_format = 0;
2731 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2732 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2733 if (!desc->channel[i].normalized) {
2734 if (desc->channel[i].pure_integer)
2735 *num_format = 1;
2736 else
2737 *num_format = 2;
2738 }
2739 }
2740 return;
2741 out_unknown:
2742 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2743 }
2744
2745 int r600_vertex_elements_build_fetch_shader(struct r600_context *rctx, struct r600_vertex_element *ve)
2746 {
2747 static int dump_shaders = -1;
2748
2749 struct r600_bytecode bc;
2750 struct r600_bytecode_vtx vtx;
2751 struct pipe_vertex_element *elements = ve->elements;
2752 const struct util_format_description *desc;
2753 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2754 unsigned format, num_format, format_comp, endian;
2755 uint32_t *bytecode;
2756 int i, r;
2757
2758 memset(&bc, 0, sizeof(bc));
2759 r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
2760
2761 for (i = 0; i < ve->count; i++) {
2762 if (elements[i].instance_divisor > 1) {
2763 struct r600_bytecode_alu alu;
2764
2765 memset(&alu, 0, sizeof(alu));
2766 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2767 alu.src[0].sel = 0;
2768 alu.src[0].chan = 3;
2769
2770 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2771 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2772
2773 alu.dst.sel = i + 1;
2774 alu.dst.chan = 3;
2775 alu.dst.write = 1;
2776 alu.last = 1;
2777
2778 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2779 r600_bytecode_clear(&bc);
2780 return r;
2781 }
2782 }
2783 }
2784
2785 for (i = 0; i < ve->count; i++) {
2786 r600_vertex_data_type(ve->elements[i].src_format,
2787 &format, &num_format, &format_comp, &endian);
2788
2789 desc = util_format_description(ve->elements[i].src_format);
2790 if (desc == NULL) {
2791 r600_bytecode_clear(&bc);
2792 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2793 return -EINVAL;
2794 }
2795
2796 if (elements[i].src_offset > 65535) {
2797 r600_bytecode_clear(&bc);
2798 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2799 return -EINVAL;
2800 }
2801
2802 memset(&vtx, 0, sizeof(vtx));
2803 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2804 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2805 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2806 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2807 vtx.mega_fetch_count = 0x1F;
2808 vtx.dst_gpr = i + 1;
2809 vtx.dst_sel_x = desc->swizzle[0];
2810 vtx.dst_sel_y = desc->swizzle[1];
2811 vtx.dst_sel_z = desc->swizzle[2];
2812 vtx.dst_sel_w = desc->swizzle[3];
2813 vtx.data_format = format;
2814 vtx.num_format_all = num_format;
2815 vtx.format_comp_all = format_comp;
2816 vtx.srf_mode_all = 1;
2817 vtx.offset = elements[i].src_offset;
2818 vtx.endian = endian;
2819
2820 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2821 r600_bytecode_clear(&bc);
2822 return r;
2823 }
2824 }
2825
2826 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2827
2828 if ((r = r600_bytecode_build(&bc))) {
2829 r600_bytecode_clear(&bc);
2830 return r;
2831 }
2832
2833 if (dump_shaders == -1)
2834 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2835
2836 if (dump_shaders) {
2837 fprintf(stderr, "--------------------------------------------------------------\n");
2838 r600_bytecode_dump(&bc);
2839 fprintf(stderr, "______________________________________________________________\n");
2840 }
2841
2842 ve->fs_size = bc.ndw*4;
2843
2844 ve->fetch_shader = (struct r600_resource*)
2845 pipe_buffer_create(rctx->context.screen,
2846 PIPE_BIND_CUSTOM,
2847 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2848 if (ve->fetch_shader == NULL) {
2849 r600_bytecode_clear(&bc);
2850 return -ENOMEM;
2851 }
2852
2853 bytecode = rctx->ws->buffer_map(ve->fetch_shader->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
2854 if (bytecode == NULL) {
2855 r600_bytecode_clear(&bc);
2856 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2857 return -ENOMEM;
2858 }
2859
2860 if (R600_BIG_ENDIAN) {
2861 for (i = 0; i < ve->fs_size / 4; ++i) {
2862 bytecode[i] = bswap_32(bc.bytecode[i]);
2863 }
2864 } else {
2865 memcpy(bytecode, bc.bytecode, ve->fs_size);
2866 }
2867
2868 rctx->ws->buffer_unmap(ve->fetch_shader->cs_buf);
2869 r600_bytecode_clear(&bc);
2870
2871 if (rctx->chip_class >= EVERGREEN)
2872 evergreen_fetch_shader(&rctx->context, ve);
2873 else
2874 r600_fetch_shader(&rctx->context, ve);
2875
2876 return 0;
2877 }