2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
31 #include "util/u_memory.h"
32 #include "pipe/p_shader_tokens.h"
34 #define NUM_OF_CYCLES 3
35 #define NUM_OF_COMPONENTS 4
37 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
42 switch (bc
->chip_class
) {
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT
:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL
:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT
:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
118 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
:
119 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
:
122 "Need instruction operand number for 0x%x.\n", alu
->inst
);
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT
:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY
:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW
:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL
:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
198 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
:
199 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
:
200 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0
:
201 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT
:
202 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
:
205 "Need instruction operand number for 0x%x.\n", alu
->inst
);
213 int r700_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
);
215 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
217 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
221 LIST_INITHEAD(&cf
->list
);
222 LIST_INITHEAD(&cf
->alu
);
223 LIST_INITHEAD(&cf
->vtx
);
224 LIST_INITHEAD(&cf
->tex
);
228 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
230 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
234 LIST_INITHEAD(&alu
->list
);
238 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
240 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
244 LIST_INITHEAD(&vtx
->list
);
248 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
250 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
254 LIST_INITHEAD(&tex
->list
);
258 void r600_bytecode_init(struct r600_bytecode
*bc
,
259 enum chip_class chip_class
,
260 enum radeon_family family
,
261 enum r600_msaa_texture_mode msaa_texture_mode
)
263 if ((chip_class
== R600
) &&
264 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
265 bc
->ar_handling
= AR_HANDLE_RV6XX
;
266 bc
->r6xx_nop_after_rel_dst
= 1;
268 bc
->ar_handling
= AR_HANDLE_NORMAL
;
269 bc
->r6xx_nop_after_rel_dst
= 0;
272 LIST_INITHEAD(&bc
->cf
);
273 bc
->chip_class
= chip_class
;
274 bc
->msaa_texture_mode
= msaa_texture_mode
;
277 static int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
279 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
283 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
285 cf
->id
= bc
->cf_last
->id
+ 2;
286 if (bc
->cf_last
->eg_alu_extended
) {
287 /* take into account extended alu size */
295 bc
->force_add_cf
= 0;
300 int r600_bytecode_add_output(struct r600_bytecode
*bc
, const struct r600_bytecode_output
*output
)
304 if (output
->gpr
>= bc
->ngpr
)
305 bc
->ngpr
= output
->gpr
+ 1;
307 if (bc
->cf_last
&& (bc
->cf_last
->inst
== output
->inst
||
308 (bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
) &&
309 output
->inst
== BC_INST(bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
))) &&
310 output
->type
== bc
->cf_last
->output
.type
&&
311 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
312 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
313 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
314 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
315 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
316 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
318 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
319 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
321 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
322 bc
->cf_last
->output
.inst
= output
->inst
;
323 bc
->cf_last
->output
.gpr
= output
->gpr
;
324 bc
->cf_last
->output
.array_base
= output
->array_base
;
325 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
328 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
329 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
331 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
332 bc
->cf_last
->output
.inst
= output
->inst
;
333 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
338 r
= r600_bytecode_add_cf(bc
);
341 bc
->cf_last
->inst
= output
->inst
;
342 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
346 /* alu instructions that can ony exits once per group */
347 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
349 switch (bc
->chip_class
) {
352 return !alu
->is_op3
&& (
353 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
||
354 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
||
355 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
||
356 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
||
357 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT
||
358 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT
||
359 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT
||
360 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT
||
361 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT
||
362 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT
||
363 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT
||
364 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT
||
365 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
||
366 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
||
367 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
||
368 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
||
369 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV
||
370 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP
||
371 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR
||
372 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE
||
373 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH
||
374 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH
||
375 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH
||
376 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH
||
377 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
||
378 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT
||
379 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT
||
380 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
||
381 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT
||
382 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT
||
383 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT
||
384 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT
||
385 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT
||
386 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT
);
390 return !alu
->is_op3
&& (
391 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
||
392 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
||
393 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
||
394 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
||
395 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT
||
396 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT
||
397 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT
||
398 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT
||
399 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT
||
400 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT
||
401 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT
||
402 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT
||
403 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
||
404 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
||
405 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
||
406 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
||
407 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV
||
408 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP
||
409 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR
||
410 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE
||
411 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH
||
412 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH
||
413 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH
||
414 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH
||
415 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
||
416 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT
||
417 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT
||
418 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
||
419 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT
||
420 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT
||
421 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT
||
422 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT
||
423 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT
||
424 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT
);
428 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
430 switch (bc
->chip_class
) {
433 return !alu
->is_op3
&& (
434 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
||
435 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
||
436 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
||
437 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
);
441 return !alu
->is_op3
&& (
442 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
||
443 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
||
444 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
||
445 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
);
449 static int is_alu_cube_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
451 switch (bc
->chip_class
) {
454 return !alu
->is_op3
&&
455 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
;
459 return !alu
->is_op3
&&
460 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
;
464 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
466 switch (bc
->chip_class
) {
469 return !alu
->is_op3
&& (
470 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
||
471 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
||
472 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
||
473 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
);
477 return !alu
->is_op3
&& (
478 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
);
482 static int is_opcode_in_range(unsigned opcode
, unsigned min
, unsigned max
)
484 return min
<= opcode
&& opcode
<= max
;
487 /* ALU instructions that can only execute on the vector unit:
491 * op3 : [0x08 - 0x0B]
492 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
498 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
500 switch (bc
->chip_class
) {
504 return is_opcode_in_range(alu
->inst
,
505 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64
,
506 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2
);
508 return (alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64
) ||
509 is_opcode_in_range(alu
->inst
,
510 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
,
511 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
) ||
512 is_opcode_in_range(alu
->inst
,
513 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64
,
514 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64
) ||
515 is_opcode_in_range(alu
->inst
,
516 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
,
517 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
) ||
518 is_opcode_in_range(alu
->inst
,
519 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64
,
520 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64
);
524 return is_opcode_in_range(alu
->inst
,
525 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT
,
526 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP
);
528 return is_opcode_in_range(alu
->inst
,
529 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT
,
530 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20
);
538 /* ALU instructions that can only execute on the trans unit:
547 * op2: [0x60 - 0x6F], [0x73 - 0x79]
553 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
556 switch (bc
->chip_class
) {
559 return alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
561 return is_opcode_in_range(alu
->inst
,
562 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
,
563 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
566 return alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
568 return is_opcode_in_range(alu
->inst
,
569 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
,
570 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
) ||
571 is_opcode_in_range(alu
->inst
,
572 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
,
573 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
576 return alu
->inst
== EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
578 return is_opcode_in_range(alu
->inst
,
579 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
,
580 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
);
588 /* alu instructions that can execute on any unit */
589 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
591 return !is_alu_vec_unit_inst(bc
, alu
) &&
592 !is_alu_trans_unit_inst(bc
, alu
);
595 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
597 switch (bc
->chip_class
) {
600 return (!alu
->is_op3
&& alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
604 return (!alu
->is_op3
&& alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
608 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
609 struct r600_bytecode_alu
*assignment
[5])
611 struct r600_bytecode_alu
*alu
;
612 unsigned i
, chan
, trans
;
613 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
615 for (i
= 0; i
< max_slots
; i
++)
616 assignment
[i
] = NULL
;
618 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
619 chan
= alu
->dst
.chan
;
622 else if (is_alu_trans_unit_inst(bc
, alu
))
624 else if (is_alu_vec_unit_inst(bc
, alu
))
626 else if (assignment
[chan
])
627 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
633 assert(0); /* ALU.Trans has already been allocated. */
638 if (assignment
[chan
]) {
639 assert(0); /* ALU.chan has already been allocated. */
642 assignment
[chan
] = alu
;
651 struct alu_bank_swizzle
{
652 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
653 int hw_cfile_addr
[4];
654 int hw_cfile_elem
[4];
657 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
658 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
659 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
660 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
661 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
662 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
663 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
666 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
667 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
668 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
669 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
670 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
673 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
675 int i
, cycle
, component
;
677 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
678 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
679 bs
->hw_gpr
[cycle
][component
] = -1;
680 for (i
= 0; i
< 4; i
++)
681 bs
->hw_cfile_addr
[i
] = -1;
682 for (i
= 0; i
< 4; i
++)
683 bs
->hw_cfile_elem
[i
] = -1;
686 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
688 if (bs
->hw_gpr
[cycle
][chan
] == -1)
689 bs
->hw_gpr
[cycle
][chan
] = sel
;
690 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
691 /* Another scalar operation has already used the GPR read port for the channel. */
697 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
699 int res
, num_res
= 4;
700 if (bc
->chip_class
>= R700
) {
704 for (res
= 0; res
< num_res
; ++res
) {
705 if (bs
->hw_cfile_addr
[res
] == -1) {
706 bs
->hw_cfile_addr
[res
] = sel
;
707 bs
->hw_cfile_elem
[res
] = chan
;
709 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
710 bs
->hw_cfile_elem
[res
] == chan
)
711 return 0; /* Read for this scalar element already reserved, nothing to do here. */
713 /* All cfile read ports are used, cannot reference vector element. */
717 static int is_gpr(unsigned sel
)
719 return (sel
>= 0 && sel
<= 127);
722 /* CB constants start at 512, and get translated to a kcache index when ALU
723 * clauses are constructed. Note that we handle kcache constants the same way
724 * as (the now gone) cfile constants, is that really required? */
725 static int is_cfile(unsigned sel
)
727 return (sel
> 255 && sel
< 512) ||
728 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
729 (sel
> 127 && sel
< 192); /* Kcache after translation. */
732 static int is_const(int sel
)
734 return is_cfile(sel
) ||
735 (sel
>= V_SQ_ALU_SRC_0
&&
736 sel
<= V_SQ_ALU_SRC_LITERAL
);
739 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
740 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
742 int r
, src
, num_src
, sel
, elem
, cycle
;
744 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
745 for (src
= 0; src
< num_src
; src
++) {
746 sel
= alu
->src
[src
].sel
;
747 elem
= alu
->src
[src
].chan
;
749 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
750 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
751 /* Nothing to do; special-case optimization,
752 * second source uses first source’s reservation. */
755 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
759 } else if (is_cfile(sel
)) {
760 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
764 /* No restrictions on PV, PS, literal or special constants. */
769 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
770 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
772 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
774 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
775 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
776 sel
= alu
->src
[src
].sel
;
777 elem
= alu
->src
[src
].chan
;
778 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
779 if (const_count
>= 2)
780 /* More than two references to a constant in
781 * transcendental operation. */
787 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
792 for (src
= 0; src
< num_src
; ++src
) {
793 sel
= alu
->src
[src
].sel
;
794 elem
= alu
->src
[src
].chan
;
796 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
797 if (cycle
< const_count
)
798 /* Cycle for GPR load conflicts with
799 * constant load in transcendental operation. */
801 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
805 /* PV PS restrictions */
806 if (const_count
&& (sel
== 254 || sel
== 255)) {
807 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
808 if (cycle
< const_count
)
815 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
816 struct r600_bytecode_alu
*slots
[5])
818 struct alu_bank_swizzle bs
;
820 int i
, r
= 0, forced
= 1;
821 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
822 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
824 for (i
= 0; i
< max_slots
; i
++) {
826 if (slots
[i
]->bank_swizzle_force
) {
827 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
833 if (i
< 4 && slots
[i
])
839 /* Just check every possible combination of bank swizzle.
840 * Not very efficent, but works on the first try in most of the cases. */
841 for (i
= 0; i
< 4; i
++)
842 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
843 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
845 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
847 bank_swizzle
[4] = SQ_ALU_SCL_210
;
848 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
850 if (max_slots
== 4) {
851 for (i
= 0; i
< max_slots
; i
++) {
852 if (bank_swizzle
[i
] == SQ_ALU_VEC_210
)
856 init_bank_swizzle(&bs
);
857 if (scalar_only
== false) {
858 for (i
= 0; i
< 4; i
++) {
860 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
868 if (!r
&& slots
[4] && max_slots
== 5) {
869 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
872 for (i
= 0; i
< max_slots
; i
++) {
874 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
882 for (i
= 0; i
< max_slots
; i
++) {
883 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
885 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
888 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
894 /* Couldn't find a working swizzle. */
898 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
899 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
901 struct r600_bytecode_alu
*prev
[5];
903 int i
, j
, r
, src
, num_src
;
904 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
906 r
= assign_alu_units(bc
, alu_prev
, prev
);
910 for (i
= 0; i
< max_slots
; ++i
) {
911 if (prev
[i
] && (prev
[i
]->dst
.write
|| prev
[i
]->is_op3
) && !prev
[i
]->dst
.rel
) {
912 gpr
[i
] = prev
[i
]->dst
.sel
;
913 /* cube writes more than PV.X */
914 if (!is_alu_cube_inst(bc
, prev
[i
]) && is_alu_reduction_inst(bc
, prev
[i
]))
917 chan
[i
] = prev
[i
]->dst
.chan
;
922 for (i
= 0; i
< max_slots
; ++i
) {
923 struct r600_bytecode_alu
*alu
= slots
[i
];
927 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
928 for (src
= 0; src
< num_src
; ++src
) {
929 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
932 if (bc
->chip_class
< CAYMAN
) {
933 if (alu
->src
[src
].sel
== gpr
[4] &&
934 alu
->src
[src
].chan
== chan
[4] &&
935 alu_prev
->pred_sel
== alu
->pred_sel
) {
936 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
937 alu
->src
[src
].chan
= 0;
942 for (j
= 0; j
< 4; ++j
) {
943 if (alu
->src
[src
].sel
== gpr
[j
] &&
944 alu
->src
[src
].chan
== j
&&
945 alu_prev
->pred_sel
== alu
->pred_sel
) {
946 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
947 alu
->src
[src
].chan
= chan
[j
];
957 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
)
961 *sel
= V_SQ_ALU_SRC_0
;
964 *sel
= V_SQ_ALU_SRC_1_INT
;
967 *sel
= V_SQ_ALU_SRC_M_1_INT
;
969 case 0x3F800000: /* 1.0f */
970 *sel
= V_SQ_ALU_SRC_1
;
972 case 0x3F000000: /* 0.5f */
973 *sel
= V_SQ_ALU_SRC_0_5
;
975 case 0xBF800000: /* -1.0f */
976 *sel
= V_SQ_ALU_SRC_1
;
979 case 0xBF000000: /* -0.5f */
980 *sel
= V_SQ_ALU_SRC_0_5
;
984 *sel
= V_SQ_ALU_SRC_LITERAL
;
989 /* compute how many literal are needed */
990 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
991 uint32_t literal
[4], unsigned *nliteral
)
993 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
996 for (i
= 0; i
< num_src
; ++i
) {
997 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
998 uint32_t value
= alu
->src
[i
].value
;
1000 for (j
= 0; j
< *nliteral
; ++j
) {
1001 if (literal
[j
] == value
) {
1009 literal
[(*nliteral
)++] = value
;
1016 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
1017 struct r600_bytecode_alu
*alu
,
1018 uint32_t literal
[4], unsigned nliteral
)
1020 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
1023 for (i
= 0; i
< num_src
; ++i
) {
1024 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1025 uint32_t value
= alu
->src
[i
].value
;
1026 for (j
= 0; j
< nliteral
; ++j
) {
1027 if (literal
[j
] == value
) {
1028 alu
->src
[i
].chan
= j
;
1036 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
1037 struct r600_bytecode_alu
*alu_prev
)
1039 struct r600_bytecode_alu
*prev
[5];
1040 struct r600_bytecode_alu
*result
[5] = { NULL
};
1042 uint32_t literal
[4], prev_literal
[4];
1043 unsigned nliteral
= 0, prev_nliteral
= 0;
1045 int i
, j
, r
, src
, num_src
;
1046 int num_once_inst
= 0;
1047 int have_mova
= 0, have_rel
= 0;
1048 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1050 r
= assign_alu_units(bc
, alu_prev
, prev
);
1054 for (i
= 0; i
< max_slots
; ++i
) {
1056 if (prev
[i
]->pred_sel
)
1058 if (is_alu_once_inst(bc
, prev
[i
]))
1062 if (slots
[i
]->pred_sel
)
1064 if (is_alu_once_inst(bc
, slots
[i
]))
1069 for (i
= 0; i
< max_slots
; ++i
) {
1070 struct r600_bytecode_alu
*alu
;
1072 if (num_once_inst
> 0)
1075 /* check number of literals */
1077 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
1079 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
1081 if (is_alu_mova_inst(bc
, prev
[i
])) {
1086 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
1088 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
1091 /* Let's check used slots. */
1092 if (prev
[i
] && !slots
[i
]) {
1093 result
[i
] = prev
[i
];
1095 } else if (prev
[i
] && slots
[i
]) {
1096 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
1097 /* Trans unit is still free try to use it. */
1098 if (is_alu_any_unit_inst(bc
, slots
[i
])) {
1099 result
[i
] = prev
[i
];
1100 result
[4] = slots
[i
];
1101 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
1102 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
1103 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
1104 (prev
[i
]->dst
.write
== 1 || prev
[i
]->is_op3
))
1107 result
[i
] = slots
[i
];
1108 result
[4] = prev
[i
];
1113 } else if(!slots
[i
]) {
1116 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
1117 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
1118 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
1119 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
1120 (prev
[4]->dst
.write
== 1 || prev
[4]->is_op3
))
1123 result
[i
] = slots
[i
];
1127 num_once_inst
+= is_alu_once_inst(bc
, alu
);
1129 /* don't reschedule NOPs */
1130 if (is_nop_inst(bc
, alu
))
1133 /* Let's check dst gpr. */
1140 /* Let's check source gprs */
1141 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
1142 for (src
= 0; src
< num_src
; ++src
) {
1143 if (alu
->src
[src
].rel
) {
1149 /* Constants don't matter. */
1150 if (!is_gpr(alu
->src
[src
].sel
))
1153 for (j
= 0; j
< max_slots
; ++j
) {
1154 if (!prev
[j
] || !(prev
[j
]->dst
.write
|| prev
[j
]->is_op3
))
1157 /* If it's relative then we can't determin which gpr is really used. */
1158 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
1159 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
1160 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
1166 /* more than one PRED_ or KILL_ ? */
1167 if (num_once_inst
> 1)
1170 /* check if the result can still be swizzlet */
1171 r
= check_and_set_bank_swizzle(bc
, result
);
1175 /* looks like everything worked out right, apply the changes */
1177 /* undo adding previus literals */
1178 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
1180 /* sort instructions */
1181 for (i
= 0; i
< max_slots
; ++i
) {
1182 slots
[i
] = result
[i
];
1184 LIST_DEL(&result
[i
]->list
);
1185 result
[i
]->last
= 0;
1186 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
1190 /* determine new last instruction */
1191 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
1193 /* determine new first instruction */
1194 for (i
= 0; i
< max_slots
; ++i
) {
1196 bc
->cf_last
->curr_bs_head
= result
[i
];
1201 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
1202 bc
->cf_last
->prev2_bs_head
= NULL
;
1207 /* we'll keep kcache sets sorted by bank & addr */
1208 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
1209 struct r600_bytecode_kcache
*kcache
,
1210 unsigned bank
, unsigned line
)
1212 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
1214 for (i
= 0; i
< kcache_banks
; i
++) {
1215 if (kcache
[i
].mode
) {
1218 if (kcache
[i
].bank
< bank
)
1221 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
1222 kcache
[i
].bank
> bank
) {
1223 /* try to insert new line */
1224 if (kcache
[kcache_banks
-1].mode
) {
1225 /* all sets are in use */
1229 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
1230 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
1231 kcache
[i
].bank
= bank
;
1232 kcache
[i
].addr
= line
;
1236 d
= line
- kcache
[i
].addr
;
1240 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
1241 /* we are prepending the line to the current set,
1242 * discarding the existing second line,
1243 * so we'll have to insert line+2 after it */
1246 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
1247 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
1250 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1253 } else if (d
== 1) {
1254 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
1258 } else { /* free kcache set - use it */
1259 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
1260 kcache
[i
].bank
= bank
;
1261 kcache
[i
].addr
= line
;
1268 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
1269 struct r600_bytecode_kcache
*kcache
,
1270 struct r600_bytecode_alu
*alu
)
1274 for (i
= 0; i
< 3; i
++) {
1275 unsigned bank
, line
, sel
= alu
->src
[i
].sel
;
1280 bank
= alu
->src
[i
].kc_bank
;
1281 line
= (sel
-512)>>4;
1283 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
)))
1289 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
1290 struct r600_bytecode_alu
*alu
,
1291 struct r600_bytecode_kcache
* kcache
)
1295 /* Alter the src operands to refer to the kcache. */
1296 for (i
= 0; i
< 3; ++i
) {
1297 static const unsigned int base
[] = {128, 160, 256, 288};
1298 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
1306 for (j
= 0; j
< 4 && !found
; ++j
) {
1307 switch (kcache
[j
].mode
) {
1308 case V_SQ_CF_KCACHE_NOP
:
1309 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
1310 R600_ERR("unexpected kcache line mode\n");
1313 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
1314 kcache
[j
].addr
<= line
&&
1315 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1316 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1317 alu
->src
[i
].sel
+= base
[j
];
1326 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, int type
)
1328 struct r600_bytecode_kcache kcache_sets
[4];
1329 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1332 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1334 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1335 /* can't alloc, need to start new clause */
1336 if ((r
= r600_bytecode_add_cf(bc
))) {
1339 bc
->cf_last
->inst
= type
;
1341 /* retry with the new clause */
1342 kcache
= bc
->cf_last
->kcache
;
1343 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1344 /* can't alloc again- should never happen */
1348 /* update kcache sets */
1349 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1352 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1353 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
) {
1354 if (bc
->chip_class
< EVERGREEN
)
1356 bc
->cf_last
->eg_alu_extended
= 1;
1362 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1364 struct r600_bytecode_alu alu
;
1367 for (i
= 0; i
< 4; i
++) {
1368 memset(&alu
, 0, sizeof(alu
));
1369 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
1370 alu
.src
[0].chan
= i
;
1372 alu
.last
= (i
== 3);
1373 r
= r600_bytecode_add_alu(bc
, &alu
);
1380 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1381 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1383 struct r600_bytecode_alu alu
;
1389 /* hack to avoid making MOVA the last instruction in the clause */
1390 if ((bc
->cf_last
->ndw
>>1) >= 110)
1391 bc
->force_add_cf
= 1;
1393 memset(&alu
, 0, sizeof(alu
));
1394 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
;
1395 alu
.src
[0].sel
= bc
->ar_reg
;
1397 alu
.index_mode
= INDEX_MODE_LOOP
;
1398 r
= r600_bytecode_add_alu(bc
, &alu
);
1402 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1407 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1408 static int load_ar(struct r600_bytecode
*bc
)
1410 struct r600_bytecode_alu alu
;
1413 if (bc
->ar_handling
)
1414 return load_ar_r6xx(bc
);
1419 /* hack to avoid making MOVA the last instruction in the clause */
1420 if ((bc
->cf_last
->ndw
>>1) >= 110)
1421 bc
->force_add_cf
= 1;
1423 memset(&alu
, 0, sizeof(alu
));
1424 alu
.inst
= BC_INST(bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
);
1425 alu
.src
[0].sel
= bc
->ar_reg
;
1427 r
= r600_bytecode_add_alu(bc
, &alu
);
1431 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1436 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
, int type
)
1438 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1439 struct r600_bytecode_alu
*lalu
;
1444 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1446 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->inst
!= type
) {
1447 /* check if we could add it anyway */
1448 if (bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
) &&
1449 type
== BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
)) {
1450 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1451 if (lalu
->execute_mask
) {
1452 bc
->force_add_cf
= 1;
1457 bc
->force_add_cf
= 1;
1460 /* cf can contains only alu or only vtx or only tex */
1461 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1462 r
= r600_bytecode_add_cf(bc
);
1468 bc
->cf_last
->inst
= type
;
1470 /* Check AR usage and load it if required */
1471 for (i
= 0; i
< 3; i
++)
1472 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1475 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1478 /* Setup the kcache for this ALU instruction. This will start a new
1479 * ALU clause if needed. */
1480 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1485 if (!bc
->cf_last
->curr_bs_head
) {
1486 bc
->cf_last
->curr_bs_head
= nalu
;
1488 /* number of gpr == the last gpr used in any alu */
1489 for (i
= 0; i
< 3; i
++) {
1490 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1491 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1493 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1494 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1495 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
);
1497 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1498 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1500 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1501 /* each alu use 2 dwords */
1502 bc
->cf_last
->ndw
+= 2;
1505 /* process cur ALU instructions for bank swizzle */
1507 uint32_t literal
[4];
1509 struct r600_bytecode_alu
*slots
[5];
1510 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1511 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1515 if (bc
->cf_last
->prev_bs_head
) {
1516 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1521 if (bc
->cf_last
->prev_bs_head
) {
1522 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1527 r
= check_and_set_bank_swizzle(bc
, slots
);
1531 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1533 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1538 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1540 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1542 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1543 bc
->force_add_cf
= 1;
1546 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1547 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1548 bc
->cf_last
->curr_bs_head
= NULL
;
1551 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1552 insert_nop_r6xx(bc
);
1557 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1559 return r600_bytecode_add_alu_type(bc
, alu
, BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
1562 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1564 switch (bc
->chip_class
) {
1574 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1579 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1581 switch (bc
->chip_class
) {
1584 return bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX
&&
1585 bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
;
1587 return bc
->cf_last
->inst
!= EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1589 return bc
->cf_last
->inst
!= CM_V_SQ_CF_WORD1_SQ_CF_INST_TC
;
1591 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1596 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1598 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1603 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1605 /* cf can contains only alu or only vtx or only tex */
1606 if (bc
->cf_last
== NULL
||
1607 last_inst_was_not_vtx_fetch(bc
) ||
1609 r
= r600_bytecode_add_cf(bc
);
1614 switch (bc
->chip_class
) {
1617 bc
->cf_last
->inst
= V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1620 bc
->cf_last
->inst
= EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1623 bc
->cf_last
->inst
= CM_V_SQ_CF_WORD1_SQ_CF_INST_TC
;
1626 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1630 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1631 /* each fetch use 4 dwords */
1632 bc
->cf_last
->ndw
+= 4;
1634 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1635 bc
->force_add_cf
= 1;
1637 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1638 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1643 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1645 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1650 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1652 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1653 if (bc
->cf_last
!= NULL
&&
1654 bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
)) {
1655 struct r600_bytecode_tex
*ttex
;
1656 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1657 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1658 bc
->force_add_cf
= 1;
1662 /* slight hack to make gradients always go into same cf */
1663 if (ntex
->inst
== SQ_TEX_INST_SET_GRADIENTS_H
)
1664 bc
->force_add_cf
= 1;
1667 /* cf can contains only alu or only vtx or only tex */
1668 if (bc
->cf_last
== NULL
||
1669 bc
->cf_last
->inst
!= BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
) ||
1671 r
= r600_bytecode_add_cf(bc
);
1676 bc
->cf_last
->inst
= BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
);
1678 if (ntex
->src_gpr
>= bc
->ngpr
) {
1679 bc
->ngpr
= ntex
->src_gpr
+ 1;
1681 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1682 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1684 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1685 /* each texture fetch use 4 dwords */
1686 bc
->cf_last
->ndw
+= 4;
1688 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1689 bc
->force_add_cf
= 1;
1693 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, int inst
)
1696 r
= r600_bytecode_add_cf(bc
);
1700 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1701 bc
->cf_last
->inst
= inst
;
1705 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1707 return r600_bytecode_add_cfinst(bc
, CM_V_SQ_CF_WORD1_SQ_CF_INST_END
);
1710 /* common to all 3 families */
1711 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1713 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1714 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1715 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1716 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1717 if (bc
->chip_class
< CAYMAN
)
1718 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1720 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1721 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1722 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1723 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1724 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1725 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1726 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1727 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1728 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1729 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1730 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1731 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1732 if (bc
->chip_class
< CAYMAN
)
1733 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1735 bc
->bytecode
[id
++] = 0;
1739 /* common to all 3 families */
1740 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1742 bc
->bytecode
[id
++] = S_SQ_TEX_WORD0_TEX_INST(tex
->inst
) |
1743 EG_S_SQ_TEX_WORD0_INST_MOD(tex
->inst_mod
) |
1744 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1745 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1746 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1747 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1748 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1749 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1750 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1751 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1752 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1753 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1754 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1755 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1756 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1757 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1758 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1759 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1760 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1761 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1762 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1763 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1764 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1765 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1766 bc
->bytecode
[id
++] = 0;
1770 /* r600 only, r700/eg bits in r700_asm.c */
1771 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1773 /* don't replace gpr by pv or ps for destination register */
1774 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1775 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1776 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1777 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1778 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1779 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1780 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1781 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1782 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1783 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1784 S_SQ_ALU_WORD0_LAST(alu
->last
);
1787 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1788 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1789 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1790 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1791 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1792 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1793 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1794 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1795 S_SQ_ALU_WORD1_OP3_ALU_INST(alu
->inst
) |
1796 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1798 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1799 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1800 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1801 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1802 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1803 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1804 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1805 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1806 S_SQ_ALU_WORD1_OP2_ALU_INST(alu
->inst
) |
1807 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1808 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1809 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1814 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1816 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1817 *bytecode
++ = cf
->inst
|
1818 S_SQ_CF_WORD1_BARRIER(1) |
1819 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1822 /* common for r600/r700 - eg in eg_asm.c */
1823 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1825 unsigned id
= cf
->id
;
1828 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1829 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1830 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1831 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1832 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1833 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1834 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1835 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1837 bc
->bytecode
[id
++] = cf
->inst
|
1838 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1839 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1840 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1841 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1842 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1843 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1845 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1846 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1847 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1848 if (bc
->chip_class
== R700
)
1849 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1851 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1853 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1854 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1855 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1856 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1857 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1858 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1859 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1860 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1861 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1862 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1863 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1864 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1866 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
);
1868 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
1869 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
1870 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
1871 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
1872 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1873 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1874 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1875 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1876 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1877 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1879 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
) |
1880 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1881 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1883 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1884 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1885 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1886 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1887 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
1888 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1889 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1890 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1891 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1892 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1893 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1894 bc
->bytecode
[id
++] = cf
->inst
|
1895 S_SQ_CF_WORD1_BARRIER(1) |
1896 S_SQ_CF_WORD1_COND(cf
->cond
) |
1897 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
);
1901 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1907 int r600_bytecode_build(struct r600_bytecode
*bc
)
1909 struct r600_bytecode_cf
*cf
;
1910 struct r600_bytecode_alu
*alu
;
1911 struct r600_bytecode_vtx
*vtx
;
1912 struct r600_bytecode_tex
*tex
;
1913 uint32_t literal
[4];
1918 if (bc
->callstack
[0].max
> 0)
1919 bc
->nstack
= ((bc
->callstack
[0].max
+ 3) >> 2) + 2;
1920 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1924 /* first path compute addr of each CF block */
1925 /* addr start after all the CF instructions */
1926 addr
= bc
->cf_last
->id
+ 2;
1927 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1928 if (bc
->chip_class
>= EVERGREEN
) {
1930 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1931 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1932 /* fetch node need to be 16 bytes aligned*/
1934 addr
&= 0xFFFFFFFCUL
;
1936 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1937 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1938 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1939 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1940 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1941 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1942 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
1943 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
1944 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
1945 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
1946 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
1947 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
1948 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
1949 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
1950 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
1951 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
1952 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
1953 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
1954 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
1955 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
1956 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
1957 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
1958 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1959 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1960 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1961 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1962 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
1963 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1964 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1965 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1966 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1967 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1968 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
1972 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1977 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1978 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1979 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1980 /* fetch node need to be 16 bytes aligned*/
1982 addr
&= 0xFFFFFFFCUL
;
1984 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1985 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1986 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1987 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1988 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1989 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1990 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
1991 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
1992 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
1993 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
1994 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1995 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1996 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1997 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
1998 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1999 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2000 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2001 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2002 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2005 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2011 bc
->ndw
= cf
->addr
+ cf
->ndw
;
2014 bc
->bytecode
= calloc(1, bc
->ndw
* 4);
2015 if (bc
->bytecode
== NULL
)
2017 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2019 if (bc
->chip_class
>= EVERGREEN
) {
2020 r
= eg_bytecode_cf_build(bc
, cf
);
2025 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2026 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2027 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2028 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2030 memset(literal
, 0, sizeof(literal
));
2031 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2032 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2035 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
2036 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
2038 switch(bc
->chip_class
) {
2039 case EVERGREEN
: /* eg alu is same encoding as r700 */
2041 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
2044 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
2051 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
2052 bc
->bytecode
[addr
++] = literal
[i
];
2055 memset(literal
, 0, sizeof(literal
));
2059 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2060 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2061 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2067 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2068 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2069 assert(bc
->chip_class
>= EVERGREEN
);
2070 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2075 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2076 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
2082 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2083 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2084 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
2085 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
2086 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
2087 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
2088 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
2089 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
2090 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
2091 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
2092 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
2093 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
2094 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
2095 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
2096 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
2097 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
2098 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
2099 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
2100 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2101 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2102 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2103 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2104 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2105 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2106 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2107 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2108 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2109 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2110 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
2115 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2119 r
= r600_bytecode_cf_build(bc
, cf
);
2124 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2125 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2126 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2127 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2129 memset(literal
, 0, sizeof(literal
));
2130 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2131 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2134 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
2135 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
2137 switch(bc
->chip_class
) {
2139 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
2142 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
2145 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
2152 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
2153 bc
->bytecode
[addr
++] = literal
[i
];
2156 memset(literal
, 0, sizeof(literal
));
2160 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2161 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
2162 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2163 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2169 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2170 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2171 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
2177 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2178 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2179 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
2180 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
2181 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
2182 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
2183 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2184 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2185 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2186 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2187 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2188 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2189 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2190 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2191 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2192 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2195 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2203 void r600_bytecode_clear(struct r600_bytecode
*bc
)
2205 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
2208 bc
->bytecode
= NULL
;
2210 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
2211 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
2212 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
2213 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
2215 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
2219 LIST_INITHEAD(&cf
->alu
);
2221 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
2225 LIST_INITHEAD(&cf
->tex
);
2227 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
2231 LIST_INITHEAD(&cf
->vtx
);
2236 LIST_INITHEAD(&cf
->list
);
2239 void r600_bytecode_dump(struct r600_bytecode
*bc
)
2241 struct r600_bytecode_cf
*cf
= NULL
;
2242 struct r600_bytecode_alu
*alu
= NULL
;
2243 struct r600_bytecode_vtx
*vtx
= NULL
;
2244 struct r600_bytecode_tex
*tex
= NULL
;
2247 uint32_t literal
[4];
2251 switch (bc
->chip_class
) {
2266 fprintf(stderr
, "bytecode %d dw -- %d gprs ---------------------\n", bc
->ndw
, bc
->ngpr
);
2267 fprintf(stderr
, " %c\n", chip
);
2269 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2272 if (bc
->chip_class
>= EVERGREEN
) {
2274 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2275 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2276 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2277 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2278 if (cf
->eg_alu_extended
) {
2279 fprintf(stderr
, "%04d %08X ALU_EXT0 ", id
, bc
->bytecode
[id
]);
2280 fprintf(stderr
, "KCACHE_BANK2:%X ", cf
->kcache
[2].bank
);
2281 fprintf(stderr
, "KCACHE_BANK3:%X ", cf
->kcache
[3].bank
);
2282 fprintf(stderr
, "KCACHE_MODE2:%X\n", cf
->kcache
[2].mode
);
2284 fprintf(stderr
, "%04d %08X ALU_EXT1 ", id
, bc
->bytecode
[id
]);
2285 fprintf(stderr
, "KCACHE_MODE3:%X ", cf
->kcache
[3].mode
);
2286 fprintf(stderr
, "KCACHE_ADDR2:%X ", cf
->kcache
[2].addr
);
2287 fprintf(stderr
, "KCACHE_ADDR3:%X\n", cf
->kcache
[3].addr
);
2291 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2292 fprintf(stderr
, "ADDR:%d ", cf
->addr
);
2293 fprintf(stderr
, "KCACHE_MODE0:%X ", cf
->kcache
[0].mode
);
2294 fprintf(stderr
, "KCACHE_BANK0:%X ", cf
->kcache
[0].bank
);
2295 fprintf(stderr
, "KCACHE_BANK1:%X\n", cf
->kcache
[1].bank
);
2297 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2298 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
));
2299 fprintf(stderr
, "KCACHE_MODE1:%X ", cf
->kcache
[1].mode
);
2300 fprintf(stderr
, "KCACHE_ADDR0:%X ", cf
->kcache
[0].addr
);
2301 fprintf(stderr
, "KCACHE_ADDR1:%X ", cf
->kcache
[1].addr
);
2302 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 2);
2304 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2305 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2306 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2307 fprintf(stderr
, "ADDR:%d\n", cf
->addr
);
2309 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2310 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2311 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 4);
2313 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2314 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2315 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2316 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2317 fprintf(stderr
, "ELEM_SIZE:%X ", cf
->output
.elem_size
);
2318 fprintf(stderr
, "ARRAY_BASE:%X ", cf
->output
.array_base
);
2319 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2321 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2322 fprintf(stderr
, "SWIZ_X:%X ", cf
->output
.swizzle_x
);
2323 fprintf(stderr
, "SWIZ_Y:%X ", cf
->output
.swizzle_y
);
2324 fprintf(stderr
, "SWIZ_Z:%X ", cf
->output
.swizzle_z
);
2325 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
2326 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2327 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
));
2328 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2329 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2331 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
2332 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
2333 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
2334 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
2335 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
2336 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
2337 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
2338 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
2339 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
2340 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
2341 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
2342 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
2343 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
2344 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
2345 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
2346 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
2347 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id
, bc
->bytecode
[id
],
2348 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2349 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) / 4,
2350 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2351 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) % 4);
2352 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2353 fprintf(stderr
, "ELEM_SIZE:%i ", cf
->output
.elem_size
);
2354 fprintf(stderr
, "ARRAY_BASE:%i ", cf
->output
.array_base
);
2355 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2357 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id
, bc
->bytecode
[id
],
2358 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2359 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) / 4,
2360 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2361 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) % 4);
2362 fprintf(stderr
, "ARRAY_SIZE:%i ", cf
->output
.array_size
);
2363 fprintf(stderr
, "COMP_MASK:%X ", cf
->output
.comp_mask
);
2364 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2365 fprintf(stderr
, "INST:%d ", cf
->output
.inst
);
2366 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2367 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2369 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2370 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2371 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2372 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2373 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2374 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2375 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2376 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2377 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2378 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2379 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
2380 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2381 fprintf(stderr
, "ADDR:%d\n", cf
->cf_addr
);
2383 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2384 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2385 fprintf(stderr
, "COND:%X ", cf
->cond
);
2386 fprintf(stderr
, "POP_COUNT:%X\n", cf
->pop_count
);
2389 fprintf(stderr
, "%04d %08X CF NATIVE\n", id
, bc
->bytecode
[id
]);
2390 fprintf(stderr
, "%04d %08X CF NATIVE\n", id
+ 1, bc
->bytecode
[id
+ 1]);
2393 R600_ERR("Unknown instruction %0x\n", cf
->inst
);
2397 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2398 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2399 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2400 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2401 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2402 fprintf(stderr
, "ADDR:%d ", cf
->addr
);
2403 fprintf(stderr
, "KCACHE_MODE0:%X ", cf
->kcache
[0].mode
);
2404 fprintf(stderr
, "KCACHE_BANK0:%X ", cf
->kcache
[0].bank
);
2405 fprintf(stderr
, "KCACHE_BANK1:%X\n", cf
->kcache
[1].bank
);
2407 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2408 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
));
2409 fprintf(stderr
, "KCACHE_MODE1:%X ", cf
->kcache
[1].mode
);
2410 fprintf(stderr
, "KCACHE_ADDR0:%X ", cf
->kcache
[0].addr
);
2411 fprintf(stderr
, "KCACHE_ADDR1:%X ", cf
->kcache
[1].addr
);
2412 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 2);
2414 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2415 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2416 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
2417 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2418 fprintf(stderr
, "ADDR:%d\n", cf
->addr
);
2420 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2421 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2422 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 4);
2424 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2425 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2426 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2427 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2428 fprintf(stderr
, "ELEM_SIZE:%X ", cf
->output
.elem_size
);
2429 fprintf(stderr
, "ARRAY_BASE:%X ", cf
->output
.array_base
);
2430 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2432 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2433 fprintf(stderr
, "SWIZ_X:%X ", cf
->output
.swizzle_x
);
2434 fprintf(stderr
, "SWIZ_Y:%X ", cf
->output
.swizzle_y
);
2435 fprintf(stderr
, "SWIZ_Z:%X ", cf
->output
.swizzle_z
);
2436 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
2437 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2438 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
));
2439 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2440 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2442 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
2443 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
2444 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
2445 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
2446 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i ", id
, bc
->bytecode
[id
],
2447 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2448 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
));
2449 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2450 fprintf(stderr
, "ELEM_SIZE:%i ", cf
->output
.elem_size
);
2451 fprintf(stderr
, "ARRAY_BASE:%i ", cf
->output
.array_base
);
2452 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2454 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i ", id
, bc
->bytecode
[id
],
2455 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2456 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
));
2457 fprintf(stderr
, "ARRAY_SIZE:%i ", cf
->output
.array_size
);
2458 fprintf(stderr
, "COMP_MASK:%X ", cf
->output
.comp_mask
);
2459 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2460 fprintf(stderr
, "INST:%d ", cf
->output
.inst
);
2461 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2462 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2464 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2465 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2466 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2467 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2468 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2469 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2470 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2471 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2472 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2473 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2474 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2475 fprintf(stderr
, "ADDR:%d\n", cf
->cf_addr
);
2477 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2478 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2479 fprintf(stderr
, "COND:%X ", cf
->cond
);
2480 fprintf(stderr
, "POP_COUNT:%X\n", cf
->pop_count
);
2483 R600_ERR("Unknown instruction %0x\n", cf
->inst
);
2489 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2490 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2492 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2493 fprintf(stderr
, "SRC0(SEL:%d ", alu
->src
[0].sel
);
2494 fprintf(stderr
, "REL:%d ", alu
->src
[0].rel
);
2495 fprintf(stderr
, "CHAN:%d ", alu
->src
[0].chan
);
2496 fprintf(stderr
, "NEG:%d) ", alu
->src
[0].neg
);
2497 fprintf(stderr
, "SRC1(SEL:%d ", alu
->src
[1].sel
);
2498 fprintf(stderr
, "REL:%d ", alu
->src
[1].rel
);
2499 fprintf(stderr
, "CHAN:%d ", alu
->src
[1].chan
);
2500 fprintf(stderr
, "NEG:%d ", alu
->src
[1].neg
);
2501 fprintf(stderr
, "IM:%d) ", alu
->index_mode
);
2502 fprintf(stderr
, "PRED_SEL:%d ", alu
->pred_sel
);
2503 fprintf(stderr
, "LAST:%d)\n", alu
->last
);
2505 fprintf(stderr
, "%04d %08X %c ", id
, bc
->bytecode
[id
], alu
->last
? '*' : ' ');
2506 fprintf(stderr
, "INST:0x%x ", alu
->inst
);
2507 fprintf(stderr
, "DST(SEL:%d ", alu
->dst
.sel
);
2508 fprintf(stderr
, "CHAN:%d ", alu
->dst
.chan
);
2509 fprintf(stderr
, "REL:%d ", alu
->dst
.rel
);
2510 fprintf(stderr
, "CLAMP:%d) ", alu
->dst
.clamp
);
2511 fprintf(stderr
, "BANK_SWIZZLE:%d ", alu
->bank_swizzle
);
2513 fprintf(stderr
, "SRC2(SEL:%d ", alu
->src
[2].sel
);
2514 fprintf(stderr
, "REL:%d ", alu
->src
[2].rel
);
2515 fprintf(stderr
, "CHAN:%d ", alu
->src
[2].chan
);
2516 fprintf(stderr
, "NEG:%d)\n", alu
->src
[2].neg
);
2518 fprintf(stderr
, "SRC0_ABS:%d ", alu
->src
[0].abs
);
2519 fprintf(stderr
, "SRC1_ABS:%d ", alu
->src
[1].abs
);
2520 fprintf(stderr
, "WRITE_MASK:%d ", alu
->dst
.write
);
2521 fprintf(stderr
, "OMOD:%d ", alu
->omod
);
2522 fprintf(stderr
, "EXECUTE_MASK:%d ", alu
->execute_mask
);
2523 fprintf(stderr
, "UPDATE_PRED:%d\n", alu
->update_pred
);
2528 for (i
= 0; i
< nliteral
; i
++, id
++) {
2529 float *f
= (float*)(bc
->bytecode
+ id
);
2530 fprintf(stderr
, "%04d %08X\t%f (%d)\n", id
, bc
->bytecode
[id
], *f
,
2531 *(bc
->bytecode
+ id
));
2538 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2539 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2540 fprintf(stderr
, "INST:0x%x ", tex
->inst
);
2541 fprintf(stderr
, "RESOURCE_ID:%d ", tex
->resource_id
);
2542 fprintf(stderr
, "SRC(GPR:%d ", tex
->src_gpr
);
2543 fprintf(stderr
, "REL:%d)\n", tex
->src_rel
);
2545 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2546 fprintf(stderr
, "DST(GPR:%d ", tex
->dst_gpr
);
2547 fprintf(stderr
, "REL:%d ", tex
->dst_rel
);
2548 fprintf(stderr
, "SEL_X:%d ", tex
->dst_sel_x
);
2549 fprintf(stderr
, "SEL_Y:%d ", tex
->dst_sel_y
);
2550 fprintf(stderr
, "SEL_Z:%d ", tex
->dst_sel_z
);
2551 fprintf(stderr
, "SEL_W:%d) ", tex
->dst_sel_w
);
2552 fprintf(stderr
, "LOD_BIAS:%d ", tex
->lod_bias
);
2553 fprintf(stderr
, "COORD_TYPE_X:%d ", tex
->coord_type_x
);
2554 fprintf(stderr
, "COORD_TYPE_Y:%d ", tex
->coord_type_y
);
2555 fprintf(stderr
, "COORD_TYPE_Z:%d ", tex
->coord_type_z
);
2556 fprintf(stderr
, "COORD_TYPE_W:%d\n", tex
->coord_type_w
);
2558 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2559 fprintf(stderr
, "OFFSET_X:%d ", tex
->offset_x
);
2560 fprintf(stderr
, "OFFSET_Y:%d ", tex
->offset_y
);
2561 fprintf(stderr
, "OFFSET_Z:%d ", tex
->offset_z
);
2562 fprintf(stderr
, "SAMPLER_ID:%d ", tex
->sampler_id
);
2563 fprintf(stderr
, "SRC(SEL_X:%d ", tex
->src_sel_x
);
2564 fprintf(stderr
, "SEL_Y:%d ", tex
->src_sel_y
);
2565 fprintf(stderr
, "SEL_Z:%d ", tex
->src_sel_z
);
2566 fprintf(stderr
, "SEL_W:%d)\n", tex
->src_sel_w
);
2568 fprintf(stderr
, "%04d %08X \n", id
, bc
->bytecode
[id
]);
2572 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2573 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2574 fprintf(stderr
, "INST:%d ", vtx
->inst
);
2575 fprintf(stderr
, "FETCH_TYPE:%d ", vtx
->fetch_type
);
2576 fprintf(stderr
, "BUFFER_ID:%d\n", vtx
->buffer_id
);
2578 /* This assumes that no semantic fetches exist */
2579 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2580 fprintf(stderr
, "SRC(GPR:%d ", vtx
->src_gpr
);
2581 fprintf(stderr
, "SEL_X:%d) ", vtx
->src_sel_x
);
2582 if (bc
->chip_class
< CAYMAN
)
2583 fprintf(stderr
, "MEGA_FETCH_COUNT:%d ", vtx
->mega_fetch_count
);
2585 fprintf(stderr
, "SEL_Y:%d) ", 0);
2586 fprintf(stderr
, "DST(GPR:%d ", vtx
->dst_gpr
);
2587 fprintf(stderr
, "SEL_X:%d ", vtx
->dst_sel_x
);
2588 fprintf(stderr
, "SEL_Y:%d ", vtx
->dst_sel_y
);
2589 fprintf(stderr
, "SEL_Z:%d ", vtx
->dst_sel_z
);
2590 fprintf(stderr
, "SEL_W:%d) ", vtx
->dst_sel_w
);
2591 fprintf(stderr
, "USE_CONST_FIELDS:%d ", vtx
->use_const_fields
);
2592 fprintf(stderr
, "FORMAT(DATA:%d ", vtx
->data_format
);
2593 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2594 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2595 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2597 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2598 fprintf(stderr
, "ENDIAN:%d ", vtx
->endian
);
2599 fprintf(stderr
, "OFFSET:%d\n", vtx
->offset
);
2602 fprintf(stderr
, "%04d %08X \n", id
, bc
->bytecode
[id
]);
2607 fprintf(stderr
, "--------------------------------------\n");
2610 static void r600_vertex_data_type(enum pipe_format pformat
,
2612 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2614 const struct util_format_description
*desc
;
2620 *endian
= ENDIAN_NONE
;
2622 desc
= util_format_description(pformat
);
2623 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2627 /* Find the first non-VOID channel. */
2628 for (i
= 0; i
< 4; i
++) {
2629 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2634 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2636 switch (desc
->channel
[i
].type
) {
2637 /* Half-floats, floats, ints */
2638 case UTIL_FORMAT_TYPE_FLOAT
:
2639 switch (desc
->channel
[i
].size
) {
2641 switch (desc
->nr_channels
) {
2643 *format
= FMT_16_FLOAT
;
2646 *format
= FMT_16_16_FLOAT
;
2650 *format
= FMT_16_16_16_16_FLOAT
;
2655 switch (desc
->nr_channels
) {
2657 *format
= FMT_32_FLOAT
;
2660 *format
= FMT_32_32_FLOAT
;
2663 *format
= FMT_32_32_32_FLOAT
;
2666 *format
= FMT_32_32_32_32_FLOAT
;
2675 case UTIL_FORMAT_TYPE_UNSIGNED
:
2677 case UTIL_FORMAT_TYPE_SIGNED
:
2678 switch (desc
->channel
[i
].size
) {
2680 switch (desc
->nr_channels
) {
2689 *format
= FMT_8_8_8_8
;
2694 if (desc
->nr_channels
!= 4)
2697 *format
= FMT_2_10_10_10
;
2700 switch (desc
->nr_channels
) {
2705 *format
= FMT_16_16
;
2709 *format
= FMT_16_16_16_16
;
2714 switch (desc
->nr_channels
) {
2719 *format
= FMT_32_32
;
2722 *format
= FMT_32_32_32
;
2725 *format
= FMT_32_32_32_32
;
2737 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2742 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2743 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2744 if (!desc
->channel
[i
].normalized
) {
2745 if (desc
->channel
[i
].pure_integer
)
2753 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2756 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2758 const struct pipe_vertex_element
*elements
)
2760 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2761 static int dump_shaders
= -1;
2762 struct r600_bytecode bc
;
2763 struct r600_bytecode_vtx vtx
;
2764 const struct util_format_description
*desc
;
2765 unsigned fetch_resource_start
= rctx
->chip_class
>= EVERGREEN
? 0 : 160;
2766 unsigned format
, num_format
, format_comp
, endian
;
2768 int i
, j
, r
, fs_size
;
2769 struct r600_resource
*fetch_shader
;
2773 memset(&bc
, 0, sizeof(bc
));
2774 r600_bytecode_init(&bc
, rctx
->chip_class
, rctx
->family
,
2775 rctx
->screen
->msaa_texture_support
);
2777 for (i
= 0; i
< count
; i
++) {
2778 if (elements
[i
].instance_divisor
> 1) {
2779 if (rctx
->chip_class
== CAYMAN
) {
2780 for (j
= 0; j
< 4; j
++) {
2781 struct r600_bytecode_alu alu
;
2782 memset(&alu
, 0, sizeof(alu
));
2783 alu
.inst
= BC_INST(&bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2785 alu
.src
[0].chan
= 3;
2786 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2787 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2788 alu
.dst
.sel
= i
+ 1;
2790 alu
.dst
.write
= j
== 3;
2792 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2793 r600_bytecode_clear(&bc
);
2798 struct r600_bytecode_alu alu
;
2799 memset(&alu
, 0, sizeof(alu
));
2800 alu
.inst
= BC_INST(&bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2802 alu
.src
[0].chan
= 3;
2803 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2804 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2805 alu
.dst
.sel
= i
+ 1;
2809 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2810 r600_bytecode_clear(&bc
);
2817 for (i
= 0; i
< count
; i
++) {
2818 r600_vertex_data_type(elements
[i
].src_format
,
2819 &format
, &num_format
, &format_comp
, &endian
);
2821 desc
= util_format_description(elements
[i
].src_format
);
2823 r600_bytecode_clear(&bc
);
2824 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2828 if (elements
[i
].src_offset
> 65535) {
2829 r600_bytecode_clear(&bc
);
2830 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2834 memset(&vtx
, 0, sizeof(vtx
));
2835 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2836 vtx
.fetch_type
= elements
[i
].instance_divisor
? 1 : 0;
2837 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2838 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2839 vtx
.mega_fetch_count
= 0x1F;
2840 vtx
.dst_gpr
= i
+ 1;
2841 vtx
.dst_sel_x
= desc
->swizzle
[0];
2842 vtx
.dst_sel_y
= desc
->swizzle
[1];
2843 vtx
.dst_sel_z
= desc
->swizzle
[2];
2844 vtx
.dst_sel_w
= desc
->swizzle
[3];
2845 vtx
.data_format
= format
;
2846 vtx
.num_format_all
= num_format
;
2847 vtx
.format_comp_all
= format_comp
;
2848 vtx
.srf_mode_all
= 1;
2849 vtx
.offset
= elements
[i
].src_offset
;
2850 vtx
.endian
= endian
;
2852 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2853 r600_bytecode_clear(&bc
);
2858 r600_bytecode_add_cfinst(&bc
, BC_INST(&bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
));
2860 if ((r
= r600_bytecode_build(&bc
))) {
2861 r600_bytecode_clear(&bc
);
2865 if (dump_shaders
== -1)
2866 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
2869 fprintf(stderr
, "--------------------------------------------------------------\n");
2870 r600_bytecode_dump(&bc
);
2871 fprintf(stderr
, "______________________________________________________________\n");
2876 fetch_shader
= (struct r600_resource
*)
2877 pipe_buffer_create(rctx
->context
.screen
,
2879 PIPE_USAGE_IMMUTABLE
, fs_size
);
2880 if (fetch_shader
== NULL
) {
2881 r600_bytecode_clear(&bc
);
2885 bytecode
= rctx
->ws
->buffer_map(fetch_shader
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
2886 if (bytecode
== NULL
) {
2887 r600_bytecode_clear(&bc
);
2888 pipe_resource_reference((struct pipe_resource
**)&fetch_shader
, NULL
);
2892 if (R600_BIG_ENDIAN
) {
2893 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2894 bytecode
[i
] = bswap_32(bc
.bytecode
[i
]);
2897 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2900 rctx
->ws
->buffer_unmap(fetch_shader
->cs_buf
);
2901 r600_bytecode_clear(&bc
);
2903 return fetch_shader
;
2906 void r600_bytecode_alu_read(struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2909 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2910 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2911 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2912 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2913 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2914 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2915 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2916 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2917 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2918 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2919 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2922 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2923 if (alu
->bank_swizzle
)
2924 alu
->bank_swizzle_force
= alu
->bank_swizzle
;
2925 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2926 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2927 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2928 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2929 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2932 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2933 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2934 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2935 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2936 alu
->inst
= G_SQ_ALU_WORD1_OP3_ALU_INST(word1
);
2938 else /*ALU_DWORD1_OP2*/
2940 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2941 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2942 alu
->inst
= G_SQ_ALU_WORD1_OP2_ALU_INST(word1
);
2943 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2944 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2945 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2947 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);