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gallium: remove pipe_surface::usage
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include <byteswap.h>
31 #include "util/u_memory.h"
32 #include "pipe/p_shader_tokens.h"
33
34 #define NUM_OF_CYCLES 3
35 #define NUM_OF_COMPONENTS 4
36
37 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
38 {
39 if(alu->is_op3)
40 return 3;
41
42 switch (bc->chip_class) {
43 case R600:
44 case R700:
45 switch (alu->inst) {
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
47 return 0;
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
92 return 2;
93
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
118 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
119 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
120 return 1;
121 default: R600_ERR(
122 "Need instruction operand number for 0x%x.\n", alu->inst);
123 }
124 break;
125 case EVERGREEN:
126 case CAYMAN:
127 switch (alu->inst) {
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
129 return 0;
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
176 return 2;
177
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
198 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
199 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
200 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
201 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
202 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
203 return 1;
204 default: R600_ERR(
205 "Need instruction operand number for 0x%x.\n", alu->inst);
206 }
207 break;
208 }
209
210 return 3;
211 }
212
213 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
214
215 static struct r600_bytecode_cf *r600_bytecode_cf(void)
216 {
217 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
218
219 if (cf == NULL)
220 return NULL;
221 LIST_INITHEAD(&cf->list);
222 LIST_INITHEAD(&cf->alu);
223 LIST_INITHEAD(&cf->vtx);
224 LIST_INITHEAD(&cf->tex);
225 return cf;
226 }
227
228 static struct r600_bytecode_alu *r600_bytecode_alu(void)
229 {
230 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
231
232 if (alu == NULL)
233 return NULL;
234 LIST_INITHEAD(&alu->list);
235 return alu;
236 }
237
238 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
239 {
240 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
241
242 if (vtx == NULL)
243 return NULL;
244 LIST_INITHEAD(&vtx->list);
245 return vtx;
246 }
247
248 static struct r600_bytecode_tex *r600_bytecode_tex(void)
249 {
250 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
251
252 if (tex == NULL)
253 return NULL;
254 LIST_INITHEAD(&tex->list);
255 return tex;
256 }
257
258 void r600_bytecode_init(struct r600_bytecode *bc,
259 enum chip_class chip_class,
260 enum radeon_family family,
261 enum r600_msaa_texture_mode msaa_texture_mode)
262 {
263 if ((chip_class == R600) &&
264 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
265 bc->ar_handling = AR_HANDLE_RV6XX;
266 bc->r6xx_nop_after_rel_dst = 1;
267 } else {
268 bc->ar_handling = AR_HANDLE_NORMAL;
269 bc->r6xx_nop_after_rel_dst = 0;
270 }
271
272 LIST_INITHEAD(&bc->cf);
273 bc->chip_class = chip_class;
274 bc->msaa_texture_mode = msaa_texture_mode;
275 }
276
277 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
278 {
279 struct r600_bytecode_cf *cf = r600_bytecode_cf();
280
281 if (cf == NULL)
282 return -ENOMEM;
283 LIST_ADDTAIL(&cf->list, &bc->cf);
284 if (bc->cf_last) {
285 cf->id = bc->cf_last->id + 2;
286 if (bc->cf_last->eg_alu_extended) {
287 /* take into account extended alu size */
288 cf->id += 2;
289 bc->ndw += 2;
290 }
291 }
292 bc->cf_last = cf;
293 bc->ncf++;
294 bc->ndw += 2;
295 bc->force_add_cf = 0;
296 bc->ar_loaded = 0;
297 return 0;
298 }
299
300 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
301 {
302 int r;
303
304 if (output->gpr >= bc->ngpr)
305 bc->ngpr = output->gpr + 1;
306
307 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
308 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
309 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
310 output->type == bc->cf_last->output.type &&
311 output->elem_size == bc->cf_last->output.elem_size &&
312 output->swizzle_x == bc->cf_last->output.swizzle_x &&
313 output->swizzle_y == bc->cf_last->output.swizzle_y &&
314 output->swizzle_z == bc->cf_last->output.swizzle_z &&
315 output->swizzle_w == bc->cf_last->output.swizzle_w &&
316 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
317
318 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
319 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
320
321 bc->cf_last->output.end_of_program |= output->end_of_program;
322 bc->cf_last->output.inst = output->inst;
323 bc->cf_last->output.gpr = output->gpr;
324 bc->cf_last->output.array_base = output->array_base;
325 bc->cf_last->output.burst_count += output->burst_count;
326 return 0;
327
328 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
329 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
330
331 bc->cf_last->output.end_of_program |= output->end_of_program;
332 bc->cf_last->output.inst = output->inst;
333 bc->cf_last->output.burst_count += output->burst_count;
334 return 0;
335 }
336 }
337
338 r = r600_bytecode_add_cf(bc);
339 if (r)
340 return r;
341 bc->cf_last->inst = output->inst;
342 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
343 return 0;
344 }
345
346 /* alu instructions that can ony exits once per group */
347 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
348 {
349 switch (bc->chip_class) {
350 case R600:
351 case R700:
352 return !alu->is_op3 && (
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
377 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
378 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
379 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
380 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
381 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
382 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
383 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
384 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
385 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
386 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
387 case EVERGREEN:
388 case CAYMAN:
389 default:
390 return !alu->is_op3 && (
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
415 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
416 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
417 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
418 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
419 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
420 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
421 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
422 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
423 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
424 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
425 }
426 }
427
428 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
429 {
430 switch (bc->chip_class) {
431 case R600:
432 case R700:
433 return !alu->is_op3 && (
434 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
435 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
436 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
437 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
438 case EVERGREEN:
439 case CAYMAN:
440 default:
441 return !alu->is_op3 && (
442 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
443 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
444 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
445 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
446 }
447 }
448
449 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
450 {
451 switch (bc->chip_class) {
452 case R600:
453 case R700:
454 return !alu->is_op3 &&
455 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
456 case EVERGREEN:
457 case CAYMAN:
458 default:
459 return !alu->is_op3 &&
460 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
461 }
462 }
463
464 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
465 {
466 switch (bc->chip_class) {
467 case R600:
468 case R700:
469 return !alu->is_op3 && (
470 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
471 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
472 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
473 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
474 case EVERGREEN:
475 case CAYMAN:
476 default:
477 return !alu->is_op3 && (
478 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
479 }
480 }
481
482 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
483 {
484 return min <= opcode && opcode <= max;
485 }
486
487 /* ALU instructions that can only execute on the vector unit:
488 *
489 * opcode ranges:
490 * R6xx/R7xx:
491 * op3 : [0x08 - 0x0B]
492 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
493 *
494 * EVERGREEN:
495 * op3: [0x04 - 0x11]
496 * op2: [0xA0 - 0xE2]
497 */
498 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
499 {
500 switch (bc->chip_class) {
501 case R600:
502 case R700:
503 if (alu->is_op3)
504 return is_opcode_in_range(alu->inst,
505 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
506 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
507 else
508 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
509 is_opcode_in_range(alu->inst,
510 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
511 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
512 is_opcode_in_range(alu->inst,
513 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
514 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
515 is_opcode_in_range(alu->inst,
516 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
517 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
518 is_opcode_in_range(alu->inst,
519 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
520 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
521
522 case EVERGREEN:
523 if (alu->is_op3)
524 return is_opcode_in_range(alu->inst,
525 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
526 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
527 else
528 return is_opcode_in_range(alu->inst,
529 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
530 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
531 case CAYMAN:
532 default:
533 assert(0);
534 return 0;
535 }
536 }
537
538 /* ALU instructions that can only execute on the trans unit:
539 *
540 * opcode ranges:
541 * R600:
542 * op3: 0x0C
543 * op2: [0x60 - 0x79]
544 *
545 * R700:
546 * op3: 0x0C
547 * op2: [0x60 - 0x6F], [0x73 - 0x79]
548 *
549 * EVERGREEN:
550 * op3: 0x1F
551 * op2: [0x81 - 0x9C]
552 */
553 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
554 {
555
556 switch (bc->chip_class) {
557 case R600:
558 if (alu->is_op3)
559 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
560 else
561 return is_opcode_in_range(alu->inst,
562 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
563 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
564 case R700:
565 if (alu->is_op3)
566 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
567 else
568 return is_opcode_in_range(alu->inst,
569 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
570 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
571 is_opcode_in_range(alu->inst,
572 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
573 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
574 case EVERGREEN:
575 if (alu->is_op3)
576 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
577 else
578 return is_opcode_in_range(alu->inst,
579 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
580 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
581 case CAYMAN:
582 default:
583 assert(0);
584 return 0;
585 }
586 }
587
588 /* alu instructions that can execute on any unit */
589 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
590 {
591 return !is_alu_vec_unit_inst(bc, alu) &&
592 !is_alu_trans_unit_inst(bc, alu);
593 }
594
595 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
596 {
597 switch (bc->chip_class) {
598 case R600:
599 case R700:
600 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
601 case EVERGREEN:
602 case CAYMAN:
603 default:
604 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
605 }
606 }
607
608 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
609 struct r600_bytecode_alu *assignment[5])
610 {
611 struct r600_bytecode_alu *alu;
612 unsigned i, chan, trans;
613 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
614
615 for (i = 0; i < max_slots; i++)
616 assignment[i] = NULL;
617
618 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
619 chan = alu->dst.chan;
620 if (max_slots == 4)
621 trans = 0;
622 else if (is_alu_trans_unit_inst(bc, alu))
623 trans = 1;
624 else if (is_alu_vec_unit_inst(bc, alu))
625 trans = 0;
626 else if (assignment[chan])
627 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
628 else
629 trans = 0;
630
631 if (trans) {
632 if (assignment[4]) {
633 assert(0); /* ALU.Trans has already been allocated. */
634 return -1;
635 }
636 assignment[4] = alu;
637 } else {
638 if (assignment[chan]) {
639 assert(0); /* ALU.chan has already been allocated. */
640 return -1;
641 }
642 assignment[chan] = alu;
643 }
644
645 if (alu->last)
646 break;
647 }
648 return 0;
649 }
650
651 struct alu_bank_swizzle {
652 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
653 int hw_cfile_addr[4];
654 int hw_cfile_elem[4];
655 };
656
657 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
658 [SQ_ALU_VEC_012] = { 0, 1, 2 },
659 [SQ_ALU_VEC_021] = { 0, 2, 1 },
660 [SQ_ALU_VEC_120] = { 1, 2, 0 },
661 [SQ_ALU_VEC_102] = { 1, 0, 2 },
662 [SQ_ALU_VEC_201] = { 2, 0, 1 },
663 [SQ_ALU_VEC_210] = { 2, 1, 0 }
664 };
665
666 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
667 [SQ_ALU_SCL_210] = { 2, 1, 0 },
668 [SQ_ALU_SCL_122] = { 1, 2, 2 },
669 [SQ_ALU_SCL_212] = { 2, 1, 2 },
670 [SQ_ALU_SCL_221] = { 2, 2, 1 }
671 };
672
673 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
674 {
675 int i, cycle, component;
676 /* set up gpr use */
677 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
678 for (component = 0; component < NUM_OF_COMPONENTS; component++)
679 bs->hw_gpr[cycle][component] = -1;
680 for (i = 0; i < 4; i++)
681 bs->hw_cfile_addr[i] = -1;
682 for (i = 0; i < 4; i++)
683 bs->hw_cfile_elem[i] = -1;
684 }
685
686 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
687 {
688 if (bs->hw_gpr[cycle][chan] == -1)
689 bs->hw_gpr[cycle][chan] = sel;
690 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
691 /* Another scalar operation has already used the GPR read port for the channel. */
692 return -1;
693 }
694 return 0;
695 }
696
697 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
698 {
699 int res, num_res = 4;
700 if (bc->chip_class >= R700) {
701 num_res = 2;
702 chan /= 2;
703 }
704 for (res = 0; res < num_res; ++res) {
705 if (bs->hw_cfile_addr[res] == -1) {
706 bs->hw_cfile_addr[res] = sel;
707 bs->hw_cfile_elem[res] = chan;
708 return 0;
709 } else if (bs->hw_cfile_addr[res] == sel &&
710 bs->hw_cfile_elem[res] == chan)
711 return 0; /* Read for this scalar element already reserved, nothing to do here. */
712 }
713 /* All cfile read ports are used, cannot reference vector element. */
714 return -1;
715 }
716
717 static int is_gpr(unsigned sel)
718 {
719 return (sel >= 0 && sel <= 127);
720 }
721
722 /* CB constants start at 512, and get translated to a kcache index when ALU
723 * clauses are constructed. Note that we handle kcache constants the same way
724 * as (the now gone) cfile constants, is that really required? */
725 static int is_cfile(unsigned sel)
726 {
727 return (sel > 255 && sel < 512) ||
728 (sel > 511 && sel < 4607) || /* Kcache before translation. */
729 (sel > 127 && sel < 192); /* Kcache after translation. */
730 }
731
732 static int is_const(int sel)
733 {
734 return is_cfile(sel) ||
735 (sel >= V_SQ_ALU_SRC_0 &&
736 sel <= V_SQ_ALU_SRC_LITERAL);
737 }
738
739 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
740 struct alu_bank_swizzle *bs, int bank_swizzle)
741 {
742 int r, src, num_src, sel, elem, cycle;
743
744 num_src = r600_bytecode_get_num_operands(bc, alu);
745 for (src = 0; src < num_src; src++) {
746 sel = alu->src[src].sel;
747 elem = alu->src[src].chan;
748 if (is_gpr(sel)) {
749 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
750 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
751 /* Nothing to do; special-case optimization,
752 * second source uses first source’s reservation. */
753 continue;
754 else {
755 r = reserve_gpr(bs, sel, elem, cycle);
756 if (r)
757 return r;
758 }
759 } else if (is_cfile(sel)) {
760 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
761 if (r)
762 return r;
763 }
764 /* No restrictions on PV, PS, literal or special constants. */
765 }
766 return 0;
767 }
768
769 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
770 struct alu_bank_swizzle *bs, int bank_swizzle)
771 {
772 int r, src, num_src, const_count, sel, elem, cycle;
773
774 num_src = r600_bytecode_get_num_operands(bc, alu);
775 for (const_count = 0, src = 0; src < num_src; ++src) {
776 sel = alu->src[src].sel;
777 elem = alu->src[src].chan;
778 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
779 if (const_count >= 2)
780 /* More than two references to a constant in
781 * transcendental operation. */
782 return -1;
783 else
784 const_count++;
785 }
786 if (is_cfile(sel)) {
787 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
788 if (r)
789 return r;
790 }
791 }
792 for (src = 0; src < num_src; ++src) {
793 sel = alu->src[src].sel;
794 elem = alu->src[src].chan;
795 if (is_gpr(sel)) {
796 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
797 if (cycle < const_count)
798 /* Cycle for GPR load conflicts with
799 * constant load in transcendental operation. */
800 return -1;
801 r = reserve_gpr(bs, sel, elem, cycle);
802 if (r)
803 return r;
804 }
805 /* PV PS restrictions */
806 if (const_count && (sel == 254 || sel == 255)) {
807 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
808 if (cycle < const_count)
809 return -1;
810 }
811 }
812 return 0;
813 }
814
815 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
816 struct r600_bytecode_alu *slots[5])
817 {
818 struct alu_bank_swizzle bs;
819 int bank_swizzle[5];
820 int i, r = 0, forced = 1;
821 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
822 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
823
824 for (i = 0; i < max_slots; i++) {
825 if (slots[i]) {
826 if (slots[i]->bank_swizzle_force) {
827 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
828 } else {
829 forced = 0;
830 }
831 }
832
833 if (i < 4 && slots[i])
834 scalar_only = false;
835 }
836 if (forced)
837 return 0;
838
839 /* Just check every possible combination of bank swizzle.
840 * Not very efficent, but works on the first try in most of the cases. */
841 for (i = 0; i < 4; i++)
842 if (!slots[i] || !slots[i]->bank_swizzle_force)
843 bank_swizzle[i] = SQ_ALU_VEC_012;
844 else
845 bank_swizzle[i] = slots[i]->bank_swizzle;
846
847 bank_swizzle[4] = SQ_ALU_SCL_210;
848 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
849
850 if (max_slots == 4) {
851 for (i = 0; i < max_slots; i++) {
852 if (bank_swizzle[i] == SQ_ALU_VEC_210)
853 return -1;
854 }
855 }
856 init_bank_swizzle(&bs);
857 if (scalar_only == false) {
858 for (i = 0; i < 4; i++) {
859 if (slots[i]) {
860 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
861 if (r)
862 break;
863 }
864 }
865 } else
866 r = 0;
867
868 if (!r && slots[4] && max_slots == 5) {
869 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
870 }
871 if (!r) {
872 for (i = 0; i < max_slots; i++) {
873 if (slots[i])
874 slots[i]->bank_swizzle = bank_swizzle[i];
875 }
876 return 0;
877 }
878
879 if (scalar_only) {
880 bank_swizzle[4]++;
881 } else {
882 for (i = 0; i < max_slots; i++) {
883 if (!slots[i] || !slots[i]->bank_swizzle_force) {
884 bank_swizzle[i]++;
885 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
886 break;
887 else
888 bank_swizzle[i] = SQ_ALU_VEC_012;
889 }
890 }
891 }
892 }
893
894 /* Couldn't find a working swizzle. */
895 return -1;
896 }
897
898 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
899 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
900 {
901 struct r600_bytecode_alu *prev[5];
902 int gpr[5], chan[5];
903 int i, j, r, src, num_src;
904 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
905
906 r = assign_alu_units(bc, alu_prev, prev);
907 if (r)
908 return r;
909
910 for (i = 0; i < max_slots; ++i) {
911 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
912 gpr[i] = prev[i]->dst.sel;
913 /* cube writes more than PV.X */
914 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
915 chan[i] = 0;
916 else
917 chan[i] = prev[i]->dst.chan;
918 } else
919 gpr[i] = -1;
920 }
921
922 for (i = 0; i < max_slots; ++i) {
923 struct r600_bytecode_alu *alu = slots[i];
924 if(!alu)
925 continue;
926
927 num_src = r600_bytecode_get_num_operands(bc, alu);
928 for (src = 0; src < num_src; ++src) {
929 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
930 continue;
931
932 if (bc->chip_class < CAYMAN) {
933 if (alu->src[src].sel == gpr[4] &&
934 alu->src[src].chan == chan[4] &&
935 alu_prev->pred_sel == alu->pred_sel) {
936 alu->src[src].sel = V_SQ_ALU_SRC_PS;
937 alu->src[src].chan = 0;
938 continue;
939 }
940 }
941
942 for (j = 0; j < 4; ++j) {
943 if (alu->src[src].sel == gpr[j] &&
944 alu->src[src].chan == j &&
945 alu_prev->pred_sel == alu->pred_sel) {
946 alu->src[src].sel = V_SQ_ALU_SRC_PV;
947 alu->src[src].chan = chan[j];
948 break;
949 }
950 }
951 }
952 }
953
954 return 0;
955 }
956
957 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
958 {
959 switch(value) {
960 case 0:
961 *sel = V_SQ_ALU_SRC_0;
962 break;
963 case 1:
964 *sel = V_SQ_ALU_SRC_1_INT;
965 break;
966 case -1:
967 *sel = V_SQ_ALU_SRC_M_1_INT;
968 break;
969 case 0x3F800000: /* 1.0f */
970 *sel = V_SQ_ALU_SRC_1;
971 break;
972 case 0x3F000000: /* 0.5f */
973 *sel = V_SQ_ALU_SRC_0_5;
974 break;
975 case 0xBF800000: /* -1.0f */
976 *sel = V_SQ_ALU_SRC_1;
977 *neg ^= 1;
978 break;
979 case 0xBF000000: /* -0.5f */
980 *sel = V_SQ_ALU_SRC_0_5;
981 *neg ^= 1;
982 break;
983 default:
984 *sel = V_SQ_ALU_SRC_LITERAL;
985 break;
986 }
987 }
988
989 /* compute how many literal are needed */
990 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
991 uint32_t literal[4], unsigned *nliteral)
992 {
993 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
994 unsigned i, j;
995
996 for (i = 0; i < num_src; ++i) {
997 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
998 uint32_t value = alu->src[i].value;
999 unsigned found = 0;
1000 for (j = 0; j < *nliteral; ++j) {
1001 if (literal[j] == value) {
1002 found = 1;
1003 break;
1004 }
1005 }
1006 if (!found) {
1007 if (*nliteral >= 4)
1008 return -EINVAL;
1009 literal[(*nliteral)++] = value;
1010 }
1011 }
1012 }
1013 return 0;
1014 }
1015
1016 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1017 struct r600_bytecode_alu *alu,
1018 uint32_t literal[4], unsigned nliteral)
1019 {
1020 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1021 unsigned i, j;
1022
1023 for (i = 0; i < num_src; ++i) {
1024 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1025 uint32_t value = alu->src[i].value;
1026 for (j = 0; j < nliteral; ++j) {
1027 if (literal[j] == value) {
1028 alu->src[i].chan = j;
1029 break;
1030 }
1031 }
1032 }
1033 }
1034 }
1035
1036 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1037 struct r600_bytecode_alu *alu_prev)
1038 {
1039 struct r600_bytecode_alu *prev[5];
1040 struct r600_bytecode_alu *result[5] = { NULL };
1041
1042 uint32_t literal[4], prev_literal[4];
1043 unsigned nliteral = 0, prev_nliteral = 0;
1044
1045 int i, j, r, src, num_src;
1046 int num_once_inst = 0;
1047 int have_mova = 0, have_rel = 0;
1048 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1049
1050 r = assign_alu_units(bc, alu_prev, prev);
1051 if (r)
1052 return r;
1053
1054 for (i = 0; i < max_slots; ++i) {
1055 if (prev[i]) {
1056 if (prev[i]->pred_sel)
1057 return 0;
1058 if (is_alu_once_inst(bc, prev[i]))
1059 return 0;
1060 }
1061 if (slots[i]) {
1062 if (slots[i]->pred_sel)
1063 return 0;
1064 if (is_alu_once_inst(bc, slots[i]))
1065 return 0;
1066 }
1067 }
1068
1069 for (i = 0; i < max_slots; ++i) {
1070 struct r600_bytecode_alu *alu;
1071
1072 if (num_once_inst > 0)
1073 return 0;
1074
1075 /* check number of literals */
1076 if (prev[i]) {
1077 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1078 return 0;
1079 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1080 return 0;
1081 if (is_alu_mova_inst(bc, prev[i])) {
1082 if (have_rel)
1083 return 0;
1084 have_mova = 1;
1085 }
1086 num_once_inst += is_alu_once_inst(bc, prev[i]);
1087 }
1088 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1089 return 0;
1090
1091 /* Let's check used slots. */
1092 if (prev[i] && !slots[i]) {
1093 result[i] = prev[i];
1094 continue;
1095 } else if (prev[i] && slots[i]) {
1096 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1097 /* Trans unit is still free try to use it. */
1098 if (is_alu_any_unit_inst(bc, slots[i])) {
1099 result[i] = prev[i];
1100 result[4] = slots[i];
1101 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1102 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1103 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1104 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1105 return 0;
1106
1107 result[i] = slots[i];
1108 result[4] = prev[i];
1109 } else
1110 return 0;
1111 } else
1112 return 0;
1113 } else if(!slots[i]) {
1114 continue;
1115 } else {
1116 if (max_slots == 5 && slots[i] && prev[4] &&
1117 slots[i]->dst.sel == prev[4]->dst.sel &&
1118 slots[i]->dst.chan == prev[4]->dst.chan &&
1119 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1120 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1121 return 0;
1122
1123 result[i] = slots[i];
1124 }
1125
1126 alu = slots[i];
1127 num_once_inst += is_alu_once_inst(bc, alu);
1128
1129 /* don't reschedule NOPs */
1130 if (is_nop_inst(bc, alu))
1131 return 0;
1132
1133 /* Let's check dst gpr. */
1134 if (alu->dst.rel) {
1135 if (have_mova)
1136 return 0;
1137 have_rel = 1;
1138 }
1139
1140 /* Let's check source gprs */
1141 num_src = r600_bytecode_get_num_operands(bc, alu);
1142 for (src = 0; src < num_src; ++src) {
1143 if (alu->src[src].rel) {
1144 if (have_mova)
1145 return 0;
1146 have_rel = 1;
1147 }
1148
1149 /* Constants don't matter. */
1150 if (!is_gpr(alu->src[src].sel))
1151 continue;
1152
1153 for (j = 0; j < max_slots; ++j) {
1154 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1155 continue;
1156
1157 /* If it's relative then we can't determin which gpr is really used. */
1158 if (prev[j]->dst.chan == alu->src[src].chan &&
1159 (prev[j]->dst.sel == alu->src[src].sel ||
1160 prev[j]->dst.rel || alu->src[src].rel))
1161 return 0;
1162 }
1163 }
1164 }
1165
1166 /* more than one PRED_ or KILL_ ? */
1167 if (num_once_inst > 1)
1168 return 0;
1169
1170 /* check if the result can still be swizzlet */
1171 r = check_and_set_bank_swizzle(bc, result);
1172 if (r)
1173 return 0;
1174
1175 /* looks like everything worked out right, apply the changes */
1176
1177 /* undo adding previus literals */
1178 bc->cf_last->ndw -= align(prev_nliteral, 2);
1179
1180 /* sort instructions */
1181 for (i = 0; i < max_slots; ++i) {
1182 slots[i] = result[i];
1183 if (result[i]) {
1184 LIST_DEL(&result[i]->list);
1185 result[i]->last = 0;
1186 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1187 }
1188 }
1189
1190 /* determine new last instruction */
1191 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1192
1193 /* determine new first instruction */
1194 for (i = 0; i < max_slots; ++i) {
1195 if (result[i]) {
1196 bc->cf_last->curr_bs_head = result[i];
1197 break;
1198 }
1199 }
1200
1201 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1202 bc->cf_last->prev2_bs_head = NULL;
1203
1204 return 0;
1205 }
1206
1207 /* we'll keep kcache sets sorted by bank & addr */
1208 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1209 struct r600_bytecode_kcache *kcache,
1210 unsigned bank, unsigned line)
1211 {
1212 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1213
1214 for (i = 0; i < kcache_banks; i++) {
1215 if (kcache[i].mode) {
1216 int d;
1217
1218 if (kcache[i].bank < bank)
1219 continue;
1220
1221 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1222 kcache[i].bank > bank) {
1223 /* try to insert new line */
1224 if (kcache[kcache_banks-1].mode) {
1225 /* all sets are in use */
1226 return -ENOMEM;
1227 }
1228
1229 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1230 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1231 kcache[i].bank = bank;
1232 kcache[i].addr = line;
1233 return 0;
1234 }
1235
1236 d = line - kcache[i].addr;
1237
1238 if (d == -1) {
1239 kcache[i].addr--;
1240 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1241 /* we are prepending the line to the current set,
1242 * discarding the existing second line,
1243 * so we'll have to insert line+2 after it */
1244 line += 2;
1245 continue;
1246 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1247 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1248 return 0;
1249 } else {
1250 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1251 return -ENOMEM;
1252 }
1253 } else if (d == 1) {
1254 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1255 return 0;
1256 } else if (d == 0)
1257 return 0;
1258 } else { /* free kcache set - use it */
1259 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1260 kcache[i].bank = bank;
1261 kcache[i].addr = line;
1262 return 0;
1263 }
1264 }
1265 return -ENOMEM;
1266 }
1267
1268 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1269 struct r600_bytecode_kcache *kcache,
1270 struct r600_bytecode_alu *alu)
1271 {
1272 int i, r;
1273
1274 for (i = 0; i < 3; i++) {
1275 unsigned bank, line, sel = alu->src[i].sel;
1276
1277 if (sel < 512)
1278 continue;
1279
1280 bank = alu->src[i].kc_bank;
1281 line = (sel-512)>>4;
1282
1283 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1284 return r;
1285 }
1286 return 0;
1287 }
1288
1289 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1290 struct r600_bytecode_alu *alu,
1291 struct r600_bytecode_kcache * kcache)
1292 {
1293 int i, j;
1294
1295 /* Alter the src operands to refer to the kcache. */
1296 for (i = 0; i < 3; ++i) {
1297 static const unsigned int base[] = {128, 160, 256, 288};
1298 unsigned int line, sel = alu->src[i].sel, found = 0;
1299
1300 if (sel < 512)
1301 continue;
1302
1303 sel -= 512;
1304 line = sel>>4;
1305
1306 for (j = 0; j < 4 && !found; ++j) {
1307 switch (kcache[j].mode) {
1308 case V_SQ_CF_KCACHE_NOP:
1309 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1310 R600_ERR("unexpected kcache line mode\n");
1311 return -ENOMEM;
1312 default:
1313 if (kcache[j].bank == alu->src[i].kc_bank &&
1314 kcache[j].addr <= line &&
1315 line < kcache[j].addr + kcache[j].mode) {
1316 alu->src[i].sel = sel - (kcache[j].addr<<4);
1317 alu->src[i].sel += base[j];
1318 found=1;
1319 }
1320 }
1321 }
1322 }
1323 return 0;
1324 }
1325
1326 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1327 {
1328 struct r600_bytecode_kcache kcache_sets[4];
1329 struct r600_bytecode_kcache *kcache = kcache_sets;
1330 int r;
1331
1332 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1333
1334 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1335 /* can't alloc, need to start new clause */
1336 if ((r = r600_bytecode_add_cf(bc))) {
1337 return r;
1338 }
1339 bc->cf_last->inst = type;
1340
1341 /* retry with the new clause */
1342 kcache = bc->cf_last->kcache;
1343 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1344 /* can't alloc again- should never happen */
1345 return r;
1346 }
1347 } else {
1348 /* update kcache sets */
1349 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1350 }
1351
1352 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1353 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1354 if (bc->chip_class < EVERGREEN)
1355 return -ENOMEM;
1356 bc->cf_last->eg_alu_extended = 1;
1357 }
1358
1359 return 0;
1360 }
1361
1362 static int insert_nop_r6xx(struct r600_bytecode *bc)
1363 {
1364 struct r600_bytecode_alu alu;
1365 int r, i;
1366
1367 for (i = 0; i < 4; i++) {
1368 memset(&alu, 0, sizeof(alu));
1369 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1370 alu.src[0].chan = i;
1371 alu.dst.chan = i;
1372 alu.last = (i == 3);
1373 r = r600_bytecode_add_alu(bc, &alu);
1374 if (r)
1375 return r;
1376 }
1377 return 0;
1378 }
1379
1380 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1381 static int load_ar_r6xx(struct r600_bytecode *bc)
1382 {
1383 struct r600_bytecode_alu alu;
1384 int r;
1385
1386 if (bc->ar_loaded)
1387 return 0;
1388
1389 /* hack to avoid making MOVA the last instruction in the clause */
1390 if ((bc->cf_last->ndw>>1) >= 110)
1391 bc->force_add_cf = 1;
1392
1393 memset(&alu, 0, sizeof(alu));
1394 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1395 alu.src[0].sel = bc->ar_reg;
1396 alu.last = 1;
1397 alu.index_mode = INDEX_MODE_LOOP;
1398 r = r600_bytecode_add_alu(bc, &alu);
1399 if (r)
1400 return r;
1401
1402 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1403 bc->ar_loaded = 1;
1404 return 0;
1405 }
1406
1407 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1408 static int load_ar(struct r600_bytecode *bc)
1409 {
1410 struct r600_bytecode_alu alu;
1411 int r;
1412
1413 if (bc->ar_handling)
1414 return load_ar_r6xx(bc);
1415
1416 if (bc->ar_loaded)
1417 return 0;
1418
1419 /* hack to avoid making MOVA the last instruction in the clause */
1420 if ((bc->cf_last->ndw>>1) >= 110)
1421 bc->force_add_cf = 1;
1422
1423 memset(&alu, 0, sizeof(alu));
1424 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1425 alu.src[0].sel = bc->ar_reg;
1426 alu.last = 1;
1427 r = r600_bytecode_add_alu(bc, &alu);
1428 if (r)
1429 return r;
1430
1431 bc->cf_last->r6xx_uses_waterfall = 1;
1432 bc->ar_loaded = 1;
1433 return 0;
1434 }
1435
1436 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1437 {
1438 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1439 struct r600_bytecode_alu *lalu;
1440 int i, r;
1441
1442 if (nalu == NULL)
1443 return -ENOMEM;
1444 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1445
1446 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1447 /* check if we could add it anyway */
1448 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1449 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1450 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1451 if (lalu->execute_mask) {
1452 bc->force_add_cf = 1;
1453 break;
1454 }
1455 }
1456 } else
1457 bc->force_add_cf = 1;
1458 }
1459
1460 /* cf can contains only alu or only vtx or only tex */
1461 if (bc->cf_last == NULL || bc->force_add_cf) {
1462 r = r600_bytecode_add_cf(bc);
1463 if (r) {
1464 free(nalu);
1465 return r;
1466 }
1467 }
1468 bc->cf_last->inst = type;
1469
1470 /* Check AR usage and load it if required */
1471 for (i = 0; i < 3; i++)
1472 if (nalu->src[i].rel && !bc->ar_loaded)
1473 load_ar(bc);
1474
1475 if (nalu->dst.rel && !bc->ar_loaded)
1476 load_ar(bc);
1477
1478 /* Setup the kcache for this ALU instruction. This will start a new
1479 * ALU clause if needed. */
1480 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1481 free(nalu);
1482 return r;
1483 }
1484
1485 if (!bc->cf_last->curr_bs_head) {
1486 bc->cf_last->curr_bs_head = nalu;
1487 }
1488 /* number of gpr == the last gpr used in any alu */
1489 for (i = 0; i < 3; i++) {
1490 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1491 bc->ngpr = nalu->src[i].sel + 1;
1492 }
1493 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1494 r600_bytecode_special_constants(nalu->src[i].value,
1495 &nalu->src[i].sel, &nalu->src[i].neg);
1496 }
1497 if (nalu->dst.sel >= bc->ngpr) {
1498 bc->ngpr = nalu->dst.sel + 1;
1499 }
1500 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1501 /* each alu use 2 dwords */
1502 bc->cf_last->ndw += 2;
1503 bc->ndw += 2;
1504
1505 /* process cur ALU instructions for bank swizzle */
1506 if (nalu->last) {
1507 uint32_t literal[4];
1508 unsigned nliteral;
1509 struct r600_bytecode_alu *slots[5];
1510 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1511 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1512 if (r)
1513 return r;
1514
1515 if (bc->cf_last->prev_bs_head) {
1516 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1517 if (r)
1518 return r;
1519 }
1520
1521 if (bc->cf_last->prev_bs_head) {
1522 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1523 if (r)
1524 return r;
1525 }
1526
1527 r = check_and_set_bank_swizzle(bc, slots);
1528 if (r)
1529 return r;
1530
1531 for (i = 0, nliteral = 0; i < max_slots; i++) {
1532 if (slots[i]) {
1533 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1534 if (r)
1535 return r;
1536 }
1537 }
1538 bc->cf_last->ndw += align(nliteral, 2);
1539
1540 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1541 * worst case */
1542 if ((bc->cf_last->ndw >> 1) >= 120) {
1543 bc->force_add_cf = 1;
1544 }
1545
1546 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1547 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1548 bc->cf_last->curr_bs_head = NULL;
1549 }
1550
1551 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1552 insert_nop_r6xx(bc);
1553
1554 return 0;
1555 }
1556
1557 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1558 {
1559 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1560 }
1561
1562 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1563 {
1564 switch (bc->chip_class) {
1565 case R600:
1566 return 8;
1567
1568 case R700:
1569 case EVERGREEN:
1570 case CAYMAN:
1571 return 16;
1572
1573 default:
1574 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1575 return 8;
1576 }
1577 }
1578
1579 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1580 {
1581 switch (bc->chip_class) {
1582 case R700:
1583 case R600:
1584 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1585 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1586 case EVERGREEN:
1587 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1588 case CAYMAN:
1589 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1590 default:
1591 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1592 return FALSE;
1593 }
1594 }
1595
1596 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1597 {
1598 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1599 int r;
1600
1601 if (nvtx == NULL)
1602 return -ENOMEM;
1603 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1604
1605 /* cf can contains only alu or only vtx or only tex */
1606 if (bc->cf_last == NULL ||
1607 last_inst_was_not_vtx_fetch(bc) ||
1608 bc->force_add_cf) {
1609 r = r600_bytecode_add_cf(bc);
1610 if (r) {
1611 free(nvtx);
1612 return r;
1613 }
1614 switch (bc->chip_class) {
1615 case R600:
1616 case R700:
1617 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1618 break;
1619 case EVERGREEN:
1620 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1621 break;
1622 case CAYMAN:
1623 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1624 break;
1625 default:
1626 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1627 return -EINVAL;
1628 }
1629 }
1630 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1631 /* each fetch use 4 dwords */
1632 bc->cf_last->ndw += 4;
1633 bc->ndw += 4;
1634 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1635 bc->force_add_cf = 1;
1636
1637 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1638 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1639
1640 return 0;
1641 }
1642
1643 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1644 {
1645 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1646 int r;
1647
1648 if (ntex == NULL)
1649 return -ENOMEM;
1650 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1651
1652 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1653 if (bc->cf_last != NULL &&
1654 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1655 struct r600_bytecode_tex *ttex;
1656 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1657 if (ttex->dst_gpr == ntex->src_gpr) {
1658 bc->force_add_cf = 1;
1659 break;
1660 }
1661 }
1662 /* slight hack to make gradients always go into same cf */
1663 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1664 bc->force_add_cf = 1;
1665 }
1666
1667 /* cf can contains only alu or only vtx or only tex */
1668 if (bc->cf_last == NULL ||
1669 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1670 bc->force_add_cf) {
1671 r = r600_bytecode_add_cf(bc);
1672 if (r) {
1673 free(ntex);
1674 return r;
1675 }
1676 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1677 }
1678 if (ntex->src_gpr >= bc->ngpr) {
1679 bc->ngpr = ntex->src_gpr + 1;
1680 }
1681 if (ntex->dst_gpr >= bc->ngpr) {
1682 bc->ngpr = ntex->dst_gpr + 1;
1683 }
1684 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1685 /* each texture fetch use 4 dwords */
1686 bc->cf_last->ndw += 4;
1687 bc->ndw += 4;
1688 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1689 bc->force_add_cf = 1;
1690 return 0;
1691 }
1692
1693 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1694 {
1695 int r;
1696 r = r600_bytecode_add_cf(bc);
1697 if (r)
1698 return r;
1699
1700 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1701 bc->cf_last->inst = inst;
1702 return 0;
1703 }
1704
1705 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1706 {
1707 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1708 }
1709
1710 /* common to all 3 families */
1711 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1712 {
1713 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1714 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1715 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1716 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1717 if (bc->chip_class < CAYMAN)
1718 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1719 id++;
1720 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1721 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1722 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1723 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1724 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1725 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1726 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1727 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1728 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1729 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1730 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1731 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1732 if (bc->chip_class < CAYMAN)
1733 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1734 id++;
1735 bc->bytecode[id++] = 0;
1736 return 0;
1737 }
1738
1739 /* common to all 3 families */
1740 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1741 {
1742 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1743 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1744 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1745 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1746 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1747 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1748 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1749 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1750 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1751 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1752 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1753 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1754 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1755 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1756 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1757 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1758 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1759 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1760 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1761 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1762 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1763 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1764 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1765 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1766 bc->bytecode[id++] = 0;
1767 return 0;
1768 }
1769
1770 /* r600 only, r700/eg bits in r700_asm.c */
1771 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1772 {
1773 /* don't replace gpr by pv or ps for destination register */
1774 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1775 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1776 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1777 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1778 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1779 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1780 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1781 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1782 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1783 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1784 S_SQ_ALU_WORD0_LAST(alu->last);
1785
1786 if (alu->is_op3) {
1787 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1788 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1789 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1790 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1791 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1792 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1793 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1794 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1795 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1796 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1797 } else {
1798 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1799 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1800 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1801 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1802 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1803 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1804 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1805 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1806 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1807 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1808 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1809 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1810 }
1811 return 0;
1812 }
1813
1814 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1815 {
1816 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1817 *bytecode++ = cf->inst |
1818 S_SQ_CF_WORD1_BARRIER(1) |
1819 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1820 }
1821
1822 /* common for r600/r700 - eg in eg_asm.c */
1823 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1824 {
1825 unsigned id = cf->id;
1826
1827 switch (cf->inst) {
1828 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1829 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1830 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1831 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1832 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1833 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1834 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1835 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1836
1837 bc->bytecode[id++] = cf->inst |
1838 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1839 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1840 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1841 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1842 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1843 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1844 break;
1845 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1846 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1847 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1848 if (bc->chip_class == R700)
1849 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1850 else
1851 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1852 break;
1853 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1854 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1855 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1856 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1857 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1858 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1859 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1860 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1861 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1862 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1863 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1864 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1865 cf->output.inst |
1866 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1867 break;
1868 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1869 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1870 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1871 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1872 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1873 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1874 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1875 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1876 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1877 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1878 cf->output.inst |
1879 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1880 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1881 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1882 break;
1883 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1884 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1885 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1886 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1887 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
1888 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1889 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1890 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1891 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1892 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1893 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1894 bc->bytecode[id++] = cf->inst |
1895 S_SQ_CF_WORD1_BARRIER(1) |
1896 S_SQ_CF_WORD1_COND(cf->cond) |
1897 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1898
1899 break;
1900 default:
1901 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1902 return -EINVAL;
1903 }
1904 return 0;
1905 }
1906
1907 int r600_bytecode_build(struct r600_bytecode *bc)
1908 {
1909 struct r600_bytecode_cf *cf;
1910 struct r600_bytecode_alu *alu;
1911 struct r600_bytecode_vtx *vtx;
1912 struct r600_bytecode_tex *tex;
1913 uint32_t literal[4];
1914 unsigned nliteral;
1915 unsigned addr;
1916 int i, r;
1917
1918 if (bc->callstack[0].max > 0)
1919 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1920 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1921 bc->nstack = 1;
1922 }
1923
1924 /* first path compute addr of each CF block */
1925 /* addr start after all the CF instructions */
1926 addr = bc->cf_last->id + 2;
1927 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1928 if (bc->chip_class >= EVERGREEN) {
1929 switch (cf->inst) {
1930 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1931 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1932 /* fetch node need to be 16 bytes aligned*/
1933 addr += 3;
1934 addr &= 0xFFFFFFFCUL;
1935 break;
1936 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1937 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1938 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1939 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1940 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1941 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1942 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1943 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1944 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1945 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1946 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1947 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1948 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1949 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1950 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1951 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1952 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1953 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1954 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1955 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1956 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1957 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1958 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1959 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1960 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1961 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1962 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
1963 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1964 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1965 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1966 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1967 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1968 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1969 case CF_NATIVE:
1970 break;
1971 default:
1972 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1973 return -EINVAL;
1974 }
1975 } else {
1976 switch (cf->inst) {
1977 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1978 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1979 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1980 /* fetch node need to be 16 bytes aligned*/
1981 addr += 3;
1982 addr &= 0xFFFFFFFCUL;
1983 break;
1984 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1985 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1986 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1987 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1988 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1989 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1990 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1991 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1992 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1993 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1994 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1995 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1996 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1997 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
1998 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1999 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2000 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2001 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2002 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2003 break;
2004 default:
2005 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2006 return -EINVAL;
2007 }
2008 }
2009 cf->addr = addr;
2010 addr += cf->ndw;
2011 bc->ndw = cf->addr + cf->ndw;
2012 }
2013 free(bc->bytecode);
2014 bc->bytecode = calloc(1, bc->ndw * 4);
2015 if (bc->bytecode == NULL)
2016 return -ENOMEM;
2017 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2018 addr = cf->addr;
2019 if (bc->chip_class >= EVERGREEN) {
2020 r = eg_bytecode_cf_build(bc, cf);
2021 if (r)
2022 return r;
2023
2024 switch (cf->inst) {
2025 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2026 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2027 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2028 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2029 nliteral = 0;
2030 memset(literal, 0, sizeof(literal));
2031 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2032 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2033 if (r)
2034 return r;
2035 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2036 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2037
2038 switch(bc->chip_class) {
2039 case EVERGREEN: /* eg alu is same encoding as r700 */
2040 case CAYMAN:
2041 r = r700_bytecode_alu_build(bc, alu, addr);
2042 break;
2043 default:
2044 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2045 return -EINVAL;
2046 }
2047 if (r)
2048 return r;
2049 addr += 2;
2050 if (alu->last) {
2051 for (i = 0; i < align(nliteral, 2); ++i) {
2052 bc->bytecode[addr++] = literal[i];
2053 }
2054 nliteral = 0;
2055 memset(literal, 0, sizeof(literal));
2056 }
2057 }
2058 break;
2059 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2060 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2061 r = r600_bytecode_vtx_build(bc, vtx, addr);
2062 if (r)
2063 return r;
2064 addr += 4;
2065 }
2066 break;
2067 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2068 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2069 assert(bc->chip_class >= EVERGREEN);
2070 r = r600_bytecode_vtx_build(bc, vtx, addr);
2071 if (r)
2072 return r;
2073 addr += 4;
2074 }
2075 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2076 r = r600_bytecode_tex_build(bc, tex, addr);
2077 if (r)
2078 return r;
2079 addr += 4;
2080 }
2081 break;
2082 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2083 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2084 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2085 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2086 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2087 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2088 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2089 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2090 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2091 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2092 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2093 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2094 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2095 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2096 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2097 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2098 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2099 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2100 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2101 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2102 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2103 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2104 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2105 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2106 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2107 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2108 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2109 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2110 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2111 break;
2112 case CF_NATIVE:
2113 break;
2114 default:
2115 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2116 return -EINVAL;
2117 }
2118 } else {
2119 r = r600_bytecode_cf_build(bc, cf);
2120 if (r)
2121 return r;
2122
2123 switch (cf->inst) {
2124 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2125 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2126 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2127 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2128 nliteral = 0;
2129 memset(literal, 0, sizeof(literal));
2130 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2131 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2132 if (r)
2133 return r;
2134 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2135 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2136
2137 switch(bc->chip_class) {
2138 case R600:
2139 r = r600_bytecode_alu_build(bc, alu, addr);
2140 break;
2141 case R700:
2142 r = r700_bytecode_alu_build(bc, alu, addr);
2143 break;
2144 default:
2145 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2146 return -EINVAL;
2147 }
2148 if (r)
2149 return r;
2150 addr += 2;
2151 if (alu->last) {
2152 for (i = 0; i < align(nliteral, 2); ++i) {
2153 bc->bytecode[addr++] = literal[i];
2154 }
2155 nliteral = 0;
2156 memset(literal, 0, sizeof(literal));
2157 }
2158 }
2159 break;
2160 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2161 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2162 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2163 r = r600_bytecode_vtx_build(bc, vtx, addr);
2164 if (r)
2165 return r;
2166 addr += 4;
2167 }
2168 break;
2169 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2170 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2171 r = r600_bytecode_tex_build(bc, tex, addr);
2172 if (r)
2173 return r;
2174 addr += 4;
2175 }
2176 break;
2177 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2178 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2179 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2180 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2181 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2182 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2183 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2184 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2185 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2186 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2187 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2188 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2189 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2190 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2191 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2192 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2193 break;
2194 default:
2195 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2196 return -EINVAL;
2197 }
2198 }
2199 }
2200 return 0;
2201 }
2202
2203 void r600_bytecode_clear(struct r600_bytecode *bc)
2204 {
2205 struct r600_bytecode_cf *cf = NULL, *next_cf;
2206
2207 free(bc->bytecode);
2208 bc->bytecode = NULL;
2209
2210 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2211 struct r600_bytecode_alu *alu = NULL, *next_alu;
2212 struct r600_bytecode_tex *tex = NULL, *next_tex;
2213 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2214
2215 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2216 free(alu);
2217 }
2218
2219 LIST_INITHEAD(&cf->alu);
2220
2221 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2222 free(tex);
2223 }
2224
2225 LIST_INITHEAD(&cf->tex);
2226
2227 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2228 free(vtx);
2229 }
2230
2231 LIST_INITHEAD(&cf->vtx);
2232
2233 free(cf);
2234 }
2235
2236 LIST_INITHEAD(&cf->list);
2237 }
2238
2239 void r600_bytecode_dump(struct r600_bytecode *bc)
2240 {
2241 struct r600_bytecode_cf *cf = NULL;
2242 struct r600_bytecode_alu *alu = NULL;
2243 struct r600_bytecode_vtx *vtx = NULL;
2244 struct r600_bytecode_tex *tex = NULL;
2245
2246 unsigned i, id;
2247 uint32_t literal[4];
2248 unsigned nliteral;
2249 char chip = '6';
2250
2251 switch (bc->chip_class) {
2252 case R700:
2253 chip = '7';
2254 break;
2255 case EVERGREEN:
2256 chip = 'E';
2257 break;
2258 case CAYMAN:
2259 chip = 'C';
2260 break;
2261 case R600:
2262 default:
2263 chip = '6';
2264 break;
2265 }
2266 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2267 fprintf(stderr, " %c\n", chip);
2268
2269 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2270 id = cf->id;
2271
2272 if (bc->chip_class >= EVERGREEN) {
2273 switch (cf->inst) {
2274 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2275 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2276 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2277 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2278 if (cf->eg_alu_extended) {
2279 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2280 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2281 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2282 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2283 id++;
2284 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2285 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2286 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2287 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2288 id++;
2289 }
2290
2291 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2292 fprintf(stderr, "ADDR:%d ", cf->addr);
2293 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2294 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2295 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2296 id++;
2297 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2298 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2299 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2300 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2301 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2302 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2303 break;
2304 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2305 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2306 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2307 fprintf(stderr, "ADDR:%d\n", cf->addr);
2308 id++;
2309 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2310 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2311 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2312 break;
2313 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2314 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2315 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2316 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2317 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2318 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2319 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2320 id++;
2321 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2322 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2323 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2324 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2325 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2326 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2327 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2328 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2329 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2330 break;
2331 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2332 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2333 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2334 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2335 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2336 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2337 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2338 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2339 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2340 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2341 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2342 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2343 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2344 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2345 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2346 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2347 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2348 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2349 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2350 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2351 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2352 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2353 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2354 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2355 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2356 id++;
2357 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2358 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2359 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2360 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2361 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2362 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2363 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2364 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2365 fprintf(stderr, "INST:%d ", cf->output.inst);
2366 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2367 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2368 break;
2369 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2370 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2371 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2372 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2373 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2374 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2375 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2376 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2377 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2378 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2379 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2380 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2381 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2382 id++;
2383 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2384 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2385 fprintf(stderr, "COND:%X ", cf->cond);
2386 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2387 break;
2388 case CF_NATIVE:
2389 fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
2390 fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
2391 break;
2392 default:
2393 R600_ERR("Unknown instruction %0x\n", cf->inst);
2394 }
2395 } else {
2396 switch (cf->inst) {
2397 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2398 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2399 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2400 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2401 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2402 fprintf(stderr, "ADDR:%d ", cf->addr);
2403 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2404 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2405 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2406 id++;
2407 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2408 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2409 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2410 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2411 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2412 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2413 break;
2414 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2415 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2416 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2417 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2418 fprintf(stderr, "ADDR:%d\n", cf->addr);
2419 id++;
2420 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2421 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2422 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2423 break;
2424 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2425 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2426 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2427 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2428 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2429 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2430 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2431 id++;
2432 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2433 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2434 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2435 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2436 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2437 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2438 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2439 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2440 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2441 break;
2442 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2443 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2444 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2445 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2446 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2447 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2448 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2449 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2450 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2451 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2452 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2453 id++;
2454 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2455 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2456 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2457 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2458 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2459 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2460 fprintf(stderr, "INST:%d ", cf->output.inst);
2461 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2462 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2463 break;
2464 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2465 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2466 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2467 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2468 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2469 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2470 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2471 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2472 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2473 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2474 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2475 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2476 id++;
2477 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2478 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2479 fprintf(stderr, "COND:%X ", cf->cond);
2480 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2481 break;
2482 default:
2483 R600_ERR("Unknown instruction %0x\n", cf->inst);
2484 }
2485 }
2486
2487 id = cf->addr;
2488 nliteral = 0;
2489 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2490 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2491
2492 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2493 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2494 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2495 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2496 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2497 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2498 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2499 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2500 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2501 fprintf(stderr, "IM:%d) ", alu->index_mode);
2502 fprintf(stderr, "PRED_SEL:%d ", alu->pred_sel);
2503 fprintf(stderr, "LAST:%d)\n", alu->last);
2504 id++;
2505 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2506 fprintf(stderr, "INST:0x%x ", alu->inst);
2507 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2508 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2509 fprintf(stderr, "REL:%d ", alu->dst.rel);
2510 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2511 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2512 if (alu->is_op3) {
2513 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2514 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2515 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2516 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2517 } else {
2518 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2519 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2520 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2521 fprintf(stderr, "OMOD:%d ", alu->omod);
2522 fprintf(stderr, "EXECUTE_MASK:%d ", alu->execute_mask);
2523 fprintf(stderr, "UPDATE_PRED:%d\n", alu->update_pred);
2524 }
2525
2526 id++;
2527 if (alu->last) {
2528 for (i = 0; i < nliteral; i++, id++) {
2529 float *f = (float*)(bc->bytecode + id);
2530 fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
2531 *(bc->bytecode + id));
2532 }
2533 id += nliteral & 1;
2534 nliteral = 0;
2535 }
2536 }
2537
2538 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2539 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2540 fprintf(stderr, "INST:0x%x ", tex->inst);
2541 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2542 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2543 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2544 id++;
2545 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2546 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2547 fprintf(stderr, "REL:%d ", tex->dst_rel);
2548 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2549 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2550 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2551 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2552 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2553 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2554 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2555 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2556 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2557 id++;
2558 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2559 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2560 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2561 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2562 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2563 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2564 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2565 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2566 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2567 id++;
2568 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2569 id++;
2570 }
2571
2572 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2573 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2574 fprintf(stderr, "INST:%d ", vtx->inst);
2575 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2576 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2577 id++;
2578 /* This assumes that no semantic fetches exist */
2579 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2580 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2581 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2582 if (bc->chip_class < CAYMAN)
2583 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2584 else
2585 fprintf(stderr, "SEL_Y:%d) ", 0);
2586 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2587 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2588 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2589 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2590 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2591 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2592 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2593 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2594 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2595 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2596 id++;
2597 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2598 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2599 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2600 /* XXX */
2601 id++;
2602 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2603 id++;
2604 }
2605 }
2606
2607 fprintf(stderr, "--------------------------------------\n");
2608 }
2609
2610 static void r600_vertex_data_type(enum pipe_format pformat,
2611 unsigned *format,
2612 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2613 {
2614 const struct util_format_description *desc;
2615 unsigned i;
2616
2617 *format = 0;
2618 *num_format = 0;
2619 *format_comp = 0;
2620 *endian = ENDIAN_NONE;
2621
2622 desc = util_format_description(pformat);
2623 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2624 goto out_unknown;
2625 }
2626
2627 /* Find the first non-VOID channel. */
2628 for (i = 0; i < 4; i++) {
2629 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2630 break;
2631 }
2632 }
2633
2634 *endian = r600_endian_swap(desc->channel[i].size);
2635
2636 switch (desc->channel[i].type) {
2637 /* Half-floats, floats, ints */
2638 case UTIL_FORMAT_TYPE_FLOAT:
2639 switch (desc->channel[i].size) {
2640 case 16:
2641 switch (desc->nr_channels) {
2642 case 1:
2643 *format = FMT_16_FLOAT;
2644 break;
2645 case 2:
2646 *format = FMT_16_16_FLOAT;
2647 break;
2648 case 3:
2649 case 4:
2650 *format = FMT_16_16_16_16_FLOAT;
2651 break;
2652 }
2653 break;
2654 case 32:
2655 switch (desc->nr_channels) {
2656 case 1:
2657 *format = FMT_32_FLOAT;
2658 break;
2659 case 2:
2660 *format = FMT_32_32_FLOAT;
2661 break;
2662 case 3:
2663 *format = FMT_32_32_32_FLOAT;
2664 break;
2665 case 4:
2666 *format = FMT_32_32_32_32_FLOAT;
2667 break;
2668 }
2669 break;
2670 default:
2671 goto out_unknown;
2672 }
2673 break;
2674 /* Unsigned ints */
2675 case UTIL_FORMAT_TYPE_UNSIGNED:
2676 /* Signed ints */
2677 case UTIL_FORMAT_TYPE_SIGNED:
2678 switch (desc->channel[i].size) {
2679 case 8:
2680 switch (desc->nr_channels) {
2681 case 1:
2682 *format = FMT_8;
2683 break;
2684 case 2:
2685 *format = FMT_8_8;
2686 break;
2687 case 3:
2688 case 4:
2689 *format = FMT_8_8_8_8;
2690 break;
2691 }
2692 break;
2693 case 10:
2694 if (desc->nr_channels != 4)
2695 goto out_unknown;
2696
2697 *format = FMT_2_10_10_10;
2698 break;
2699 case 16:
2700 switch (desc->nr_channels) {
2701 case 1:
2702 *format = FMT_16;
2703 break;
2704 case 2:
2705 *format = FMT_16_16;
2706 break;
2707 case 3:
2708 case 4:
2709 *format = FMT_16_16_16_16;
2710 break;
2711 }
2712 break;
2713 case 32:
2714 switch (desc->nr_channels) {
2715 case 1:
2716 *format = FMT_32;
2717 break;
2718 case 2:
2719 *format = FMT_32_32;
2720 break;
2721 case 3:
2722 *format = FMT_32_32_32;
2723 break;
2724 case 4:
2725 *format = FMT_32_32_32_32;
2726 break;
2727 }
2728 break;
2729 default:
2730 goto out_unknown;
2731 }
2732 break;
2733 default:
2734 goto out_unknown;
2735 }
2736
2737 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2738 *format_comp = 1;
2739 }
2740
2741 *num_format = 0;
2742 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2743 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2744 if (!desc->channel[i].normalized) {
2745 if (desc->channel[i].pure_integer)
2746 *num_format = 1;
2747 else
2748 *num_format = 2;
2749 }
2750 }
2751 return;
2752 out_unknown:
2753 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2754 }
2755
2756 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2757 unsigned count,
2758 const struct pipe_vertex_element *elements)
2759 {
2760 struct r600_context *rctx = (struct r600_context *)ctx;
2761 static int dump_shaders = -1;
2762 struct r600_bytecode bc;
2763 struct r600_bytecode_vtx vtx;
2764 const struct util_format_description *desc;
2765 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2766 unsigned format, num_format, format_comp, endian;
2767 uint32_t *bytecode;
2768 int i, j, r, fs_size;
2769 struct r600_resource *fetch_shader;
2770
2771 assert(count < 32);
2772
2773 memset(&bc, 0, sizeof(bc));
2774 r600_bytecode_init(&bc, rctx->chip_class, rctx->family,
2775 rctx->screen->msaa_texture_support);
2776
2777 for (i = 0; i < count; i++) {
2778 if (elements[i].instance_divisor > 1) {
2779 if (rctx->chip_class == CAYMAN) {
2780 for (j = 0; j < 4; j++) {
2781 struct r600_bytecode_alu alu;
2782 memset(&alu, 0, sizeof(alu));
2783 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2784 alu.src[0].sel = 0;
2785 alu.src[0].chan = 3;
2786 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2787 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2788 alu.dst.sel = i + 1;
2789 alu.dst.chan = j;
2790 alu.dst.write = j == 3;
2791 alu.last = j == 3;
2792 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2793 r600_bytecode_clear(&bc);
2794 return NULL;
2795 }
2796 }
2797 } else {
2798 struct r600_bytecode_alu alu;
2799 memset(&alu, 0, sizeof(alu));
2800 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2801 alu.src[0].sel = 0;
2802 alu.src[0].chan = 3;
2803 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2804 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2805 alu.dst.sel = i + 1;
2806 alu.dst.chan = 3;
2807 alu.dst.write = 1;
2808 alu.last = 1;
2809 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2810 r600_bytecode_clear(&bc);
2811 return NULL;
2812 }
2813 }
2814 }
2815 }
2816
2817 for (i = 0; i < count; i++) {
2818 r600_vertex_data_type(elements[i].src_format,
2819 &format, &num_format, &format_comp, &endian);
2820
2821 desc = util_format_description(elements[i].src_format);
2822 if (desc == NULL) {
2823 r600_bytecode_clear(&bc);
2824 R600_ERR("unknown format %d\n", elements[i].src_format);
2825 return NULL;
2826 }
2827
2828 if (elements[i].src_offset > 65535) {
2829 r600_bytecode_clear(&bc);
2830 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2831 return NULL;
2832 }
2833
2834 memset(&vtx, 0, sizeof(vtx));
2835 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2836 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2837 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2838 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2839 vtx.mega_fetch_count = 0x1F;
2840 vtx.dst_gpr = i + 1;
2841 vtx.dst_sel_x = desc->swizzle[0];
2842 vtx.dst_sel_y = desc->swizzle[1];
2843 vtx.dst_sel_z = desc->swizzle[2];
2844 vtx.dst_sel_w = desc->swizzle[3];
2845 vtx.data_format = format;
2846 vtx.num_format_all = num_format;
2847 vtx.format_comp_all = format_comp;
2848 vtx.srf_mode_all = 1;
2849 vtx.offset = elements[i].src_offset;
2850 vtx.endian = endian;
2851
2852 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2853 r600_bytecode_clear(&bc);
2854 return NULL;
2855 }
2856 }
2857
2858 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2859
2860 if ((r = r600_bytecode_build(&bc))) {
2861 r600_bytecode_clear(&bc);
2862 return NULL;
2863 }
2864
2865 if (dump_shaders == -1)
2866 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2867
2868 if (dump_shaders) {
2869 fprintf(stderr, "--------------------------------------------------------------\n");
2870 r600_bytecode_dump(&bc);
2871 fprintf(stderr, "______________________________________________________________\n");
2872 }
2873
2874 fs_size = bc.ndw*4;
2875
2876 fetch_shader = (struct r600_resource*)
2877 pipe_buffer_create(rctx->context.screen,
2878 PIPE_BIND_CUSTOM,
2879 PIPE_USAGE_IMMUTABLE, fs_size);
2880 if (fetch_shader == NULL) {
2881 r600_bytecode_clear(&bc);
2882 return NULL;
2883 }
2884
2885 bytecode = rctx->ws->buffer_map(fetch_shader->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
2886 if (bytecode == NULL) {
2887 r600_bytecode_clear(&bc);
2888 pipe_resource_reference((struct pipe_resource**)&fetch_shader, NULL);
2889 return NULL;
2890 }
2891
2892 if (R600_BIG_ENDIAN) {
2893 for (i = 0; i < fs_size / 4; ++i) {
2894 bytecode[i] = bswap_32(bc.bytecode[i]);
2895 }
2896 } else {
2897 memcpy(bytecode, bc.bytecode, fs_size);
2898 }
2899
2900 rctx->ws->buffer_unmap(fetch_shader->cs_buf);
2901 r600_bytecode_clear(&bc);
2902
2903 return fetch_shader;
2904 }
2905
2906 void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2907 {
2908 /* WORD0 */
2909 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2910 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2911 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2912 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2913 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2914 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2915 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2916 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2917 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2918 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2919 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2920
2921 /* WORD1 */
2922 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2923 if (alu->bank_swizzle)
2924 alu->bank_swizzle_force = alu->bank_swizzle;
2925 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2926 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2927 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2928 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2929 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2930 {
2931 alu->is_op3 = 1;
2932 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2933 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2934 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2935 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2936 alu->inst = G_SQ_ALU_WORD1_OP3_ALU_INST(word1);
2937 }
2938 else /*ALU_DWORD1_OP2*/
2939 {
2940 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2941 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2942 alu->inst = G_SQ_ALU_WORD1_OP2_ALU_INST(word1);
2943 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2944 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2945 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2946 alu->execute_mask =
2947 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2948 }
2949 }
2950
2951 void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2952 {
2953 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2954 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2955 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2956 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2957
2958 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2959 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2960 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2961 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2962 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2963 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2964 output->inst = R600_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
2965 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2966 }