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[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
35
36 #include "sb/sb_public.h"
37
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
40
41 static inline bool alu_writes(struct r600_bytecode_alu *alu)
42 {
43 return alu->dst.write || alu->is_op3;
44 }
45
46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu)
47 {
48 return r600_isa_alu(alu->op)->src_count;
49 }
50
51 static struct r600_bytecode_cf *r600_bytecode_cf(void)
52 {
53 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
54
55 if (!cf)
56 return NULL;
57 LIST_INITHEAD(&cf->list);
58 LIST_INITHEAD(&cf->alu);
59 LIST_INITHEAD(&cf->vtx);
60 LIST_INITHEAD(&cf->tex);
61 LIST_INITHEAD(&cf->gds);
62 return cf;
63 }
64
65 static struct r600_bytecode_alu *r600_bytecode_alu(void)
66 {
67 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
68
69 if (!alu)
70 return NULL;
71 LIST_INITHEAD(&alu->list);
72 return alu;
73 }
74
75 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
76 {
77 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
78
79 if (!vtx)
80 return NULL;
81 LIST_INITHEAD(&vtx->list);
82 return vtx;
83 }
84
85 static struct r600_bytecode_tex *r600_bytecode_tex(void)
86 {
87 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
88
89 if (!tex)
90 return NULL;
91 LIST_INITHEAD(&tex->list);
92 return tex;
93 }
94
95 static struct r600_bytecode_gds *r600_bytecode_gds(void)
96 {
97 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
98
99 if (gds == NULL)
100 return NULL;
101 LIST_INITHEAD(&gds->list);
102 return gds;
103 }
104
105 static unsigned stack_entry_size(enum radeon_family chip) {
106 /* Wavefront size:
107 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
108 * Aruba/Sumo/Sumo2/redwood/juniper
109 * 32: R630/R730/R710/Palm/Cedar
110 * 16: R610/Rs780
111 *
112 * Stack row size:
113 * Wavefront Size 16 32 48 64
114 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
115 * Columns per Row (R9xx+) 8 4 4 4 */
116
117 switch (chip) {
118 /* FIXME: are some chips missing here? */
119 /* wavefront size 16 */
120 case CHIP_RV610:
121 case CHIP_RS780:
122 case CHIP_RV620:
123 case CHIP_RS880:
124 /* wavefront size 32 */
125 case CHIP_RV630:
126 case CHIP_RV635:
127 case CHIP_RV730:
128 case CHIP_RV710:
129 case CHIP_PALM:
130 case CHIP_CEDAR:
131 return 8;
132
133 /* wavefront size 64 */
134 default:
135 return 4;
136 }
137 }
138
139 void r600_bytecode_init(struct r600_bytecode *bc,
140 enum chip_class chip_class,
141 enum radeon_family family,
142 bool has_compressed_msaa_texturing)
143 {
144 static unsigned next_shader_id = 0;
145
146 bc->debug_id = ++next_shader_id;
147
148 if ((chip_class == R600) &&
149 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
150 bc->ar_handling = AR_HANDLE_RV6XX;
151 bc->r6xx_nop_after_rel_dst = 1;
152 } else {
153 bc->ar_handling = AR_HANDLE_NORMAL;
154 bc->r6xx_nop_after_rel_dst = 0;
155 }
156
157 LIST_INITHEAD(&bc->cf);
158 bc->chip_class = chip_class;
159 bc->family = family;
160 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
161 bc->stack.entry_size = stack_entry_size(family);
162 }
163
164 int r600_bytecode_add_cf(struct r600_bytecode *bc)
165 {
166 struct r600_bytecode_cf *cf = r600_bytecode_cf();
167
168 if (!cf)
169 return -ENOMEM;
170 LIST_ADDTAIL(&cf->list, &bc->cf);
171 if (bc->cf_last) {
172 cf->id = bc->cf_last->id + 2;
173 if (bc->cf_last->eg_alu_extended) {
174 /* take into account extended alu size */
175 cf->id += 2;
176 bc->ndw += 2;
177 }
178 }
179 bc->cf_last = cf;
180 bc->ncf++;
181 bc->ndw += 2;
182 bc->force_add_cf = 0;
183 bc->ar_loaded = 0;
184 return 0;
185 }
186
187 int r600_bytecode_add_output(struct r600_bytecode *bc,
188 const struct r600_bytecode_output *output)
189 {
190 int r;
191
192 if (output->gpr >= bc->ngpr)
193 bc->ngpr = output->gpr + 1;
194
195 if (bc->cf_last && (bc->cf_last->op == output->op ||
196 (bc->cf_last->op == CF_OP_EXPORT &&
197 output->op == CF_OP_EXPORT_DONE)) &&
198 output->type == bc->cf_last->output.type &&
199 output->elem_size == bc->cf_last->output.elem_size &&
200 output->swizzle_x == bc->cf_last->output.swizzle_x &&
201 output->swizzle_y == bc->cf_last->output.swizzle_y &&
202 output->swizzle_z == bc->cf_last->output.swizzle_z &&
203 output->swizzle_w == bc->cf_last->output.swizzle_w &&
204 output->comp_mask == bc->cf_last->output.comp_mask &&
205 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
206
207 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
208 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
209
210 bc->cf_last->op = bc->cf_last->output.op = output->op;
211 bc->cf_last->output.gpr = output->gpr;
212 bc->cf_last->output.array_base = output->array_base;
213 bc->cf_last->output.burst_count += output->burst_count;
214 return 0;
215
216 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
217 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
218
219 bc->cf_last->op = bc->cf_last->output.op = output->op;
220 bc->cf_last->output.burst_count += output->burst_count;
221 return 0;
222 }
223 }
224
225 r = r600_bytecode_add_cf(bc);
226 if (r)
227 return r;
228 bc->cf_last->op = output->op;
229 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
230 bc->cf_last->barrier = 1;
231 return 0;
232 }
233
234 /* alu instructions that can ony exits once per group */
235 static int is_alu_once_inst(struct r600_bytecode_alu *alu)
236 {
237 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
238 }
239
240 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
241 {
242 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
243 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
244 }
245
246 static int is_alu_mova_inst(struct r600_bytecode_alu *alu)
247 {
248 return r600_isa_alu(alu->op)->flags & AF_MOVA;
249 }
250
251 static int alu_uses_rel(struct r600_bytecode_alu *alu)
252 {
253 unsigned num_src = r600_bytecode_get_num_operands(alu);
254 unsigned src;
255
256 if (alu->dst.rel) {
257 return 1;
258 }
259
260 for (src = 0; src < num_src; ++src) {
261 if (alu->src[src].rel) {
262 return 1;
263 }
264 }
265 return 0;
266 }
267
268 static int is_lds_read(int sel)
269 {
270 return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel == EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
271 }
272
273 static int alu_uses_lds(struct r600_bytecode_alu *alu)
274 {
275 unsigned num_src = r600_bytecode_get_num_operands(alu);
276 unsigned src;
277
278 for (src = 0; src < num_src; ++src) {
279 if (is_lds_read(alu->src[src].sel)) {
280 return 1;
281 }
282 }
283 return 0;
284 }
285
286 static int is_alu_64bit_inst(struct r600_bytecode_alu *alu)
287 {
288 const struct alu_op_info *op = r600_isa_alu(alu->op);
289 return (op->flags & AF_64);
290 }
291
292 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
293 {
294 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
295 return !(slots & AF_S);
296 }
297
298 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
299 {
300 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
301 return !(slots & AF_V);
302 }
303
304 /* alu instructions that can execute on any unit */
305 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
306 {
307 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
308 return slots == AF_VS;
309 }
310
311 static int is_nop_inst(struct r600_bytecode_alu *alu)
312 {
313 return alu->op == ALU_OP0_NOP;
314 }
315
316 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
317 struct r600_bytecode_alu *assignment[5])
318 {
319 struct r600_bytecode_alu *alu;
320 unsigned i, chan, trans;
321 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
322
323 for (i = 0; i < max_slots; i++)
324 assignment[i] = NULL;
325
326 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
327 chan = alu->dst.chan;
328 if (max_slots == 4)
329 trans = 0;
330 else if (is_alu_trans_unit_inst(bc, alu))
331 trans = 1;
332 else if (is_alu_vec_unit_inst(bc, alu))
333 trans = 0;
334 else if (assignment[chan])
335 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
336 else
337 trans = 0;
338
339 if (trans) {
340 if (assignment[4]) {
341 assert(0); /* ALU.Trans has already been allocated. */
342 return -1;
343 }
344 assignment[4] = alu;
345 } else {
346 if (assignment[chan]) {
347 assert(0); /* ALU.chan has already been allocated. */
348 return -1;
349 }
350 assignment[chan] = alu;
351 }
352
353 if (alu->last)
354 break;
355 }
356 return 0;
357 }
358
359 struct alu_bank_swizzle {
360 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
361 int hw_cfile_addr[4];
362 int hw_cfile_elem[4];
363 };
364
365 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
366 [SQ_ALU_VEC_012] = { 0, 1, 2 },
367 [SQ_ALU_VEC_021] = { 0, 2, 1 },
368 [SQ_ALU_VEC_120] = { 1, 2, 0 },
369 [SQ_ALU_VEC_102] = { 1, 0, 2 },
370 [SQ_ALU_VEC_201] = { 2, 0, 1 },
371 [SQ_ALU_VEC_210] = { 2, 1, 0 }
372 };
373
374 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
375 [SQ_ALU_SCL_210] = { 2, 1, 0 },
376 [SQ_ALU_SCL_122] = { 1, 2, 2 },
377 [SQ_ALU_SCL_212] = { 2, 1, 2 },
378 [SQ_ALU_SCL_221] = { 2, 2, 1 }
379 };
380
381 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
382 {
383 int i, cycle, component;
384 /* set up gpr use */
385 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
386 for (component = 0; component < NUM_OF_COMPONENTS; component++)
387 bs->hw_gpr[cycle][component] = -1;
388 for (i = 0; i < 4; i++)
389 bs->hw_cfile_addr[i] = -1;
390 for (i = 0; i < 4; i++)
391 bs->hw_cfile_elem[i] = -1;
392 }
393
394 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
395 {
396 if (bs->hw_gpr[cycle][chan] == -1)
397 bs->hw_gpr[cycle][chan] = sel;
398 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
399 /* Another scalar operation has already used the GPR read port for the channel. */
400 return -1;
401 }
402 return 0;
403 }
404
405 static int reserve_cfile(const struct r600_bytecode *bc,
406 struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
407 {
408 int res, num_res = 4;
409 if (bc->chip_class >= R700) {
410 num_res = 2;
411 chan /= 2;
412 }
413 for (res = 0; res < num_res; ++res) {
414 if (bs->hw_cfile_addr[res] == -1) {
415 bs->hw_cfile_addr[res] = sel;
416 bs->hw_cfile_elem[res] = chan;
417 return 0;
418 } else if (bs->hw_cfile_addr[res] == sel &&
419 bs->hw_cfile_elem[res] == chan)
420 return 0; /* Read for this scalar element already reserved, nothing to do here. */
421 }
422 /* All cfile read ports are used, cannot reference vector element. */
423 return -1;
424 }
425
426 static int is_gpr(unsigned sel)
427 {
428 return (sel <= 127);
429 }
430
431 /* CB constants start at 512, and get translated to a kcache index when ALU
432 * clauses are constructed. Note that we handle kcache constants the same way
433 * as (the now gone) cfile constants, is that really required? */
434 static int is_cfile(unsigned sel)
435 {
436 return (sel > 255 && sel < 512) ||
437 (sel > 511 && sel < 4607) || /* Kcache before translation. */
438 (sel > 127 && sel < 192); /* Kcache after translation. */
439 }
440
441 static int is_const(int sel)
442 {
443 return is_cfile(sel) ||
444 (sel >= V_SQ_ALU_SRC_0 &&
445 sel <= V_SQ_ALU_SRC_LITERAL);
446 }
447
448 static int check_vector(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
449 struct alu_bank_swizzle *bs, int bank_swizzle)
450 {
451 int r, src, num_src, sel, elem, cycle;
452
453 num_src = r600_bytecode_get_num_operands(alu);
454 for (src = 0; src < num_src; src++) {
455 sel = alu->src[src].sel;
456 elem = alu->src[src].chan;
457 if (is_gpr(sel)) {
458 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
459 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
460 /* Nothing to do; special-case optimization,
461 * second source uses first source’s reservation. */
462 continue;
463 else {
464 r = reserve_gpr(bs, sel, elem, cycle);
465 if (r)
466 return r;
467 }
468 } else if (is_cfile(sel)) {
469 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
470 if (r)
471 return r;
472 }
473 /* No restrictions on PV, PS, literal or special constants. */
474 }
475 return 0;
476 }
477
478 static int check_scalar(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
479 struct alu_bank_swizzle *bs, int bank_swizzle)
480 {
481 int r, src, num_src, const_count, sel, elem, cycle;
482
483 num_src = r600_bytecode_get_num_operands(alu);
484 for (const_count = 0, src = 0; src < num_src; ++src) {
485 sel = alu->src[src].sel;
486 elem = alu->src[src].chan;
487 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
488 if (const_count >= 2)
489 /* More than two references to a constant in
490 * transcendental operation. */
491 return -1;
492 else
493 const_count++;
494 }
495 if (is_cfile(sel)) {
496 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
497 if (r)
498 return r;
499 }
500 }
501 for (src = 0; src < num_src; ++src) {
502 sel = alu->src[src].sel;
503 elem = alu->src[src].chan;
504 if (is_gpr(sel)) {
505 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
506 if (cycle < const_count)
507 /* Cycle for GPR load conflicts with
508 * constant load in transcendental operation. */
509 return -1;
510 r = reserve_gpr(bs, sel, elem, cycle);
511 if (r)
512 return r;
513 }
514 /* PV PS restrictions */
515 if (const_count && (sel == 254 || sel == 255)) {
516 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
517 if (cycle < const_count)
518 return -1;
519 }
520 }
521 return 0;
522 }
523
524 static int check_and_set_bank_swizzle(const struct r600_bytecode *bc,
525 struct r600_bytecode_alu *slots[5])
526 {
527 struct alu_bank_swizzle bs;
528 int bank_swizzle[5];
529 int i, r = 0, forced = 1;
530 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
531 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
532
533 for (i = 0; i < max_slots; i++) {
534 if (slots[i]) {
535 if (slots[i]->bank_swizzle_force) {
536 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
537 } else {
538 forced = 0;
539 }
540 }
541
542 if (i < 4 && slots[i])
543 scalar_only = false;
544 }
545 if (forced)
546 return 0;
547
548 /* Just check every possible combination of bank swizzle.
549 * Not very efficent, but works on the first try in most of the cases. */
550 for (i = 0; i < 4; i++)
551 if (!slots[i] || !slots[i]->bank_swizzle_force)
552 bank_swizzle[i] = SQ_ALU_VEC_012;
553 else
554 bank_swizzle[i] = slots[i]->bank_swizzle;
555
556 bank_swizzle[4] = SQ_ALU_SCL_210;
557 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
558
559 init_bank_swizzle(&bs);
560 if (scalar_only == false) {
561 for (i = 0; i < 4; i++) {
562 if (slots[i]) {
563 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
564 if (r)
565 break;
566 }
567 }
568 } else
569 r = 0;
570
571 if (!r && max_slots == 5 && slots[4]) {
572 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
573 }
574 if (!r) {
575 for (i = 0; i < max_slots; i++) {
576 if (slots[i])
577 slots[i]->bank_swizzle = bank_swizzle[i];
578 }
579 return 0;
580 }
581
582 if (scalar_only) {
583 bank_swizzle[4]++;
584 } else {
585 for (i = 0; i < max_slots; i++) {
586 if (!slots[i] || !slots[i]->bank_swizzle_force) {
587 bank_swizzle[i]++;
588 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
589 break;
590 else if (i < max_slots - 1)
591 bank_swizzle[i] = SQ_ALU_VEC_012;
592 else
593 return -1;
594 }
595 }
596 }
597 }
598
599 /* Couldn't find a working swizzle. */
600 return -1;
601 }
602
603 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
604 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
605 {
606 struct r600_bytecode_alu *prev[5];
607 int gpr[5], chan[5];
608 int i, j, r, src, num_src;
609 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
610
611 r = assign_alu_units(bc, alu_prev, prev);
612 if (r)
613 return r;
614
615 for (i = 0; i < max_slots; ++i) {
616 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
617
618 if (is_alu_64bit_inst(prev[i])) {
619 gpr[i] = -1;
620 continue;
621 }
622
623 gpr[i] = prev[i]->dst.sel;
624 /* cube writes more than PV.X */
625 if (is_alu_reduction_inst(bc, prev[i]))
626 chan[i] = 0;
627 else
628 chan[i] = prev[i]->dst.chan;
629 } else
630 gpr[i] = -1;
631 }
632
633 for (i = 0; i < max_slots; ++i) {
634 struct r600_bytecode_alu *alu = slots[i];
635 if (!alu)
636 continue;
637
638 if (is_alu_64bit_inst(alu))
639 continue;
640 num_src = r600_bytecode_get_num_operands(alu);
641 for (src = 0; src < num_src; ++src) {
642 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
643 continue;
644
645 if (bc->chip_class < CAYMAN) {
646 if (alu->src[src].sel == gpr[4] &&
647 alu->src[src].chan == chan[4] &&
648 alu_prev->pred_sel == alu->pred_sel) {
649 alu->src[src].sel = V_SQ_ALU_SRC_PS;
650 alu->src[src].chan = 0;
651 continue;
652 }
653 }
654
655 for (j = 0; j < 4; ++j) {
656 if (alu->src[src].sel == gpr[j] &&
657 alu->src[src].chan == j &&
658 alu_prev->pred_sel == alu->pred_sel) {
659 alu->src[src].sel = V_SQ_ALU_SRC_PV;
660 alu->src[src].chan = chan[j];
661 break;
662 }
663 }
664 }
665 }
666
667 return 0;
668 }
669
670 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
671 {
672 switch(value) {
673 case 0:
674 *sel = V_SQ_ALU_SRC_0;
675 break;
676 case 1:
677 *sel = V_SQ_ALU_SRC_1_INT;
678 break;
679 case -1:
680 *sel = V_SQ_ALU_SRC_M_1_INT;
681 break;
682 case 0x3F800000: /* 1.0f */
683 *sel = V_SQ_ALU_SRC_1;
684 break;
685 case 0x3F000000: /* 0.5f */
686 *sel = V_SQ_ALU_SRC_0_5;
687 break;
688 case 0xBF800000: /* -1.0f */
689 *sel = V_SQ_ALU_SRC_1;
690 *neg ^= !abs;
691 break;
692 case 0xBF000000: /* -0.5f */
693 *sel = V_SQ_ALU_SRC_0_5;
694 *neg ^= !abs;
695 break;
696 default:
697 *sel = V_SQ_ALU_SRC_LITERAL;
698 break;
699 }
700 }
701
702 /* compute how many literal are needed */
703 static int r600_bytecode_alu_nliterals(struct r600_bytecode_alu *alu,
704 uint32_t literal[4], unsigned *nliteral)
705 {
706 unsigned num_src = r600_bytecode_get_num_operands(alu);
707 unsigned i, j;
708
709 for (i = 0; i < num_src; ++i) {
710 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
711 uint32_t value = alu->src[i].value;
712 unsigned found = 0;
713 for (j = 0; j < *nliteral; ++j) {
714 if (literal[j] == value) {
715 found = 1;
716 break;
717 }
718 }
719 if (!found) {
720 if (*nliteral >= 4)
721 return -EINVAL;
722 literal[(*nliteral)++] = value;
723 }
724 }
725 }
726 return 0;
727 }
728
729 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu *alu,
730 uint32_t literal[4], unsigned nliteral)
731 {
732 unsigned num_src = r600_bytecode_get_num_operands(alu);
733 unsigned i, j;
734
735 for (i = 0; i < num_src; ++i) {
736 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
737 uint32_t value = alu->src[i].value;
738 for (j = 0; j < nliteral; ++j) {
739 if (literal[j] == value) {
740 alu->src[i].chan = j;
741 break;
742 }
743 }
744 }
745 }
746 }
747
748 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
749 struct r600_bytecode_alu *alu_prev)
750 {
751 struct r600_bytecode_alu *prev[5];
752 struct r600_bytecode_alu *result[5] = { NULL };
753
754 uint32_t literal[4], prev_literal[4];
755 unsigned nliteral = 0, prev_nliteral = 0;
756
757 int i, j, r, src, num_src;
758 int num_once_inst = 0;
759 int have_mova = 0, have_rel = 0;
760 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
761
762 r = assign_alu_units(bc, alu_prev, prev);
763 if (r)
764 return r;
765
766 for (i = 0; i < max_slots; ++i) {
767 if (prev[i]) {
768 if (prev[i]->pred_sel)
769 return 0;
770 if (is_alu_once_inst(prev[i]))
771 return 0;
772 }
773 if (slots[i]) {
774 if (slots[i]->pred_sel)
775 return 0;
776 if (is_alu_once_inst(slots[i]))
777 return 0;
778 }
779 }
780
781 for (i = 0; i < max_slots; ++i) {
782 struct r600_bytecode_alu *alu;
783
784 if (num_once_inst > 0)
785 return 0;
786
787 /* check number of literals */
788 if (prev[i]) {
789 if (r600_bytecode_alu_nliterals(prev[i], literal, &nliteral))
790 return 0;
791 if (r600_bytecode_alu_nliterals(prev[i], prev_literal, &prev_nliteral))
792 return 0;
793 if (is_alu_mova_inst(prev[i])) {
794 if (have_rel)
795 return 0;
796 have_mova = 1;
797 }
798
799 if (alu_uses_rel(prev[i])) {
800 if (have_mova) {
801 return 0;
802 }
803 have_rel = 1;
804 }
805 if (alu_uses_lds(prev[i]))
806 return 0;
807
808 num_once_inst += is_alu_once_inst(prev[i]);
809 }
810 if (slots[i] && r600_bytecode_alu_nliterals(slots[i], literal, &nliteral))
811 return 0;
812
813 /* Let's check used slots. */
814 if (prev[i] && !slots[i]) {
815 result[i] = prev[i];
816 continue;
817 } else if (prev[i] && slots[i]) {
818 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
819 /* Trans unit is still free try to use it. */
820 if (is_alu_any_unit_inst(bc, slots[i]) && !alu_uses_lds(slots[i])) {
821 result[i] = prev[i];
822 result[4] = slots[i];
823 } else if (is_alu_any_unit_inst(bc, prev[i])) {
824 if (slots[i]->dst.sel == prev[i]->dst.sel &&
825 alu_writes(slots[i]) &&
826 alu_writes(prev[i]))
827 return 0;
828
829 result[i] = slots[i];
830 result[4] = prev[i];
831 } else
832 return 0;
833 } else
834 return 0;
835 } else if(!slots[i]) {
836 continue;
837 } else {
838 if (max_slots == 5 && slots[i] && prev[4] &&
839 slots[i]->dst.sel == prev[4]->dst.sel &&
840 slots[i]->dst.chan == prev[4]->dst.chan &&
841 alu_writes(slots[i]) &&
842 alu_writes(prev[4]))
843 return 0;
844
845 result[i] = slots[i];
846 }
847
848 alu = slots[i];
849 num_once_inst += is_alu_once_inst(alu);
850
851 /* don't reschedule NOPs */
852 if (is_nop_inst(alu))
853 return 0;
854
855 if (is_alu_mova_inst(alu)) {
856 if (have_rel) {
857 return 0;
858 }
859 have_mova = 1;
860 }
861
862 if (alu_uses_rel(alu)) {
863 if (have_mova) {
864 return 0;
865 }
866 have_rel = 1;
867 }
868
869 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
870 alu->op == ALU_OP0_SET_CF_IDX1)
871 return 0; /* data hazard with MOVA */
872
873 /* Let's check source gprs */
874 num_src = r600_bytecode_get_num_operands(alu);
875 for (src = 0; src < num_src; ++src) {
876
877 /* Constants don't matter. */
878 if (!is_gpr(alu->src[src].sel))
879 continue;
880
881 for (j = 0; j < max_slots; ++j) {
882 if (!prev[j] || !alu_writes(prev[j]))
883 continue;
884
885 /* If it's relative then we can't determin which gpr is really used. */
886 if (prev[j]->dst.chan == alu->src[src].chan &&
887 (prev[j]->dst.sel == alu->src[src].sel ||
888 prev[j]->dst.rel || alu->src[src].rel))
889 return 0;
890 }
891 }
892 }
893
894 /* more than one PRED_ or KILL_ ? */
895 if (num_once_inst > 1)
896 return 0;
897
898 /* check if the result can still be swizzlet */
899 r = check_and_set_bank_swizzle(bc, result);
900 if (r)
901 return 0;
902
903 /* looks like everything worked out right, apply the changes */
904
905 /* undo adding previus literals */
906 bc->cf_last->ndw -= align(prev_nliteral, 2);
907
908 /* sort instructions */
909 for (i = 0; i < max_slots; ++i) {
910 slots[i] = result[i];
911 if (result[i]) {
912 LIST_DEL(&result[i]->list);
913 result[i]->last = 0;
914 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
915 }
916 }
917
918 /* determine new last instruction */
919 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
920
921 /* determine new first instruction */
922 for (i = 0; i < max_slots; ++i) {
923 if (result[i]) {
924 bc->cf_last->curr_bs_head = result[i];
925 break;
926 }
927 }
928
929 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
930 bc->cf_last->prev2_bs_head = NULL;
931
932 return 0;
933 }
934
935 /* we'll keep kcache sets sorted by bank & addr */
936 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
937 struct r600_bytecode_kcache *kcache,
938 unsigned bank, unsigned line, unsigned index_mode)
939 {
940 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
941
942 for (i = 0; i < kcache_banks; i++) {
943 if (kcache[i].mode) {
944 int d;
945
946 if (kcache[i].bank < bank)
947 continue;
948
949 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
950 kcache[i].bank > bank) {
951 /* try to insert new line */
952 if (kcache[kcache_banks-1].mode) {
953 /* all sets are in use */
954 return -ENOMEM;
955 }
956
957 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
958 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
959 kcache[i].bank = bank;
960 kcache[i].addr = line;
961 kcache[i].index_mode = index_mode;
962 return 0;
963 }
964
965 d = line - kcache[i].addr;
966
967 if (d == -1) {
968 kcache[i].addr--;
969 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
970 /* we are prepending the line to the current set,
971 * discarding the existing second line,
972 * so we'll have to insert line+2 after it */
973 line += 2;
974 continue;
975 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
976 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
977 return 0;
978 } else {
979 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
980 return -ENOMEM;
981 }
982 } else if (d == 1) {
983 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
984 return 0;
985 } else if (d == 0)
986 return 0;
987 } else { /* free kcache set - use it */
988 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
989 kcache[i].bank = bank;
990 kcache[i].addr = line;
991 kcache[i].index_mode = index_mode;
992 return 0;
993 }
994 }
995 return -ENOMEM;
996 }
997
998 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
999 struct r600_bytecode_kcache *kcache,
1000 struct r600_bytecode_alu *alu)
1001 {
1002 int i, r;
1003
1004 for (i = 0; i < 3; i++) {
1005 unsigned bank, line, sel = alu->src[i].sel, index_mode;
1006
1007 if (sel < 512)
1008 continue;
1009
1010 bank = alu->src[i].kc_bank;
1011 line = (sel-512)>>4;
1012 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1013
1014 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
1015 return r;
1016 }
1017 return 0;
1018 }
1019
1020 static int r600_bytecode_assign_kcache_banks(
1021 struct r600_bytecode_alu *alu,
1022 struct r600_bytecode_kcache * kcache)
1023 {
1024 int i, j;
1025
1026 /* Alter the src operands to refer to the kcache. */
1027 for (i = 0; i < 3; ++i) {
1028 static const unsigned int base[] = {128, 160, 256, 288};
1029 unsigned int line, sel = alu->src[i].sel, found = 0;
1030
1031 if (sel < 512)
1032 continue;
1033
1034 sel -= 512;
1035 line = sel>>4;
1036
1037 for (j = 0; j < 4 && !found; ++j) {
1038 switch (kcache[j].mode) {
1039 case V_SQ_CF_KCACHE_NOP:
1040 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1041 R600_ERR("unexpected kcache line mode\n");
1042 return -ENOMEM;
1043 default:
1044 if (kcache[j].bank == alu->src[i].kc_bank &&
1045 kcache[j].addr <= line &&
1046 line < kcache[j].addr + kcache[j].mode) {
1047 alu->src[i].sel = sel - (kcache[j].addr<<4);
1048 alu->src[i].sel += base[j];
1049 found=1;
1050 }
1051 }
1052 }
1053 }
1054 return 0;
1055 }
1056
1057 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1058 struct r600_bytecode_alu *alu,
1059 unsigned type)
1060 {
1061 struct r600_bytecode_kcache kcache_sets[4];
1062 struct r600_bytecode_kcache *kcache = kcache_sets;
1063 int r;
1064
1065 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1066
1067 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1068 /* can't alloc, need to start new clause */
1069 if ((r = r600_bytecode_add_cf(bc))) {
1070 return r;
1071 }
1072 bc->cf_last->op = type;
1073
1074 /* retry with the new clause */
1075 kcache = bc->cf_last->kcache;
1076 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1077 /* can't alloc again- should never happen */
1078 return r;
1079 }
1080 } else {
1081 /* update kcache sets */
1082 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1083 }
1084
1085 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1086 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1087 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1088 if (bc->chip_class < EVERGREEN)
1089 return -ENOMEM;
1090 bc->cf_last->eg_alu_extended = 1;
1091 }
1092
1093 return 0;
1094 }
1095
1096 static int insert_nop_r6xx(struct r600_bytecode *bc)
1097 {
1098 struct r600_bytecode_alu alu;
1099 int r, i;
1100
1101 for (i = 0; i < 4; i++) {
1102 memset(&alu, 0, sizeof(alu));
1103 alu.op = ALU_OP0_NOP;
1104 alu.src[0].chan = i;
1105 alu.dst.chan = i;
1106 alu.last = (i == 3);
1107 r = r600_bytecode_add_alu(bc, &alu);
1108 if (r)
1109 return r;
1110 }
1111 return 0;
1112 }
1113
1114 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1115 static int load_ar_r6xx(struct r600_bytecode *bc)
1116 {
1117 struct r600_bytecode_alu alu;
1118 int r;
1119
1120 if (bc->ar_loaded)
1121 return 0;
1122
1123 /* hack to avoid making MOVA the last instruction in the clause */
1124 if ((bc->cf_last->ndw>>1) >= 110)
1125 bc->force_add_cf = 1;
1126
1127 memset(&alu, 0, sizeof(alu));
1128 alu.op = ALU_OP1_MOVA_GPR_INT;
1129 alu.src[0].sel = bc->ar_reg;
1130 alu.src[0].chan = bc->ar_chan;
1131 alu.last = 1;
1132 alu.index_mode = INDEX_MODE_LOOP;
1133 r = r600_bytecode_add_alu(bc, &alu);
1134 if (r)
1135 return r;
1136
1137 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1138 bc->ar_loaded = 1;
1139 return 0;
1140 }
1141
1142 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1143 static int load_ar(struct r600_bytecode *bc)
1144 {
1145 struct r600_bytecode_alu alu;
1146 int r;
1147
1148 if (bc->ar_handling)
1149 return load_ar_r6xx(bc);
1150
1151 if (bc->ar_loaded)
1152 return 0;
1153
1154 /* hack to avoid making MOVA the last instruction in the clause */
1155 if ((bc->cf_last->ndw>>1) >= 110)
1156 bc->force_add_cf = 1;
1157
1158 memset(&alu, 0, sizeof(alu));
1159 alu.op = ALU_OP1_MOVA_INT;
1160 alu.src[0].sel = bc->ar_reg;
1161 alu.src[0].chan = bc->ar_chan;
1162 alu.last = 1;
1163 r = r600_bytecode_add_alu(bc, &alu);
1164 if (r)
1165 return r;
1166
1167 bc->cf_last->r6xx_uses_waterfall = 1;
1168 bc->ar_loaded = 1;
1169 return 0;
1170 }
1171
1172 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1173 const struct r600_bytecode_alu *alu, unsigned type)
1174 {
1175 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1176 struct r600_bytecode_alu *lalu;
1177 int i, r;
1178
1179 if (!nalu)
1180 return -ENOMEM;
1181 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1182
1183 if (alu->is_op3) {
1184 /* will fail later since alu does not support it. */
1185 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1186 }
1187
1188 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1189 /* check if we could add it anyway */
1190 if (bc->cf_last->op == CF_OP_ALU &&
1191 type == CF_OP_ALU_PUSH_BEFORE) {
1192 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1193 if (lalu->execute_mask) {
1194 bc->force_add_cf = 1;
1195 break;
1196 }
1197 }
1198 } else
1199 bc->force_add_cf = 1;
1200 }
1201
1202 /* cf can contains only alu or only vtx or only tex */
1203 if (bc->cf_last == NULL || bc->force_add_cf) {
1204 r = r600_bytecode_add_cf(bc);
1205 if (r) {
1206 free(nalu);
1207 return r;
1208 }
1209 }
1210 bc->cf_last->op = type;
1211
1212 /* Load index register if required */
1213 if (bc->chip_class >= EVERGREEN) {
1214 for (i = 0; i < 3; i++)
1215 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1216 egcm_load_index_reg(bc, 0, true);
1217 }
1218
1219 /* Check AR usage and load it if required */
1220 for (i = 0; i < 3; i++)
1221 if (nalu->src[i].rel && !bc->ar_loaded)
1222 load_ar(bc);
1223
1224 if (nalu->dst.rel && !bc->ar_loaded)
1225 load_ar(bc);
1226
1227 /* Setup the kcache for this ALU instruction. This will start a new
1228 * ALU clause if needed. */
1229 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1230 free(nalu);
1231 return r;
1232 }
1233
1234 if (!bc->cf_last->curr_bs_head) {
1235 bc->cf_last->curr_bs_head = nalu;
1236 }
1237 /* number of gpr == the last gpr used in any alu */
1238 for (i = 0; i < 3; i++) {
1239 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1240 bc->ngpr = nalu->src[i].sel + 1;
1241 }
1242 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1243 r600_bytecode_special_constants(nalu->src[i].value,
1244 &nalu->src[i].sel, &nalu->src[i].neg, nalu->src[i].abs);
1245 }
1246 if (nalu->dst.sel >= bc->ngpr) {
1247 bc->ngpr = nalu->dst.sel + 1;
1248 }
1249 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1250 /* each alu use 2 dwords */
1251 bc->cf_last->ndw += 2;
1252 bc->ndw += 2;
1253
1254 /* process cur ALU instructions for bank swizzle */
1255 if (nalu->last) {
1256 uint32_t literal[4];
1257 unsigned nliteral;
1258 struct r600_bytecode_alu *slots[5];
1259 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1260 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1261 if (r)
1262 return r;
1263
1264 if (bc->cf_last->prev_bs_head) {
1265 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1266 if (r)
1267 return r;
1268 }
1269
1270 if (bc->cf_last->prev_bs_head) {
1271 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1272 if (r)
1273 return r;
1274 }
1275
1276 r = check_and_set_bank_swizzle(bc, slots);
1277 if (r)
1278 return r;
1279
1280 for (i = 0, nliteral = 0; i < max_slots; i++) {
1281 if (slots[i]) {
1282 r = r600_bytecode_alu_nliterals(slots[i], literal, &nliteral);
1283 if (r)
1284 return r;
1285 }
1286 }
1287 bc->cf_last->ndw += align(nliteral, 2);
1288
1289 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1290 * worst case */
1291 if ((bc->cf_last->ndw >> 1) >= 120) {
1292 bc->force_add_cf = 1;
1293 }
1294
1295 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1296 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1297 bc->cf_last->curr_bs_head = NULL;
1298 }
1299
1300 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1301 insert_nop_r6xx(bc);
1302
1303 return 0;
1304 }
1305
1306 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1307 {
1308 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1309 }
1310
1311 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1312 {
1313 switch (bc->chip_class) {
1314 case R600:
1315 return 8;
1316
1317 case R700:
1318 case EVERGREEN:
1319 case CAYMAN:
1320 return 16;
1321
1322 default:
1323 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1324 return 8;
1325 }
1326 }
1327
1328 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1329 {
1330 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1331 bc->cf_last->op != CF_OP_GDS &&
1332 (bc->chip_class == CAYMAN ||
1333 bc->cf_last->op != CF_OP_TEX));
1334 }
1335
1336 static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx,
1337 bool use_tc)
1338 {
1339 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1340 int r;
1341
1342 if (!nvtx)
1343 return -ENOMEM;
1344 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1345
1346 /* Load index register if required */
1347 if (bc->chip_class >= EVERGREEN) {
1348 if (vtx->buffer_index_mode)
1349 egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false);
1350 }
1351
1352 /* cf can contains only alu or only vtx or only tex */
1353 if (bc->cf_last == NULL ||
1354 last_inst_was_not_vtx_fetch(bc) ||
1355 bc->force_add_cf) {
1356 r = r600_bytecode_add_cf(bc);
1357 if (r) {
1358 free(nvtx);
1359 return r;
1360 }
1361 switch (bc->chip_class) {
1362 case R600:
1363 case R700:
1364 bc->cf_last->op = CF_OP_VTX;
1365 break;
1366 case EVERGREEN:
1367 if (use_tc)
1368 bc->cf_last->op = CF_OP_TEX;
1369 else
1370 bc->cf_last->op = CF_OP_VTX;
1371 break;
1372 case CAYMAN:
1373 bc->cf_last->op = CF_OP_TEX;
1374 break;
1375 default:
1376 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1377 free(nvtx);
1378 return -EINVAL;
1379 }
1380 }
1381 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1382 /* each fetch use 4 dwords */
1383 bc->cf_last->ndw += 4;
1384 bc->ndw += 4;
1385 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1386 bc->force_add_cf = 1;
1387
1388 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1389 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1390
1391 return 0;
1392 }
1393
1394 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1395 {
1396 return r600_bytecode_add_vtx_internal(bc, vtx, false);
1397 }
1398
1399 int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1400 {
1401 return r600_bytecode_add_vtx_internal(bc, vtx, true);
1402 }
1403
1404 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1405 {
1406 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1407 int r;
1408
1409 if (!ntex)
1410 return -ENOMEM;
1411 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1412
1413 /* Load index register if required */
1414 if (bc->chip_class >= EVERGREEN) {
1415 if (tex->sampler_index_mode || tex->resource_index_mode)
1416 egcm_load_index_reg(bc, 1, false);
1417 }
1418
1419 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1420 if (bc->cf_last != NULL &&
1421 bc->cf_last->op == CF_OP_TEX) {
1422 struct r600_bytecode_tex *ttex;
1423 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1424 if (ttex->dst_gpr == ntex->src_gpr) {
1425 bc->force_add_cf = 1;
1426 break;
1427 }
1428 }
1429 /* slight hack to make gradients always go into same cf */
1430 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1431 bc->force_add_cf = 1;
1432 }
1433
1434 /* cf can contains only alu or only vtx or only tex */
1435 if (bc->cf_last == NULL ||
1436 bc->cf_last->op != CF_OP_TEX ||
1437 bc->force_add_cf) {
1438 r = r600_bytecode_add_cf(bc);
1439 if (r) {
1440 free(ntex);
1441 return r;
1442 }
1443 bc->cf_last->op = CF_OP_TEX;
1444 }
1445 if (ntex->src_gpr >= bc->ngpr) {
1446 bc->ngpr = ntex->src_gpr + 1;
1447 }
1448 if (ntex->dst_gpr >= bc->ngpr) {
1449 bc->ngpr = ntex->dst_gpr + 1;
1450 }
1451 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1452 /* each texture fetch use 4 dwords */
1453 bc->cf_last->ndw += 4;
1454 bc->ndw += 4;
1455 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1456 bc->force_add_cf = 1;
1457 return 0;
1458 }
1459
1460 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1461 {
1462 struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1463 int r;
1464
1465 if (ngds == NULL)
1466 return -ENOMEM;
1467 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1468
1469 if (bc->chip_class >= EVERGREEN) {
1470 if (gds->uav_index_mode)
1471 egcm_load_index_reg(bc, gds->uav_index_mode - 1, false);
1472 }
1473
1474 if (bc->cf_last == NULL ||
1475 bc->cf_last->op != CF_OP_GDS ||
1476 bc->force_add_cf) {
1477 r = r600_bytecode_add_cf(bc);
1478 if (r) {
1479 free(ngds);
1480 return r;
1481 }
1482 bc->cf_last->op = CF_OP_GDS;
1483 }
1484
1485 LIST_ADDTAIL(&ngds->list, &bc->cf_last->gds);
1486 bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1487 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1488 bc->force_add_cf = 1;
1489 return 0;
1490 }
1491
1492 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1493 {
1494 int r;
1495 r = r600_bytecode_add_cf(bc);
1496 if (r)
1497 return r;
1498
1499 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1500 bc->cf_last->op = op;
1501 return 0;
1502 }
1503
1504 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1505 {
1506 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1507 }
1508
1509 /* common to all 3 families */
1510 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1511 {
1512 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1513 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1514 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1515 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1516 if (bc->chip_class < CAYMAN)
1517 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1518 id++;
1519 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1520 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1521 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1522 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1523 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1524 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1525 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1526 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1527 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1528 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1529 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1530 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1531 if (bc->chip_class >= EVERGREEN)
1532 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1533 if (bc->chip_class < CAYMAN)
1534 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1535 id++;
1536 bc->bytecode[id++] = 0;
1537 return 0;
1538 }
1539
1540 /* common to all 3 families */
1541 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1542 {
1543 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1544 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1545 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1546 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1547 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1548 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1549 if (bc->chip_class >= EVERGREEN)
1550 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1551 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1552 id++;
1553 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1554 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1555 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1556 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1557 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1558 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1559 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1560 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1561 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1562 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1563 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1564 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1565 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1566 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1567 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1568 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1569 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1570 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1571 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1572 bc->bytecode[id++] = 0;
1573 return 0;
1574 }
1575
1576 /* r600 only, r700/eg bits in r700_asm.c */
1577 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1578 {
1579 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1580
1581 /* don't replace gpr by pv or ps for destination register */
1582 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1583 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1584 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1585 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1586 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1587 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1588 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1589 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1590 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1591 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1592 S_SQ_ALU_WORD0_LAST(alu->last);
1593
1594 if (alu->is_op3) {
1595 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1596 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1597 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1598 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1599 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1600 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1601 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1602 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1603 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1604 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1605 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1606 } else {
1607 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1608 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1609 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1610 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1611 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1612 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1613 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1614 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1615 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1616 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1617 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1618 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1619 }
1620 return 0;
1621 }
1622
1623 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1624 {
1625 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1626 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1627 S_SQ_CF_WORD1_BARRIER(1) |
1628 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1629 }
1630
1631 /* common for r600/r700 - eg in eg_asm.c */
1632 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1633 {
1634 unsigned id = cf->id;
1635 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1636 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1637
1638
1639 if (cf->op == CF_NATIVE) {
1640 bc->bytecode[id++] = cf->isa[0];
1641 bc->bytecode[id++] = cf->isa[1];
1642 } else if (cfop->flags & CF_ALU) {
1643 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1644 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1645 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1646 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1647
1648 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1649 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1650 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1651 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1652 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1653 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1654 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1655 } else if (cfop->flags & CF_FETCH) {
1656 if (bc->chip_class == R700)
1657 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1658 else
1659 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1660 } else if (cfop->flags & CF_EXP) {
1661 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1662 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1663 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1664 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1665 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1666 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1667 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1668 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1669 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1670 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1671 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1672 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1673 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1674 } else if (cfop->flags & CF_MEM) {
1675 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1676 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1677 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1678 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1679 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1680 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1681 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1682 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1683 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1684 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1685 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1686 } else {
1687 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1688 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1689 S_SQ_CF_WORD1_BARRIER(1) |
1690 S_SQ_CF_WORD1_COND(cf->cond) |
1691 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1692 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1693 }
1694 return 0;
1695 }
1696
1697 int r600_bytecode_build(struct r600_bytecode *bc)
1698 {
1699 struct r600_bytecode_cf *cf;
1700 struct r600_bytecode_alu *alu;
1701 struct r600_bytecode_vtx *vtx;
1702 struct r600_bytecode_tex *tex;
1703 struct r600_bytecode_gds *gds;
1704 uint32_t literal[4];
1705 unsigned nliteral;
1706 unsigned addr;
1707 int i, r;
1708
1709 if (!bc->nstack) { // If not 0, Stack_size already provided by llvm
1710 if (bc->stack.max_entries)
1711 bc->nstack = bc->stack.max_entries;
1712 else if (bc->type == PIPE_SHADER_VERTEX ||
1713 bc->type == PIPE_SHADER_TESS_EVAL ||
1714 bc->type == PIPE_SHADER_TESS_CTRL)
1715 bc->nstack = 1;
1716 }
1717
1718 /* first path compute addr of each CF block */
1719 /* addr start after all the CF instructions */
1720 addr = bc->cf_last->id + 2;
1721 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1722 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1723 addr += 3;
1724 addr &= 0xFFFFFFFCUL;
1725 }
1726 cf->addr = addr;
1727 addr += cf->ndw;
1728 bc->ndw = cf->addr + cf->ndw;
1729 }
1730 free(bc->bytecode);
1731 bc->bytecode = calloc(4, bc->ndw);
1732 if (bc->bytecode == NULL)
1733 return -ENOMEM;
1734 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1735 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1736 addr = cf->addr;
1737 if (bc->chip_class >= EVERGREEN)
1738 r = eg_bytecode_cf_build(bc, cf);
1739 else
1740 r = r600_bytecode_cf_build(bc, cf);
1741 if (r)
1742 return r;
1743 if (cfop->flags & CF_ALU) {
1744 nliteral = 0;
1745 memset(literal, 0, sizeof(literal));
1746 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1747 r = r600_bytecode_alu_nliterals(alu, literal, &nliteral);
1748 if (r)
1749 return r;
1750 r600_bytecode_alu_adjust_literals(alu, literal, nliteral);
1751 r600_bytecode_assign_kcache_banks(alu, cf->kcache);
1752
1753 switch(bc->chip_class) {
1754 case R600:
1755 r = r600_bytecode_alu_build(bc, alu, addr);
1756 break;
1757 case R700:
1758 r = r700_bytecode_alu_build(bc, alu, addr);
1759 break;
1760 case EVERGREEN:
1761 case CAYMAN:
1762 r = eg_bytecode_alu_build(bc, alu, addr);
1763 break;
1764 default:
1765 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1766 return -EINVAL;
1767 }
1768 if (r)
1769 return r;
1770 addr += 2;
1771 if (alu->last) {
1772 for (i = 0; i < align(nliteral, 2); ++i) {
1773 bc->bytecode[addr++] = literal[i];
1774 }
1775 nliteral = 0;
1776 memset(literal, 0, sizeof(literal));
1777 }
1778 }
1779 } else if (cf->op == CF_OP_VTX) {
1780 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1781 r = r600_bytecode_vtx_build(bc, vtx, addr);
1782 if (r)
1783 return r;
1784 addr += 4;
1785 }
1786 } else if (cf->op == CF_OP_GDS) {
1787 assert(bc->chip_class >= EVERGREEN);
1788 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1789 r = eg_bytecode_gds_build(bc, gds, addr);
1790 if (r)
1791 return r;
1792 addr += 4;
1793 }
1794 } else if (cf->op == CF_OP_TEX) {
1795 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1796 assert(bc->chip_class >= EVERGREEN);
1797 r = r600_bytecode_vtx_build(bc, vtx, addr);
1798 if (r)
1799 return r;
1800 addr += 4;
1801 }
1802 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1803 r = r600_bytecode_tex_build(bc, tex, addr);
1804 if (r)
1805 return r;
1806 addr += 4;
1807 }
1808 }
1809 }
1810 return 0;
1811 }
1812
1813 void r600_bytecode_clear(struct r600_bytecode *bc)
1814 {
1815 struct r600_bytecode_cf *cf = NULL, *next_cf;
1816
1817 free(bc->bytecode);
1818 bc->bytecode = NULL;
1819
1820 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1821 struct r600_bytecode_alu *alu = NULL, *next_alu;
1822 struct r600_bytecode_tex *tex = NULL, *next_tex;
1823 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1824 struct r600_bytecode_gds *gds = NULL, *next_gds;
1825
1826 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1827 free(alu);
1828 }
1829
1830 LIST_INITHEAD(&cf->alu);
1831
1832 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1833 free(tex);
1834 }
1835
1836 LIST_INITHEAD(&cf->tex);
1837
1838 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1839 free(vtx);
1840 }
1841
1842 LIST_INITHEAD(&cf->vtx);
1843
1844 LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1845 free(gds);
1846 }
1847
1848 LIST_INITHEAD(&cf->gds);
1849
1850 free(cf);
1851 }
1852
1853 LIST_INITHEAD(&cf->list);
1854 }
1855
1856 static int print_swizzle(unsigned swz)
1857 {
1858 const char * swzchars = "xyzw01?_";
1859 assert(swz<8 && swz != 6);
1860 return fprintf(stderr, "%c", swzchars[swz]);
1861 }
1862
1863 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1864 unsigned need_brackets)
1865 {
1866 int o = 0;
1867 if (rel && index_mode >= 5 && sel < 128)
1868 o += fprintf(stderr, "G");
1869 if (rel || need_brackets) {
1870 o += fprintf(stderr, "[");
1871 }
1872 o += fprintf(stderr, "%d", sel);
1873 if (rel) {
1874 if (index_mode == 0 || index_mode == 6)
1875 o += fprintf(stderr, "+AR");
1876 else if (index_mode == 4)
1877 o += fprintf(stderr, "+AL");
1878 }
1879 if (rel || need_brackets) {
1880 o += fprintf(stderr, "]");
1881 }
1882 return o;
1883 }
1884
1885 static int print_dst(struct r600_bytecode_alu *alu)
1886 {
1887 int o = 0;
1888 unsigned sel = alu->dst.sel;
1889 char reg_char = 'R';
1890 if (sel > 128 - 4) { /* clause temporary gpr */
1891 sel -= 128 - 4;
1892 reg_char = 'T';
1893 }
1894
1895 if (alu_writes(alu)) {
1896 o += fprintf(stderr, "%c", reg_char);
1897 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1898 } else {
1899 o += fprintf(stderr, "__");
1900 }
1901 o += fprintf(stderr, ".");
1902 o += print_swizzle(alu->dst.chan);
1903 return o;
1904 }
1905
1906 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1907 {
1908 int o = 0;
1909 struct r600_bytecode_alu_src *src = &alu->src[idx];
1910 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1911
1912 if (src->neg)
1913 o += fprintf(stderr,"-");
1914 if (src->abs)
1915 o += fprintf(stderr,"|");
1916
1917 if (sel < 128 - 4) {
1918 o += fprintf(stderr, "R");
1919 } else if (sel < 128) {
1920 o += fprintf(stderr, "T");
1921 sel -= 128 - 4;
1922 } else if (sel < 160) {
1923 o += fprintf(stderr, "KC0");
1924 need_brackets = 1;
1925 sel -= 128;
1926 } else if (sel < 192) {
1927 o += fprintf(stderr, "KC1");
1928 need_brackets = 1;
1929 sel -= 160;
1930 } else if (sel >= 512) {
1931 o += fprintf(stderr, "C%d", src->kc_bank);
1932 need_brackets = 1;
1933 sel -= 512;
1934 } else if (sel >= 448) {
1935 o += fprintf(stderr, "Param");
1936 sel -= 448;
1937 need_chan = 0;
1938 } else if (sel >= 288) {
1939 o += fprintf(stderr, "KC3");
1940 need_brackets = 1;
1941 sel -= 288;
1942 } else if (sel >= 256) {
1943 o += fprintf(stderr, "KC2");
1944 need_brackets = 1;
1945 sel -= 256;
1946 } else {
1947 need_sel = 0;
1948 need_chan = 0;
1949 switch (sel) {
1950 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A:
1951 o += fprintf(stderr, "LDS_A[0x%08X]", src->value);
1952 break;
1953 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B:
1954 o += fprintf(stderr, "LDS_B[0x%08X]", src->value);
1955 break;
1956 case EG_V_SQ_ALU_SRC_LDS_OQ_A:
1957 o += fprintf(stderr, "LDS_OQ_A");
1958 need_chan = 1;
1959 break;
1960 case EG_V_SQ_ALU_SRC_LDS_OQ_B:
1961 o += fprintf(stderr, "LDS_OQ_B");
1962 need_chan = 1;
1963 break;
1964 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP:
1965 o += fprintf(stderr, "LDS_OQ_A_POP");
1966 need_chan = 1;
1967 break;
1968 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP:
1969 o += fprintf(stderr, "LDS_OQ_B_POP");
1970 need_chan = 1;
1971 break;
1972 case V_SQ_ALU_SRC_PS:
1973 o += fprintf(stderr, "PS");
1974 break;
1975 case V_SQ_ALU_SRC_PV:
1976 o += fprintf(stderr, "PV");
1977 need_chan = 1;
1978 break;
1979 case V_SQ_ALU_SRC_LITERAL:
1980 o += fprintf(stderr, "[0x%08X %f]", src->value, u_bitcast_u2f(src->value));
1981 break;
1982 case V_SQ_ALU_SRC_0_5:
1983 o += fprintf(stderr, "0.5");
1984 break;
1985 case V_SQ_ALU_SRC_M_1_INT:
1986 o += fprintf(stderr, "-1");
1987 break;
1988 case V_SQ_ALU_SRC_1_INT:
1989 o += fprintf(stderr, "1");
1990 break;
1991 case V_SQ_ALU_SRC_1:
1992 o += fprintf(stderr, "1.0");
1993 break;
1994 case V_SQ_ALU_SRC_0:
1995 o += fprintf(stderr, "0");
1996 break;
1997 default:
1998 o += fprintf(stderr, "??IMM_%d", sel);
1999 break;
2000 }
2001 }
2002
2003 if (need_sel)
2004 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
2005
2006 if (need_chan) {
2007 o += fprintf(stderr, ".");
2008 o += print_swizzle(src->chan);
2009 }
2010
2011 if (src->abs)
2012 o += fprintf(stderr,"|");
2013
2014 return o;
2015 }
2016
2017 static int print_indent(int p, int c)
2018 {
2019 int o = 0;
2020 while (p++ < c)
2021 o += fprintf(stderr, " ");
2022 return o;
2023 }
2024
2025 void r600_bytecode_disasm(struct r600_bytecode *bc)
2026 {
2027 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2028 static int index = 0;
2029 struct r600_bytecode_cf *cf = NULL;
2030 struct r600_bytecode_alu *alu = NULL;
2031 struct r600_bytecode_vtx *vtx = NULL;
2032 struct r600_bytecode_tex *tex = NULL;
2033 struct r600_bytecode_gds *gds = NULL;
2034
2035 unsigned i, id, ngr = 0, last;
2036 uint32_t literal[4];
2037 unsigned nliteral;
2038 char chip = '6';
2039
2040 switch (bc->chip_class) {
2041 case R700:
2042 chip = '7';
2043 break;
2044 case EVERGREEN:
2045 chip = 'E';
2046 break;
2047 case CAYMAN:
2048 chip = 'C';
2049 break;
2050 case R600:
2051 default:
2052 chip = '6';
2053 break;
2054 }
2055 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2056 bc->ndw, bc->ngpr, bc->nstack);
2057 fprintf(stderr, "shader %d -- %c\n", index++, chip);
2058
2059 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2060 id = cf->id;
2061 if (cf->op == CF_NATIVE) {
2062 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
2063 bc->bytecode[id + 1]);
2064 } else {
2065 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2066 if (cfop->flags & CF_ALU) {
2067 if (cf->eg_alu_extended) {
2068 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2069 bc->bytecode[id + 1], "ALU_EXT");
2070 id += 2;
2071 }
2072 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2073 bc->bytecode[id + 1], cfop->name);
2074 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2075 for (i = 0; i < 4; ++i) {
2076 if (cf->kcache[i].mode) {
2077 int c_start = (cf->kcache[i].addr << 4);
2078 int c_end = c_start + (cf->kcache[i].mode << 4);
2079 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2080 i, cf->kcache[i].bank, c_start, c_end,
2081 cf->kcache[i].index_mode ? " " : "",
2082 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2083 }
2084 }
2085 fprintf(stderr, "\n");
2086 } else if (cfop->flags & CF_FETCH) {
2087 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2088 bc->bytecode[id + 1], cfop->name);
2089 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2090 fprintf(stderr, "\n");
2091 } else if (cfop->flags & CF_EXP) {
2092 int o = 0;
2093 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2094 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2095 bc->bytecode[id + 1], cfop->name);
2096 o += print_indent(o, 43);
2097 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2098 if (cf->output.burst_count > 1) {
2099 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2100 cf->output.array_base + cf->output.burst_count - 1);
2101
2102 o += print_indent(o, 55);
2103 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2104 cf->output.gpr + cf->output.burst_count - 1);
2105 } else {
2106 o += fprintf(stderr, "%d ", cf->output.array_base);
2107 o += print_indent(o, 55);
2108 o += fprintf(stderr, "R%d.", cf->output.gpr);
2109 }
2110
2111 o += print_swizzle(cf->output.swizzle_x);
2112 o += print_swizzle(cf->output.swizzle_y);
2113 o += print_swizzle(cf->output.swizzle_z);
2114 o += print_swizzle(cf->output.swizzle_w);
2115
2116 print_indent(o, 67);
2117
2118 fprintf(stderr, " ES:%X ", cf->output.elem_size);
2119 if (!cf->barrier)
2120 fprintf(stderr, "NO_BARRIER ");
2121 if (cf->end_of_program)
2122 fprintf(stderr, "EOP ");
2123 fprintf(stderr, "\n");
2124 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2125 int o = 0;
2126 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2127 "WRITE_IND_ACK"};
2128 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2129 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2130 o += print_indent(o, 43);
2131 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2132 if (cf->output.burst_count > 1) {
2133 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2134 cf->output.array_base + cf->output.burst_count - 1);
2135 o += print_indent(o, 55);
2136 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2137 cf->output.gpr + cf->output.burst_count - 1);
2138 } else {
2139 o += fprintf(stderr, "%d ", cf->output.array_base);
2140 o += print_indent(o, 55);
2141 o += fprintf(stderr, "R%d.", cf->output.gpr);
2142 }
2143 for (i = 0; i < 4; ++i) {
2144 if (cf->output.comp_mask & (1 << i))
2145 o += print_swizzle(i);
2146 else
2147 o += print_swizzle(7);
2148 }
2149
2150 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND ||
2151 cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND)
2152 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2153
2154 o += print_indent(o, 67);
2155
2156 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2157 if (cf->output.array_size != 0xFFF)
2158 fprintf(stderr, "AS:%i ", cf->output.array_size);
2159 if (!cf->barrier)
2160 fprintf(stderr, "NO_BARRIER ");
2161 if (cf->end_of_program)
2162 fprintf(stderr, "EOP ");
2163 fprintf(stderr, "\n");
2164 } else {
2165 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2166 bc->bytecode[id + 1], cfop->name);
2167 fprintf(stderr, "@%d ", cf->cf_addr);
2168 if (cf->cond)
2169 fprintf(stderr, "CND:%X ", cf->cond);
2170 if (cf->pop_count)
2171 fprintf(stderr, "POP:%X ", cf->pop_count);
2172 if (cf->count && (cfop->flags & CF_EMIT))
2173 fprintf(stderr, "STREAM%d ", cf->count);
2174 if (cf->end_of_program)
2175 fprintf(stderr, "EOP ");
2176 fprintf(stderr, "\n");
2177 }
2178 }
2179
2180 id = cf->addr;
2181 nliteral = 0;
2182 last = 1;
2183 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2184 const char *omod_str[] = {"","*2","*4","/2"};
2185 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2186 int o = 0;
2187
2188 r600_bytecode_alu_nliterals(alu, literal, &nliteral);
2189 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2190 if (last)
2191 o += fprintf(stderr, "%4d ", ++ngr);
2192 else
2193 o += fprintf(stderr, " ");
2194 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2195 alu->update_pred ? 'P':' ',
2196 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2197
2198 o += fprintf(stderr, "%s%s%s ", aop->name,
2199 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2200
2201 o += print_indent(o,60);
2202 o += print_dst(alu);
2203 for (i = 0; i < aop->src_count; ++i) {
2204 o += fprintf(stderr, i == 0 ? ", ": ", ");
2205 o += print_src(alu, i);
2206 }
2207
2208 if (alu->bank_swizzle) {
2209 o += print_indent(o,75);
2210 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2211 }
2212
2213 fprintf(stderr, "\n");
2214 id += 2;
2215
2216 if (alu->last) {
2217 for (i = 0; i < nliteral; i++, id++) {
2218 float *f = (float*)(bc->bytecode + id);
2219 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2220 print_indent(o, 60);
2221 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2222 }
2223 id += nliteral & 1;
2224 nliteral = 0;
2225 }
2226 last = alu->last;
2227 }
2228
2229 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2230 int o = 0;
2231 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2232 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2233
2234 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2235
2236 o += print_indent(o, 50);
2237
2238 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2239 o += print_swizzle(tex->dst_sel_x);
2240 o += print_swizzle(tex->dst_sel_y);
2241 o += print_swizzle(tex->dst_sel_z);
2242 o += print_swizzle(tex->dst_sel_w);
2243
2244 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2245 o += print_swizzle(tex->src_sel_x);
2246 o += print_swizzle(tex->src_sel_y);
2247 o += print_swizzle(tex->src_sel_z);
2248 o += print_swizzle(tex->src_sel_w);
2249
2250 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2251 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2252
2253 if (tex->sampler_index_mode)
2254 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2255
2256 if (tex->lod_bias)
2257 fprintf(stderr, "LB:%d ", tex->lod_bias);
2258
2259 fprintf(stderr, "CT:%c%c%c%c ",
2260 tex->coord_type_x ? 'N' : 'U',
2261 tex->coord_type_y ? 'N' : 'U',
2262 tex->coord_type_z ? 'N' : 'U',
2263 tex->coord_type_w ? 'N' : 'U');
2264
2265 if (tex->offset_x)
2266 fprintf(stderr, "OX:%d ", tex->offset_x);
2267 if (tex->offset_y)
2268 fprintf(stderr, "OY:%d ", tex->offset_y);
2269 if (tex->offset_z)
2270 fprintf(stderr, "OZ:%d ", tex->offset_z);
2271
2272 id += 4;
2273 fprintf(stderr, "\n");
2274 }
2275
2276 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2277 int o = 0;
2278 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2279 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2280 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2281
2282 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2283
2284 o += print_indent(o, 50);
2285
2286 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2287 o += print_swizzle(vtx->dst_sel_x);
2288 o += print_swizzle(vtx->dst_sel_y);
2289 o += print_swizzle(vtx->dst_sel_z);
2290 o += print_swizzle(vtx->dst_sel_w);
2291
2292 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2293 o += print_swizzle(vtx->src_sel_x);
2294
2295 if (vtx->offset)
2296 fprintf(stderr, " +%db", vtx->offset);
2297
2298 o += print_indent(o, 55);
2299
2300 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2301
2302 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2303
2304 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2305 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2306
2307 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2308 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2309
2310 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2311 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2312 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2313 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2314 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2315
2316 id += 4;
2317 }
2318
2319 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2320 int o = 0;
2321 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2322 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2323
2324 o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2325
2326 if (gds->op != FETCH_OP_TF_WRITE) {
2327 o += fprintf(stderr, "R%d.", gds->dst_gpr);
2328 o += print_swizzle(gds->dst_sel_x);
2329 o += print_swizzle(gds->dst_sel_y);
2330 o += print_swizzle(gds->dst_sel_z);
2331 o += print_swizzle(gds->dst_sel_w);
2332 }
2333
2334 o += fprintf(stderr, ", R%d.", gds->src_gpr);
2335 o += print_swizzle(gds->src_sel_x);
2336 o += print_swizzle(gds->src_sel_y);
2337 o += print_swizzle(gds->src_sel_z);
2338
2339 if (gds->op != FETCH_OP_TF_WRITE) {
2340 o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2341 }
2342 if (gds->alloc_consume) {
2343 o += fprintf(stderr, " UAV: %d", gds->uav_id);
2344 if (gds->uav_index_mode)
2345 o += fprintf(stderr, "[%s]", index_mode[gds->uav_index_mode]);
2346 }
2347 fprintf(stderr, "\n");
2348 id += 4;
2349 }
2350 }
2351
2352 fprintf(stderr, "--------------------------------------\n");
2353 }
2354
2355 void r600_vertex_data_type(enum pipe_format pformat,
2356 unsigned *format,
2357 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2358 {
2359 const struct util_format_description *desc;
2360 unsigned i;
2361
2362 *format = 0;
2363 *num_format = 0;
2364 *format_comp = 0;
2365 *endian = ENDIAN_NONE;
2366
2367 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2368 *format = FMT_10_11_11_FLOAT;
2369 *endian = r600_endian_swap(32);
2370 return;
2371 }
2372
2373 if (pformat == PIPE_FORMAT_B5G6R5_UNORM) {
2374 *format = FMT_5_6_5;
2375 *endian = r600_endian_swap(16);
2376 return;
2377 }
2378
2379 desc = util_format_description(pformat);
2380 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2381 goto out_unknown;
2382 }
2383
2384 /* Find the first non-VOID channel. */
2385 for (i = 0; i < 4; i++) {
2386 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2387 break;
2388 }
2389 }
2390
2391 *endian = r600_endian_swap(desc->channel[i].size);
2392
2393 switch (desc->channel[i].type) {
2394 /* Half-floats, floats, ints */
2395 case UTIL_FORMAT_TYPE_FLOAT:
2396 switch (desc->channel[i].size) {
2397 case 16:
2398 switch (desc->nr_channels) {
2399 case 1:
2400 *format = FMT_16_FLOAT;
2401 break;
2402 case 2:
2403 *format = FMT_16_16_FLOAT;
2404 break;
2405 case 3:
2406 case 4:
2407 *format = FMT_16_16_16_16_FLOAT;
2408 break;
2409 }
2410 break;
2411 case 32:
2412 switch (desc->nr_channels) {
2413 case 1:
2414 *format = FMT_32_FLOAT;
2415 break;
2416 case 2:
2417 *format = FMT_32_32_FLOAT;
2418 break;
2419 case 3:
2420 *format = FMT_32_32_32_FLOAT;
2421 break;
2422 case 4:
2423 *format = FMT_32_32_32_32_FLOAT;
2424 break;
2425 }
2426 break;
2427 default:
2428 goto out_unknown;
2429 }
2430 break;
2431 /* Unsigned ints */
2432 case UTIL_FORMAT_TYPE_UNSIGNED:
2433 /* Signed ints */
2434 case UTIL_FORMAT_TYPE_SIGNED:
2435 switch (desc->channel[i].size) {
2436 case 8:
2437 switch (desc->nr_channels) {
2438 case 1:
2439 *format = FMT_8;
2440 break;
2441 case 2:
2442 *format = FMT_8_8;
2443 break;
2444 case 3:
2445 case 4:
2446 *format = FMT_8_8_8_8;
2447 break;
2448 }
2449 break;
2450 case 10:
2451 if (desc->nr_channels != 4)
2452 goto out_unknown;
2453
2454 *format = FMT_2_10_10_10;
2455 break;
2456 case 16:
2457 switch (desc->nr_channels) {
2458 case 1:
2459 *format = FMT_16;
2460 break;
2461 case 2:
2462 *format = FMT_16_16;
2463 break;
2464 case 3:
2465 case 4:
2466 *format = FMT_16_16_16_16;
2467 break;
2468 }
2469 break;
2470 case 32:
2471 switch (desc->nr_channels) {
2472 case 1:
2473 *format = FMT_32;
2474 break;
2475 case 2:
2476 *format = FMT_32_32;
2477 break;
2478 case 3:
2479 *format = FMT_32_32_32;
2480 break;
2481 case 4:
2482 *format = FMT_32_32_32_32;
2483 break;
2484 }
2485 break;
2486 default:
2487 goto out_unknown;
2488 }
2489 break;
2490 default:
2491 goto out_unknown;
2492 }
2493
2494 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2495 *format_comp = 1;
2496 }
2497
2498 *num_format = 0;
2499 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2500 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2501 if (!desc->channel[i].normalized) {
2502 if (desc->channel[i].pure_integer)
2503 *num_format = 1;
2504 else
2505 *num_format = 2;
2506 }
2507 }
2508 return;
2509 out_unknown:
2510 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2511 }
2512
2513 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2514 unsigned count,
2515 const struct pipe_vertex_element *elements)
2516 {
2517 struct r600_context *rctx = (struct r600_context *)ctx;
2518 struct r600_bytecode bc;
2519 struct r600_bytecode_vtx vtx;
2520 const struct util_format_description *desc;
2521 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2522 unsigned format, num_format, format_comp, endian;
2523 uint32_t *bytecode;
2524 int i, j, r, fs_size;
2525 struct r600_fetch_shader *shader;
2526 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2527 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2528
2529 assert(count < 32);
2530
2531 memset(&bc, 0, sizeof(bc));
2532 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2533 rctx->screen->has_compressed_msaa_texturing);
2534
2535 bc.isa = rctx->isa;
2536
2537 for (i = 0; i < count; i++) {
2538 if (elements[i].instance_divisor > 1) {
2539 if (rctx->b.chip_class == CAYMAN) {
2540 for (j = 0; j < 4; j++) {
2541 struct r600_bytecode_alu alu;
2542 memset(&alu, 0, sizeof(alu));
2543 alu.op = ALU_OP2_MULHI_UINT;
2544 alu.src[0].sel = 0;
2545 alu.src[0].chan = 3;
2546 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2547 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2548 alu.dst.sel = i + 1;
2549 alu.dst.chan = j;
2550 alu.dst.write = j == 3;
2551 alu.last = j == 3;
2552 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2553 r600_bytecode_clear(&bc);
2554 return NULL;
2555 }
2556 }
2557 } else {
2558 struct r600_bytecode_alu alu;
2559 memset(&alu, 0, sizeof(alu));
2560 alu.op = ALU_OP2_MULHI_UINT;
2561 alu.src[0].sel = 0;
2562 alu.src[0].chan = 3;
2563 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2564 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2565 alu.dst.sel = i + 1;
2566 alu.dst.chan = 3;
2567 alu.dst.write = 1;
2568 alu.last = 1;
2569 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2570 r600_bytecode_clear(&bc);
2571 return NULL;
2572 }
2573 }
2574 }
2575 }
2576
2577 for (i = 0; i < count; i++) {
2578 r600_vertex_data_type(elements[i].src_format,
2579 &format, &num_format, &format_comp, &endian);
2580
2581 desc = util_format_description(elements[i].src_format);
2582 if (!desc) {
2583 r600_bytecode_clear(&bc);
2584 R600_ERR("unknown format %d\n", elements[i].src_format);
2585 return NULL;
2586 }
2587
2588 if (elements[i].src_offset > 65535) {
2589 r600_bytecode_clear(&bc);
2590 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2591 return NULL;
2592 }
2593
2594 memset(&vtx, 0, sizeof(vtx));
2595 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2596 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2597 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2598 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2599 vtx.mega_fetch_count = 0x1F;
2600 vtx.dst_gpr = i + 1;
2601 vtx.dst_sel_x = desc->swizzle[0];
2602 vtx.dst_sel_y = desc->swizzle[1];
2603 vtx.dst_sel_z = desc->swizzle[2];
2604 vtx.dst_sel_w = desc->swizzle[3];
2605 vtx.data_format = format;
2606 vtx.num_format_all = num_format;
2607 vtx.format_comp_all = format_comp;
2608 vtx.offset = elements[i].src_offset;
2609 vtx.endian = endian;
2610
2611 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2612 r600_bytecode_clear(&bc);
2613 return NULL;
2614 }
2615 }
2616
2617 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2618
2619 if ((r = r600_bytecode_build(&bc))) {
2620 r600_bytecode_clear(&bc);
2621 return NULL;
2622 }
2623
2624 if (rctx->screen->b.debug_flags & DBG_FS) {
2625 fprintf(stderr, "--------------------------------------------------------------\n");
2626 fprintf(stderr, "Vertex elements state:\n");
2627 for (i = 0; i < count; i++) {
2628 fprintf(stderr, " ");
2629 util_dump_vertex_element(stderr, elements+i);
2630 fprintf(stderr, "\n");
2631 }
2632
2633 if (!sb_disasm) {
2634 r600_bytecode_disasm(&bc);
2635
2636 fprintf(stderr, "______________________________________________________________\n");
2637 } else {
2638 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2639 }
2640 }
2641
2642 fs_size = bc.ndw*4;
2643
2644 /* Allocate the CSO. */
2645 shader = CALLOC_STRUCT(r600_fetch_shader);
2646 if (!shader) {
2647 r600_bytecode_clear(&bc);
2648 return NULL;
2649 }
2650
2651 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, 256,
2652 &shader->offset,
2653 (struct pipe_resource**)&shader->buffer);
2654 if (!shader->buffer) {
2655 r600_bytecode_clear(&bc);
2656 FREE(shader);
2657 return NULL;
2658 }
2659
2660 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2661 bytecode += shader->offset / 4;
2662
2663 if (R600_BIG_ENDIAN) {
2664 for (i = 0; i < fs_size / 4; ++i) {
2665 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2666 }
2667 } else {
2668 memcpy(bytecode, bc.bytecode, fs_size);
2669 }
2670 rctx->b.ws->buffer_unmap(shader->buffer->buf);
2671
2672 r600_bytecode_clear(&bc);
2673 return shader;
2674 }
2675
2676 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2677 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2678 {
2679 /* WORD0 */
2680 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2681 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2682 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2683 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2684 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2685 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2686 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2687 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2688 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2689 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2690 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2691
2692 /* WORD1 */
2693 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2694 if (alu->bank_swizzle)
2695 alu->bank_swizzle_force = alu->bank_swizzle;
2696 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2697 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2698 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2699 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2700 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2701 {
2702 alu->is_op3 = 1;
2703 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2704 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2705 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2706 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2707 alu->op = r600_isa_alu_by_opcode(bc->isa,
2708 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2709
2710 }
2711 else /*ALU_DWORD1_OP2*/
2712 {
2713 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2714 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2715 alu->op = r600_isa_alu_by_opcode(bc->isa,
2716 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2717 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2718 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2719 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2720 alu->execute_mask =
2721 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2722 }
2723 }
2724
2725 #if 0
2726 void r600_bytecode_export_read(struct r600_bytecode *bc,
2727 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2728 {
2729 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2730 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2731 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2732 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2733
2734 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2735 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2736 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2737 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2738 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2739 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2740 output->op = r600_isa_cf_by_opcode(bc->isa,
2741 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2742 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2743 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2744 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2745 }
2746 #endif