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fc792f1cf71f48ae6aac5be5c77ed630b0086570
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <byteswap.h>
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "r600_pipe.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600_asm.h"
33 #include "r600_formats.h"
34 #include "r600d.h"
35
36 #define NUM_OF_CYCLES 3
37 #define NUM_OF_COMPONENTS 4
38
39 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
40 {
41 if(alu->is_op3)
42 return 3;
43
44 switch (bc->chip_class) {
45 case R600:
46 case R700:
47 switch (alu->inst) {
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
49 return 0;
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
73 return 2;
74
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
93 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
94 return 1;
95 default: R600_ERR(
96 "Need instruction operand number for 0x%x.\n", alu->inst);
97 }
98 break;
99 case EVERGREEN:
100 case CAYMAN:
101 switch (alu->inst) {
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
103 return 0;
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
117 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
118 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
144 return 2;
145
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
165 return 1;
166 default: R600_ERR(
167 "Need instruction operand number for 0x%x.\n", alu->inst);
168 }
169 break;
170 }
171
172 return 3;
173 }
174
175 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
176
177 static struct r600_bytecode_cf *r600_bytecode_cf(void)
178 {
179 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
180
181 if (cf == NULL)
182 return NULL;
183 LIST_INITHEAD(&cf->list);
184 LIST_INITHEAD(&cf->alu);
185 LIST_INITHEAD(&cf->vtx);
186 LIST_INITHEAD(&cf->tex);
187 return cf;
188 }
189
190 static struct r600_bytecode_alu *r600_bytecode_alu(void)
191 {
192 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
193
194 if (alu == NULL)
195 return NULL;
196 LIST_INITHEAD(&alu->list);
197 return alu;
198 }
199
200 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
201 {
202 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
203
204 if (vtx == NULL)
205 return NULL;
206 LIST_INITHEAD(&vtx->list);
207 return vtx;
208 }
209
210 static struct r600_bytecode_tex *r600_bytecode_tex(void)
211 {
212 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
213
214 if (tex == NULL)
215 return NULL;
216 LIST_INITHEAD(&tex->list);
217 return tex;
218 }
219
220 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class)
221 {
222 LIST_INITHEAD(&bc->cf);
223 bc->chip_class = chip_class;
224 }
225
226 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
227 {
228 struct r600_bytecode_cf *cf = r600_bytecode_cf();
229
230 if (cf == NULL)
231 return -ENOMEM;
232 LIST_ADDTAIL(&cf->list, &bc->cf);
233 if (bc->cf_last)
234 cf->id = bc->cf_last->id + 2;
235 bc->cf_last = cf;
236 bc->ncf++;
237 bc->ndw += 2;
238 bc->force_add_cf = 0;
239 return 0;
240 }
241
242 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
243 {
244 int r;
245
246 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
247 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
248 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
249 output->type == bc->cf_last->output.type &&
250 output->elem_size == bc->cf_last->output.elem_size &&
251 output->swizzle_x == bc->cf_last->output.swizzle_x &&
252 output->swizzle_y == bc->cf_last->output.swizzle_y &&
253 output->swizzle_z == bc->cf_last->output.swizzle_z &&
254 output->swizzle_w == bc->cf_last->output.swizzle_w &&
255 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
256
257 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
258 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
259
260 bc->cf_last->output.end_of_program |= output->end_of_program;
261 bc->cf_last->output.inst = output->inst;
262 bc->cf_last->output.gpr = output->gpr;
263 bc->cf_last->output.array_base = output->array_base;
264 bc->cf_last->output.burst_count += output->burst_count;
265 return 0;
266
267 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
268 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
269
270 bc->cf_last->output.end_of_program |= output->end_of_program;
271 bc->cf_last->output.inst = output->inst;
272 bc->cf_last->output.burst_count += output->burst_count;
273 return 0;
274 }
275 }
276
277 r = r600_bytecode_add_cf(bc);
278 if (r)
279 return r;
280 bc->cf_last->inst = output->inst;
281 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
282 return 0;
283 }
284
285 /* alu instructions that can ony exits once per group */
286 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
287 {
288 switch (bc->chip_class) {
289 case R600:
290 case R700:
291 return !alu->is_op3 && (
292 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
293 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
294 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
295 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
296 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
297 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
298 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
299 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
300 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
301 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
302 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
303 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
304 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
305 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
306 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
307 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
308 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
309 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
310 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
311 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
312 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
313 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
314 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
315 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
316 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
317 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
318 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
319 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
320 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
321 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
322 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
323 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
324 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
325 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
326 case EVERGREEN:
327 case CAYMAN:
328 default:
329 return !alu->is_op3 && (
330 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
331 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
332 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
333 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
334 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
335 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
336 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
337 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
338 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
339 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
340 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
341 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
342 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
343 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
344 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
345 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
346 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
347 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
348 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
349 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
350 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
351 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
352 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
353 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
354 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
355 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
356 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
357 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
358 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
359 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
360 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
361 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
362 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
363 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
364 }
365 }
366
367 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
368 {
369 switch (bc->chip_class) {
370 case R600:
371 case R700:
372 return !alu->is_op3 && (
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
377 case EVERGREEN:
378 case CAYMAN:
379 default:
380 return !alu->is_op3 && (
381 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
385 }
386 }
387
388 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
389 {
390 switch (bc->chip_class) {
391 case R600:
392 case R700:
393 return !alu->is_op3 &&
394 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
395 case EVERGREEN:
396 case CAYMAN:
397 default:
398 return !alu->is_op3 &&
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
400 }
401 }
402
403 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
404 {
405 switch (bc->chip_class) {
406 case R600:
407 case R700:
408 return !alu->is_op3 && (
409 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
410 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
411 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
412 case EVERGREEN:
413 case CAYMAN:
414 default:
415 return !alu->is_op3 && (
416 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
417 }
418 }
419
420 /* alu instructions that can only execute on the vector unit */
421 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
422 {
423 return is_alu_reduction_inst(bc, alu) ||
424 is_alu_mova_inst(bc, alu) ||
425 (bc->chip_class == EVERGREEN &&
426 (alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
427 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR));
428 }
429
430 /* alu instructions that can only execute on the trans unit */
431 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
432 {
433 switch (bc->chip_class) {
434 case R600:
435 case R700:
436 if (!alu->is_op3)
437 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
438 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
439 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
440 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
441 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
442 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
443 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
444 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
445 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
446 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
447 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
448 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
449 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
450 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
451 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
452 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
453 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
454 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
455 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
456 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
457 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
458 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
459 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
460 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
461 else
462 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
463 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
464 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
465 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
466 case EVERGREEN:
467 case CAYMAN:
468 default:
469 if (!alu->is_op3)
470 /* Note that FLT_TO_INT_* instructions are vector-only instructions
471 * on Evergreen, despite what the documentation says. FLT_TO_INT
472 * can do both vector and scalar. */
473 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
474 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
475 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
476 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
477 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
478 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
479 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
480 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
481 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
482 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
483 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
484 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
485 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
486 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
487 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
488 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
489 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
490 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
491 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
492 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
493 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
494 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
495 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
496 else
497 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
498 }
499 }
500
501 /* alu instructions that can execute on any unit */
502 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
503 {
504 return !is_alu_vec_unit_inst(bc, alu) &&
505 !is_alu_trans_unit_inst(bc, alu);
506 }
507
508 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
509 struct r600_bytecode_alu *assignment[5])
510 {
511 struct r600_bytecode_alu *alu;
512 unsigned i, chan, trans;
513 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
514
515 for (i = 0; i < max_slots; i++)
516 assignment[i] = NULL;
517
518 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
519 chan = alu->dst.chan;
520 if (max_slots == 4)
521 trans = 0;
522 else if (is_alu_trans_unit_inst(bc, alu))
523 trans = 1;
524 else if (is_alu_vec_unit_inst(bc, alu))
525 trans = 0;
526 else if (assignment[chan])
527 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
528 else
529 trans = 0;
530
531 if (trans) {
532 if (assignment[4]) {
533 assert(0); /* ALU.Trans has already been allocated. */
534 return -1;
535 }
536 assignment[4] = alu;
537 } else {
538 if (assignment[chan]) {
539 assert(0); /* ALU.chan has already been allocated. */
540 return -1;
541 }
542 assignment[chan] = alu;
543 }
544
545 if (alu->last)
546 break;
547 }
548 return 0;
549 }
550
551 struct alu_bank_swizzle {
552 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
553 int hw_cfile_addr[4];
554 int hw_cfile_elem[4];
555 };
556
557 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
558 [SQ_ALU_VEC_012] = { 0, 1, 2 },
559 [SQ_ALU_VEC_021] = { 0, 2, 1 },
560 [SQ_ALU_VEC_120] = { 1, 2, 0 },
561 [SQ_ALU_VEC_102] = { 1, 0, 2 },
562 [SQ_ALU_VEC_201] = { 2, 0, 1 },
563 [SQ_ALU_VEC_210] = { 2, 1, 0 }
564 };
565
566 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
567 [SQ_ALU_SCL_210] = { 2, 1, 0 },
568 [SQ_ALU_SCL_122] = { 1, 2, 2 },
569 [SQ_ALU_SCL_212] = { 2, 1, 2 },
570 [SQ_ALU_SCL_221] = { 2, 2, 1 }
571 };
572
573 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
574 {
575 int i, cycle, component;
576 /* set up gpr use */
577 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
578 for (component = 0; component < NUM_OF_COMPONENTS; component++)
579 bs->hw_gpr[cycle][component] = -1;
580 for (i = 0; i < 4; i++)
581 bs->hw_cfile_addr[i] = -1;
582 for (i = 0; i < 4; i++)
583 bs->hw_cfile_elem[i] = -1;
584 }
585
586 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
587 {
588 if (bs->hw_gpr[cycle][chan] == -1)
589 bs->hw_gpr[cycle][chan] = sel;
590 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
591 /* Another scalar operation has already used the GPR read port for the channel. */
592 return -1;
593 }
594 return 0;
595 }
596
597 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
598 {
599 int res, num_res = 4;
600 if (bc->chip_class >= R700) {
601 num_res = 2;
602 chan /= 2;
603 }
604 for (res = 0; res < num_res; ++res) {
605 if (bs->hw_cfile_addr[res] == -1) {
606 bs->hw_cfile_addr[res] = sel;
607 bs->hw_cfile_elem[res] = chan;
608 return 0;
609 } else if (bs->hw_cfile_addr[res] == sel &&
610 bs->hw_cfile_elem[res] == chan)
611 return 0; /* Read for this scalar element already reserved, nothing to do here. */
612 }
613 /* All cfile read ports are used, cannot reference vector element. */
614 return -1;
615 }
616
617 static int is_gpr(unsigned sel)
618 {
619 return (sel >= 0 && sel <= 127);
620 }
621
622 /* CB constants start at 512, and get translated to a kcache index when ALU
623 * clauses are constructed. Note that we handle kcache constants the same way
624 * as (the now gone) cfile constants, is that really required? */
625 static int is_cfile(unsigned sel)
626 {
627 return (sel > 255 && sel < 512) ||
628 (sel > 511 && sel < 4607) || /* Kcache before translation. */
629 (sel > 127 && sel < 192); /* Kcache after translation. */
630 }
631
632 static int is_const(int sel)
633 {
634 return is_cfile(sel) ||
635 (sel >= V_SQ_ALU_SRC_0 &&
636 sel <= V_SQ_ALU_SRC_LITERAL);
637 }
638
639 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
640 struct alu_bank_swizzle *bs, int bank_swizzle)
641 {
642 int r, src, num_src, sel, elem, cycle;
643
644 num_src = r600_bytecode_get_num_operands(bc, alu);
645 for (src = 0; src < num_src; src++) {
646 sel = alu->src[src].sel;
647 elem = alu->src[src].chan;
648 if (is_gpr(sel)) {
649 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
650 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
651 /* Nothing to do; special-case optimization,
652 * second source uses first source’s reservation. */
653 continue;
654 else {
655 r = reserve_gpr(bs, sel, elem, cycle);
656 if (r)
657 return r;
658 }
659 } else if (is_cfile(sel)) {
660 r = reserve_cfile(bc, bs, sel, elem);
661 if (r)
662 return r;
663 }
664 /* No restrictions on PV, PS, literal or special constants. */
665 }
666 return 0;
667 }
668
669 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
670 struct alu_bank_swizzle *bs, int bank_swizzle)
671 {
672 int r, src, num_src, const_count, sel, elem, cycle;
673
674 num_src = r600_bytecode_get_num_operands(bc, alu);
675 for (const_count = 0, src = 0; src < num_src; ++src) {
676 sel = alu->src[src].sel;
677 elem = alu->src[src].chan;
678 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
679 if (const_count >= 2)
680 /* More than two references to a constant in
681 * transcendental operation. */
682 return -1;
683 else
684 const_count++;
685 }
686 if (is_cfile(sel)) {
687 r = reserve_cfile(bc, bs, sel, elem);
688 if (r)
689 return r;
690 }
691 }
692 for (src = 0; src < num_src; ++src) {
693 sel = alu->src[src].sel;
694 elem = alu->src[src].chan;
695 if (is_gpr(sel)) {
696 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
697 if (cycle < const_count)
698 /* Cycle for GPR load conflicts with
699 * constant load in transcendental operation. */
700 return -1;
701 r = reserve_gpr(bs, sel, elem, cycle);
702 if (r)
703 return r;
704 }
705 /* PV PS restrictions */
706 if (const_count && (sel == 254 || sel == 255)) {
707 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
708 if (cycle < const_count)
709 return -1;
710 }
711 }
712 return 0;
713 }
714
715 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
716 struct r600_bytecode_alu *slots[5])
717 {
718 struct alu_bank_swizzle bs;
719 int bank_swizzle[5];
720 int i, r = 0, forced = 1;
721 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
722 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
723
724 for (i = 0; i < max_slots; i++) {
725 if (slots[i]) {
726 if (slots[i]->bank_swizzle_force) {
727 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
728 } else {
729 forced = 0;
730 }
731 }
732
733 if (i < 4 && slots[i])
734 scalar_only = false;
735 }
736 if (forced)
737 return 0;
738
739 /* Just check every possible combination of bank swizzle.
740 * Not very efficent, but works on the first try in most of the cases. */
741 for (i = 0; i < 4; i++)
742 if (!slots[i] || !slots[i]->bank_swizzle_force)
743 bank_swizzle[i] = SQ_ALU_VEC_012;
744 else
745 bank_swizzle[i] = slots[i]->bank_swizzle;
746
747 bank_swizzle[4] = SQ_ALU_SCL_210;
748 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
749
750 if (max_slots == 4) {
751 for (i = 0; i < max_slots; i++) {
752 if (bank_swizzle[i] == SQ_ALU_VEC_210)
753 return -1;
754 }
755 }
756 init_bank_swizzle(&bs);
757 if (scalar_only == false) {
758 for (i = 0; i < 4; i++) {
759 if (slots[i]) {
760 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
761 if (r)
762 break;
763 }
764 }
765 } else
766 r = 0;
767
768 if (!r && slots[4] && max_slots == 5) {
769 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
770 }
771 if (!r) {
772 for (i = 0; i < max_slots; i++) {
773 if (slots[i])
774 slots[i]->bank_swizzle = bank_swizzle[i];
775 }
776 return 0;
777 }
778
779 if (scalar_only) {
780 bank_swizzle[4]++;
781 } else {
782 for (i = 0; i < max_slots; i++) {
783 if (!slots[i] || !slots[i]->bank_swizzle_force) {
784 bank_swizzle[i]++;
785 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
786 break;
787 else
788 bank_swizzle[i] = SQ_ALU_VEC_012;
789 }
790 }
791 }
792 }
793
794 /* Couldn't find a working swizzle. */
795 return -1;
796 }
797
798 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
799 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
800 {
801 struct r600_bytecode_alu *prev[5];
802 int gpr[5], chan[5];
803 int i, j, r, src, num_src;
804 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
805
806 r = assign_alu_units(bc, alu_prev, prev);
807 if (r)
808 return r;
809
810 for (i = 0; i < max_slots; ++i) {
811 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
812 gpr[i] = prev[i]->dst.sel;
813 /* cube writes more than PV.X */
814 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
815 chan[i] = 0;
816 else
817 chan[i] = prev[i]->dst.chan;
818 } else
819 gpr[i] = -1;
820 }
821
822 for (i = 0; i < max_slots; ++i) {
823 struct r600_bytecode_alu *alu = slots[i];
824 if(!alu)
825 continue;
826
827 num_src = r600_bytecode_get_num_operands(bc, alu);
828 for (src = 0; src < num_src; ++src) {
829 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
830 continue;
831
832 if (bc->chip_class < CAYMAN) {
833 if (alu->src[src].sel == gpr[4] &&
834 alu->src[src].chan == chan[4]) {
835 alu->src[src].sel = V_SQ_ALU_SRC_PS;
836 alu->src[src].chan = 0;
837 continue;
838 }
839 }
840
841 for (j = 0; j < 4; ++j) {
842 if (alu->src[src].sel == gpr[j] &&
843 alu->src[src].chan == j) {
844 alu->src[src].sel = V_SQ_ALU_SRC_PV;
845 alu->src[src].chan = chan[j];
846 break;
847 }
848 }
849 }
850 }
851
852 return 0;
853 }
854
855 void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
856 {
857 switch(value) {
858 case 0:
859 *sel = V_SQ_ALU_SRC_0;
860 break;
861 case 1:
862 *sel = V_SQ_ALU_SRC_1_INT;
863 break;
864 case -1:
865 *sel = V_SQ_ALU_SRC_M_1_INT;
866 break;
867 case 0x3F800000: /* 1.0f */
868 *sel = V_SQ_ALU_SRC_1;
869 break;
870 case 0x3F000000: /* 0.5f */
871 *sel = V_SQ_ALU_SRC_0_5;
872 break;
873 case 0xBF800000: /* -1.0f */
874 *sel = V_SQ_ALU_SRC_1;
875 *neg ^= 1;
876 break;
877 case 0xBF000000: /* -0.5f */
878 *sel = V_SQ_ALU_SRC_0_5;
879 *neg ^= 1;
880 break;
881 default:
882 *sel = V_SQ_ALU_SRC_LITERAL;
883 break;
884 }
885 }
886
887 /* compute how many literal are needed */
888 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
889 uint32_t literal[4], unsigned *nliteral)
890 {
891 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
892 unsigned i, j;
893
894 for (i = 0; i < num_src; ++i) {
895 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
896 uint32_t value = alu->src[i].value;
897 unsigned found = 0;
898 for (j = 0; j < *nliteral; ++j) {
899 if (literal[j] == value) {
900 found = 1;
901 break;
902 }
903 }
904 if (!found) {
905 if (*nliteral >= 4)
906 return -EINVAL;
907 literal[(*nliteral)++] = value;
908 }
909 }
910 }
911 return 0;
912 }
913
914 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
915 struct r600_bytecode_alu *alu,
916 uint32_t literal[4], unsigned nliteral)
917 {
918 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
919 unsigned i, j;
920
921 for (i = 0; i < num_src; ++i) {
922 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
923 uint32_t value = alu->src[i].value;
924 for (j = 0; j < nliteral; ++j) {
925 if (literal[j] == value) {
926 alu->src[i].chan = j;
927 break;
928 }
929 }
930 }
931 }
932 }
933
934 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
935 struct r600_bytecode_alu *alu_prev)
936 {
937 struct r600_bytecode_alu *prev[5];
938 struct r600_bytecode_alu *result[5] = { NULL };
939
940 uint32_t literal[4], prev_literal[4];
941 unsigned nliteral = 0, prev_nliteral = 0;
942
943 int i, j, r, src, num_src;
944 int num_once_inst = 0;
945 int have_mova = 0, have_rel = 0;
946 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
947
948 r = assign_alu_units(bc, alu_prev, prev);
949 if (r)
950 return r;
951
952 for (i = 0; i < max_slots; ++i) {
953 struct r600_bytecode_alu *alu;
954
955 /* check number of literals */
956 if (prev[i]) {
957 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
958 return 0;
959 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
960 return 0;
961 if (is_alu_mova_inst(bc, prev[i])) {
962 if (have_rel)
963 return 0;
964 have_mova = 1;
965 }
966 num_once_inst += is_alu_once_inst(bc, prev[i]);
967 }
968 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
969 return 0;
970
971 /* Let's check used slots. */
972 if (prev[i] && !slots[i]) {
973 result[i] = prev[i];
974 continue;
975 } else if (prev[i] && slots[i]) {
976 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
977 /* Trans unit is still free try to use it. */
978 if (is_alu_any_unit_inst(bc, slots[i])) {
979 result[i] = prev[i];
980 result[4] = slots[i];
981 } else if (is_alu_any_unit_inst(bc, prev[i])) {
982 result[i] = slots[i];
983 result[4] = prev[i];
984 } else
985 return 0;
986 } else
987 return 0;
988 } else if(!slots[i]) {
989 continue;
990 } else
991 result[i] = slots[i];
992
993 alu = slots[i];
994 num_once_inst += is_alu_once_inst(bc, alu);
995
996 /* Let's check dst gpr. */
997 if (alu->dst.rel) {
998 if (have_mova)
999 return 0;
1000 have_rel = 1;
1001 }
1002
1003 /* Let's check source gprs */
1004 num_src = r600_bytecode_get_num_operands(bc, alu);
1005 for (src = 0; src < num_src; ++src) {
1006 if (alu->src[src].rel) {
1007 if (have_mova)
1008 return 0;
1009 have_rel = 1;
1010 }
1011
1012 /* Constants don't matter. */
1013 if (!is_gpr(alu->src[src].sel))
1014 continue;
1015
1016 for (j = 0; j < max_slots; ++j) {
1017 if (!prev[j] || !prev[j]->dst.write)
1018 continue;
1019
1020 /* If it's relative then we can't determin which gpr is really used. */
1021 if (prev[j]->dst.chan == alu->src[src].chan &&
1022 (prev[j]->dst.sel == alu->src[src].sel ||
1023 prev[j]->dst.rel || alu->src[src].rel))
1024 return 0;
1025 }
1026 }
1027 }
1028
1029 /* more than one PRED_ or KILL_ ? */
1030 if (num_once_inst > 1)
1031 return 0;
1032
1033 /* check if the result can still be swizzlet */
1034 r = check_and_set_bank_swizzle(bc, result);
1035 if (r)
1036 return 0;
1037
1038 /* looks like everything worked out right, apply the changes */
1039
1040 /* undo adding previus literals */
1041 bc->cf_last->ndw -= align(prev_nliteral, 2);
1042
1043 /* sort instructions */
1044 for (i = 0; i < max_slots; ++i) {
1045 slots[i] = result[i];
1046 if (result[i]) {
1047 LIST_DEL(&result[i]->list);
1048 result[i]->last = 0;
1049 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1050 }
1051 }
1052
1053 /* determine new last instruction */
1054 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1055
1056 /* determine new first instruction */
1057 for (i = 0; i < max_slots; ++i) {
1058 if (result[i]) {
1059 bc->cf_last->curr_bs_head = result[i];
1060 break;
1061 }
1062 }
1063
1064 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1065 bc->cf_last->prev2_bs_head = NULL;
1066
1067 return 0;
1068 }
1069
1070 /* This code handles kcache lines as single blocks of 32 constants. We could
1071 * probably do slightly better by recognizing that we actually have two
1072 * consecutive lines of 16 constants, but the resulting code would also be
1073 * somewhat more complicated. */
1074 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1075 {
1076 struct r600_bytecode_kcache *kcache = bc->cf_last->kcache;
1077 unsigned int required_lines;
1078 unsigned int free_lines = 0;
1079 unsigned int cache_line[3];
1080 unsigned int count = 0;
1081 unsigned int i, j;
1082 int r;
1083
1084 /* Collect required cache lines. */
1085 for (i = 0; i < 3; ++i) {
1086 boolean found = false;
1087 unsigned int line;
1088
1089 if (alu->src[i].sel < 512)
1090 continue;
1091
1092 line = ((alu->src[i].sel - 512) / 32) * 2;
1093
1094 for (j = 0; j < count; ++j) {
1095 if (cache_line[j] == line) {
1096 found = true;
1097 break;
1098 }
1099 }
1100
1101 if (!found)
1102 cache_line[count++] = line;
1103 }
1104
1105 /* This should never actually happen. */
1106 if (count >= 3) return -ENOMEM;
1107
1108 for (i = 0; i < 2; ++i) {
1109 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1110 ++free_lines;
1111 }
1112 }
1113
1114 /* Filter lines pulled in by previous intructions. Note that this is
1115 * only for the required_lines count, we can't remove these from the
1116 * cache_line array since we may have to start a new ALU clause. */
1117 for (i = 0, required_lines = count; i < count; ++i) {
1118 for (j = 0; j < 2; ++j) {
1119 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1120 kcache[j].addr == cache_line[i]) {
1121 --required_lines;
1122 break;
1123 }
1124 }
1125 }
1126
1127 /* Start a new ALU clause if needed. */
1128 if (required_lines > free_lines) {
1129 if ((r = r600_bytecode_add_cf(bc))) {
1130 return r;
1131 }
1132 bc->cf_last->inst = (type << 3);
1133 kcache = bc->cf_last->kcache;
1134 }
1135
1136 /* Setup the kcache lines. */
1137 for (i = 0; i < count; ++i) {
1138 boolean found = false;
1139
1140 for (j = 0; j < 2; ++j) {
1141 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1142 kcache[j].addr == cache_line[i]) {
1143 found = true;
1144 break;
1145 }
1146 }
1147
1148 if (found) continue;
1149
1150 for (j = 0; j < 2; ++j) {
1151 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1152 kcache[j].bank = 0;
1153 kcache[j].addr = cache_line[i];
1154 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1155 break;
1156 }
1157 }
1158 }
1159
1160 /* Alter the src operands to refer to the kcache. */
1161 for (i = 0; i < 3; ++i) {
1162 static const unsigned int base[] = {128, 160, 256, 288};
1163 unsigned int line;
1164
1165 if (alu->src[i].sel < 512)
1166 continue;
1167
1168 alu->src[i].sel -= 512;
1169 line = (alu->src[i].sel / 32) * 2;
1170
1171 for (j = 0; j < 2; ++j) {
1172 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1173 kcache[j].addr == line) {
1174 alu->src[i].sel &= 0x1f;
1175 alu->src[i].sel += base[j];
1176 break;
1177 }
1178 }
1179 }
1180
1181 return 0;
1182 }
1183
1184 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1185 {
1186 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1187 struct r600_bytecode_alu *lalu;
1188 int i, r;
1189
1190 if (nalu == NULL)
1191 return -ENOMEM;
1192 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1193
1194 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1195 /* check if we could add it anyway */
1196 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1197 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1198 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1199 if (lalu->predicate) {
1200 bc->force_add_cf = 1;
1201 break;
1202 }
1203 }
1204 } else
1205 bc->force_add_cf = 1;
1206 }
1207
1208 /* cf can contains only alu or only vtx or only tex */
1209 if (bc->cf_last == NULL || bc->force_add_cf) {
1210 r = r600_bytecode_add_cf(bc);
1211 if (r) {
1212 free(nalu);
1213 return r;
1214 }
1215 }
1216 bc->cf_last->inst = (type << 3);
1217
1218 /* Setup the kcache for this ALU instruction. This will start a new
1219 * ALU clause if needed. */
1220 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1221 free(nalu);
1222 return r;
1223 }
1224
1225 if (!bc->cf_last->curr_bs_head) {
1226 bc->cf_last->curr_bs_head = nalu;
1227 }
1228 /* number of gpr == the last gpr used in any alu */
1229 for (i = 0; i < 3; i++) {
1230 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1231 bc->ngpr = nalu->src[i].sel + 1;
1232 }
1233 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1234 r600_bytecode_special_constants(nalu->src[i].value,
1235 &nalu->src[i].sel, &nalu->src[i].neg);
1236 }
1237 if (nalu->dst.sel >= bc->ngpr) {
1238 bc->ngpr = nalu->dst.sel + 1;
1239 }
1240 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1241 /* each alu use 2 dwords */
1242 bc->cf_last->ndw += 2;
1243 bc->ndw += 2;
1244
1245 /* process cur ALU instructions for bank swizzle */
1246 if (nalu->last) {
1247 uint32_t literal[4];
1248 unsigned nliteral;
1249 struct r600_bytecode_alu *slots[5];
1250 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1251 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1252 if (r)
1253 return r;
1254
1255 if (bc->cf_last->prev_bs_head) {
1256 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1257 if (r)
1258 return r;
1259 }
1260
1261 if (bc->cf_last->prev_bs_head) {
1262 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1263 if (r)
1264 return r;
1265 }
1266
1267 r = check_and_set_bank_swizzle(bc, slots);
1268 if (r)
1269 return r;
1270
1271 for (i = 0, nliteral = 0; i < max_slots; i++) {
1272 if (slots[i]) {
1273 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1274 if (r)
1275 return r;
1276 }
1277 }
1278 bc->cf_last->ndw += align(nliteral, 2);
1279
1280 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1281 * worst case */
1282 if ((bc->cf_last->ndw >> 1) >= 120) {
1283 bc->force_add_cf = 1;
1284 }
1285
1286 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1287 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1288 bc->cf_last->curr_bs_head = NULL;
1289 }
1290 return 0;
1291 }
1292
1293 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1294 {
1295 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1296 }
1297
1298 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1299 {
1300 switch (bc->chip_class) {
1301 case R600:
1302 return 8;
1303
1304 case R700:
1305 return 16;
1306
1307 case EVERGREEN:
1308 case CAYMAN:
1309 return 64;
1310
1311 default:
1312 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1313 return 8;
1314 }
1315 }
1316
1317 static inline boolean last_inst_was_vtx_fetch(struct r600_bytecode *bc)
1318 {
1319 if (bc->chip_class == CAYMAN) {
1320 if (bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC)
1321 return TRUE;
1322 } else {
1323 if (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1324 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC)
1325 return TRUE;
1326 }
1327 return FALSE;
1328 }
1329
1330 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1331 {
1332 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1333 int r;
1334
1335 if (nvtx == NULL)
1336 return -ENOMEM;
1337 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1338
1339 /* cf can contains only alu or only vtx or only tex */
1340 if (bc->cf_last == NULL ||
1341 last_inst_was_vtx_fetch(bc) ||
1342 bc->force_add_cf) {
1343 r = r600_bytecode_add_cf(bc);
1344 if (r) {
1345 free(nvtx);
1346 return r;
1347 }
1348 if (bc->chip_class == CAYMAN)
1349 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1350 else
1351 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1352 }
1353 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1354 /* each fetch use 4 dwords */
1355 bc->cf_last->ndw += 4;
1356 bc->ndw += 4;
1357 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1358 bc->force_add_cf = 1;
1359 return 0;
1360 }
1361
1362 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1363 {
1364 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1365 int r;
1366
1367 if (ntex == NULL)
1368 return -ENOMEM;
1369 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1370
1371 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1372 if (bc->cf_last != NULL &&
1373 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
1374 struct r600_bytecode_tex *ttex;
1375 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1376 if (ttex->dst_gpr == ntex->src_gpr) {
1377 bc->force_add_cf = 1;
1378 break;
1379 }
1380 }
1381 /* slight hack to make gradients always go into same cf */
1382 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1383 bc->force_add_cf = 1;
1384 }
1385
1386 /* cf can contains only alu or only vtx or only tex */
1387 if (bc->cf_last == NULL ||
1388 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1389 bc->force_add_cf) {
1390 r = r600_bytecode_add_cf(bc);
1391 if (r) {
1392 free(ntex);
1393 return r;
1394 }
1395 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1396 }
1397 if (ntex->src_gpr >= bc->ngpr) {
1398 bc->ngpr = ntex->src_gpr + 1;
1399 }
1400 if (ntex->dst_gpr >= bc->ngpr) {
1401 bc->ngpr = ntex->dst_gpr + 1;
1402 }
1403 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1404 /* each texture fetch use 4 dwords */
1405 bc->cf_last->ndw += 4;
1406 bc->ndw += 4;
1407 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1408 bc->force_add_cf = 1;
1409 return 0;
1410 }
1411
1412 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1413 {
1414 int r;
1415 r = r600_bytecode_add_cf(bc);
1416 if (r)
1417 return r;
1418
1419 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1420 bc->cf_last->inst = inst;
1421 return 0;
1422 }
1423
1424 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1425 {
1426 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1427 }
1428
1429 /* common to all 3 families */
1430 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1431 {
1432 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1433 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1434 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1435 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1436 if (bc->chip_class < CAYMAN)
1437 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1438 id++;
1439 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1440 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1441 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1442 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1443 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1444 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1445 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1446 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1447 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1448 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1449 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1450 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1451 if (bc->chip_class < CAYMAN)
1452 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1453 id++;
1454 bc->bytecode[id++] = 0;
1455 return 0;
1456 }
1457
1458 /* common to all 3 families */
1459 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1460 {
1461 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1462 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1463 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1464 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1465 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1466 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1467 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1468 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1469 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1470 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1471 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1472 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1473 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1474 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1475 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1476 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1477 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1478 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1479 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1480 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1481 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1482 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1483 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1484 bc->bytecode[id++] = 0;
1485 return 0;
1486 }
1487
1488 /* r600 only, r700/eg bits in r700_asm.c */
1489 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1490 {
1491 /* don't replace gpr by pv or ps for destination register */
1492 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1493 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1494 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1495 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1496 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1497 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1498 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1499 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1500 S_SQ_ALU_WORD0_LAST(alu->last);
1501
1502 if (alu->is_op3) {
1503 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1504 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1505 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1506 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1507 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1508 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1509 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1510 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1511 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1512 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1513 } else {
1514 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1515 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1516 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1517 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1518 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1519 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1520 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1521 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1522 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1523 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1524 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1525 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1526 }
1527 return 0;
1528 }
1529
1530 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1531 {
1532 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1533 *bytecode++ = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1534 S_SQ_CF_WORD1_BARRIER(1) |
1535 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1536 }
1537
1538 /* common for r600/r700 - eg in eg_asm.c */
1539 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1540 {
1541 unsigned id = cf->id;
1542
1543 switch (cf->inst) {
1544 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1545 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1546 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1547 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1548 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1549 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1550 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1551 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1552
1553 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1554 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1555 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1556 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1557 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1558 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1559 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1560 break;
1561 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1562 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1563 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1564 if (bc->chip_class == R700)
1565 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1566 else
1567 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1568 break;
1569 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1570 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1571 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1572 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1573 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1574 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1575 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1576 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1577 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1578 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1579 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1580 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1581 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1582 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1583 break;
1584 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1585 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1586 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1587 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1588 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1589 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1590 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1591 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1592 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1593 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1594 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1595 S_SQ_CF_WORD1_BARRIER(1) |
1596 S_SQ_CF_WORD1_COND(cf->cond) |
1597 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1598
1599 break;
1600 default:
1601 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1602 return -EINVAL;
1603 }
1604 return 0;
1605 }
1606
1607 int r600_bytecode_build(struct r600_bytecode *bc)
1608 {
1609 struct r600_bytecode_cf *cf;
1610 struct r600_bytecode_alu *alu;
1611 struct r600_bytecode_vtx *vtx;
1612 struct r600_bytecode_tex *tex;
1613 uint32_t literal[4];
1614 unsigned nliteral;
1615 unsigned addr;
1616 int i, r;
1617
1618 if (bc->callstack[0].max > 0)
1619 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1620 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1621 bc->nstack = 1;
1622 }
1623
1624 /* first path compute addr of each CF block */
1625 /* addr start after all the CF instructions */
1626 addr = bc->cf_last->id + 2;
1627 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1628 switch (cf->inst) {
1629 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1630 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1631 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1632 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1633 break;
1634 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1635 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1636 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1637 /* fetch node need to be 16 bytes aligned*/
1638 addr += 3;
1639 addr &= 0xFFFFFFFCUL;
1640 break;
1641 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1642 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1643 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1644 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1645 break;
1646 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1647 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1648 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1649 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1650 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1651 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1652 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1653 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1654 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1655 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1656 break;
1657 default:
1658 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1659 return -EINVAL;
1660 }
1661 cf->addr = addr;
1662 addr += cf->ndw;
1663 bc->ndw = cf->addr + cf->ndw;
1664 }
1665 free(bc->bytecode);
1666 bc->bytecode = calloc(1, bc->ndw * 4);
1667 if (bc->bytecode == NULL)
1668 return -ENOMEM;
1669 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1670 addr = cf->addr;
1671 if (bc->chip_class >= EVERGREEN)
1672 r = eg_bytecode_cf_build(bc, cf);
1673 else
1674 r = r600_bytecode_cf_build(bc, cf);
1675 if (r)
1676 return r;
1677 switch (cf->inst) {
1678 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1679 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1680 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1681 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1682 nliteral = 0;
1683 memset(literal, 0, sizeof(literal));
1684 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1685 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1686 if (r)
1687 return r;
1688 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1689 switch(bc->chip_class) {
1690 case R600:
1691 r = r600_bytecode_alu_build(bc, alu, addr);
1692 break;
1693 case R700:
1694 case EVERGREEN: /* eg alu is same encoding as r700 */
1695 case CAYMAN: /* eg alu is same encoding as r700 */
1696 r = r700_bytecode_alu_build(bc, alu, addr);
1697 break;
1698 default:
1699 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1700 return -EINVAL;
1701 }
1702 if (r)
1703 return r;
1704 addr += 2;
1705 if (alu->last) {
1706 for (i = 0; i < align(nliteral, 2); ++i) {
1707 bc->bytecode[addr++] = literal[i];
1708 }
1709 nliteral = 0;
1710 memset(literal, 0, sizeof(literal));
1711 }
1712 }
1713 break;
1714 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1715 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1716 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1717 r = r600_bytecode_vtx_build(bc, vtx, addr);
1718 if (r)
1719 return r;
1720 addr += 4;
1721 }
1722 break;
1723 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1724 if (bc->chip_class == CAYMAN) {
1725 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1726 r = r600_bytecode_vtx_build(bc, vtx, addr);
1727 if (r)
1728 return r;
1729 addr += 4;
1730 }
1731 }
1732 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1733 r = r600_bytecode_tex_build(bc, tex, addr);
1734 if (r)
1735 return r;
1736 addr += 4;
1737 }
1738 break;
1739 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1740 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1741 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1742 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1743 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1744 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1745 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1746 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1747 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1748 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1749 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1750 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1751 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1752 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1753 break;
1754 default:
1755 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1756 return -EINVAL;
1757 }
1758 }
1759 return 0;
1760 }
1761
1762 void r600_bytecode_clear(struct r600_bytecode *bc)
1763 {
1764 struct r600_bytecode_cf *cf = NULL, *next_cf;
1765
1766 free(bc->bytecode);
1767 bc->bytecode = NULL;
1768
1769 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1770 struct r600_bytecode_alu *alu = NULL, *next_alu;
1771 struct r600_bytecode_tex *tex = NULL, *next_tex;
1772 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1773
1774 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1775 free(alu);
1776 }
1777
1778 LIST_INITHEAD(&cf->alu);
1779
1780 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1781 free(tex);
1782 }
1783
1784 LIST_INITHEAD(&cf->tex);
1785
1786 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1787 free(vtx);
1788 }
1789
1790 LIST_INITHEAD(&cf->vtx);
1791
1792 free(cf);
1793 }
1794
1795 LIST_INITHEAD(&cf->list);
1796 }
1797
1798 void r600_bytecode_dump(struct r600_bytecode *bc)
1799 {
1800 struct r600_bytecode_cf *cf = NULL;
1801 struct r600_bytecode_alu *alu = NULL;
1802 struct r600_bytecode_vtx *vtx = NULL;
1803 struct r600_bytecode_tex *tex = NULL;
1804
1805 unsigned i, id;
1806 uint32_t literal[4];
1807 unsigned nliteral;
1808 char chip = '6';
1809
1810 switch (bc->chip_class) {
1811 case R700:
1812 chip = '7';
1813 break;
1814 case EVERGREEN:
1815 chip = 'E';
1816 break;
1817 case CAYMAN:
1818 chip = 'C';
1819 break;
1820 case R600:
1821 default:
1822 chip = '6';
1823 break;
1824 }
1825 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1826 fprintf(stderr, " %c\n", chip);
1827
1828 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1829 id = cf->id;
1830
1831 switch (cf->inst) {
1832 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1833 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1834 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1835 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1836 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1837 fprintf(stderr, "ADDR:%d ", cf->addr);
1838 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1839 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1840 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1841 id++;
1842 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1843 fprintf(stderr, "INST:%d ", cf->inst);
1844 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1845 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1846 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1847 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1848 break;
1849 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1850 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1851 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1852 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1853 fprintf(stderr, "ADDR:%d\n", cf->addr);
1854 id++;
1855 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1856 fprintf(stderr, "INST:%d ", cf->inst);
1857 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1858 break;
1859 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1860 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1861 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1862 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1863 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1864 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1865 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1866 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1867 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1868 id++;
1869 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1870 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1871 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1872 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1873 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1874 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1875 fprintf(stderr, "INST:%d ", cf->output.inst);
1876 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
1877 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1878 break;
1879 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1880 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1881 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1882 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1883 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1884 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1885 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1886 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1887 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1888 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1889 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1890 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1891 id++;
1892 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1893 fprintf(stderr, "INST:%d ", cf->inst);
1894 fprintf(stderr, "COND:%X ", cf->cond);
1895 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1896 break;
1897 }
1898
1899 id = cf->addr;
1900 nliteral = 0;
1901 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1902 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1903
1904 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1905 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1906 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1907 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1908 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1909 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1910 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1911 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1912 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1913 fprintf(stderr, "LAST:%d)\n", alu->last);
1914 id++;
1915 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1916 fprintf(stderr, "INST:%d ", alu->inst);
1917 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1918 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1919 fprintf(stderr, "REL:%d ", alu->dst.rel);
1920 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1921 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1922 if (alu->is_op3) {
1923 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1924 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1925 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1926 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1927 } else {
1928 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1929 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1930 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1931 fprintf(stderr, "OMOD:%d ", alu->omod);
1932 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1933 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1934 }
1935
1936 id++;
1937 if (alu->last) {
1938 for (i = 0; i < nliteral; i++, id++) {
1939 float *f = (float*)(bc->bytecode + id);
1940 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1941 }
1942 id += nliteral & 1;
1943 nliteral = 0;
1944 }
1945 }
1946
1947 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1948 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1949 fprintf(stderr, "INST:%d ", tex->inst);
1950 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
1951 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
1952 fprintf(stderr, "REL:%d)\n", tex->src_rel);
1953 id++;
1954 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1955 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
1956 fprintf(stderr, "REL:%d ", tex->dst_rel);
1957 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
1958 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
1959 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
1960 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
1961 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
1962 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
1963 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
1964 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
1965 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
1966 id++;
1967 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1968 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
1969 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
1970 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
1971 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
1972 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
1973 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
1974 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
1975 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
1976 id++;
1977 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
1978 id++;
1979 }
1980
1981 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1982 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1983 fprintf(stderr, "INST:%d ", vtx->inst);
1984 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
1985 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
1986 id++;
1987 /* This assumes that no semantic fetches exist */
1988 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1989 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
1990 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
1991 if (bc->chip_class < CAYMAN)
1992 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
1993 else
1994 fprintf(stderr, "SEL_Y:%d) ", 0);
1995 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
1996 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
1997 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
1998 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
1999 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2000 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2001 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2002 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2003 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2004 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2005 id++;
2006 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2007 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2008 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2009 /* TODO */
2010 id++;
2011 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2012 id++;
2013 }
2014 }
2015
2016 fprintf(stderr, "--------------------------------------\n");
2017 }
2018
2019 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
2020 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2021 {
2022 const struct util_format_description *desc;
2023 unsigned i;
2024
2025 *format = 0;
2026 *num_format = 0;
2027 *format_comp = 0;
2028 *endian = ENDIAN_NONE;
2029
2030 desc = util_format_description(pformat);
2031 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2032 goto out_unknown;
2033 }
2034
2035 /* Find the first non-VOID channel. */
2036 for (i = 0; i < 4; i++) {
2037 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2038 break;
2039 }
2040 }
2041
2042 *endian = r600_endian_swap(desc->channel[i].size);
2043
2044 switch (desc->channel[i].type) {
2045 /* Half-floats, floats, ints */
2046 case UTIL_FORMAT_TYPE_FLOAT:
2047 switch (desc->channel[i].size) {
2048 case 16:
2049 switch (desc->nr_channels) {
2050 case 1:
2051 *format = FMT_16_FLOAT;
2052 break;
2053 case 2:
2054 *format = FMT_16_16_FLOAT;
2055 break;
2056 case 3:
2057 case 4:
2058 *format = FMT_16_16_16_16_FLOAT;
2059 break;
2060 }
2061 break;
2062 case 32:
2063 switch (desc->nr_channels) {
2064 case 1:
2065 *format = FMT_32_FLOAT;
2066 break;
2067 case 2:
2068 *format = FMT_32_32_FLOAT;
2069 break;
2070 case 3:
2071 *format = FMT_32_32_32_FLOAT;
2072 break;
2073 case 4:
2074 *format = FMT_32_32_32_32_FLOAT;
2075 break;
2076 }
2077 break;
2078 default:
2079 goto out_unknown;
2080 }
2081 break;
2082 /* Unsigned ints */
2083 case UTIL_FORMAT_TYPE_UNSIGNED:
2084 /* Signed ints */
2085 case UTIL_FORMAT_TYPE_SIGNED:
2086 switch (desc->channel[i].size) {
2087 case 8:
2088 switch (desc->nr_channels) {
2089 case 1:
2090 *format = FMT_8;
2091 break;
2092 case 2:
2093 *format = FMT_8_8;
2094 break;
2095 case 3:
2096 case 4:
2097 *format = FMT_8_8_8_8;
2098 break;
2099 }
2100 break;
2101 case 10:
2102 if (desc->nr_channels != 4)
2103 goto out_unknown;
2104
2105 *format = FMT_2_10_10_10;
2106 break;
2107 case 16:
2108 switch (desc->nr_channels) {
2109 case 1:
2110 *format = FMT_16;
2111 break;
2112 case 2:
2113 *format = FMT_16_16;
2114 break;
2115 case 3:
2116 case 4:
2117 *format = FMT_16_16_16_16;
2118 break;
2119 }
2120 break;
2121 case 32:
2122 switch (desc->nr_channels) {
2123 case 1:
2124 *format = FMT_32;
2125 break;
2126 case 2:
2127 *format = FMT_32_32;
2128 break;
2129 case 3:
2130 *format = FMT_32_32_32;
2131 break;
2132 case 4:
2133 *format = FMT_32_32_32_32;
2134 break;
2135 }
2136 break;
2137 default:
2138 goto out_unknown;
2139 }
2140 break;
2141 default:
2142 goto out_unknown;
2143 }
2144
2145 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2146 *format_comp = 1;
2147 }
2148 if (desc->channel[i].normalized) {
2149 *num_format = 0;
2150 } else {
2151 *num_format = 2;
2152 }
2153 return;
2154 out_unknown:
2155 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2156 }
2157
2158 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2159 {
2160 static int dump_shaders = -1;
2161
2162 struct r600_bytecode bc;
2163 struct r600_bytecode_vtx vtx;
2164 struct pipe_vertex_element *elements = ve->elements;
2165 const struct util_format_description *desc;
2166 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2167 unsigned format, num_format, format_comp, endian;
2168 u32 *bytecode;
2169 int i, r;
2170
2171 /* Vertex element offsets need special handling. If the offset is
2172 * bigger than what we can put in the fetch instruction we need to
2173 * alter the vertex resource offset. In order to simplify code we
2174 * will bind one resource per element in such cases. It's a worst
2175 * case scenario. */
2176 for (i = 0; i < ve->count; i++) {
2177 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2178 if (ve->vbuffer_offset[i]) {
2179 ve->vbuffer_need_offset = 1;
2180 }
2181 }
2182
2183 memset(&bc, 0, sizeof(bc));
2184 r600_bytecode_init(&bc, rctx->chip_class);
2185
2186 for (i = 0; i < ve->count; i++) {
2187 if (elements[i].instance_divisor > 1) {
2188 struct r600_bytecode_alu alu;
2189
2190 memset(&alu, 0, sizeof(alu));
2191 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2192 alu.src[0].sel = 0;
2193 alu.src[0].chan = 3;
2194
2195 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2196 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2197
2198 alu.dst.sel = i + 1;
2199 alu.dst.chan = 3;
2200 alu.dst.write = 1;
2201 alu.last = 1;
2202
2203 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2204 r600_bytecode_clear(&bc);
2205 return r;
2206 }
2207 }
2208 }
2209
2210 for (i = 0; i < ve->count; i++) {
2211 unsigned vbuffer_index;
2212 r600_vertex_data_type(ve->elements[i].src_format, &format, &num_format, &format_comp, &endian);
2213 desc = util_format_description(ve->elements[i].src_format);
2214 if (desc == NULL) {
2215 r600_bytecode_clear(&bc);
2216 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2217 return -EINVAL;
2218 }
2219
2220 /* see above for vbuffer_need_offset explanation */
2221 vbuffer_index = elements[i].vertex_buffer_index;
2222 memset(&vtx, 0, sizeof(vtx));
2223 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2224 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2225 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2226 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2227 vtx.mega_fetch_count = 0x1F;
2228 vtx.dst_gpr = i + 1;
2229 vtx.dst_sel_x = desc->swizzle[0];
2230 vtx.dst_sel_y = desc->swizzle[1];
2231 vtx.dst_sel_z = desc->swizzle[2];
2232 vtx.dst_sel_w = desc->swizzle[3];
2233 vtx.data_format = format;
2234 vtx.num_format_all = num_format;
2235 vtx.format_comp_all = format_comp;
2236 vtx.srf_mode_all = 1;
2237 vtx.offset = elements[i].src_offset;
2238 vtx.endian = endian;
2239
2240 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2241 r600_bytecode_clear(&bc);
2242 return r;
2243 }
2244 }
2245
2246 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2247
2248 if ((r = r600_bytecode_build(&bc))) {
2249 r600_bytecode_clear(&bc);
2250 return r;
2251 }
2252
2253 if (dump_shaders == -1)
2254 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2255
2256 if (dump_shaders) {
2257 fprintf(stderr, "--------------------------------------------------------------\n");
2258 r600_bytecode_dump(&bc);
2259 fprintf(stderr, "______________________________________________________________\n");
2260 }
2261
2262 ve->fs_size = bc.ndw*4;
2263
2264 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
2265 ve->fetch_shader = r600_bo(rctx->radeon, ve->fs_size, 256, PIPE_BIND_VERTEX_BUFFER, PIPE_USAGE_IMMUTABLE);
2266 if (ve->fetch_shader == NULL) {
2267 r600_bytecode_clear(&bc);
2268 return -ENOMEM;
2269 }
2270
2271 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
2272 if (bytecode == NULL) {
2273 r600_bytecode_clear(&bc);
2274 r600_bo_reference(&ve->fetch_shader, NULL);
2275 return -ENOMEM;
2276 }
2277
2278 if (R600_BIG_ENDIAN) {
2279 for (i = 0; i < ve->fs_size / 4; ++i) {
2280 bytecode[i] = bswap_32(bc.bytecode[i]);
2281 }
2282 } else {
2283 memcpy(bytecode, bc.bytecode, ve->fs_size);
2284 }
2285
2286 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
2287 r600_bytecode_clear(&bc);
2288
2289 if (rctx->chip_class >= EVERGREEN)
2290 evergreen_fetch_shader(&rctx->context, ve);
2291 else
2292 r600_fetch_shader(&rctx->context, ve);
2293
2294 return 0;
2295 }