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gallium/drivers: Sanitize NULL checks into canonical form
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
34
35 #include "sb/sb_public.h"
36
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
39
40 static inline bool alu_writes(struct r600_bytecode_alu *alu)
41 {
42 return alu->dst.write || alu->is_op3;
43 }
44
45 static inline unsigned int r600_bytecode_get_num_operands(
46 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
47 {
48 return r600_isa_alu(alu->op)->src_count;
49 }
50
51 int r700_bytecode_alu_build(struct r600_bytecode *bc,
52 struct r600_bytecode_alu *alu, unsigned id);
53
54 static struct r600_bytecode_cf *r600_bytecode_cf(void)
55 {
56 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
57
58 if (!cf)
59 return NULL;
60 LIST_INITHEAD(&cf->list);
61 LIST_INITHEAD(&cf->alu);
62 LIST_INITHEAD(&cf->vtx);
63 LIST_INITHEAD(&cf->tex);
64 return cf;
65 }
66
67 static struct r600_bytecode_alu *r600_bytecode_alu(void)
68 {
69 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
70
71 if (!alu)
72 return NULL;
73 LIST_INITHEAD(&alu->list);
74 return alu;
75 }
76
77 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
78 {
79 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
80
81 if (!vtx)
82 return NULL;
83 LIST_INITHEAD(&vtx->list);
84 return vtx;
85 }
86
87 static struct r600_bytecode_tex *r600_bytecode_tex(void)
88 {
89 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
90
91 if (!tex)
92 return NULL;
93 LIST_INITHEAD(&tex->list);
94 return tex;
95 }
96
97 static unsigned stack_entry_size(enum radeon_family chip) {
98 /* Wavefront size:
99 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
100 * Aruba/Sumo/Sumo2/redwood/juniper
101 * 32: R630/R730/R710/Palm/Cedar
102 * 16: R610/Rs780
103 *
104 * Stack row size:
105 * Wavefront Size 16 32 48 64
106 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
107 * Columns per Row (R9xx+) 8 4 4 4 */
108
109 switch (chip) {
110 /* FIXME: are some chips missing here? */
111 /* wavefront size 16 */
112 case CHIP_RV610:
113 case CHIP_RS780:
114 case CHIP_RV620:
115 case CHIP_RS880:
116 /* wavefront size 32 */
117 case CHIP_RV630:
118 case CHIP_RV635:
119 case CHIP_RV730:
120 case CHIP_RV710:
121 case CHIP_PALM:
122 case CHIP_CEDAR:
123 return 8;
124
125 /* wavefront size 64 */
126 default:
127 return 4;
128 }
129 }
130
131 void r600_bytecode_init(struct r600_bytecode *bc,
132 enum chip_class chip_class,
133 enum radeon_family family,
134 bool has_compressed_msaa_texturing)
135 {
136 static unsigned next_shader_id = 0;
137
138 bc->debug_id = ++next_shader_id;
139
140 if ((chip_class == R600) &&
141 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
142 bc->ar_handling = AR_HANDLE_RV6XX;
143 bc->r6xx_nop_after_rel_dst = 1;
144 } else {
145 bc->ar_handling = AR_HANDLE_NORMAL;
146 bc->r6xx_nop_after_rel_dst = 0;
147 }
148
149 LIST_INITHEAD(&bc->cf);
150 bc->chip_class = chip_class;
151 bc->family = family;
152 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
153 bc->stack.entry_size = stack_entry_size(family);
154 }
155
156 int r600_bytecode_add_cf(struct r600_bytecode *bc)
157 {
158 struct r600_bytecode_cf *cf = r600_bytecode_cf();
159
160 if (!cf)
161 return -ENOMEM;
162 LIST_ADDTAIL(&cf->list, &bc->cf);
163 if (bc->cf_last) {
164 cf->id = bc->cf_last->id + 2;
165 if (bc->cf_last->eg_alu_extended) {
166 /* take into account extended alu size */
167 cf->id += 2;
168 bc->ndw += 2;
169 }
170 }
171 bc->cf_last = cf;
172 bc->ncf++;
173 bc->ndw += 2;
174 bc->force_add_cf = 0;
175 bc->ar_loaded = 0;
176 return 0;
177 }
178
179 int r600_bytecode_add_output(struct r600_bytecode *bc,
180 const struct r600_bytecode_output *output)
181 {
182 int r;
183
184 if (output->gpr >= bc->ngpr)
185 bc->ngpr = output->gpr + 1;
186
187 if (bc->cf_last && (bc->cf_last->op == output->op ||
188 (bc->cf_last->op == CF_OP_EXPORT &&
189 output->op == CF_OP_EXPORT_DONE)) &&
190 output->type == bc->cf_last->output.type &&
191 output->elem_size == bc->cf_last->output.elem_size &&
192 output->swizzle_x == bc->cf_last->output.swizzle_x &&
193 output->swizzle_y == bc->cf_last->output.swizzle_y &&
194 output->swizzle_z == bc->cf_last->output.swizzle_z &&
195 output->swizzle_w == bc->cf_last->output.swizzle_w &&
196 output->comp_mask == bc->cf_last->output.comp_mask &&
197 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
198
199 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
200 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
201
202 bc->cf_last->op = bc->cf_last->output.op = output->op;
203 bc->cf_last->output.gpr = output->gpr;
204 bc->cf_last->output.array_base = output->array_base;
205 bc->cf_last->output.burst_count += output->burst_count;
206 return 0;
207
208 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
209 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
210
211 bc->cf_last->op = bc->cf_last->output.op = output->op;
212 bc->cf_last->output.burst_count += output->burst_count;
213 return 0;
214 }
215 }
216
217 r = r600_bytecode_add_cf(bc);
218 if (r)
219 return r;
220 bc->cf_last->op = output->op;
221 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
222 bc->cf_last->barrier = 1;
223 return 0;
224 }
225
226 /* alu instructions that can ony exits once per group */
227 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
228 {
229 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
230 }
231
232 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
233 {
234 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
235 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
236 }
237
238 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
239 {
240 return r600_isa_alu(alu->op)->flags & AF_MOVA;
241 }
242
243 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
244 {
245 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
246 unsigned src;
247
248 if (alu->dst.rel) {
249 return 1;
250 }
251
252 for (src = 0; src < num_src; ++src) {
253 if (alu->src[src].rel) {
254 return 1;
255 }
256 }
257 return 0;
258 }
259
260 static int is_alu_64bit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
261 {
262 const struct alu_op_info *op = r600_isa_alu(alu->op);
263 return (op->flags & AF_64);
264 }
265
266 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
267 {
268 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
269 return !(slots & AF_S);
270 }
271
272 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
273 {
274 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
275 return !(slots & AF_V);
276 }
277
278 /* alu instructions that can execute on any unit */
279 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
280 {
281 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
282 return slots == AF_VS;
283 }
284
285 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
286 {
287 return alu->op == ALU_OP0_NOP;
288 }
289
290 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
291 struct r600_bytecode_alu *assignment[5])
292 {
293 struct r600_bytecode_alu *alu;
294 unsigned i, chan, trans;
295 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
296
297 for (i = 0; i < max_slots; i++)
298 assignment[i] = NULL;
299
300 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
301 chan = alu->dst.chan;
302 if (max_slots == 4)
303 trans = 0;
304 else if (is_alu_trans_unit_inst(bc, alu))
305 trans = 1;
306 else if (is_alu_vec_unit_inst(bc, alu))
307 trans = 0;
308 else if (assignment[chan])
309 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
310 else
311 trans = 0;
312
313 if (trans) {
314 if (assignment[4]) {
315 assert(0); /* ALU.Trans has already been allocated. */
316 return -1;
317 }
318 assignment[4] = alu;
319 } else {
320 if (assignment[chan]) {
321 assert(0); /* ALU.chan has already been allocated. */
322 return -1;
323 }
324 assignment[chan] = alu;
325 }
326
327 if (alu->last)
328 break;
329 }
330 return 0;
331 }
332
333 struct alu_bank_swizzle {
334 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
335 int hw_cfile_addr[4];
336 int hw_cfile_elem[4];
337 };
338
339 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
340 [SQ_ALU_VEC_012] = { 0, 1, 2 },
341 [SQ_ALU_VEC_021] = { 0, 2, 1 },
342 [SQ_ALU_VEC_120] = { 1, 2, 0 },
343 [SQ_ALU_VEC_102] = { 1, 0, 2 },
344 [SQ_ALU_VEC_201] = { 2, 0, 1 },
345 [SQ_ALU_VEC_210] = { 2, 1, 0 }
346 };
347
348 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
349 [SQ_ALU_SCL_210] = { 2, 1, 0 },
350 [SQ_ALU_SCL_122] = { 1, 2, 2 },
351 [SQ_ALU_SCL_212] = { 2, 1, 2 },
352 [SQ_ALU_SCL_221] = { 2, 2, 1 }
353 };
354
355 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
356 {
357 int i, cycle, component;
358 /* set up gpr use */
359 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
360 for (component = 0; component < NUM_OF_COMPONENTS; component++)
361 bs->hw_gpr[cycle][component] = -1;
362 for (i = 0; i < 4; i++)
363 bs->hw_cfile_addr[i] = -1;
364 for (i = 0; i < 4; i++)
365 bs->hw_cfile_elem[i] = -1;
366 }
367
368 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
369 {
370 if (bs->hw_gpr[cycle][chan] == -1)
371 bs->hw_gpr[cycle][chan] = sel;
372 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
373 /* Another scalar operation has already used the GPR read port for the channel. */
374 return -1;
375 }
376 return 0;
377 }
378
379 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
380 {
381 int res, num_res = 4;
382 if (bc->chip_class >= R700) {
383 num_res = 2;
384 chan /= 2;
385 }
386 for (res = 0; res < num_res; ++res) {
387 if (bs->hw_cfile_addr[res] == -1) {
388 bs->hw_cfile_addr[res] = sel;
389 bs->hw_cfile_elem[res] = chan;
390 return 0;
391 } else if (bs->hw_cfile_addr[res] == sel &&
392 bs->hw_cfile_elem[res] == chan)
393 return 0; /* Read for this scalar element already reserved, nothing to do here. */
394 }
395 /* All cfile read ports are used, cannot reference vector element. */
396 return -1;
397 }
398
399 static int is_gpr(unsigned sel)
400 {
401 return (sel <= 127);
402 }
403
404 /* CB constants start at 512, and get translated to a kcache index when ALU
405 * clauses are constructed. Note that we handle kcache constants the same way
406 * as (the now gone) cfile constants, is that really required? */
407 static int is_cfile(unsigned sel)
408 {
409 return (sel > 255 && sel < 512) ||
410 (sel > 511 && sel < 4607) || /* Kcache before translation. */
411 (sel > 127 && sel < 192); /* Kcache after translation. */
412 }
413
414 static int is_const(int sel)
415 {
416 return is_cfile(sel) ||
417 (sel >= V_SQ_ALU_SRC_0 &&
418 sel <= V_SQ_ALU_SRC_LITERAL);
419 }
420
421 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
422 struct alu_bank_swizzle *bs, int bank_swizzle)
423 {
424 int r, src, num_src, sel, elem, cycle;
425
426 num_src = r600_bytecode_get_num_operands(bc, alu);
427 for (src = 0; src < num_src; src++) {
428 sel = alu->src[src].sel;
429 elem = alu->src[src].chan;
430 if (is_gpr(sel)) {
431 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
432 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
433 /* Nothing to do; special-case optimization,
434 * second source uses first source’s reservation. */
435 continue;
436 else {
437 r = reserve_gpr(bs, sel, elem, cycle);
438 if (r)
439 return r;
440 }
441 } else if (is_cfile(sel)) {
442 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
443 if (r)
444 return r;
445 }
446 /* No restrictions on PV, PS, literal or special constants. */
447 }
448 return 0;
449 }
450
451 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
452 struct alu_bank_swizzle *bs, int bank_swizzle)
453 {
454 int r, src, num_src, const_count, sel, elem, cycle;
455
456 num_src = r600_bytecode_get_num_operands(bc, alu);
457 for (const_count = 0, src = 0; src < num_src; ++src) {
458 sel = alu->src[src].sel;
459 elem = alu->src[src].chan;
460 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
461 if (const_count >= 2)
462 /* More than two references to a constant in
463 * transcendental operation. */
464 return -1;
465 else
466 const_count++;
467 }
468 if (is_cfile(sel)) {
469 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
470 if (r)
471 return r;
472 }
473 }
474 for (src = 0; src < num_src; ++src) {
475 sel = alu->src[src].sel;
476 elem = alu->src[src].chan;
477 if (is_gpr(sel)) {
478 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
479 if (cycle < const_count)
480 /* Cycle for GPR load conflicts with
481 * constant load in transcendental operation. */
482 return -1;
483 r = reserve_gpr(bs, sel, elem, cycle);
484 if (r)
485 return r;
486 }
487 /* PV PS restrictions */
488 if (const_count && (sel == 254 || sel == 255)) {
489 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
490 if (cycle < const_count)
491 return -1;
492 }
493 }
494 return 0;
495 }
496
497 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
498 struct r600_bytecode_alu *slots[5])
499 {
500 struct alu_bank_swizzle bs;
501 int bank_swizzle[5];
502 int i, r = 0, forced = 1;
503 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
504 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
505
506 for (i = 0; i < max_slots; i++) {
507 if (slots[i]) {
508 if (slots[i]->bank_swizzle_force) {
509 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
510 } else {
511 forced = 0;
512 }
513 }
514
515 if (i < 4 && slots[i])
516 scalar_only = false;
517 }
518 if (forced)
519 return 0;
520
521 /* Just check every possible combination of bank swizzle.
522 * Not very efficent, but works on the first try in most of the cases. */
523 for (i = 0; i < 4; i++)
524 if (!slots[i] || !slots[i]->bank_swizzle_force)
525 bank_swizzle[i] = SQ_ALU_VEC_012;
526 else
527 bank_swizzle[i] = slots[i]->bank_swizzle;
528
529 bank_swizzle[4] = SQ_ALU_SCL_210;
530 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
531
532 init_bank_swizzle(&bs);
533 if (scalar_only == false) {
534 for (i = 0; i < 4; i++) {
535 if (slots[i]) {
536 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
537 if (r)
538 break;
539 }
540 }
541 } else
542 r = 0;
543
544 if (!r && max_slots == 5 && slots[4]) {
545 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
546 }
547 if (!r) {
548 for (i = 0; i < max_slots; i++) {
549 if (slots[i])
550 slots[i]->bank_swizzle = bank_swizzle[i];
551 }
552 return 0;
553 }
554
555 if (scalar_only) {
556 bank_swizzle[4]++;
557 } else {
558 for (i = 0; i < max_slots; i++) {
559 if (!slots[i] || !slots[i]->bank_swizzle_force) {
560 bank_swizzle[i]++;
561 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
562 break;
563 else if (i < max_slots - 1)
564 bank_swizzle[i] = SQ_ALU_VEC_012;
565 else
566 return -1;
567 }
568 }
569 }
570 }
571
572 /* Couldn't find a working swizzle. */
573 return -1;
574 }
575
576 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
577 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
578 {
579 struct r600_bytecode_alu *prev[5];
580 int gpr[5], chan[5];
581 int i, j, r, src, num_src;
582 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
583
584 r = assign_alu_units(bc, alu_prev, prev);
585 if (r)
586 return r;
587
588 for (i = 0; i < max_slots; ++i) {
589 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
590
591 if (is_alu_64bit_inst(bc, prev[i])) {
592 gpr[i] = -1;
593 continue;
594 }
595
596 gpr[i] = prev[i]->dst.sel;
597 /* cube writes more than PV.X */
598 if (is_alu_reduction_inst(bc, prev[i]))
599 chan[i] = 0;
600 else
601 chan[i] = prev[i]->dst.chan;
602 } else
603 gpr[i] = -1;
604 }
605
606 for (i = 0; i < max_slots; ++i) {
607 struct r600_bytecode_alu *alu = slots[i];
608 if (!alu)
609 continue;
610
611 if (is_alu_64bit_inst(bc, alu))
612 continue;
613 num_src = r600_bytecode_get_num_operands(bc, alu);
614 for (src = 0; src < num_src; ++src) {
615 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
616 continue;
617
618 if (bc->chip_class < CAYMAN) {
619 if (alu->src[src].sel == gpr[4] &&
620 alu->src[src].chan == chan[4] &&
621 alu_prev->pred_sel == alu->pred_sel) {
622 alu->src[src].sel = V_SQ_ALU_SRC_PS;
623 alu->src[src].chan = 0;
624 continue;
625 }
626 }
627
628 for (j = 0; j < 4; ++j) {
629 if (alu->src[src].sel == gpr[j] &&
630 alu->src[src].chan == j &&
631 alu_prev->pred_sel == alu->pred_sel) {
632 alu->src[src].sel = V_SQ_ALU_SRC_PV;
633 alu->src[src].chan = chan[j];
634 break;
635 }
636 }
637 }
638 }
639
640 return 0;
641 }
642
643 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
644 {
645 switch(value) {
646 case 0:
647 *sel = V_SQ_ALU_SRC_0;
648 break;
649 case 1:
650 *sel = V_SQ_ALU_SRC_1_INT;
651 break;
652 case -1:
653 *sel = V_SQ_ALU_SRC_M_1_INT;
654 break;
655 case 0x3F800000: /* 1.0f */
656 *sel = V_SQ_ALU_SRC_1;
657 break;
658 case 0x3F000000: /* 0.5f */
659 *sel = V_SQ_ALU_SRC_0_5;
660 break;
661 case 0xBF800000: /* -1.0f */
662 *sel = V_SQ_ALU_SRC_1;
663 *neg ^= !abs;
664 break;
665 case 0xBF000000: /* -0.5f */
666 *sel = V_SQ_ALU_SRC_0_5;
667 *neg ^= !abs;
668 break;
669 default:
670 *sel = V_SQ_ALU_SRC_LITERAL;
671 break;
672 }
673 }
674
675 /* compute how many literal are needed */
676 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
677 uint32_t literal[4], unsigned *nliteral)
678 {
679 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
680 unsigned i, j;
681
682 for (i = 0; i < num_src; ++i) {
683 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
684 uint32_t value = alu->src[i].value;
685 unsigned found = 0;
686 for (j = 0; j < *nliteral; ++j) {
687 if (literal[j] == value) {
688 found = 1;
689 break;
690 }
691 }
692 if (!found) {
693 if (*nliteral >= 4)
694 return -EINVAL;
695 literal[(*nliteral)++] = value;
696 }
697 }
698 }
699 return 0;
700 }
701
702 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
703 struct r600_bytecode_alu *alu,
704 uint32_t literal[4], unsigned nliteral)
705 {
706 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
707 unsigned i, j;
708
709 for (i = 0; i < num_src; ++i) {
710 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
711 uint32_t value = alu->src[i].value;
712 for (j = 0; j < nliteral; ++j) {
713 if (literal[j] == value) {
714 alu->src[i].chan = j;
715 break;
716 }
717 }
718 }
719 }
720 }
721
722 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
723 struct r600_bytecode_alu *alu_prev)
724 {
725 struct r600_bytecode_alu *prev[5];
726 struct r600_bytecode_alu *result[5] = { NULL };
727
728 uint32_t literal[4], prev_literal[4];
729 unsigned nliteral = 0, prev_nliteral = 0;
730
731 int i, j, r, src, num_src;
732 int num_once_inst = 0;
733 int have_mova = 0, have_rel = 0;
734 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
735
736 r = assign_alu_units(bc, alu_prev, prev);
737 if (r)
738 return r;
739
740 for (i = 0; i < max_slots; ++i) {
741 if (prev[i]) {
742 if (prev[i]->pred_sel)
743 return 0;
744 if (is_alu_once_inst(bc, prev[i]))
745 return 0;
746 }
747 if (slots[i]) {
748 if (slots[i]->pred_sel)
749 return 0;
750 if (is_alu_once_inst(bc, slots[i]))
751 return 0;
752 }
753 }
754
755 for (i = 0; i < max_slots; ++i) {
756 struct r600_bytecode_alu *alu;
757
758 if (num_once_inst > 0)
759 return 0;
760
761 /* check number of literals */
762 if (prev[i]) {
763 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
764 return 0;
765 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
766 return 0;
767 if (is_alu_mova_inst(bc, prev[i])) {
768 if (have_rel)
769 return 0;
770 have_mova = 1;
771 }
772
773 if (alu_uses_rel(bc, prev[i])) {
774 if (have_mova) {
775 return 0;
776 }
777 have_rel = 1;
778 }
779
780 num_once_inst += is_alu_once_inst(bc, prev[i]);
781 }
782 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
783 return 0;
784
785 /* Let's check used slots. */
786 if (prev[i] && !slots[i]) {
787 result[i] = prev[i];
788 continue;
789 } else if (prev[i] && slots[i]) {
790 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
791 /* Trans unit is still free try to use it. */
792 if (is_alu_any_unit_inst(bc, slots[i])) {
793 result[i] = prev[i];
794 result[4] = slots[i];
795 } else if (is_alu_any_unit_inst(bc, prev[i])) {
796 if (slots[i]->dst.sel == prev[i]->dst.sel &&
797 alu_writes(slots[i]) &&
798 alu_writes(prev[i]))
799 return 0;
800
801 result[i] = slots[i];
802 result[4] = prev[i];
803 } else
804 return 0;
805 } else
806 return 0;
807 } else if(!slots[i]) {
808 continue;
809 } else {
810 if (max_slots == 5 && slots[i] && prev[4] &&
811 slots[i]->dst.sel == prev[4]->dst.sel &&
812 slots[i]->dst.chan == prev[4]->dst.chan &&
813 alu_writes(slots[i]) &&
814 alu_writes(prev[4]))
815 return 0;
816
817 result[i] = slots[i];
818 }
819
820 alu = slots[i];
821 num_once_inst += is_alu_once_inst(bc, alu);
822
823 /* don't reschedule NOPs */
824 if (is_nop_inst(bc, alu))
825 return 0;
826
827 if (is_alu_mova_inst(bc, alu)) {
828 if (have_rel) {
829 return 0;
830 }
831 have_mova = 1;
832 }
833
834 if (alu_uses_rel(bc, alu)) {
835 if (have_mova) {
836 return 0;
837 }
838 have_rel = 1;
839 }
840
841 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
842 alu->op == ALU_OP0_SET_CF_IDX1)
843 return 0; /* data hazard with MOVA */
844
845 /* Let's check source gprs */
846 num_src = r600_bytecode_get_num_operands(bc, alu);
847 for (src = 0; src < num_src; ++src) {
848
849 /* Constants don't matter. */
850 if (!is_gpr(alu->src[src].sel))
851 continue;
852
853 for (j = 0; j < max_slots; ++j) {
854 if (!prev[j] || !alu_writes(prev[j]))
855 continue;
856
857 /* If it's relative then we can't determin which gpr is really used. */
858 if (prev[j]->dst.chan == alu->src[src].chan &&
859 (prev[j]->dst.sel == alu->src[src].sel ||
860 prev[j]->dst.rel || alu->src[src].rel))
861 return 0;
862 }
863 }
864 }
865
866 /* more than one PRED_ or KILL_ ? */
867 if (num_once_inst > 1)
868 return 0;
869
870 /* check if the result can still be swizzlet */
871 r = check_and_set_bank_swizzle(bc, result);
872 if (r)
873 return 0;
874
875 /* looks like everything worked out right, apply the changes */
876
877 /* undo adding previus literals */
878 bc->cf_last->ndw -= align(prev_nliteral, 2);
879
880 /* sort instructions */
881 for (i = 0; i < max_slots; ++i) {
882 slots[i] = result[i];
883 if (result[i]) {
884 LIST_DEL(&result[i]->list);
885 result[i]->last = 0;
886 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
887 }
888 }
889
890 /* determine new last instruction */
891 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
892
893 /* determine new first instruction */
894 for (i = 0; i < max_slots; ++i) {
895 if (result[i]) {
896 bc->cf_last->curr_bs_head = result[i];
897 break;
898 }
899 }
900
901 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
902 bc->cf_last->prev2_bs_head = NULL;
903
904 return 0;
905 }
906
907 /* we'll keep kcache sets sorted by bank & addr */
908 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
909 struct r600_bytecode_kcache *kcache,
910 unsigned bank, unsigned line, unsigned index_mode)
911 {
912 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
913
914 for (i = 0; i < kcache_banks; i++) {
915 if (kcache[i].mode) {
916 int d;
917
918 if (kcache[i].bank < bank)
919 continue;
920
921 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
922 kcache[i].bank > bank) {
923 /* try to insert new line */
924 if (kcache[kcache_banks-1].mode) {
925 /* all sets are in use */
926 return -ENOMEM;
927 }
928
929 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
930 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
931 kcache[i].bank = bank;
932 kcache[i].addr = line;
933 kcache[i].index_mode = index_mode;
934 return 0;
935 }
936
937 d = line - kcache[i].addr;
938
939 if (d == -1) {
940 kcache[i].addr--;
941 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
942 /* we are prepending the line to the current set,
943 * discarding the existing second line,
944 * so we'll have to insert line+2 after it */
945 line += 2;
946 continue;
947 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
948 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
949 return 0;
950 } else {
951 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
952 return -ENOMEM;
953 }
954 } else if (d == 1) {
955 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
956 return 0;
957 } else if (d == 0)
958 return 0;
959 } else { /* free kcache set - use it */
960 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
961 kcache[i].bank = bank;
962 kcache[i].addr = line;
963 kcache[i].index_mode = index_mode;
964 return 0;
965 }
966 }
967 return -ENOMEM;
968 }
969
970 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
971 struct r600_bytecode_kcache *kcache,
972 struct r600_bytecode_alu *alu)
973 {
974 int i, r;
975
976 for (i = 0; i < 3; i++) {
977 unsigned bank, line, sel = alu->src[i].sel, index_mode;
978
979 if (sel < 512)
980 continue;
981
982 bank = alu->src[i].kc_bank;
983 line = (sel-512)>>4;
984 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
985
986 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
987 return r;
988 }
989 return 0;
990 }
991
992 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
993 struct r600_bytecode_alu *alu,
994 struct r600_bytecode_kcache * kcache)
995 {
996 int i, j;
997
998 /* Alter the src operands to refer to the kcache. */
999 for (i = 0; i < 3; ++i) {
1000 static const unsigned int base[] = {128, 160, 256, 288};
1001 unsigned int line, sel = alu->src[i].sel, found = 0;
1002
1003 if (sel < 512)
1004 continue;
1005
1006 sel -= 512;
1007 line = sel>>4;
1008
1009 for (j = 0; j < 4 && !found; ++j) {
1010 switch (kcache[j].mode) {
1011 case V_SQ_CF_KCACHE_NOP:
1012 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1013 R600_ERR("unexpected kcache line mode\n");
1014 return -ENOMEM;
1015 default:
1016 if (kcache[j].bank == alu->src[i].kc_bank &&
1017 kcache[j].addr <= line &&
1018 line < kcache[j].addr + kcache[j].mode) {
1019 alu->src[i].sel = sel - (kcache[j].addr<<4);
1020 alu->src[i].sel += base[j];
1021 found=1;
1022 }
1023 }
1024 }
1025 }
1026 return 0;
1027 }
1028
1029 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1030 struct r600_bytecode_alu *alu,
1031 unsigned type)
1032 {
1033 struct r600_bytecode_kcache kcache_sets[4];
1034 struct r600_bytecode_kcache *kcache = kcache_sets;
1035 int r;
1036
1037 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1038
1039 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1040 /* can't alloc, need to start new clause */
1041 if ((r = r600_bytecode_add_cf(bc))) {
1042 return r;
1043 }
1044 bc->cf_last->op = type;
1045
1046 /* retry with the new clause */
1047 kcache = bc->cf_last->kcache;
1048 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1049 /* can't alloc again- should never happen */
1050 return r;
1051 }
1052 } else {
1053 /* update kcache sets */
1054 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1055 }
1056
1057 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1058 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1059 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1060 if (bc->chip_class < EVERGREEN)
1061 return -ENOMEM;
1062 bc->cf_last->eg_alu_extended = 1;
1063 }
1064
1065 return 0;
1066 }
1067
1068 static int insert_nop_r6xx(struct r600_bytecode *bc)
1069 {
1070 struct r600_bytecode_alu alu;
1071 int r, i;
1072
1073 for (i = 0; i < 4; i++) {
1074 memset(&alu, 0, sizeof(alu));
1075 alu.op = ALU_OP0_NOP;
1076 alu.src[0].chan = i;
1077 alu.dst.chan = i;
1078 alu.last = (i == 3);
1079 r = r600_bytecode_add_alu(bc, &alu);
1080 if (r)
1081 return r;
1082 }
1083 return 0;
1084 }
1085
1086 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1087 static int load_ar_r6xx(struct r600_bytecode *bc)
1088 {
1089 struct r600_bytecode_alu alu;
1090 int r;
1091
1092 if (bc->ar_loaded)
1093 return 0;
1094
1095 /* hack to avoid making MOVA the last instruction in the clause */
1096 if ((bc->cf_last->ndw>>1) >= 110)
1097 bc->force_add_cf = 1;
1098
1099 memset(&alu, 0, sizeof(alu));
1100 alu.op = ALU_OP1_MOVA_GPR_INT;
1101 alu.src[0].sel = bc->ar_reg;
1102 alu.src[0].chan = bc->ar_chan;
1103 alu.last = 1;
1104 alu.index_mode = INDEX_MODE_LOOP;
1105 r = r600_bytecode_add_alu(bc, &alu);
1106 if (r)
1107 return r;
1108
1109 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1110 bc->ar_loaded = 1;
1111 return 0;
1112 }
1113
1114 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1115 static int load_ar(struct r600_bytecode *bc)
1116 {
1117 struct r600_bytecode_alu alu;
1118 int r;
1119
1120 if (bc->ar_handling)
1121 return load_ar_r6xx(bc);
1122
1123 if (bc->ar_loaded)
1124 return 0;
1125
1126 /* hack to avoid making MOVA the last instruction in the clause */
1127 if ((bc->cf_last->ndw>>1) >= 110)
1128 bc->force_add_cf = 1;
1129
1130 memset(&alu, 0, sizeof(alu));
1131 alu.op = ALU_OP1_MOVA_INT;
1132 alu.src[0].sel = bc->ar_reg;
1133 alu.src[0].chan = bc->ar_chan;
1134 alu.last = 1;
1135 r = r600_bytecode_add_alu(bc, &alu);
1136 if (r)
1137 return r;
1138
1139 bc->cf_last->r6xx_uses_waterfall = 1;
1140 bc->ar_loaded = 1;
1141 return 0;
1142 }
1143
1144 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1145 const struct r600_bytecode_alu *alu, unsigned type)
1146 {
1147 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1148 struct r600_bytecode_alu *lalu;
1149 int i, r;
1150
1151 if (!nalu)
1152 return -ENOMEM;
1153 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1154
1155 if (alu->is_op3) {
1156 /* will fail later since alu does not support it. */
1157 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1158 }
1159
1160 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1161 /* check if we could add it anyway */
1162 if (bc->cf_last->op == CF_OP_ALU &&
1163 type == CF_OP_ALU_PUSH_BEFORE) {
1164 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1165 if (lalu->execute_mask) {
1166 bc->force_add_cf = 1;
1167 break;
1168 }
1169 }
1170 } else
1171 bc->force_add_cf = 1;
1172 }
1173
1174 /* cf can contains only alu or only vtx or only tex */
1175 if (bc->cf_last == NULL || bc->force_add_cf) {
1176 r = r600_bytecode_add_cf(bc);
1177 if (r) {
1178 free(nalu);
1179 return r;
1180 }
1181 }
1182 bc->cf_last->op = type;
1183
1184 /* Load index register if required */
1185 if (bc->chip_class >= EVERGREEN) {
1186 for (i = 0; i < 3; i++)
1187 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1188 egcm_load_index_reg(bc, 0, true);
1189 }
1190
1191 /* Check AR usage and load it if required */
1192 for (i = 0; i < 3; i++)
1193 if (nalu->src[i].rel && !bc->ar_loaded)
1194 load_ar(bc);
1195
1196 if (nalu->dst.rel && !bc->ar_loaded)
1197 load_ar(bc);
1198
1199 /* Setup the kcache for this ALU instruction. This will start a new
1200 * ALU clause if needed. */
1201 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1202 free(nalu);
1203 return r;
1204 }
1205
1206 if (!bc->cf_last->curr_bs_head) {
1207 bc->cf_last->curr_bs_head = nalu;
1208 }
1209 /* number of gpr == the last gpr used in any alu */
1210 for (i = 0; i < 3; i++) {
1211 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1212 bc->ngpr = nalu->src[i].sel + 1;
1213 }
1214 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1215 r600_bytecode_special_constants(nalu->src[i].value,
1216 &nalu->src[i].sel, &nalu->src[i].neg, nalu->src[i].abs);
1217 }
1218 if (nalu->dst.sel >= bc->ngpr) {
1219 bc->ngpr = nalu->dst.sel + 1;
1220 }
1221 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1222 /* each alu use 2 dwords */
1223 bc->cf_last->ndw += 2;
1224 bc->ndw += 2;
1225
1226 /* process cur ALU instructions for bank swizzle */
1227 if (nalu->last) {
1228 uint32_t literal[4];
1229 unsigned nliteral;
1230 struct r600_bytecode_alu *slots[5];
1231 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1232 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1233 if (r)
1234 return r;
1235
1236 if (bc->cf_last->prev_bs_head) {
1237 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1238 if (r)
1239 return r;
1240 }
1241
1242 if (bc->cf_last->prev_bs_head) {
1243 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1244 if (r)
1245 return r;
1246 }
1247
1248 r = check_and_set_bank_swizzle(bc, slots);
1249 if (r)
1250 return r;
1251
1252 for (i = 0, nliteral = 0; i < max_slots; i++) {
1253 if (slots[i]) {
1254 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1255 if (r)
1256 return r;
1257 }
1258 }
1259 bc->cf_last->ndw += align(nliteral, 2);
1260
1261 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1262 * worst case */
1263 if ((bc->cf_last->ndw >> 1) >= 120) {
1264 bc->force_add_cf = 1;
1265 }
1266
1267 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1268 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1269 bc->cf_last->curr_bs_head = NULL;
1270 }
1271
1272 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1273 insert_nop_r6xx(bc);
1274
1275 return 0;
1276 }
1277
1278 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1279 {
1280 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1281 }
1282
1283 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1284 {
1285 switch (bc->chip_class) {
1286 case R600:
1287 return 8;
1288
1289 case R700:
1290 case EVERGREEN:
1291 case CAYMAN:
1292 return 16;
1293
1294 default:
1295 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1296 return 8;
1297 }
1298 }
1299
1300 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1301 {
1302 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1303 (bc->chip_class == CAYMAN ||
1304 bc->cf_last->op != CF_OP_TEX));
1305 }
1306
1307 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1308 {
1309 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1310 int r;
1311
1312 if (!nvtx)
1313 return -ENOMEM;
1314 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1315
1316 /* Load index register if required */
1317 if (bc->chip_class >= EVERGREEN) {
1318 if (vtx->buffer_index_mode)
1319 egcm_load_index_reg(bc, 0, false);
1320 }
1321
1322 /* cf can contains only alu or only vtx or only tex */
1323 if (bc->cf_last == NULL ||
1324 last_inst_was_not_vtx_fetch(bc) ||
1325 bc->force_add_cf) {
1326 r = r600_bytecode_add_cf(bc);
1327 if (r) {
1328 free(nvtx);
1329 return r;
1330 }
1331 switch (bc->chip_class) {
1332 case R600:
1333 case R700:
1334 case EVERGREEN:
1335 bc->cf_last->op = CF_OP_VTX;
1336 break;
1337 case CAYMAN:
1338 bc->cf_last->op = CF_OP_TEX;
1339 break;
1340 default:
1341 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1342 free(nvtx);
1343 return -EINVAL;
1344 }
1345 }
1346 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1347 /* each fetch use 4 dwords */
1348 bc->cf_last->ndw += 4;
1349 bc->ndw += 4;
1350 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1351 bc->force_add_cf = 1;
1352
1353 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1354 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1355
1356 return 0;
1357 }
1358
1359 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1360 {
1361 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1362 int r;
1363
1364 if (!ntex)
1365 return -ENOMEM;
1366 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1367
1368 /* Load index register if required */
1369 if (bc->chip_class >= EVERGREEN) {
1370 if (tex->sampler_index_mode || tex->resource_index_mode)
1371 egcm_load_index_reg(bc, 1, false);
1372 }
1373
1374 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1375 if (bc->cf_last != NULL &&
1376 bc->cf_last->op == CF_OP_TEX) {
1377 struct r600_bytecode_tex *ttex;
1378 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1379 if (ttex->dst_gpr == ntex->src_gpr) {
1380 bc->force_add_cf = 1;
1381 break;
1382 }
1383 }
1384 /* slight hack to make gradients always go into same cf */
1385 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1386 bc->force_add_cf = 1;
1387 }
1388
1389 /* cf can contains only alu or only vtx or only tex */
1390 if (bc->cf_last == NULL ||
1391 bc->cf_last->op != CF_OP_TEX ||
1392 bc->force_add_cf) {
1393 r = r600_bytecode_add_cf(bc);
1394 if (r) {
1395 free(ntex);
1396 return r;
1397 }
1398 bc->cf_last->op = CF_OP_TEX;
1399 }
1400 if (ntex->src_gpr >= bc->ngpr) {
1401 bc->ngpr = ntex->src_gpr + 1;
1402 }
1403 if (ntex->dst_gpr >= bc->ngpr) {
1404 bc->ngpr = ntex->dst_gpr + 1;
1405 }
1406 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1407 /* each texture fetch use 4 dwords */
1408 bc->cf_last->ndw += 4;
1409 bc->ndw += 4;
1410 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1411 bc->force_add_cf = 1;
1412 return 0;
1413 }
1414
1415 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1416 {
1417 int r;
1418 r = r600_bytecode_add_cf(bc);
1419 if (r)
1420 return r;
1421
1422 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1423 bc->cf_last->op = op;
1424 return 0;
1425 }
1426
1427 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1428 {
1429 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1430 }
1431
1432 /* common to all 3 families */
1433 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1434 {
1435 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1436 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1437 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1438 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1439 if (bc->chip_class < CAYMAN)
1440 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1441 id++;
1442 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1443 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1444 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1445 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1446 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1447 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1448 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1449 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1450 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1451 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1452 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1453 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1454 if (bc->chip_class >= EVERGREEN)
1455 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1456 if (bc->chip_class < CAYMAN)
1457 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1458 id++;
1459 bc->bytecode[id++] = 0;
1460 return 0;
1461 }
1462
1463 /* common to all 3 families */
1464 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1465 {
1466 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1467 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1468 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1469 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1470 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1471 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1472 if (bc->chip_class >= EVERGREEN)
1473 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1474 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1475 id++;
1476 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1477 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1478 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1479 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1480 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1481 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1482 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1483 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1484 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1485 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1486 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1487 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1488 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1489 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1490 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1491 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1492 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1493 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1494 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1495 bc->bytecode[id++] = 0;
1496 return 0;
1497 }
1498
1499 /* r600 only, r700/eg bits in r700_asm.c */
1500 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1501 {
1502 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1503
1504 /* don't replace gpr by pv or ps for destination register */
1505 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1506 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1507 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1508 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1509 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1510 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1511 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1512 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1513 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1514 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1515 S_SQ_ALU_WORD0_LAST(alu->last);
1516
1517 if (alu->is_op3) {
1518 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1519 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1520 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1521 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1522 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1523 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1524 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1525 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1526 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1527 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1528 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1529 } else {
1530 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1531 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1532 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1533 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1534 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1535 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1536 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1537 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1538 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1539 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1540 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1541 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1542 }
1543 return 0;
1544 }
1545
1546 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1547 {
1548 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1549 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1550 S_SQ_CF_WORD1_BARRIER(1) |
1551 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1552 }
1553
1554 /* common for r600/r700 - eg in eg_asm.c */
1555 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1556 {
1557 unsigned id = cf->id;
1558 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1559 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1560
1561
1562 if (cf->op == CF_NATIVE) {
1563 bc->bytecode[id++] = cf->isa[0];
1564 bc->bytecode[id++] = cf->isa[1];
1565 } else if (cfop->flags & CF_ALU) {
1566 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1567 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1568 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1569 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1570
1571 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1572 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1573 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1574 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1575 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1576 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1577 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1578 } else if (cfop->flags & CF_FETCH) {
1579 if (bc->chip_class == R700)
1580 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1581 else
1582 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1583 } else if (cfop->flags & CF_EXP) {
1584 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1585 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1586 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1587 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1588 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1589 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1590 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1591 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1592 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1593 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1594 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1595 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1596 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1597 } else if (cfop->flags & CF_MEM) {
1598 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1599 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1600 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1601 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1602 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1603 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1604 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1605 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1606 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1607 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1608 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1609 } else {
1610 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1611 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1612 S_SQ_CF_WORD1_BARRIER(1) |
1613 S_SQ_CF_WORD1_COND(cf->cond) |
1614 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1615 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1616 }
1617 return 0;
1618 }
1619
1620 int r600_bytecode_build(struct r600_bytecode *bc)
1621 {
1622 struct r600_bytecode_cf *cf;
1623 struct r600_bytecode_alu *alu;
1624 struct r600_bytecode_vtx *vtx;
1625 struct r600_bytecode_tex *tex;
1626 uint32_t literal[4];
1627 unsigned nliteral;
1628 unsigned addr;
1629 int i, r;
1630
1631 if (!bc->nstack) // If not 0, Stack_size already provided by llvm
1632 bc->nstack = bc->stack.max_entries;
1633
1634 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1635 bc->nstack = 1;
1636 }
1637
1638 /* first path compute addr of each CF block */
1639 /* addr start after all the CF instructions */
1640 addr = bc->cf_last->id + 2;
1641 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1642 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1643 addr += 3;
1644 addr &= 0xFFFFFFFCUL;
1645 }
1646 cf->addr = addr;
1647 addr += cf->ndw;
1648 bc->ndw = cf->addr + cf->ndw;
1649 }
1650 free(bc->bytecode);
1651 bc->bytecode = calloc(4, bc->ndw);
1652 if (bc->bytecode == NULL)
1653 return -ENOMEM;
1654 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1655 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1656 addr = cf->addr;
1657 if (bc->chip_class >= EVERGREEN)
1658 r = eg_bytecode_cf_build(bc, cf);
1659 else
1660 r = r600_bytecode_cf_build(bc, cf);
1661 if (r)
1662 return r;
1663 if (cfop->flags & CF_ALU) {
1664 nliteral = 0;
1665 memset(literal, 0, sizeof(literal));
1666 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1667 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1668 if (r)
1669 return r;
1670 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1671 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1672
1673 switch(bc->chip_class) {
1674 case R600:
1675 r = r600_bytecode_alu_build(bc, alu, addr);
1676 break;
1677 case R700:
1678 case EVERGREEN: /* eg alu is same encoding as r700 */
1679 case CAYMAN:
1680 r = r700_bytecode_alu_build(bc, alu, addr);
1681 break;
1682 default:
1683 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1684 return -EINVAL;
1685 }
1686 if (r)
1687 return r;
1688 addr += 2;
1689 if (alu->last) {
1690 for (i = 0; i < align(nliteral, 2); ++i) {
1691 bc->bytecode[addr++] = literal[i];
1692 }
1693 nliteral = 0;
1694 memset(literal, 0, sizeof(literal));
1695 }
1696 }
1697 } else if (cf->op == CF_OP_VTX) {
1698 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1699 r = r600_bytecode_vtx_build(bc, vtx, addr);
1700 if (r)
1701 return r;
1702 addr += 4;
1703 }
1704 } else if (cf->op == CF_OP_TEX) {
1705 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1706 assert(bc->chip_class >= EVERGREEN);
1707 r = r600_bytecode_vtx_build(bc, vtx, addr);
1708 if (r)
1709 return r;
1710 addr += 4;
1711 }
1712 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1713 r = r600_bytecode_tex_build(bc, tex, addr);
1714 if (r)
1715 return r;
1716 addr += 4;
1717 }
1718 }
1719 }
1720 return 0;
1721 }
1722
1723 void r600_bytecode_clear(struct r600_bytecode *bc)
1724 {
1725 struct r600_bytecode_cf *cf = NULL, *next_cf;
1726
1727 free(bc->bytecode);
1728 bc->bytecode = NULL;
1729
1730 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1731 struct r600_bytecode_alu *alu = NULL, *next_alu;
1732 struct r600_bytecode_tex *tex = NULL, *next_tex;
1733 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1734
1735 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1736 free(alu);
1737 }
1738
1739 LIST_INITHEAD(&cf->alu);
1740
1741 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1742 free(tex);
1743 }
1744
1745 LIST_INITHEAD(&cf->tex);
1746
1747 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1748 free(vtx);
1749 }
1750
1751 LIST_INITHEAD(&cf->vtx);
1752
1753 free(cf);
1754 }
1755
1756 LIST_INITHEAD(&cf->list);
1757 }
1758
1759 static int print_swizzle(unsigned swz)
1760 {
1761 const char * swzchars = "xyzw01?_";
1762 assert(swz<8 && swz != 6);
1763 return fprintf(stderr, "%c", swzchars[swz]);
1764 }
1765
1766 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1767 unsigned need_brackets)
1768 {
1769 int o = 0;
1770 if (rel && index_mode >= 5 && sel < 128)
1771 o += fprintf(stderr, "G");
1772 if (rel || need_brackets) {
1773 o += fprintf(stderr, "[");
1774 }
1775 o += fprintf(stderr, "%d", sel);
1776 if (rel) {
1777 if (index_mode == 0 || index_mode == 6)
1778 o += fprintf(stderr, "+AR");
1779 else if (index_mode == 4)
1780 o += fprintf(stderr, "+AL");
1781 }
1782 if (rel || need_brackets) {
1783 o += fprintf(stderr, "]");
1784 }
1785 return o;
1786 }
1787
1788 static int print_dst(struct r600_bytecode_alu *alu)
1789 {
1790 int o = 0;
1791 unsigned sel = alu->dst.sel;
1792 char reg_char = 'R';
1793 if (sel > 128 - 4) { /* clause temporary gpr */
1794 sel -= 128 - 4;
1795 reg_char = 'T';
1796 }
1797
1798 if (alu_writes(alu)) {
1799 o += fprintf(stderr, "%c", reg_char);
1800 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1801 } else {
1802 o += fprintf(stderr, "__");
1803 }
1804 o += fprintf(stderr, ".");
1805 o += print_swizzle(alu->dst.chan);
1806 return o;
1807 }
1808
1809 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1810 {
1811 int o = 0;
1812 struct r600_bytecode_alu_src *src = &alu->src[idx];
1813 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1814
1815 if (src->neg)
1816 o += fprintf(stderr,"-");
1817 if (src->abs)
1818 o += fprintf(stderr,"|");
1819
1820 if (sel < 128 - 4) {
1821 o += fprintf(stderr, "R");
1822 } else if (sel < 128) {
1823 o += fprintf(stderr, "T");
1824 sel -= 128 - 4;
1825 } else if (sel < 160) {
1826 o += fprintf(stderr, "KC0");
1827 need_brackets = 1;
1828 sel -= 128;
1829 } else if (sel < 192) {
1830 o += fprintf(stderr, "KC1");
1831 need_brackets = 1;
1832 sel -= 160;
1833 } else if (sel >= 512) {
1834 o += fprintf(stderr, "C%d", src->kc_bank);
1835 need_brackets = 1;
1836 sel -= 512;
1837 } else if (sel >= 448) {
1838 o += fprintf(stderr, "Param");
1839 sel -= 448;
1840 need_chan = 0;
1841 } else if (sel >= 288) {
1842 o += fprintf(stderr, "KC3");
1843 need_brackets = 1;
1844 sel -= 288;
1845 } else if (sel >= 256) {
1846 o += fprintf(stderr, "KC2");
1847 need_brackets = 1;
1848 sel -= 256;
1849 } else {
1850 need_sel = 0;
1851 need_chan = 0;
1852 switch (sel) {
1853 case V_SQ_ALU_SRC_PS:
1854 o += fprintf(stderr, "PS");
1855 break;
1856 case V_SQ_ALU_SRC_PV:
1857 o += fprintf(stderr, "PV");
1858 need_chan = 1;
1859 break;
1860 case V_SQ_ALU_SRC_LITERAL:
1861 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value);
1862 break;
1863 case V_SQ_ALU_SRC_0_5:
1864 o += fprintf(stderr, "0.5");
1865 break;
1866 case V_SQ_ALU_SRC_M_1_INT:
1867 o += fprintf(stderr, "-1");
1868 break;
1869 case V_SQ_ALU_SRC_1_INT:
1870 o += fprintf(stderr, "1");
1871 break;
1872 case V_SQ_ALU_SRC_1:
1873 o += fprintf(stderr, "1.0");
1874 break;
1875 case V_SQ_ALU_SRC_0:
1876 o += fprintf(stderr, "0");
1877 break;
1878 default:
1879 o += fprintf(stderr, "??IMM_%d", sel);
1880 break;
1881 }
1882 }
1883
1884 if (need_sel)
1885 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
1886
1887 if (need_chan) {
1888 o += fprintf(stderr, ".");
1889 o += print_swizzle(src->chan);
1890 }
1891
1892 if (src->abs)
1893 o += fprintf(stderr,"|");
1894
1895 return o;
1896 }
1897
1898 static int print_indent(int p, int c)
1899 {
1900 int o = 0;
1901 while (p++ < c)
1902 o += fprintf(stderr, " ");
1903 return o;
1904 }
1905
1906 void r600_bytecode_disasm(struct r600_bytecode *bc)
1907 {
1908 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
1909 static int index = 0;
1910 struct r600_bytecode_cf *cf = NULL;
1911 struct r600_bytecode_alu *alu = NULL;
1912 struct r600_bytecode_vtx *vtx = NULL;
1913 struct r600_bytecode_tex *tex = NULL;
1914
1915 unsigned i, id, ngr = 0, last;
1916 uint32_t literal[4];
1917 unsigned nliteral;
1918 char chip = '6';
1919
1920 switch (bc->chip_class) {
1921 case R700:
1922 chip = '7';
1923 break;
1924 case EVERGREEN:
1925 chip = 'E';
1926 break;
1927 case CAYMAN:
1928 chip = 'C';
1929 break;
1930 case R600:
1931 default:
1932 chip = '6';
1933 break;
1934 }
1935 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1936 bc->ndw, bc->ngpr, bc->nstack);
1937 fprintf(stderr, "shader %d -- %c\n", index++, chip);
1938
1939 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1940 id = cf->id;
1941 if (cf->op == CF_NATIVE) {
1942 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
1943 bc->bytecode[id + 1]);
1944 } else {
1945 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1946 if (cfop->flags & CF_ALU) {
1947 if (cf->eg_alu_extended) {
1948 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
1949 bc->bytecode[id + 1], "ALU_EXT");
1950 id += 2;
1951 }
1952 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1953 bc->bytecode[id + 1], cfop->name);
1954 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
1955 for (i = 0; i < 4; ++i) {
1956 if (cf->kcache[i].mode) {
1957 int c_start = (cf->kcache[i].addr << 4);
1958 int c_end = c_start + (cf->kcache[i].mode << 4);
1959 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
1960 i, cf->kcache[i].bank, c_start, c_end,
1961 cf->kcache[i].index_mode ? " " : "",
1962 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
1963 }
1964 }
1965 fprintf(stderr, "\n");
1966 } else if (cfop->flags & CF_FETCH) {
1967 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1968 bc->bytecode[id + 1], cfop->name);
1969 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
1970 fprintf(stderr, "\n");
1971 } else if (cfop->flags & CF_EXP) {
1972 int o = 0;
1973 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
1974 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1975 bc->bytecode[id + 1], cfop->name);
1976 o += print_indent(o, 43);
1977 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1978 if (cf->output.burst_count > 1) {
1979 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1980 cf->output.array_base + cf->output.burst_count - 1);
1981
1982 o += print_indent(o, 55);
1983 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1984 cf->output.gpr + cf->output.burst_count - 1);
1985 } else {
1986 o += fprintf(stderr, "%d ", cf->output.array_base);
1987 o += print_indent(o, 55);
1988 o += fprintf(stderr, "R%d.", cf->output.gpr);
1989 }
1990
1991 o += print_swizzle(cf->output.swizzle_x);
1992 o += print_swizzle(cf->output.swizzle_y);
1993 o += print_swizzle(cf->output.swizzle_z);
1994 o += print_swizzle(cf->output.swizzle_w);
1995
1996 print_indent(o, 67);
1997
1998 fprintf(stderr, " ES:%X ", cf->output.elem_size);
1999 if (!cf->barrier)
2000 fprintf(stderr, "NO_BARRIER ");
2001 if (cf->end_of_program)
2002 fprintf(stderr, "EOP ");
2003 fprintf(stderr, "\n");
2004 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2005 int o = 0;
2006 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2007 "WRITE_IND_ACK"};
2008 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2009 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2010 o += print_indent(o, 43);
2011 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2012 if (cf->output.burst_count > 1) {
2013 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2014 cf->output.array_base + cf->output.burst_count - 1);
2015 o += print_indent(o, 55);
2016 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2017 cf->output.gpr + cf->output.burst_count - 1);
2018 } else {
2019 o += fprintf(stderr, "%d ", cf->output.array_base);
2020 o += print_indent(o, 55);
2021 o += fprintf(stderr, "R%d.", cf->output.gpr);
2022 }
2023 for (i = 0; i < 4; ++i) {
2024 if (cf->output.comp_mask & (1 << i))
2025 o += print_swizzle(i);
2026 else
2027 o += print_swizzle(7);
2028 }
2029
2030 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND)
2031 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2032
2033 o += print_indent(o, 67);
2034
2035 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2036 if (cf->output.array_size != 0xFFF)
2037 fprintf(stderr, "AS:%i ", cf->output.array_size);
2038 if (!cf->barrier)
2039 fprintf(stderr, "NO_BARRIER ");
2040 if (cf->end_of_program)
2041 fprintf(stderr, "EOP ");
2042 fprintf(stderr, "\n");
2043 } else {
2044 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2045 bc->bytecode[id + 1], cfop->name);
2046 fprintf(stderr, "@%d ", cf->cf_addr);
2047 if (cf->cond)
2048 fprintf(stderr, "CND:%X ", cf->cond);
2049 if (cf->pop_count)
2050 fprintf(stderr, "POP:%X ", cf->pop_count);
2051 if (cf->count && (cfop->flags & CF_EMIT))
2052 fprintf(stderr, "STREAM%d ", cf->count);
2053 if (cf->end_of_program)
2054 fprintf(stderr, "EOP ");
2055 fprintf(stderr, "\n");
2056 }
2057 }
2058
2059 id = cf->addr;
2060 nliteral = 0;
2061 last = 1;
2062 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2063 const char *omod_str[] = {"","*2","*4","/2"};
2064 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2065 int o = 0;
2066
2067 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2068 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2069 if (last)
2070 o += fprintf(stderr, "%4d ", ++ngr);
2071 else
2072 o += fprintf(stderr, " ");
2073 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2074 alu->update_pred ? 'P':' ',
2075 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2076
2077 o += fprintf(stderr, "%s%s%s ", aop->name,
2078 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2079
2080 o += print_indent(o,60);
2081 o += print_dst(alu);
2082 for (i = 0; i < aop->src_count; ++i) {
2083 o += fprintf(stderr, i == 0 ? ", ": ", ");
2084 o += print_src(alu, i);
2085 }
2086
2087 if (alu->bank_swizzle) {
2088 o += print_indent(o,75);
2089 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2090 }
2091
2092 fprintf(stderr, "\n");
2093 id += 2;
2094
2095 if (alu->last) {
2096 for (i = 0; i < nliteral; i++, id++) {
2097 float *f = (float*)(bc->bytecode + id);
2098 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2099 print_indent(o, 60);
2100 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2101 }
2102 id += nliteral & 1;
2103 nliteral = 0;
2104 }
2105 last = alu->last;
2106 }
2107
2108 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2109 int o = 0;
2110 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2111 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2112
2113 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2114
2115 o += print_indent(o, 50);
2116
2117 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2118 o += print_swizzle(tex->dst_sel_x);
2119 o += print_swizzle(tex->dst_sel_y);
2120 o += print_swizzle(tex->dst_sel_z);
2121 o += print_swizzle(tex->dst_sel_w);
2122
2123 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2124 o += print_swizzle(tex->src_sel_x);
2125 o += print_swizzle(tex->src_sel_y);
2126 o += print_swizzle(tex->src_sel_z);
2127 o += print_swizzle(tex->src_sel_w);
2128
2129 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2130 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2131
2132 if (tex->sampler_index_mode)
2133 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2134
2135 if (tex->lod_bias)
2136 fprintf(stderr, "LB:%d ", tex->lod_bias);
2137
2138 fprintf(stderr, "CT:%c%c%c%c ",
2139 tex->coord_type_x ? 'N' : 'U',
2140 tex->coord_type_y ? 'N' : 'U',
2141 tex->coord_type_z ? 'N' : 'U',
2142 tex->coord_type_w ? 'N' : 'U');
2143
2144 if (tex->offset_x)
2145 fprintf(stderr, "OX:%d ", tex->offset_x);
2146 if (tex->offset_y)
2147 fprintf(stderr, "OY:%d ", tex->offset_y);
2148 if (tex->offset_z)
2149 fprintf(stderr, "OZ:%d ", tex->offset_z);
2150
2151 id += 4;
2152 fprintf(stderr, "\n");
2153 }
2154
2155 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2156 int o = 0;
2157 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2158 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2159 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2160
2161 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2162
2163 o += print_indent(o, 50);
2164
2165 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2166 o += print_swizzle(vtx->dst_sel_x);
2167 o += print_swizzle(vtx->dst_sel_y);
2168 o += print_swizzle(vtx->dst_sel_z);
2169 o += print_swizzle(vtx->dst_sel_w);
2170
2171 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2172 o += print_swizzle(vtx->src_sel_x);
2173
2174 if (vtx->offset)
2175 fprintf(stderr, " +%db", vtx->offset);
2176
2177 o += print_indent(o, 55);
2178
2179 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2180
2181 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2182
2183 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2184 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2185
2186 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2187 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2188
2189 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2190 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2191 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2192 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2193 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2194
2195 id += 4;
2196 }
2197 }
2198
2199 fprintf(stderr, "--------------------------------------\n");
2200 }
2201
2202 void r600_vertex_data_type(enum pipe_format pformat,
2203 unsigned *format,
2204 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2205 {
2206 const struct util_format_description *desc;
2207 unsigned i;
2208
2209 *format = 0;
2210 *num_format = 0;
2211 *format_comp = 0;
2212 *endian = ENDIAN_NONE;
2213
2214 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2215 *format = FMT_10_11_11_FLOAT;
2216 *endian = r600_endian_swap(32);
2217 return;
2218 }
2219
2220 desc = util_format_description(pformat);
2221 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2222 goto out_unknown;
2223 }
2224
2225 /* Find the first non-VOID channel. */
2226 for (i = 0; i < 4; i++) {
2227 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2228 break;
2229 }
2230 }
2231
2232 *endian = r600_endian_swap(desc->channel[i].size);
2233
2234 switch (desc->channel[i].type) {
2235 /* Half-floats, floats, ints */
2236 case UTIL_FORMAT_TYPE_FLOAT:
2237 switch (desc->channel[i].size) {
2238 case 16:
2239 switch (desc->nr_channels) {
2240 case 1:
2241 *format = FMT_16_FLOAT;
2242 break;
2243 case 2:
2244 *format = FMT_16_16_FLOAT;
2245 break;
2246 case 3:
2247 case 4:
2248 *format = FMT_16_16_16_16_FLOAT;
2249 break;
2250 }
2251 break;
2252 case 32:
2253 switch (desc->nr_channels) {
2254 case 1:
2255 *format = FMT_32_FLOAT;
2256 break;
2257 case 2:
2258 *format = FMT_32_32_FLOAT;
2259 break;
2260 case 3:
2261 *format = FMT_32_32_32_FLOAT;
2262 break;
2263 case 4:
2264 *format = FMT_32_32_32_32_FLOAT;
2265 break;
2266 }
2267 break;
2268 default:
2269 goto out_unknown;
2270 }
2271 break;
2272 /* Unsigned ints */
2273 case UTIL_FORMAT_TYPE_UNSIGNED:
2274 /* Signed ints */
2275 case UTIL_FORMAT_TYPE_SIGNED:
2276 switch (desc->channel[i].size) {
2277 case 8:
2278 switch (desc->nr_channels) {
2279 case 1:
2280 *format = FMT_8;
2281 break;
2282 case 2:
2283 *format = FMT_8_8;
2284 break;
2285 case 3:
2286 case 4:
2287 *format = FMT_8_8_8_8;
2288 break;
2289 }
2290 break;
2291 case 10:
2292 if (desc->nr_channels != 4)
2293 goto out_unknown;
2294
2295 *format = FMT_2_10_10_10;
2296 break;
2297 case 16:
2298 switch (desc->nr_channels) {
2299 case 1:
2300 *format = FMT_16;
2301 break;
2302 case 2:
2303 *format = FMT_16_16;
2304 break;
2305 case 3:
2306 case 4:
2307 *format = FMT_16_16_16_16;
2308 break;
2309 }
2310 break;
2311 case 32:
2312 switch (desc->nr_channels) {
2313 case 1:
2314 *format = FMT_32;
2315 break;
2316 case 2:
2317 *format = FMT_32_32;
2318 break;
2319 case 3:
2320 *format = FMT_32_32_32;
2321 break;
2322 case 4:
2323 *format = FMT_32_32_32_32;
2324 break;
2325 }
2326 break;
2327 default:
2328 goto out_unknown;
2329 }
2330 break;
2331 default:
2332 goto out_unknown;
2333 }
2334
2335 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2336 *format_comp = 1;
2337 }
2338
2339 *num_format = 0;
2340 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2341 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2342 if (!desc->channel[i].normalized) {
2343 if (desc->channel[i].pure_integer)
2344 *num_format = 1;
2345 else
2346 *num_format = 2;
2347 }
2348 }
2349 return;
2350 out_unknown:
2351 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2352 }
2353
2354 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2355 unsigned count,
2356 const struct pipe_vertex_element *elements)
2357 {
2358 struct r600_context *rctx = (struct r600_context *)ctx;
2359 struct r600_bytecode bc;
2360 struct r600_bytecode_vtx vtx;
2361 const struct util_format_description *desc;
2362 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2363 unsigned format, num_format, format_comp, endian;
2364 uint32_t *bytecode;
2365 int i, j, r, fs_size;
2366 struct r600_fetch_shader *shader;
2367 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2368 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2369
2370 assert(count < 32);
2371
2372 memset(&bc, 0, sizeof(bc));
2373 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2374 rctx->screen->has_compressed_msaa_texturing);
2375
2376 bc.isa = rctx->isa;
2377
2378 for (i = 0; i < count; i++) {
2379 if (elements[i].instance_divisor > 1) {
2380 if (rctx->b.chip_class == CAYMAN) {
2381 for (j = 0; j < 4; j++) {
2382 struct r600_bytecode_alu alu;
2383 memset(&alu, 0, sizeof(alu));
2384 alu.op = ALU_OP2_MULHI_UINT;
2385 alu.src[0].sel = 0;
2386 alu.src[0].chan = 3;
2387 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2388 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2389 alu.dst.sel = i + 1;
2390 alu.dst.chan = j;
2391 alu.dst.write = j == 3;
2392 alu.last = j == 3;
2393 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2394 r600_bytecode_clear(&bc);
2395 return NULL;
2396 }
2397 }
2398 } else {
2399 struct r600_bytecode_alu alu;
2400 memset(&alu, 0, sizeof(alu));
2401 alu.op = ALU_OP2_MULHI_UINT;
2402 alu.src[0].sel = 0;
2403 alu.src[0].chan = 3;
2404 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2405 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2406 alu.dst.sel = i + 1;
2407 alu.dst.chan = 3;
2408 alu.dst.write = 1;
2409 alu.last = 1;
2410 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2411 r600_bytecode_clear(&bc);
2412 return NULL;
2413 }
2414 }
2415 }
2416 }
2417
2418 for (i = 0; i < count; i++) {
2419 r600_vertex_data_type(elements[i].src_format,
2420 &format, &num_format, &format_comp, &endian);
2421
2422 desc = util_format_description(elements[i].src_format);
2423 if (!desc) {
2424 r600_bytecode_clear(&bc);
2425 R600_ERR("unknown format %d\n", elements[i].src_format);
2426 return NULL;
2427 }
2428
2429 if (elements[i].src_offset > 65535) {
2430 r600_bytecode_clear(&bc);
2431 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2432 return NULL;
2433 }
2434
2435 memset(&vtx, 0, sizeof(vtx));
2436 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2437 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2438 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2439 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2440 vtx.mega_fetch_count = 0x1F;
2441 vtx.dst_gpr = i + 1;
2442 vtx.dst_sel_x = desc->swizzle[0];
2443 vtx.dst_sel_y = desc->swizzle[1];
2444 vtx.dst_sel_z = desc->swizzle[2];
2445 vtx.dst_sel_w = desc->swizzle[3];
2446 vtx.data_format = format;
2447 vtx.num_format_all = num_format;
2448 vtx.format_comp_all = format_comp;
2449 vtx.offset = elements[i].src_offset;
2450 vtx.endian = endian;
2451
2452 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2453 r600_bytecode_clear(&bc);
2454 return NULL;
2455 }
2456 }
2457
2458 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2459
2460 if ((r = r600_bytecode_build(&bc))) {
2461 r600_bytecode_clear(&bc);
2462 return NULL;
2463 }
2464
2465 if (rctx->screen->b.debug_flags & DBG_FS) {
2466 fprintf(stderr, "--------------------------------------------------------------\n");
2467 fprintf(stderr, "Vertex elements state:\n");
2468 for (i = 0; i < count; i++) {
2469 fprintf(stderr, " ");
2470 util_dump_vertex_element(stderr, elements+i);
2471 fprintf(stderr, "\n");
2472 }
2473
2474 if (!sb_disasm) {
2475 r600_bytecode_disasm(&bc);
2476
2477 fprintf(stderr, "______________________________________________________________\n");
2478 } else {
2479 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2480 }
2481 }
2482
2483 fs_size = bc.ndw*4;
2484
2485 /* Allocate the CSO. */
2486 shader = CALLOC_STRUCT(r600_fetch_shader);
2487 if (!shader) {
2488 r600_bytecode_clear(&bc);
2489 return NULL;
2490 }
2491
2492 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2493 (struct pipe_resource**)&shader->buffer);
2494 if (!shader->buffer) {
2495 r600_bytecode_clear(&bc);
2496 FREE(shader);
2497 return NULL;
2498 }
2499
2500 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2501 bytecode += shader->offset / 4;
2502
2503 if (R600_BIG_ENDIAN) {
2504 for (i = 0; i < fs_size / 4; ++i) {
2505 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2506 }
2507 } else {
2508 memcpy(bytecode, bc.bytecode, fs_size);
2509 }
2510 rctx->b.ws->buffer_unmap(shader->buffer->cs_buf);
2511
2512 r600_bytecode_clear(&bc);
2513 return shader;
2514 }
2515
2516 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2517 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2518 {
2519 /* WORD0 */
2520 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2521 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2522 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2523 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2524 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2525 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2526 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2527 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2528 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2529 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2530 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2531
2532 /* WORD1 */
2533 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2534 if (alu->bank_swizzle)
2535 alu->bank_swizzle_force = alu->bank_swizzle;
2536 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2537 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2538 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2539 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2540 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2541 {
2542 alu->is_op3 = 1;
2543 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2544 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2545 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2546 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2547 alu->op = r600_isa_alu_by_opcode(bc->isa,
2548 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2549
2550 }
2551 else /*ALU_DWORD1_OP2*/
2552 {
2553 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2554 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2555 alu->op = r600_isa_alu_by_opcode(bc->isa,
2556 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2557 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2558 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2559 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2560 alu->execute_mask =
2561 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2562 }
2563 }
2564
2565 #if 0
2566 void r600_bytecode_export_read(struct r600_bytecode *bc,
2567 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2568 {
2569 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2570 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2571 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2572 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2573
2574 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2575 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2576 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2577 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2578 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2579 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2580 output->op = r600_isa_cf_by_opcode(bc->isa,
2581 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2582 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2583 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2584 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2585 }
2586 #endif