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r600: add support for GDS clause to the assembler.
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
34
35 #include "sb/sb_public.h"
36
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
39
40 static inline bool alu_writes(struct r600_bytecode_alu *alu)
41 {
42 return alu->dst.write || alu->is_op3;
43 }
44
45 static inline unsigned int r600_bytecode_get_num_operands(
46 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
47 {
48 return r600_isa_alu(alu->op)->src_count;
49 }
50
51 int r700_bytecode_alu_build(struct r600_bytecode *bc,
52 struct r600_bytecode_alu *alu, unsigned id);
53
54 static struct r600_bytecode_cf *r600_bytecode_cf(void)
55 {
56 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
57
58 if (!cf)
59 return NULL;
60 LIST_INITHEAD(&cf->list);
61 LIST_INITHEAD(&cf->alu);
62 LIST_INITHEAD(&cf->vtx);
63 LIST_INITHEAD(&cf->tex);
64 LIST_INITHEAD(&cf->gds);
65 return cf;
66 }
67
68 static struct r600_bytecode_alu *r600_bytecode_alu(void)
69 {
70 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
71
72 if (!alu)
73 return NULL;
74 LIST_INITHEAD(&alu->list);
75 return alu;
76 }
77
78 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
79 {
80 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
81
82 if (!vtx)
83 return NULL;
84 LIST_INITHEAD(&vtx->list);
85 return vtx;
86 }
87
88 static struct r600_bytecode_tex *r600_bytecode_tex(void)
89 {
90 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
91
92 if (!tex)
93 return NULL;
94 LIST_INITHEAD(&tex->list);
95 return tex;
96 }
97
98 static struct r600_bytecode_gds *r600_bytecode_gds(void)
99 {
100 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
101
102 if (gds == NULL)
103 return NULL;
104 LIST_INITHEAD(&gds->list);
105 return gds;
106 }
107
108 static unsigned stack_entry_size(enum radeon_family chip) {
109 /* Wavefront size:
110 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
111 * Aruba/Sumo/Sumo2/redwood/juniper
112 * 32: R630/R730/R710/Palm/Cedar
113 * 16: R610/Rs780
114 *
115 * Stack row size:
116 * Wavefront Size 16 32 48 64
117 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
118 * Columns per Row (R9xx+) 8 4 4 4 */
119
120 switch (chip) {
121 /* FIXME: are some chips missing here? */
122 /* wavefront size 16 */
123 case CHIP_RV610:
124 case CHIP_RS780:
125 case CHIP_RV620:
126 case CHIP_RS880:
127 /* wavefront size 32 */
128 case CHIP_RV630:
129 case CHIP_RV635:
130 case CHIP_RV730:
131 case CHIP_RV710:
132 case CHIP_PALM:
133 case CHIP_CEDAR:
134 return 8;
135
136 /* wavefront size 64 */
137 default:
138 return 4;
139 }
140 }
141
142 void r600_bytecode_init(struct r600_bytecode *bc,
143 enum chip_class chip_class,
144 enum radeon_family family,
145 bool has_compressed_msaa_texturing)
146 {
147 static unsigned next_shader_id = 0;
148
149 bc->debug_id = ++next_shader_id;
150
151 if ((chip_class == R600) &&
152 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
153 bc->ar_handling = AR_HANDLE_RV6XX;
154 bc->r6xx_nop_after_rel_dst = 1;
155 } else {
156 bc->ar_handling = AR_HANDLE_NORMAL;
157 bc->r6xx_nop_after_rel_dst = 0;
158 }
159
160 LIST_INITHEAD(&bc->cf);
161 bc->chip_class = chip_class;
162 bc->family = family;
163 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
164 bc->stack.entry_size = stack_entry_size(family);
165 }
166
167 int r600_bytecode_add_cf(struct r600_bytecode *bc)
168 {
169 struct r600_bytecode_cf *cf = r600_bytecode_cf();
170
171 if (!cf)
172 return -ENOMEM;
173 LIST_ADDTAIL(&cf->list, &bc->cf);
174 if (bc->cf_last) {
175 cf->id = bc->cf_last->id + 2;
176 if (bc->cf_last->eg_alu_extended) {
177 /* take into account extended alu size */
178 cf->id += 2;
179 bc->ndw += 2;
180 }
181 }
182 bc->cf_last = cf;
183 bc->ncf++;
184 bc->ndw += 2;
185 bc->force_add_cf = 0;
186 bc->ar_loaded = 0;
187 return 0;
188 }
189
190 int r600_bytecode_add_output(struct r600_bytecode *bc,
191 const struct r600_bytecode_output *output)
192 {
193 int r;
194
195 if (output->gpr >= bc->ngpr)
196 bc->ngpr = output->gpr + 1;
197
198 if (bc->cf_last && (bc->cf_last->op == output->op ||
199 (bc->cf_last->op == CF_OP_EXPORT &&
200 output->op == CF_OP_EXPORT_DONE)) &&
201 output->type == bc->cf_last->output.type &&
202 output->elem_size == bc->cf_last->output.elem_size &&
203 output->swizzle_x == bc->cf_last->output.swizzle_x &&
204 output->swizzle_y == bc->cf_last->output.swizzle_y &&
205 output->swizzle_z == bc->cf_last->output.swizzle_z &&
206 output->swizzle_w == bc->cf_last->output.swizzle_w &&
207 output->comp_mask == bc->cf_last->output.comp_mask &&
208 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
209
210 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
211 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
212
213 bc->cf_last->op = bc->cf_last->output.op = output->op;
214 bc->cf_last->output.gpr = output->gpr;
215 bc->cf_last->output.array_base = output->array_base;
216 bc->cf_last->output.burst_count += output->burst_count;
217 return 0;
218
219 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
220 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
221
222 bc->cf_last->op = bc->cf_last->output.op = output->op;
223 bc->cf_last->output.burst_count += output->burst_count;
224 return 0;
225 }
226 }
227
228 r = r600_bytecode_add_cf(bc);
229 if (r)
230 return r;
231 bc->cf_last->op = output->op;
232 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
233 bc->cf_last->barrier = 1;
234 return 0;
235 }
236
237 /* alu instructions that can ony exits once per group */
238 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
239 {
240 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
241 }
242
243 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
244 {
245 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
246 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
247 }
248
249 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
250 {
251 return r600_isa_alu(alu->op)->flags & AF_MOVA;
252 }
253
254 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
255 {
256 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
257 unsigned src;
258
259 if (alu->dst.rel) {
260 return 1;
261 }
262
263 for (src = 0; src < num_src; ++src) {
264 if (alu->src[src].rel) {
265 return 1;
266 }
267 }
268 return 0;
269 }
270
271 static int is_alu_64bit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
272 {
273 const struct alu_op_info *op = r600_isa_alu(alu->op);
274 return (op->flags & AF_64);
275 }
276
277 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
278 {
279 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
280 return !(slots & AF_S);
281 }
282
283 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
284 {
285 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
286 return !(slots & AF_V);
287 }
288
289 /* alu instructions that can execute on any unit */
290 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
291 {
292 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
293 return slots == AF_VS;
294 }
295
296 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
297 {
298 return alu->op == ALU_OP0_NOP;
299 }
300
301 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
302 struct r600_bytecode_alu *assignment[5])
303 {
304 struct r600_bytecode_alu *alu;
305 unsigned i, chan, trans;
306 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
307
308 for (i = 0; i < max_slots; i++)
309 assignment[i] = NULL;
310
311 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
312 chan = alu->dst.chan;
313 if (max_slots == 4)
314 trans = 0;
315 else if (is_alu_trans_unit_inst(bc, alu))
316 trans = 1;
317 else if (is_alu_vec_unit_inst(bc, alu))
318 trans = 0;
319 else if (assignment[chan])
320 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
321 else
322 trans = 0;
323
324 if (trans) {
325 if (assignment[4]) {
326 assert(0); /* ALU.Trans has already been allocated. */
327 return -1;
328 }
329 assignment[4] = alu;
330 } else {
331 if (assignment[chan]) {
332 assert(0); /* ALU.chan has already been allocated. */
333 return -1;
334 }
335 assignment[chan] = alu;
336 }
337
338 if (alu->last)
339 break;
340 }
341 return 0;
342 }
343
344 struct alu_bank_swizzle {
345 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
346 int hw_cfile_addr[4];
347 int hw_cfile_elem[4];
348 };
349
350 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
351 [SQ_ALU_VEC_012] = { 0, 1, 2 },
352 [SQ_ALU_VEC_021] = { 0, 2, 1 },
353 [SQ_ALU_VEC_120] = { 1, 2, 0 },
354 [SQ_ALU_VEC_102] = { 1, 0, 2 },
355 [SQ_ALU_VEC_201] = { 2, 0, 1 },
356 [SQ_ALU_VEC_210] = { 2, 1, 0 }
357 };
358
359 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
360 [SQ_ALU_SCL_210] = { 2, 1, 0 },
361 [SQ_ALU_SCL_122] = { 1, 2, 2 },
362 [SQ_ALU_SCL_212] = { 2, 1, 2 },
363 [SQ_ALU_SCL_221] = { 2, 2, 1 }
364 };
365
366 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
367 {
368 int i, cycle, component;
369 /* set up gpr use */
370 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
371 for (component = 0; component < NUM_OF_COMPONENTS; component++)
372 bs->hw_gpr[cycle][component] = -1;
373 for (i = 0; i < 4; i++)
374 bs->hw_cfile_addr[i] = -1;
375 for (i = 0; i < 4; i++)
376 bs->hw_cfile_elem[i] = -1;
377 }
378
379 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
380 {
381 if (bs->hw_gpr[cycle][chan] == -1)
382 bs->hw_gpr[cycle][chan] = sel;
383 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
384 /* Another scalar operation has already used the GPR read port for the channel. */
385 return -1;
386 }
387 return 0;
388 }
389
390 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
391 {
392 int res, num_res = 4;
393 if (bc->chip_class >= R700) {
394 num_res = 2;
395 chan /= 2;
396 }
397 for (res = 0; res < num_res; ++res) {
398 if (bs->hw_cfile_addr[res] == -1) {
399 bs->hw_cfile_addr[res] = sel;
400 bs->hw_cfile_elem[res] = chan;
401 return 0;
402 } else if (bs->hw_cfile_addr[res] == sel &&
403 bs->hw_cfile_elem[res] == chan)
404 return 0; /* Read for this scalar element already reserved, nothing to do here. */
405 }
406 /* All cfile read ports are used, cannot reference vector element. */
407 return -1;
408 }
409
410 static int is_gpr(unsigned sel)
411 {
412 return (sel <= 127);
413 }
414
415 /* CB constants start at 512, and get translated to a kcache index when ALU
416 * clauses are constructed. Note that we handle kcache constants the same way
417 * as (the now gone) cfile constants, is that really required? */
418 static int is_cfile(unsigned sel)
419 {
420 return (sel > 255 && sel < 512) ||
421 (sel > 511 && sel < 4607) || /* Kcache before translation. */
422 (sel > 127 && sel < 192); /* Kcache after translation. */
423 }
424
425 static int is_const(int sel)
426 {
427 return is_cfile(sel) ||
428 (sel >= V_SQ_ALU_SRC_0 &&
429 sel <= V_SQ_ALU_SRC_LITERAL);
430 }
431
432 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
433 struct alu_bank_swizzle *bs, int bank_swizzle)
434 {
435 int r, src, num_src, sel, elem, cycle;
436
437 num_src = r600_bytecode_get_num_operands(bc, alu);
438 for (src = 0; src < num_src; src++) {
439 sel = alu->src[src].sel;
440 elem = alu->src[src].chan;
441 if (is_gpr(sel)) {
442 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
443 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
444 /* Nothing to do; special-case optimization,
445 * second source uses first source’s reservation. */
446 continue;
447 else {
448 r = reserve_gpr(bs, sel, elem, cycle);
449 if (r)
450 return r;
451 }
452 } else if (is_cfile(sel)) {
453 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
454 if (r)
455 return r;
456 }
457 /* No restrictions on PV, PS, literal or special constants. */
458 }
459 return 0;
460 }
461
462 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
463 struct alu_bank_swizzle *bs, int bank_swizzle)
464 {
465 int r, src, num_src, const_count, sel, elem, cycle;
466
467 num_src = r600_bytecode_get_num_operands(bc, alu);
468 for (const_count = 0, src = 0; src < num_src; ++src) {
469 sel = alu->src[src].sel;
470 elem = alu->src[src].chan;
471 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
472 if (const_count >= 2)
473 /* More than two references to a constant in
474 * transcendental operation. */
475 return -1;
476 else
477 const_count++;
478 }
479 if (is_cfile(sel)) {
480 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
481 if (r)
482 return r;
483 }
484 }
485 for (src = 0; src < num_src; ++src) {
486 sel = alu->src[src].sel;
487 elem = alu->src[src].chan;
488 if (is_gpr(sel)) {
489 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
490 if (cycle < const_count)
491 /* Cycle for GPR load conflicts with
492 * constant load in transcendental operation. */
493 return -1;
494 r = reserve_gpr(bs, sel, elem, cycle);
495 if (r)
496 return r;
497 }
498 /* PV PS restrictions */
499 if (const_count && (sel == 254 || sel == 255)) {
500 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
501 if (cycle < const_count)
502 return -1;
503 }
504 }
505 return 0;
506 }
507
508 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
509 struct r600_bytecode_alu *slots[5])
510 {
511 struct alu_bank_swizzle bs;
512 int bank_swizzle[5];
513 int i, r = 0, forced = 1;
514 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
515 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
516
517 for (i = 0; i < max_slots; i++) {
518 if (slots[i]) {
519 if (slots[i]->bank_swizzle_force) {
520 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
521 } else {
522 forced = 0;
523 }
524 }
525
526 if (i < 4 && slots[i])
527 scalar_only = false;
528 }
529 if (forced)
530 return 0;
531
532 /* Just check every possible combination of bank swizzle.
533 * Not very efficent, but works on the first try in most of the cases. */
534 for (i = 0; i < 4; i++)
535 if (!slots[i] || !slots[i]->bank_swizzle_force)
536 bank_swizzle[i] = SQ_ALU_VEC_012;
537 else
538 bank_swizzle[i] = slots[i]->bank_swizzle;
539
540 bank_swizzle[4] = SQ_ALU_SCL_210;
541 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
542
543 init_bank_swizzle(&bs);
544 if (scalar_only == false) {
545 for (i = 0; i < 4; i++) {
546 if (slots[i]) {
547 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
548 if (r)
549 break;
550 }
551 }
552 } else
553 r = 0;
554
555 if (!r && max_slots == 5 && slots[4]) {
556 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
557 }
558 if (!r) {
559 for (i = 0; i < max_slots; i++) {
560 if (slots[i])
561 slots[i]->bank_swizzle = bank_swizzle[i];
562 }
563 return 0;
564 }
565
566 if (scalar_only) {
567 bank_swizzle[4]++;
568 } else {
569 for (i = 0; i < max_slots; i++) {
570 if (!slots[i] || !slots[i]->bank_swizzle_force) {
571 bank_swizzle[i]++;
572 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
573 break;
574 else if (i < max_slots - 1)
575 bank_swizzle[i] = SQ_ALU_VEC_012;
576 else
577 return -1;
578 }
579 }
580 }
581 }
582
583 /* Couldn't find a working swizzle. */
584 return -1;
585 }
586
587 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
588 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
589 {
590 struct r600_bytecode_alu *prev[5];
591 int gpr[5], chan[5];
592 int i, j, r, src, num_src;
593 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
594
595 r = assign_alu_units(bc, alu_prev, prev);
596 if (r)
597 return r;
598
599 for (i = 0; i < max_slots; ++i) {
600 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
601
602 if (is_alu_64bit_inst(bc, prev[i])) {
603 gpr[i] = -1;
604 continue;
605 }
606
607 gpr[i] = prev[i]->dst.sel;
608 /* cube writes more than PV.X */
609 if (is_alu_reduction_inst(bc, prev[i]))
610 chan[i] = 0;
611 else
612 chan[i] = prev[i]->dst.chan;
613 } else
614 gpr[i] = -1;
615 }
616
617 for (i = 0; i < max_slots; ++i) {
618 struct r600_bytecode_alu *alu = slots[i];
619 if (!alu)
620 continue;
621
622 if (is_alu_64bit_inst(bc, alu))
623 continue;
624 num_src = r600_bytecode_get_num_operands(bc, alu);
625 for (src = 0; src < num_src; ++src) {
626 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
627 continue;
628
629 if (bc->chip_class < CAYMAN) {
630 if (alu->src[src].sel == gpr[4] &&
631 alu->src[src].chan == chan[4] &&
632 alu_prev->pred_sel == alu->pred_sel) {
633 alu->src[src].sel = V_SQ_ALU_SRC_PS;
634 alu->src[src].chan = 0;
635 continue;
636 }
637 }
638
639 for (j = 0; j < 4; ++j) {
640 if (alu->src[src].sel == gpr[j] &&
641 alu->src[src].chan == j &&
642 alu_prev->pred_sel == alu->pred_sel) {
643 alu->src[src].sel = V_SQ_ALU_SRC_PV;
644 alu->src[src].chan = chan[j];
645 break;
646 }
647 }
648 }
649 }
650
651 return 0;
652 }
653
654 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
655 {
656 switch(value) {
657 case 0:
658 *sel = V_SQ_ALU_SRC_0;
659 break;
660 case 1:
661 *sel = V_SQ_ALU_SRC_1_INT;
662 break;
663 case -1:
664 *sel = V_SQ_ALU_SRC_M_1_INT;
665 break;
666 case 0x3F800000: /* 1.0f */
667 *sel = V_SQ_ALU_SRC_1;
668 break;
669 case 0x3F000000: /* 0.5f */
670 *sel = V_SQ_ALU_SRC_0_5;
671 break;
672 case 0xBF800000: /* -1.0f */
673 *sel = V_SQ_ALU_SRC_1;
674 *neg ^= !abs;
675 break;
676 case 0xBF000000: /* -0.5f */
677 *sel = V_SQ_ALU_SRC_0_5;
678 *neg ^= !abs;
679 break;
680 default:
681 *sel = V_SQ_ALU_SRC_LITERAL;
682 break;
683 }
684 }
685
686 /* compute how many literal are needed */
687 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
688 uint32_t literal[4], unsigned *nliteral)
689 {
690 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
691 unsigned i, j;
692
693 for (i = 0; i < num_src; ++i) {
694 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
695 uint32_t value = alu->src[i].value;
696 unsigned found = 0;
697 for (j = 0; j < *nliteral; ++j) {
698 if (literal[j] == value) {
699 found = 1;
700 break;
701 }
702 }
703 if (!found) {
704 if (*nliteral >= 4)
705 return -EINVAL;
706 literal[(*nliteral)++] = value;
707 }
708 }
709 }
710 return 0;
711 }
712
713 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
714 struct r600_bytecode_alu *alu,
715 uint32_t literal[4], unsigned nliteral)
716 {
717 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
718 unsigned i, j;
719
720 for (i = 0; i < num_src; ++i) {
721 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
722 uint32_t value = alu->src[i].value;
723 for (j = 0; j < nliteral; ++j) {
724 if (literal[j] == value) {
725 alu->src[i].chan = j;
726 break;
727 }
728 }
729 }
730 }
731 }
732
733 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
734 struct r600_bytecode_alu *alu_prev)
735 {
736 struct r600_bytecode_alu *prev[5];
737 struct r600_bytecode_alu *result[5] = { NULL };
738
739 uint32_t literal[4], prev_literal[4];
740 unsigned nliteral = 0, prev_nliteral = 0;
741
742 int i, j, r, src, num_src;
743 int num_once_inst = 0;
744 int have_mova = 0, have_rel = 0;
745 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
746
747 r = assign_alu_units(bc, alu_prev, prev);
748 if (r)
749 return r;
750
751 for (i = 0; i < max_slots; ++i) {
752 if (prev[i]) {
753 if (prev[i]->pred_sel)
754 return 0;
755 if (is_alu_once_inst(bc, prev[i]))
756 return 0;
757 }
758 if (slots[i]) {
759 if (slots[i]->pred_sel)
760 return 0;
761 if (is_alu_once_inst(bc, slots[i]))
762 return 0;
763 }
764 }
765
766 for (i = 0; i < max_slots; ++i) {
767 struct r600_bytecode_alu *alu;
768
769 if (num_once_inst > 0)
770 return 0;
771
772 /* check number of literals */
773 if (prev[i]) {
774 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
775 return 0;
776 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
777 return 0;
778 if (is_alu_mova_inst(bc, prev[i])) {
779 if (have_rel)
780 return 0;
781 have_mova = 1;
782 }
783
784 if (alu_uses_rel(bc, prev[i])) {
785 if (have_mova) {
786 return 0;
787 }
788 have_rel = 1;
789 }
790
791 num_once_inst += is_alu_once_inst(bc, prev[i]);
792 }
793 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
794 return 0;
795
796 /* Let's check used slots. */
797 if (prev[i] && !slots[i]) {
798 result[i] = prev[i];
799 continue;
800 } else if (prev[i] && slots[i]) {
801 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
802 /* Trans unit is still free try to use it. */
803 if (is_alu_any_unit_inst(bc, slots[i])) {
804 result[i] = prev[i];
805 result[4] = slots[i];
806 } else if (is_alu_any_unit_inst(bc, prev[i])) {
807 if (slots[i]->dst.sel == prev[i]->dst.sel &&
808 alu_writes(slots[i]) &&
809 alu_writes(prev[i]))
810 return 0;
811
812 result[i] = slots[i];
813 result[4] = prev[i];
814 } else
815 return 0;
816 } else
817 return 0;
818 } else if(!slots[i]) {
819 continue;
820 } else {
821 if (max_slots == 5 && slots[i] && prev[4] &&
822 slots[i]->dst.sel == prev[4]->dst.sel &&
823 slots[i]->dst.chan == prev[4]->dst.chan &&
824 alu_writes(slots[i]) &&
825 alu_writes(prev[4]))
826 return 0;
827
828 result[i] = slots[i];
829 }
830
831 alu = slots[i];
832 num_once_inst += is_alu_once_inst(bc, alu);
833
834 /* don't reschedule NOPs */
835 if (is_nop_inst(bc, alu))
836 return 0;
837
838 if (is_alu_mova_inst(bc, alu)) {
839 if (have_rel) {
840 return 0;
841 }
842 have_mova = 1;
843 }
844
845 if (alu_uses_rel(bc, alu)) {
846 if (have_mova) {
847 return 0;
848 }
849 have_rel = 1;
850 }
851
852 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
853 alu->op == ALU_OP0_SET_CF_IDX1)
854 return 0; /* data hazard with MOVA */
855
856 /* Let's check source gprs */
857 num_src = r600_bytecode_get_num_operands(bc, alu);
858 for (src = 0; src < num_src; ++src) {
859
860 /* Constants don't matter. */
861 if (!is_gpr(alu->src[src].sel))
862 continue;
863
864 for (j = 0; j < max_slots; ++j) {
865 if (!prev[j] || !alu_writes(prev[j]))
866 continue;
867
868 /* If it's relative then we can't determin which gpr is really used. */
869 if (prev[j]->dst.chan == alu->src[src].chan &&
870 (prev[j]->dst.sel == alu->src[src].sel ||
871 prev[j]->dst.rel || alu->src[src].rel))
872 return 0;
873 }
874 }
875 }
876
877 /* more than one PRED_ or KILL_ ? */
878 if (num_once_inst > 1)
879 return 0;
880
881 /* check if the result can still be swizzlet */
882 r = check_and_set_bank_swizzle(bc, result);
883 if (r)
884 return 0;
885
886 /* looks like everything worked out right, apply the changes */
887
888 /* undo adding previus literals */
889 bc->cf_last->ndw -= align(prev_nliteral, 2);
890
891 /* sort instructions */
892 for (i = 0; i < max_slots; ++i) {
893 slots[i] = result[i];
894 if (result[i]) {
895 LIST_DEL(&result[i]->list);
896 result[i]->last = 0;
897 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
898 }
899 }
900
901 /* determine new last instruction */
902 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
903
904 /* determine new first instruction */
905 for (i = 0; i < max_slots; ++i) {
906 if (result[i]) {
907 bc->cf_last->curr_bs_head = result[i];
908 break;
909 }
910 }
911
912 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
913 bc->cf_last->prev2_bs_head = NULL;
914
915 return 0;
916 }
917
918 /* we'll keep kcache sets sorted by bank & addr */
919 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
920 struct r600_bytecode_kcache *kcache,
921 unsigned bank, unsigned line, unsigned index_mode)
922 {
923 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
924
925 for (i = 0; i < kcache_banks; i++) {
926 if (kcache[i].mode) {
927 int d;
928
929 if (kcache[i].bank < bank)
930 continue;
931
932 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
933 kcache[i].bank > bank) {
934 /* try to insert new line */
935 if (kcache[kcache_banks-1].mode) {
936 /* all sets are in use */
937 return -ENOMEM;
938 }
939
940 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
941 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
942 kcache[i].bank = bank;
943 kcache[i].addr = line;
944 kcache[i].index_mode = index_mode;
945 return 0;
946 }
947
948 d = line - kcache[i].addr;
949
950 if (d == -1) {
951 kcache[i].addr--;
952 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
953 /* we are prepending the line to the current set,
954 * discarding the existing second line,
955 * so we'll have to insert line+2 after it */
956 line += 2;
957 continue;
958 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
959 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
960 return 0;
961 } else {
962 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
963 return -ENOMEM;
964 }
965 } else if (d == 1) {
966 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
967 return 0;
968 } else if (d == 0)
969 return 0;
970 } else { /* free kcache set - use it */
971 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
972 kcache[i].bank = bank;
973 kcache[i].addr = line;
974 kcache[i].index_mode = index_mode;
975 return 0;
976 }
977 }
978 return -ENOMEM;
979 }
980
981 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
982 struct r600_bytecode_kcache *kcache,
983 struct r600_bytecode_alu *alu)
984 {
985 int i, r;
986
987 for (i = 0; i < 3; i++) {
988 unsigned bank, line, sel = alu->src[i].sel, index_mode;
989
990 if (sel < 512)
991 continue;
992
993 bank = alu->src[i].kc_bank;
994 line = (sel-512)>>4;
995 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
996
997 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
998 return r;
999 }
1000 return 0;
1001 }
1002
1003 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1004 struct r600_bytecode_alu *alu,
1005 struct r600_bytecode_kcache * kcache)
1006 {
1007 int i, j;
1008
1009 /* Alter the src operands to refer to the kcache. */
1010 for (i = 0; i < 3; ++i) {
1011 static const unsigned int base[] = {128, 160, 256, 288};
1012 unsigned int line, sel = alu->src[i].sel, found = 0;
1013
1014 if (sel < 512)
1015 continue;
1016
1017 sel -= 512;
1018 line = sel>>4;
1019
1020 for (j = 0; j < 4 && !found; ++j) {
1021 switch (kcache[j].mode) {
1022 case V_SQ_CF_KCACHE_NOP:
1023 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1024 R600_ERR("unexpected kcache line mode\n");
1025 return -ENOMEM;
1026 default:
1027 if (kcache[j].bank == alu->src[i].kc_bank &&
1028 kcache[j].addr <= line &&
1029 line < kcache[j].addr + kcache[j].mode) {
1030 alu->src[i].sel = sel - (kcache[j].addr<<4);
1031 alu->src[i].sel += base[j];
1032 found=1;
1033 }
1034 }
1035 }
1036 }
1037 return 0;
1038 }
1039
1040 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1041 struct r600_bytecode_alu *alu,
1042 unsigned type)
1043 {
1044 struct r600_bytecode_kcache kcache_sets[4];
1045 struct r600_bytecode_kcache *kcache = kcache_sets;
1046 int r;
1047
1048 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1049
1050 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1051 /* can't alloc, need to start new clause */
1052 if ((r = r600_bytecode_add_cf(bc))) {
1053 return r;
1054 }
1055 bc->cf_last->op = type;
1056
1057 /* retry with the new clause */
1058 kcache = bc->cf_last->kcache;
1059 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1060 /* can't alloc again- should never happen */
1061 return r;
1062 }
1063 } else {
1064 /* update kcache sets */
1065 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1066 }
1067
1068 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1069 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1070 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1071 if (bc->chip_class < EVERGREEN)
1072 return -ENOMEM;
1073 bc->cf_last->eg_alu_extended = 1;
1074 }
1075
1076 return 0;
1077 }
1078
1079 static int insert_nop_r6xx(struct r600_bytecode *bc)
1080 {
1081 struct r600_bytecode_alu alu;
1082 int r, i;
1083
1084 for (i = 0; i < 4; i++) {
1085 memset(&alu, 0, sizeof(alu));
1086 alu.op = ALU_OP0_NOP;
1087 alu.src[0].chan = i;
1088 alu.dst.chan = i;
1089 alu.last = (i == 3);
1090 r = r600_bytecode_add_alu(bc, &alu);
1091 if (r)
1092 return r;
1093 }
1094 return 0;
1095 }
1096
1097 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1098 static int load_ar_r6xx(struct r600_bytecode *bc)
1099 {
1100 struct r600_bytecode_alu alu;
1101 int r;
1102
1103 if (bc->ar_loaded)
1104 return 0;
1105
1106 /* hack to avoid making MOVA the last instruction in the clause */
1107 if ((bc->cf_last->ndw>>1) >= 110)
1108 bc->force_add_cf = 1;
1109
1110 memset(&alu, 0, sizeof(alu));
1111 alu.op = ALU_OP1_MOVA_GPR_INT;
1112 alu.src[0].sel = bc->ar_reg;
1113 alu.src[0].chan = bc->ar_chan;
1114 alu.last = 1;
1115 alu.index_mode = INDEX_MODE_LOOP;
1116 r = r600_bytecode_add_alu(bc, &alu);
1117 if (r)
1118 return r;
1119
1120 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1121 bc->ar_loaded = 1;
1122 return 0;
1123 }
1124
1125 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1126 static int load_ar(struct r600_bytecode *bc)
1127 {
1128 struct r600_bytecode_alu alu;
1129 int r;
1130
1131 if (bc->ar_handling)
1132 return load_ar_r6xx(bc);
1133
1134 if (bc->ar_loaded)
1135 return 0;
1136
1137 /* hack to avoid making MOVA the last instruction in the clause */
1138 if ((bc->cf_last->ndw>>1) >= 110)
1139 bc->force_add_cf = 1;
1140
1141 memset(&alu, 0, sizeof(alu));
1142 alu.op = ALU_OP1_MOVA_INT;
1143 alu.src[0].sel = bc->ar_reg;
1144 alu.src[0].chan = bc->ar_chan;
1145 alu.last = 1;
1146 r = r600_bytecode_add_alu(bc, &alu);
1147 if (r)
1148 return r;
1149
1150 bc->cf_last->r6xx_uses_waterfall = 1;
1151 bc->ar_loaded = 1;
1152 return 0;
1153 }
1154
1155 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1156 const struct r600_bytecode_alu *alu, unsigned type)
1157 {
1158 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1159 struct r600_bytecode_alu *lalu;
1160 int i, r;
1161
1162 if (!nalu)
1163 return -ENOMEM;
1164 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1165
1166 if (alu->is_op3) {
1167 /* will fail later since alu does not support it. */
1168 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1169 }
1170
1171 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1172 /* check if we could add it anyway */
1173 if (bc->cf_last->op == CF_OP_ALU &&
1174 type == CF_OP_ALU_PUSH_BEFORE) {
1175 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1176 if (lalu->execute_mask) {
1177 bc->force_add_cf = 1;
1178 break;
1179 }
1180 }
1181 } else
1182 bc->force_add_cf = 1;
1183 }
1184
1185 /* cf can contains only alu or only vtx or only tex */
1186 if (bc->cf_last == NULL || bc->force_add_cf) {
1187 r = r600_bytecode_add_cf(bc);
1188 if (r) {
1189 free(nalu);
1190 return r;
1191 }
1192 }
1193 bc->cf_last->op = type;
1194
1195 /* Load index register if required */
1196 if (bc->chip_class >= EVERGREEN) {
1197 for (i = 0; i < 3; i++)
1198 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1199 egcm_load_index_reg(bc, 0, true);
1200 }
1201
1202 /* Check AR usage and load it if required */
1203 for (i = 0; i < 3; i++)
1204 if (nalu->src[i].rel && !bc->ar_loaded)
1205 load_ar(bc);
1206
1207 if (nalu->dst.rel && !bc->ar_loaded)
1208 load_ar(bc);
1209
1210 /* Setup the kcache for this ALU instruction. This will start a new
1211 * ALU clause if needed. */
1212 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1213 free(nalu);
1214 return r;
1215 }
1216
1217 if (!bc->cf_last->curr_bs_head) {
1218 bc->cf_last->curr_bs_head = nalu;
1219 }
1220 /* number of gpr == the last gpr used in any alu */
1221 for (i = 0; i < 3; i++) {
1222 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1223 bc->ngpr = nalu->src[i].sel + 1;
1224 }
1225 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1226 r600_bytecode_special_constants(nalu->src[i].value,
1227 &nalu->src[i].sel, &nalu->src[i].neg, nalu->src[i].abs);
1228 }
1229 if (nalu->dst.sel >= bc->ngpr) {
1230 bc->ngpr = nalu->dst.sel + 1;
1231 }
1232 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1233 /* each alu use 2 dwords */
1234 bc->cf_last->ndw += 2;
1235 bc->ndw += 2;
1236
1237 /* process cur ALU instructions for bank swizzle */
1238 if (nalu->last) {
1239 uint32_t literal[4];
1240 unsigned nliteral;
1241 struct r600_bytecode_alu *slots[5];
1242 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1243 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1244 if (r)
1245 return r;
1246
1247 if (bc->cf_last->prev_bs_head) {
1248 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1249 if (r)
1250 return r;
1251 }
1252
1253 if (bc->cf_last->prev_bs_head) {
1254 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1255 if (r)
1256 return r;
1257 }
1258
1259 r = check_and_set_bank_swizzle(bc, slots);
1260 if (r)
1261 return r;
1262
1263 for (i = 0, nliteral = 0; i < max_slots; i++) {
1264 if (slots[i]) {
1265 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1266 if (r)
1267 return r;
1268 }
1269 }
1270 bc->cf_last->ndw += align(nliteral, 2);
1271
1272 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1273 * worst case */
1274 if ((bc->cf_last->ndw >> 1) >= 120) {
1275 bc->force_add_cf = 1;
1276 }
1277
1278 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1279 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1280 bc->cf_last->curr_bs_head = NULL;
1281 }
1282
1283 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1284 insert_nop_r6xx(bc);
1285
1286 return 0;
1287 }
1288
1289 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1290 {
1291 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1292 }
1293
1294 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1295 {
1296 switch (bc->chip_class) {
1297 case R600:
1298 return 8;
1299
1300 case R700:
1301 case EVERGREEN:
1302 case CAYMAN:
1303 return 16;
1304
1305 default:
1306 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1307 return 8;
1308 }
1309 }
1310
1311 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1312 {
1313 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1314 (bc->chip_class == CAYMAN ||
1315 bc->cf_last->op != CF_OP_TEX));
1316 }
1317
1318 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1319 {
1320 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1321 int r;
1322
1323 if (!nvtx)
1324 return -ENOMEM;
1325 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1326
1327 /* Load index register if required */
1328 if (bc->chip_class >= EVERGREEN) {
1329 if (vtx->buffer_index_mode)
1330 egcm_load_index_reg(bc, 0, false);
1331 }
1332
1333 /* cf can contains only alu or only vtx or only tex */
1334 if (bc->cf_last == NULL ||
1335 last_inst_was_not_vtx_fetch(bc) ||
1336 bc->force_add_cf) {
1337 r = r600_bytecode_add_cf(bc);
1338 if (r) {
1339 free(nvtx);
1340 return r;
1341 }
1342 switch (bc->chip_class) {
1343 case R600:
1344 case R700:
1345 case EVERGREEN:
1346 bc->cf_last->op = CF_OP_VTX;
1347 break;
1348 case CAYMAN:
1349 bc->cf_last->op = CF_OP_TEX;
1350 break;
1351 default:
1352 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1353 free(nvtx);
1354 return -EINVAL;
1355 }
1356 }
1357 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1358 /* each fetch use 4 dwords */
1359 bc->cf_last->ndw += 4;
1360 bc->ndw += 4;
1361 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1362 bc->force_add_cf = 1;
1363
1364 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1365 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1366
1367 return 0;
1368 }
1369
1370 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1371 {
1372 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1373 int r;
1374
1375 if (!ntex)
1376 return -ENOMEM;
1377 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1378
1379 /* Load index register if required */
1380 if (bc->chip_class >= EVERGREEN) {
1381 if (tex->sampler_index_mode || tex->resource_index_mode)
1382 egcm_load_index_reg(bc, 1, false);
1383 }
1384
1385 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1386 if (bc->cf_last != NULL &&
1387 bc->cf_last->op == CF_OP_TEX) {
1388 struct r600_bytecode_tex *ttex;
1389 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1390 if (ttex->dst_gpr == ntex->src_gpr) {
1391 bc->force_add_cf = 1;
1392 break;
1393 }
1394 }
1395 /* slight hack to make gradients always go into same cf */
1396 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1397 bc->force_add_cf = 1;
1398 }
1399
1400 /* cf can contains only alu or only vtx or only tex */
1401 if (bc->cf_last == NULL ||
1402 bc->cf_last->op != CF_OP_TEX ||
1403 bc->force_add_cf) {
1404 r = r600_bytecode_add_cf(bc);
1405 if (r) {
1406 free(ntex);
1407 return r;
1408 }
1409 bc->cf_last->op = CF_OP_TEX;
1410 }
1411 if (ntex->src_gpr >= bc->ngpr) {
1412 bc->ngpr = ntex->src_gpr + 1;
1413 }
1414 if (ntex->dst_gpr >= bc->ngpr) {
1415 bc->ngpr = ntex->dst_gpr + 1;
1416 }
1417 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1418 /* each texture fetch use 4 dwords */
1419 bc->cf_last->ndw += 4;
1420 bc->ndw += 4;
1421 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1422 bc->force_add_cf = 1;
1423 return 0;
1424 }
1425
1426 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1427 {
1428 struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1429 int r;
1430
1431 if (ngds == NULL)
1432 return -ENOMEM;
1433 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1434
1435 if (bc->cf_last == NULL ||
1436 bc->cf_last->op != CF_OP_GDS ||
1437 bc->force_add_cf) {
1438 r = r600_bytecode_add_cf(bc);
1439 if (r) {
1440 free(ngds);
1441 return r;
1442 }
1443 bc->cf_last->op = CF_OP_GDS;
1444 }
1445
1446 LIST_ADDTAIL(&ngds->list, &bc->cf_last->gds);
1447 bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1448 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1449 bc->force_add_cf = 1;
1450 return 0;
1451 }
1452
1453 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1454 {
1455 int r;
1456 r = r600_bytecode_add_cf(bc);
1457 if (r)
1458 return r;
1459
1460 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1461 bc->cf_last->op = op;
1462 return 0;
1463 }
1464
1465 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1466 {
1467 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1468 }
1469
1470 /* common to all 3 families */
1471 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1472 {
1473 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1474 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1475 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1476 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1477 if (bc->chip_class < CAYMAN)
1478 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1479 id++;
1480 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1481 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1482 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1483 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1484 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1485 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1486 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1487 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1488 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1489 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1490 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1491 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1492 if (bc->chip_class >= EVERGREEN)
1493 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1494 if (bc->chip_class < CAYMAN)
1495 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1496 id++;
1497 bc->bytecode[id++] = 0;
1498 return 0;
1499 }
1500
1501 /* common to all 3 families */
1502 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1503 {
1504 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1505 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1506 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1507 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1508 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1509 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1510 if (bc->chip_class >= EVERGREEN)
1511 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1512 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1513 id++;
1514 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1515 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1516 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1517 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1518 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1519 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1520 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1521 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1522 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1523 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1524 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1525 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1526 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1527 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1528 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1529 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1530 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1531 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1532 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1533 bc->bytecode[id++] = 0;
1534 return 0;
1535 }
1536
1537 /* r600 only, r700/eg bits in r700_asm.c */
1538 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1539 {
1540 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1541
1542 /* don't replace gpr by pv or ps for destination register */
1543 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1544 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1545 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1546 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1547 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1548 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1549 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1550 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1551 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1552 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1553 S_SQ_ALU_WORD0_LAST(alu->last);
1554
1555 if (alu->is_op3) {
1556 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1557 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1558 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1559 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1560 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1561 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1562 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1563 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1564 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1565 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1566 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1567 } else {
1568 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1569 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1570 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1571 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1572 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1573 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1574 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1575 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1576 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1577 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1578 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1579 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1580 }
1581 return 0;
1582 }
1583
1584 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1585 {
1586 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1587 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1588 S_SQ_CF_WORD1_BARRIER(1) |
1589 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1590 }
1591
1592 /* common for r600/r700 - eg in eg_asm.c */
1593 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1594 {
1595 unsigned id = cf->id;
1596 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1597 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1598
1599
1600 if (cf->op == CF_NATIVE) {
1601 bc->bytecode[id++] = cf->isa[0];
1602 bc->bytecode[id++] = cf->isa[1];
1603 } else if (cfop->flags & CF_ALU) {
1604 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1605 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1606 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1607 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1608
1609 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1610 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1611 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1612 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1613 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1614 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1615 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1616 } else if (cfop->flags & CF_FETCH) {
1617 if (bc->chip_class == R700)
1618 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1619 else
1620 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1621 } else if (cfop->flags & CF_EXP) {
1622 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1623 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1624 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1625 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1626 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1627 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1628 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1629 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1630 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1631 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1632 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1633 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1634 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1635 } else if (cfop->flags & CF_MEM) {
1636 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1637 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1638 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1639 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1640 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1641 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1642 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1643 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1644 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1645 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1646 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1647 } else {
1648 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1649 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1650 S_SQ_CF_WORD1_BARRIER(1) |
1651 S_SQ_CF_WORD1_COND(cf->cond) |
1652 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1653 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1654 }
1655 return 0;
1656 }
1657
1658 int r600_bytecode_build(struct r600_bytecode *bc)
1659 {
1660 struct r600_bytecode_cf *cf;
1661 struct r600_bytecode_alu *alu;
1662 struct r600_bytecode_vtx *vtx;
1663 struct r600_bytecode_tex *tex;
1664 struct r600_bytecode_gds *gds;
1665 uint32_t literal[4];
1666 unsigned nliteral;
1667 unsigned addr;
1668 int i, r;
1669
1670 if (!bc->nstack) // If not 0, Stack_size already provided by llvm
1671 bc->nstack = bc->stack.max_entries;
1672
1673 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1674 bc->nstack = 1;
1675 }
1676
1677 /* first path compute addr of each CF block */
1678 /* addr start after all the CF instructions */
1679 addr = bc->cf_last->id + 2;
1680 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1681 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1682 addr += 3;
1683 addr &= 0xFFFFFFFCUL;
1684 }
1685 cf->addr = addr;
1686 addr += cf->ndw;
1687 bc->ndw = cf->addr + cf->ndw;
1688 }
1689 free(bc->bytecode);
1690 bc->bytecode = calloc(4, bc->ndw);
1691 if (bc->bytecode == NULL)
1692 return -ENOMEM;
1693 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1694 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1695 addr = cf->addr;
1696 if (bc->chip_class >= EVERGREEN)
1697 r = eg_bytecode_cf_build(bc, cf);
1698 else
1699 r = r600_bytecode_cf_build(bc, cf);
1700 if (r)
1701 return r;
1702 if (cfop->flags & CF_ALU) {
1703 nliteral = 0;
1704 memset(literal, 0, sizeof(literal));
1705 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1706 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1707 if (r)
1708 return r;
1709 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1710 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1711
1712 switch(bc->chip_class) {
1713 case R600:
1714 r = r600_bytecode_alu_build(bc, alu, addr);
1715 break;
1716 case R700:
1717 case EVERGREEN: /* eg alu is same encoding as r700 */
1718 case CAYMAN:
1719 r = r700_bytecode_alu_build(bc, alu, addr);
1720 break;
1721 default:
1722 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1723 return -EINVAL;
1724 }
1725 if (r)
1726 return r;
1727 addr += 2;
1728 if (alu->last) {
1729 for (i = 0; i < align(nliteral, 2); ++i) {
1730 bc->bytecode[addr++] = literal[i];
1731 }
1732 nliteral = 0;
1733 memset(literal, 0, sizeof(literal));
1734 }
1735 }
1736 } else if (cf->op == CF_OP_VTX) {
1737 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1738 r = r600_bytecode_vtx_build(bc, vtx, addr);
1739 if (r)
1740 return r;
1741 addr += 4;
1742 }
1743 } else if (cf->op == CF_OP_GDS) {
1744 assert(bc->chip_class >= EVERGREEN);
1745 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1746 r = eg_bytecode_gds_build(bc, gds, addr);
1747 if (r)
1748 return r;
1749 addr += 4;
1750 }
1751 } else if (cf->op == CF_OP_TEX) {
1752 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1753 assert(bc->chip_class >= EVERGREEN);
1754 r = r600_bytecode_vtx_build(bc, vtx, addr);
1755 if (r)
1756 return r;
1757 addr += 4;
1758 }
1759 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1760 r = r600_bytecode_tex_build(bc, tex, addr);
1761 if (r)
1762 return r;
1763 addr += 4;
1764 }
1765 }
1766 }
1767 return 0;
1768 }
1769
1770 void r600_bytecode_clear(struct r600_bytecode *bc)
1771 {
1772 struct r600_bytecode_cf *cf = NULL, *next_cf;
1773
1774 free(bc->bytecode);
1775 bc->bytecode = NULL;
1776
1777 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1778 struct r600_bytecode_alu *alu = NULL, *next_alu;
1779 struct r600_bytecode_tex *tex = NULL, *next_tex;
1780 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1781 struct r600_bytecode_gds *gds = NULL, *next_gds;
1782
1783 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1784 free(alu);
1785 }
1786
1787 LIST_INITHEAD(&cf->alu);
1788
1789 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1790 free(tex);
1791 }
1792
1793 LIST_INITHEAD(&cf->tex);
1794
1795 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1796 free(vtx);
1797 }
1798
1799 LIST_INITHEAD(&cf->vtx);
1800
1801 LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1802 free(gds);
1803 }
1804
1805 LIST_INITHEAD(&cf->gds);
1806
1807 free(cf);
1808 }
1809
1810 LIST_INITHEAD(&cf->list);
1811 }
1812
1813 static int print_swizzle(unsigned swz)
1814 {
1815 const char * swzchars = "xyzw01?_";
1816 assert(swz<8 && swz != 6);
1817 return fprintf(stderr, "%c", swzchars[swz]);
1818 }
1819
1820 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1821 unsigned need_brackets)
1822 {
1823 int o = 0;
1824 if (rel && index_mode >= 5 && sel < 128)
1825 o += fprintf(stderr, "G");
1826 if (rel || need_brackets) {
1827 o += fprintf(stderr, "[");
1828 }
1829 o += fprintf(stderr, "%d", sel);
1830 if (rel) {
1831 if (index_mode == 0 || index_mode == 6)
1832 o += fprintf(stderr, "+AR");
1833 else if (index_mode == 4)
1834 o += fprintf(stderr, "+AL");
1835 }
1836 if (rel || need_brackets) {
1837 o += fprintf(stderr, "]");
1838 }
1839 return o;
1840 }
1841
1842 static int print_dst(struct r600_bytecode_alu *alu)
1843 {
1844 int o = 0;
1845 unsigned sel = alu->dst.sel;
1846 char reg_char = 'R';
1847 if (sel > 128 - 4) { /* clause temporary gpr */
1848 sel -= 128 - 4;
1849 reg_char = 'T';
1850 }
1851
1852 if (alu_writes(alu)) {
1853 o += fprintf(stderr, "%c", reg_char);
1854 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1855 } else {
1856 o += fprintf(stderr, "__");
1857 }
1858 o += fprintf(stderr, ".");
1859 o += print_swizzle(alu->dst.chan);
1860 return o;
1861 }
1862
1863 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1864 {
1865 int o = 0;
1866 struct r600_bytecode_alu_src *src = &alu->src[idx];
1867 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1868
1869 if (src->neg)
1870 o += fprintf(stderr,"-");
1871 if (src->abs)
1872 o += fprintf(stderr,"|");
1873
1874 if (sel < 128 - 4) {
1875 o += fprintf(stderr, "R");
1876 } else if (sel < 128) {
1877 o += fprintf(stderr, "T");
1878 sel -= 128 - 4;
1879 } else if (sel < 160) {
1880 o += fprintf(stderr, "KC0");
1881 need_brackets = 1;
1882 sel -= 128;
1883 } else if (sel < 192) {
1884 o += fprintf(stderr, "KC1");
1885 need_brackets = 1;
1886 sel -= 160;
1887 } else if (sel >= 512) {
1888 o += fprintf(stderr, "C%d", src->kc_bank);
1889 need_brackets = 1;
1890 sel -= 512;
1891 } else if (sel >= 448) {
1892 o += fprintf(stderr, "Param");
1893 sel -= 448;
1894 need_chan = 0;
1895 } else if (sel >= 288) {
1896 o += fprintf(stderr, "KC3");
1897 need_brackets = 1;
1898 sel -= 288;
1899 } else if (sel >= 256) {
1900 o += fprintf(stderr, "KC2");
1901 need_brackets = 1;
1902 sel -= 256;
1903 } else {
1904 need_sel = 0;
1905 need_chan = 0;
1906 switch (sel) {
1907 case V_SQ_ALU_SRC_PS:
1908 o += fprintf(stderr, "PS");
1909 break;
1910 case V_SQ_ALU_SRC_PV:
1911 o += fprintf(stderr, "PV");
1912 need_chan = 1;
1913 break;
1914 case V_SQ_ALU_SRC_LITERAL:
1915 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value);
1916 break;
1917 case V_SQ_ALU_SRC_0_5:
1918 o += fprintf(stderr, "0.5");
1919 break;
1920 case V_SQ_ALU_SRC_M_1_INT:
1921 o += fprintf(stderr, "-1");
1922 break;
1923 case V_SQ_ALU_SRC_1_INT:
1924 o += fprintf(stderr, "1");
1925 break;
1926 case V_SQ_ALU_SRC_1:
1927 o += fprintf(stderr, "1.0");
1928 break;
1929 case V_SQ_ALU_SRC_0:
1930 o += fprintf(stderr, "0");
1931 break;
1932 default:
1933 o += fprintf(stderr, "??IMM_%d", sel);
1934 break;
1935 }
1936 }
1937
1938 if (need_sel)
1939 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
1940
1941 if (need_chan) {
1942 o += fprintf(stderr, ".");
1943 o += print_swizzle(src->chan);
1944 }
1945
1946 if (src->abs)
1947 o += fprintf(stderr,"|");
1948
1949 return o;
1950 }
1951
1952 static int print_indent(int p, int c)
1953 {
1954 int o = 0;
1955 while (p++ < c)
1956 o += fprintf(stderr, " ");
1957 return o;
1958 }
1959
1960 void r600_bytecode_disasm(struct r600_bytecode *bc)
1961 {
1962 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
1963 static int index = 0;
1964 struct r600_bytecode_cf *cf = NULL;
1965 struct r600_bytecode_alu *alu = NULL;
1966 struct r600_bytecode_vtx *vtx = NULL;
1967 struct r600_bytecode_tex *tex = NULL;
1968 struct r600_bytecode_gds *gds = NULL;
1969
1970 unsigned i, id, ngr = 0, last;
1971 uint32_t literal[4];
1972 unsigned nliteral;
1973 char chip = '6';
1974
1975 switch (bc->chip_class) {
1976 case R700:
1977 chip = '7';
1978 break;
1979 case EVERGREEN:
1980 chip = 'E';
1981 break;
1982 case CAYMAN:
1983 chip = 'C';
1984 break;
1985 case R600:
1986 default:
1987 chip = '6';
1988 break;
1989 }
1990 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1991 bc->ndw, bc->ngpr, bc->nstack);
1992 fprintf(stderr, "shader %d -- %c\n", index++, chip);
1993
1994 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1995 id = cf->id;
1996 if (cf->op == CF_NATIVE) {
1997 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
1998 bc->bytecode[id + 1]);
1999 } else {
2000 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2001 if (cfop->flags & CF_ALU) {
2002 if (cf->eg_alu_extended) {
2003 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2004 bc->bytecode[id + 1], "ALU_EXT");
2005 id += 2;
2006 }
2007 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2008 bc->bytecode[id + 1], cfop->name);
2009 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2010 for (i = 0; i < 4; ++i) {
2011 if (cf->kcache[i].mode) {
2012 int c_start = (cf->kcache[i].addr << 4);
2013 int c_end = c_start + (cf->kcache[i].mode << 4);
2014 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2015 i, cf->kcache[i].bank, c_start, c_end,
2016 cf->kcache[i].index_mode ? " " : "",
2017 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2018 }
2019 }
2020 fprintf(stderr, "\n");
2021 } else if (cfop->flags & CF_FETCH) {
2022 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2023 bc->bytecode[id + 1], cfop->name);
2024 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2025 fprintf(stderr, "\n");
2026 } else if (cfop->flags & CF_EXP) {
2027 int o = 0;
2028 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2029 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2030 bc->bytecode[id + 1], cfop->name);
2031 o += print_indent(o, 43);
2032 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2033 if (cf->output.burst_count > 1) {
2034 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2035 cf->output.array_base + cf->output.burst_count - 1);
2036
2037 o += print_indent(o, 55);
2038 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2039 cf->output.gpr + cf->output.burst_count - 1);
2040 } else {
2041 o += fprintf(stderr, "%d ", cf->output.array_base);
2042 o += print_indent(o, 55);
2043 o += fprintf(stderr, "R%d.", cf->output.gpr);
2044 }
2045
2046 o += print_swizzle(cf->output.swizzle_x);
2047 o += print_swizzle(cf->output.swizzle_y);
2048 o += print_swizzle(cf->output.swizzle_z);
2049 o += print_swizzle(cf->output.swizzle_w);
2050
2051 print_indent(o, 67);
2052
2053 fprintf(stderr, " ES:%X ", cf->output.elem_size);
2054 if (!cf->barrier)
2055 fprintf(stderr, "NO_BARRIER ");
2056 if (cf->end_of_program)
2057 fprintf(stderr, "EOP ");
2058 fprintf(stderr, "\n");
2059 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2060 int o = 0;
2061 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2062 "WRITE_IND_ACK"};
2063 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2064 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2065 o += print_indent(o, 43);
2066 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2067 if (cf->output.burst_count > 1) {
2068 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2069 cf->output.array_base + cf->output.burst_count - 1);
2070 o += print_indent(o, 55);
2071 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2072 cf->output.gpr + cf->output.burst_count - 1);
2073 } else {
2074 o += fprintf(stderr, "%d ", cf->output.array_base);
2075 o += print_indent(o, 55);
2076 o += fprintf(stderr, "R%d.", cf->output.gpr);
2077 }
2078 for (i = 0; i < 4; ++i) {
2079 if (cf->output.comp_mask & (1 << i))
2080 o += print_swizzle(i);
2081 else
2082 o += print_swizzle(7);
2083 }
2084
2085 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND)
2086 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2087
2088 o += print_indent(o, 67);
2089
2090 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2091 if (cf->output.array_size != 0xFFF)
2092 fprintf(stderr, "AS:%i ", cf->output.array_size);
2093 if (!cf->barrier)
2094 fprintf(stderr, "NO_BARRIER ");
2095 if (cf->end_of_program)
2096 fprintf(stderr, "EOP ");
2097 fprintf(stderr, "\n");
2098 } else {
2099 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2100 bc->bytecode[id + 1], cfop->name);
2101 fprintf(stderr, "@%d ", cf->cf_addr);
2102 if (cf->cond)
2103 fprintf(stderr, "CND:%X ", cf->cond);
2104 if (cf->pop_count)
2105 fprintf(stderr, "POP:%X ", cf->pop_count);
2106 if (cf->count && (cfop->flags & CF_EMIT))
2107 fprintf(stderr, "STREAM%d ", cf->count);
2108 if (cf->end_of_program)
2109 fprintf(stderr, "EOP ");
2110 fprintf(stderr, "\n");
2111 }
2112 }
2113
2114 id = cf->addr;
2115 nliteral = 0;
2116 last = 1;
2117 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2118 const char *omod_str[] = {"","*2","*4","/2"};
2119 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2120 int o = 0;
2121
2122 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2123 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2124 if (last)
2125 o += fprintf(stderr, "%4d ", ++ngr);
2126 else
2127 o += fprintf(stderr, " ");
2128 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2129 alu->update_pred ? 'P':' ',
2130 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2131
2132 o += fprintf(stderr, "%s%s%s ", aop->name,
2133 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2134
2135 o += print_indent(o,60);
2136 o += print_dst(alu);
2137 for (i = 0; i < aop->src_count; ++i) {
2138 o += fprintf(stderr, i == 0 ? ", ": ", ");
2139 o += print_src(alu, i);
2140 }
2141
2142 if (alu->bank_swizzle) {
2143 o += print_indent(o,75);
2144 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2145 }
2146
2147 fprintf(stderr, "\n");
2148 id += 2;
2149
2150 if (alu->last) {
2151 for (i = 0; i < nliteral; i++, id++) {
2152 float *f = (float*)(bc->bytecode + id);
2153 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2154 print_indent(o, 60);
2155 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2156 }
2157 id += nliteral & 1;
2158 nliteral = 0;
2159 }
2160 last = alu->last;
2161 }
2162
2163 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2164 int o = 0;
2165 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2166 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2167
2168 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2169
2170 o += print_indent(o, 50);
2171
2172 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2173 o += print_swizzle(tex->dst_sel_x);
2174 o += print_swizzle(tex->dst_sel_y);
2175 o += print_swizzle(tex->dst_sel_z);
2176 o += print_swizzle(tex->dst_sel_w);
2177
2178 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2179 o += print_swizzle(tex->src_sel_x);
2180 o += print_swizzle(tex->src_sel_y);
2181 o += print_swizzle(tex->src_sel_z);
2182 o += print_swizzle(tex->src_sel_w);
2183
2184 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2185 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2186
2187 if (tex->sampler_index_mode)
2188 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2189
2190 if (tex->lod_bias)
2191 fprintf(stderr, "LB:%d ", tex->lod_bias);
2192
2193 fprintf(stderr, "CT:%c%c%c%c ",
2194 tex->coord_type_x ? 'N' : 'U',
2195 tex->coord_type_y ? 'N' : 'U',
2196 tex->coord_type_z ? 'N' : 'U',
2197 tex->coord_type_w ? 'N' : 'U');
2198
2199 if (tex->offset_x)
2200 fprintf(stderr, "OX:%d ", tex->offset_x);
2201 if (tex->offset_y)
2202 fprintf(stderr, "OY:%d ", tex->offset_y);
2203 if (tex->offset_z)
2204 fprintf(stderr, "OZ:%d ", tex->offset_z);
2205
2206 id += 4;
2207 fprintf(stderr, "\n");
2208 }
2209
2210 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2211 int o = 0;
2212 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2213 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2214 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2215
2216 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2217
2218 o += print_indent(o, 50);
2219
2220 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2221 o += print_swizzle(vtx->dst_sel_x);
2222 o += print_swizzle(vtx->dst_sel_y);
2223 o += print_swizzle(vtx->dst_sel_z);
2224 o += print_swizzle(vtx->dst_sel_w);
2225
2226 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2227 o += print_swizzle(vtx->src_sel_x);
2228
2229 if (vtx->offset)
2230 fprintf(stderr, " +%db", vtx->offset);
2231
2232 o += print_indent(o, 55);
2233
2234 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2235
2236 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2237
2238 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2239 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2240
2241 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2242 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2243
2244 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2245 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2246 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2247 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2248 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2249
2250 id += 4;
2251 }
2252
2253 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2254 int o = 0;
2255 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2256 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2257
2258 o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2259
2260 if (gds->op != FETCH_OP_TF_WRITE) {
2261 o += fprintf(stderr, "R%d.", gds->dst_gpr);
2262 o += print_swizzle(gds->dst_sel_x);
2263 o += print_swizzle(gds->dst_sel_y);
2264 o += print_swizzle(gds->dst_sel_z);
2265 o += print_swizzle(gds->dst_sel_w);
2266 }
2267
2268 o += fprintf(stderr, ", R%d.", gds->src_gpr);
2269 o += print_swizzle(gds->src_sel_x);
2270 o += print_swizzle(gds->src_sel_y);
2271 o += print_swizzle(gds->src_sel_z);
2272
2273 if (gds->op != FETCH_OP_TF_WRITE) {
2274 o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2275 }
2276 fprintf(stderr, "\n");
2277 id += 4;
2278 }
2279 }
2280
2281 fprintf(stderr, "--------------------------------------\n");
2282 }
2283
2284 void r600_vertex_data_type(enum pipe_format pformat,
2285 unsigned *format,
2286 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2287 {
2288 const struct util_format_description *desc;
2289 unsigned i;
2290
2291 *format = 0;
2292 *num_format = 0;
2293 *format_comp = 0;
2294 *endian = ENDIAN_NONE;
2295
2296 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2297 *format = FMT_10_11_11_FLOAT;
2298 *endian = r600_endian_swap(32);
2299 return;
2300 }
2301
2302 desc = util_format_description(pformat);
2303 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2304 goto out_unknown;
2305 }
2306
2307 /* Find the first non-VOID channel. */
2308 for (i = 0; i < 4; i++) {
2309 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2310 break;
2311 }
2312 }
2313
2314 *endian = r600_endian_swap(desc->channel[i].size);
2315
2316 switch (desc->channel[i].type) {
2317 /* Half-floats, floats, ints */
2318 case UTIL_FORMAT_TYPE_FLOAT:
2319 switch (desc->channel[i].size) {
2320 case 16:
2321 switch (desc->nr_channels) {
2322 case 1:
2323 *format = FMT_16_FLOAT;
2324 break;
2325 case 2:
2326 *format = FMT_16_16_FLOAT;
2327 break;
2328 case 3:
2329 case 4:
2330 *format = FMT_16_16_16_16_FLOAT;
2331 break;
2332 }
2333 break;
2334 case 32:
2335 switch (desc->nr_channels) {
2336 case 1:
2337 *format = FMT_32_FLOAT;
2338 break;
2339 case 2:
2340 *format = FMT_32_32_FLOAT;
2341 break;
2342 case 3:
2343 *format = FMT_32_32_32_FLOAT;
2344 break;
2345 case 4:
2346 *format = FMT_32_32_32_32_FLOAT;
2347 break;
2348 }
2349 break;
2350 default:
2351 goto out_unknown;
2352 }
2353 break;
2354 /* Unsigned ints */
2355 case UTIL_FORMAT_TYPE_UNSIGNED:
2356 /* Signed ints */
2357 case UTIL_FORMAT_TYPE_SIGNED:
2358 switch (desc->channel[i].size) {
2359 case 8:
2360 switch (desc->nr_channels) {
2361 case 1:
2362 *format = FMT_8;
2363 break;
2364 case 2:
2365 *format = FMT_8_8;
2366 break;
2367 case 3:
2368 case 4:
2369 *format = FMT_8_8_8_8;
2370 break;
2371 }
2372 break;
2373 case 10:
2374 if (desc->nr_channels != 4)
2375 goto out_unknown;
2376
2377 *format = FMT_2_10_10_10;
2378 break;
2379 case 16:
2380 switch (desc->nr_channels) {
2381 case 1:
2382 *format = FMT_16;
2383 break;
2384 case 2:
2385 *format = FMT_16_16;
2386 break;
2387 case 3:
2388 case 4:
2389 *format = FMT_16_16_16_16;
2390 break;
2391 }
2392 break;
2393 case 32:
2394 switch (desc->nr_channels) {
2395 case 1:
2396 *format = FMT_32;
2397 break;
2398 case 2:
2399 *format = FMT_32_32;
2400 break;
2401 case 3:
2402 *format = FMT_32_32_32;
2403 break;
2404 case 4:
2405 *format = FMT_32_32_32_32;
2406 break;
2407 }
2408 break;
2409 default:
2410 goto out_unknown;
2411 }
2412 break;
2413 default:
2414 goto out_unknown;
2415 }
2416
2417 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2418 *format_comp = 1;
2419 }
2420
2421 *num_format = 0;
2422 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2423 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2424 if (!desc->channel[i].normalized) {
2425 if (desc->channel[i].pure_integer)
2426 *num_format = 1;
2427 else
2428 *num_format = 2;
2429 }
2430 }
2431 return;
2432 out_unknown:
2433 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2434 }
2435
2436 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2437 unsigned count,
2438 const struct pipe_vertex_element *elements)
2439 {
2440 struct r600_context *rctx = (struct r600_context *)ctx;
2441 struct r600_bytecode bc;
2442 struct r600_bytecode_vtx vtx;
2443 const struct util_format_description *desc;
2444 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2445 unsigned format, num_format, format_comp, endian;
2446 uint32_t *bytecode;
2447 int i, j, r, fs_size;
2448 struct r600_fetch_shader *shader;
2449 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2450 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2451
2452 assert(count < 32);
2453
2454 memset(&bc, 0, sizeof(bc));
2455 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2456 rctx->screen->has_compressed_msaa_texturing);
2457
2458 bc.isa = rctx->isa;
2459
2460 for (i = 0; i < count; i++) {
2461 if (elements[i].instance_divisor > 1) {
2462 if (rctx->b.chip_class == CAYMAN) {
2463 for (j = 0; j < 4; j++) {
2464 struct r600_bytecode_alu alu;
2465 memset(&alu, 0, sizeof(alu));
2466 alu.op = ALU_OP2_MULHI_UINT;
2467 alu.src[0].sel = 0;
2468 alu.src[0].chan = 3;
2469 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2470 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2471 alu.dst.sel = i + 1;
2472 alu.dst.chan = j;
2473 alu.dst.write = j == 3;
2474 alu.last = j == 3;
2475 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2476 r600_bytecode_clear(&bc);
2477 return NULL;
2478 }
2479 }
2480 } else {
2481 struct r600_bytecode_alu alu;
2482 memset(&alu, 0, sizeof(alu));
2483 alu.op = ALU_OP2_MULHI_UINT;
2484 alu.src[0].sel = 0;
2485 alu.src[0].chan = 3;
2486 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2487 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2488 alu.dst.sel = i + 1;
2489 alu.dst.chan = 3;
2490 alu.dst.write = 1;
2491 alu.last = 1;
2492 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2493 r600_bytecode_clear(&bc);
2494 return NULL;
2495 }
2496 }
2497 }
2498 }
2499
2500 for (i = 0; i < count; i++) {
2501 r600_vertex_data_type(elements[i].src_format,
2502 &format, &num_format, &format_comp, &endian);
2503
2504 desc = util_format_description(elements[i].src_format);
2505 if (!desc) {
2506 r600_bytecode_clear(&bc);
2507 R600_ERR("unknown format %d\n", elements[i].src_format);
2508 return NULL;
2509 }
2510
2511 if (elements[i].src_offset > 65535) {
2512 r600_bytecode_clear(&bc);
2513 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2514 return NULL;
2515 }
2516
2517 memset(&vtx, 0, sizeof(vtx));
2518 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2519 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2520 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2521 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2522 vtx.mega_fetch_count = 0x1F;
2523 vtx.dst_gpr = i + 1;
2524 vtx.dst_sel_x = desc->swizzle[0];
2525 vtx.dst_sel_y = desc->swizzle[1];
2526 vtx.dst_sel_z = desc->swizzle[2];
2527 vtx.dst_sel_w = desc->swizzle[3];
2528 vtx.data_format = format;
2529 vtx.num_format_all = num_format;
2530 vtx.format_comp_all = format_comp;
2531 vtx.offset = elements[i].src_offset;
2532 vtx.endian = endian;
2533
2534 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2535 r600_bytecode_clear(&bc);
2536 return NULL;
2537 }
2538 }
2539
2540 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2541
2542 if ((r = r600_bytecode_build(&bc))) {
2543 r600_bytecode_clear(&bc);
2544 return NULL;
2545 }
2546
2547 if (rctx->screen->b.debug_flags & DBG_FS) {
2548 fprintf(stderr, "--------------------------------------------------------------\n");
2549 fprintf(stderr, "Vertex elements state:\n");
2550 for (i = 0; i < count; i++) {
2551 fprintf(stderr, " ");
2552 util_dump_vertex_element(stderr, elements+i);
2553 fprintf(stderr, "\n");
2554 }
2555
2556 if (!sb_disasm) {
2557 r600_bytecode_disasm(&bc);
2558
2559 fprintf(stderr, "______________________________________________________________\n");
2560 } else {
2561 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2562 }
2563 }
2564
2565 fs_size = bc.ndw*4;
2566
2567 /* Allocate the CSO. */
2568 shader = CALLOC_STRUCT(r600_fetch_shader);
2569 if (!shader) {
2570 r600_bytecode_clear(&bc);
2571 return NULL;
2572 }
2573
2574 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2575 (struct pipe_resource**)&shader->buffer);
2576 if (!shader->buffer) {
2577 r600_bytecode_clear(&bc);
2578 FREE(shader);
2579 return NULL;
2580 }
2581
2582 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2583 bytecode += shader->offset / 4;
2584
2585 if (R600_BIG_ENDIAN) {
2586 for (i = 0; i < fs_size / 4; ++i) {
2587 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2588 }
2589 } else {
2590 memcpy(bytecode, bc.bytecode, fs_size);
2591 }
2592 rctx->b.ws->buffer_unmap(shader->buffer->cs_buf);
2593
2594 r600_bytecode_clear(&bc);
2595 return shader;
2596 }
2597
2598 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2599 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2600 {
2601 /* WORD0 */
2602 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2603 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2604 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2605 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2606 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2607 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2608 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2609 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2610 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2611 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2612 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2613
2614 /* WORD1 */
2615 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2616 if (alu->bank_swizzle)
2617 alu->bank_swizzle_force = alu->bank_swizzle;
2618 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2619 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2620 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2621 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2622 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2623 {
2624 alu->is_op3 = 1;
2625 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2626 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2627 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2628 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2629 alu->op = r600_isa_alu_by_opcode(bc->isa,
2630 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2631
2632 }
2633 else /*ALU_DWORD1_OP2*/
2634 {
2635 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2636 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2637 alu->op = r600_isa_alu_by_opcode(bc->isa,
2638 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2639 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2640 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2641 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2642 alu->execute_mask =
2643 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2644 }
2645 }
2646
2647 #if 0
2648 void r600_bytecode_export_read(struct r600_bytecode *bc,
2649 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2650 {
2651 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2652 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2653 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2654 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2655
2656 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2657 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2658 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2659 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2660 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2661 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2662 output->op = r600_isa_cf_by_opcode(bc->isa,
2663 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2664 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2665 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2666 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2667 }
2668 #endif