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r600g: cleanup includes
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600d.h"
27
28 #include <errno.h>
29 #include <byteswap.h>
30 #include "util/u_memory.h"
31 #include "pipe/p_shader_tokens.h"
32
33 #define NUM_OF_CYCLES 3
34 #define NUM_OF_COMPONENTS 4
35
36 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
37 {
38 if(alu->is_op3)
39 return 3;
40
41 switch (bc->chip_class) {
42 case R600:
43 case R700:
44 switch (alu->inst) {
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
46 return 0;
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
89 return 2;
90
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
93 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
115 return 1;
116 default: R600_ERR(
117 "Need instruction operand number for 0x%x.\n", alu->inst);
118 }
119 break;
120 case EVERGREEN:
121 case CAYMAN:
122 switch (alu->inst) {
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
124 return 0;
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
169 return 2;
170
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
195 return 1;
196 default: R600_ERR(
197 "Need instruction operand number for 0x%x.\n", alu->inst);
198 }
199 break;
200 }
201
202 return 3;
203 }
204
205 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
206
207 static struct r600_bytecode_cf *r600_bytecode_cf(void)
208 {
209 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
210
211 if (cf == NULL)
212 return NULL;
213 LIST_INITHEAD(&cf->list);
214 LIST_INITHEAD(&cf->alu);
215 LIST_INITHEAD(&cf->vtx);
216 LIST_INITHEAD(&cf->tex);
217 return cf;
218 }
219
220 static struct r600_bytecode_alu *r600_bytecode_alu(void)
221 {
222 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
223
224 if (alu == NULL)
225 return NULL;
226 LIST_INITHEAD(&alu->list);
227 return alu;
228 }
229
230 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
231 {
232 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
233
234 if (vtx == NULL)
235 return NULL;
236 LIST_INITHEAD(&vtx->list);
237 return vtx;
238 }
239
240 static struct r600_bytecode_tex *r600_bytecode_tex(void)
241 {
242 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
243
244 if (tex == NULL)
245 return NULL;
246 LIST_INITHEAD(&tex->list);
247 return tex;
248 }
249
250 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
251 {
252 if ((chip_class == R600) && (family != CHIP_RV670))
253 bc->ar_handling = AR_HANDLE_RV6XX;
254 else
255 bc->ar_handling = AR_HANDLE_NORMAL;
256
257 if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
258 family != CHIP_RS880))
259 bc->r6xx_nop_after_rel_dst = 1;
260 else
261 bc->r6xx_nop_after_rel_dst = 0;
262 LIST_INITHEAD(&bc->cf);
263 bc->chip_class = chip_class;
264 }
265
266 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
267 {
268 struct r600_bytecode_cf *cf = r600_bytecode_cf();
269
270 if (cf == NULL)
271 return -ENOMEM;
272 LIST_ADDTAIL(&cf->list, &bc->cf);
273 if (bc->cf_last) {
274 cf->id = bc->cf_last->id + 2;
275 if (bc->cf_last->eg_alu_extended) {
276 /* take into account extended alu size */
277 cf->id += 2;
278 bc->ndw += 2;
279 }
280 }
281 bc->cf_last = cf;
282 bc->ncf++;
283 bc->ndw += 2;
284 bc->force_add_cf = 0;
285 bc->ar_loaded = 0;
286 return 0;
287 }
288
289 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
290 {
291 int r;
292
293 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
294 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
295 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
296 output->type == bc->cf_last->output.type &&
297 output->elem_size == bc->cf_last->output.elem_size &&
298 output->swizzle_x == bc->cf_last->output.swizzle_x &&
299 output->swizzle_y == bc->cf_last->output.swizzle_y &&
300 output->swizzle_z == bc->cf_last->output.swizzle_z &&
301 output->swizzle_w == bc->cf_last->output.swizzle_w &&
302 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
303
304 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
305 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
306
307 bc->cf_last->output.end_of_program |= output->end_of_program;
308 bc->cf_last->output.inst = output->inst;
309 bc->cf_last->output.gpr = output->gpr;
310 bc->cf_last->output.array_base = output->array_base;
311 bc->cf_last->output.burst_count += output->burst_count;
312 return 0;
313
314 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
315 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
316
317 bc->cf_last->output.end_of_program |= output->end_of_program;
318 bc->cf_last->output.inst = output->inst;
319 bc->cf_last->output.burst_count += output->burst_count;
320 return 0;
321 }
322 }
323
324 r = r600_bytecode_add_cf(bc);
325 if (r)
326 return r;
327 bc->cf_last->inst = output->inst;
328 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
329 return 0;
330 }
331
332 /* alu instructions that can ony exits once per group */
333 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
334 {
335 switch (bc->chip_class) {
336 case R600:
337 case R700:
338 return !alu->is_op3 && (
339 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
340 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
341 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
342 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
343 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
348 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
373 case EVERGREEN:
374 case CAYMAN:
375 default:
376 return !alu->is_op3 && (
377 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
378 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
379 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
380 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
381 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
411 }
412 }
413
414 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
415 {
416 switch (bc->chip_class) {
417 case R600:
418 case R700:
419 return !alu->is_op3 && (
420 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
421 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
422 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
423 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
424 case EVERGREEN:
425 case CAYMAN:
426 default:
427 return !alu->is_op3 && (
428 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
429 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
430 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
431 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
432 }
433 }
434
435 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
436 {
437 switch (bc->chip_class) {
438 case R600:
439 case R700:
440 return !alu->is_op3 &&
441 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
442 case EVERGREEN:
443 case CAYMAN:
444 default:
445 return !alu->is_op3 &&
446 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
447 }
448 }
449
450 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
451 {
452 switch (bc->chip_class) {
453 case R600:
454 case R700:
455 return !alu->is_op3 && (
456 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
457 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
458 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
459 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
460 case EVERGREEN:
461 case CAYMAN:
462 default:
463 return !alu->is_op3 && (
464 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
465 }
466 }
467
468 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
469 {
470 return min <= opcode && opcode <= max;
471 }
472
473 /* ALU instructions that can only execute on the vector unit:
474 *
475 * opcode ranges:
476 * R6xx/R7xx:
477 * op3 : [0x08 - 0x0B]
478 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
479 *
480 * EVERGREEN:
481 * op3: [0x04 - 0x11]
482 * op2: [0xA0 - 0xE2]
483 */
484 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
485 {
486 switch (bc->chip_class) {
487 case R600:
488 case R700:
489 if (alu->is_op3)
490 return is_opcode_in_range(alu->inst,
491 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
492 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
493 else
494 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
495 is_opcode_in_range(alu->inst,
496 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
497 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
498 is_opcode_in_range(alu->inst,
499 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
500 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
501 is_opcode_in_range(alu->inst,
502 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
503 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
504 is_opcode_in_range(alu->inst,
505 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
506 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
507
508 case EVERGREEN:
509 if (alu->is_op3)
510 return is_opcode_in_range(alu->inst,
511 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
512 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
513 else
514 return is_opcode_in_range(alu->inst,
515 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
516 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
517 case CAYMAN:
518 default:
519 assert(0);
520 return 0;
521 }
522 }
523
524 /* ALU instructions that can only execute on the trans unit:
525 *
526 * opcode ranges:
527 * R600:
528 * op3: 0x0C
529 * op2: [0x60 - 0x79]
530 *
531 * R700:
532 * op3: 0x0C
533 * op2: [0x60 - 0x6F], [0x73 - 0x79]
534 *
535 * EVERGREEN:
536 * op3: 0x1F
537 * op2: [0x81 - 0x9C]
538 */
539 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
540 {
541
542 switch (bc->chip_class) {
543 case R600:
544 if (alu->is_op3)
545 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
546 else
547 return is_opcode_in_range(alu->inst,
548 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
549 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
550 case R700:
551 if (alu->is_op3)
552 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
553 else
554 return is_opcode_in_range(alu->inst,
555 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
556 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
557 is_opcode_in_range(alu->inst,
558 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
559 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
560 case EVERGREEN:
561 if (alu->is_op3)
562 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
563 else
564 return is_opcode_in_range(alu->inst,
565 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
566 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
567 case CAYMAN:
568 default:
569 assert(0);
570 return 0;
571 }
572 }
573
574 /* alu instructions that can execute on any unit */
575 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
576 {
577 return !is_alu_vec_unit_inst(bc, alu) &&
578 !is_alu_trans_unit_inst(bc, alu);
579 }
580
581 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
582 {
583 switch (bc->chip_class) {
584 case R600:
585 case R700:
586 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
587 case EVERGREEN:
588 case CAYMAN:
589 default:
590 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
591 }
592 }
593
594 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
595 struct r600_bytecode_alu *assignment[5])
596 {
597 struct r600_bytecode_alu *alu;
598 unsigned i, chan, trans;
599 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
600
601 for (i = 0; i < max_slots; i++)
602 assignment[i] = NULL;
603
604 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
605 chan = alu->dst.chan;
606 if (max_slots == 4)
607 trans = 0;
608 else if (is_alu_trans_unit_inst(bc, alu))
609 trans = 1;
610 else if (is_alu_vec_unit_inst(bc, alu))
611 trans = 0;
612 else if (assignment[chan])
613 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
614 else
615 trans = 0;
616
617 if (trans) {
618 if (assignment[4]) {
619 assert(0); /* ALU.Trans has already been allocated. */
620 return -1;
621 }
622 assignment[4] = alu;
623 } else {
624 if (assignment[chan]) {
625 assert(0); /* ALU.chan has already been allocated. */
626 return -1;
627 }
628 assignment[chan] = alu;
629 }
630
631 if (alu->last)
632 break;
633 }
634 return 0;
635 }
636
637 struct alu_bank_swizzle {
638 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
639 int hw_cfile_addr[4];
640 int hw_cfile_elem[4];
641 };
642
643 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
644 [SQ_ALU_VEC_012] = { 0, 1, 2 },
645 [SQ_ALU_VEC_021] = { 0, 2, 1 },
646 [SQ_ALU_VEC_120] = { 1, 2, 0 },
647 [SQ_ALU_VEC_102] = { 1, 0, 2 },
648 [SQ_ALU_VEC_201] = { 2, 0, 1 },
649 [SQ_ALU_VEC_210] = { 2, 1, 0 }
650 };
651
652 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
653 [SQ_ALU_SCL_210] = { 2, 1, 0 },
654 [SQ_ALU_SCL_122] = { 1, 2, 2 },
655 [SQ_ALU_SCL_212] = { 2, 1, 2 },
656 [SQ_ALU_SCL_221] = { 2, 2, 1 }
657 };
658
659 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
660 {
661 int i, cycle, component;
662 /* set up gpr use */
663 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
664 for (component = 0; component < NUM_OF_COMPONENTS; component++)
665 bs->hw_gpr[cycle][component] = -1;
666 for (i = 0; i < 4; i++)
667 bs->hw_cfile_addr[i] = -1;
668 for (i = 0; i < 4; i++)
669 bs->hw_cfile_elem[i] = -1;
670 }
671
672 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
673 {
674 if (bs->hw_gpr[cycle][chan] == -1)
675 bs->hw_gpr[cycle][chan] = sel;
676 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
677 /* Another scalar operation has already used the GPR read port for the channel. */
678 return -1;
679 }
680 return 0;
681 }
682
683 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
684 {
685 int res, num_res = 4;
686 if (bc->chip_class >= R700) {
687 num_res = 2;
688 chan /= 2;
689 }
690 for (res = 0; res < num_res; ++res) {
691 if (bs->hw_cfile_addr[res] == -1) {
692 bs->hw_cfile_addr[res] = sel;
693 bs->hw_cfile_elem[res] = chan;
694 return 0;
695 } else if (bs->hw_cfile_addr[res] == sel &&
696 bs->hw_cfile_elem[res] == chan)
697 return 0; /* Read for this scalar element already reserved, nothing to do here. */
698 }
699 /* All cfile read ports are used, cannot reference vector element. */
700 return -1;
701 }
702
703 static int is_gpr(unsigned sel)
704 {
705 return (sel >= 0 && sel <= 127);
706 }
707
708 /* CB constants start at 512, and get translated to a kcache index when ALU
709 * clauses are constructed. Note that we handle kcache constants the same way
710 * as (the now gone) cfile constants, is that really required? */
711 static int is_cfile(unsigned sel)
712 {
713 return (sel > 255 && sel < 512) ||
714 (sel > 511 && sel < 4607) || /* Kcache before translation. */
715 (sel > 127 && sel < 192); /* Kcache after translation. */
716 }
717
718 static int is_const(int sel)
719 {
720 return is_cfile(sel) ||
721 (sel >= V_SQ_ALU_SRC_0 &&
722 sel <= V_SQ_ALU_SRC_LITERAL);
723 }
724
725 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
726 struct alu_bank_swizzle *bs, int bank_swizzle)
727 {
728 int r, src, num_src, sel, elem, cycle;
729
730 num_src = r600_bytecode_get_num_operands(bc, alu);
731 for (src = 0; src < num_src; src++) {
732 sel = alu->src[src].sel;
733 elem = alu->src[src].chan;
734 if (is_gpr(sel)) {
735 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
736 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
737 /* Nothing to do; special-case optimization,
738 * second source uses first source’s reservation. */
739 continue;
740 else {
741 r = reserve_gpr(bs, sel, elem, cycle);
742 if (r)
743 return r;
744 }
745 } else if (is_cfile(sel)) {
746 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
747 if (r)
748 return r;
749 }
750 /* No restrictions on PV, PS, literal or special constants. */
751 }
752 return 0;
753 }
754
755 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
756 struct alu_bank_swizzle *bs, int bank_swizzle)
757 {
758 int r, src, num_src, const_count, sel, elem, cycle;
759
760 num_src = r600_bytecode_get_num_operands(bc, alu);
761 for (const_count = 0, src = 0; src < num_src; ++src) {
762 sel = alu->src[src].sel;
763 elem = alu->src[src].chan;
764 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
765 if (const_count >= 2)
766 /* More than two references to a constant in
767 * transcendental operation. */
768 return -1;
769 else
770 const_count++;
771 }
772 if (is_cfile(sel)) {
773 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
774 if (r)
775 return r;
776 }
777 }
778 for (src = 0; src < num_src; ++src) {
779 sel = alu->src[src].sel;
780 elem = alu->src[src].chan;
781 if (is_gpr(sel)) {
782 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
783 if (cycle < const_count)
784 /* Cycle for GPR load conflicts with
785 * constant load in transcendental operation. */
786 return -1;
787 r = reserve_gpr(bs, sel, elem, cycle);
788 if (r)
789 return r;
790 }
791 /* PV PS restrictions */
792 if (const_count && (sel == 254 || sel == 255)) {
793 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
794 if (cycle < const_count)
795 return -1;
796 }
797 }
798 return 0;
799 }
800
801 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
802 struct r600_bytecode_alu *slots[5])
803 {
804 struct alu_bank_swizzle bs;
805 int bank_swizzle[5];
806 int i, r = 0, forced = 1;
807 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
808 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
809
810 for (i = 0; i < max_slots; i++) {
811 if (slots[i]) {
812 if (slots[i]->bank_swizzle_force) {
813 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
814 } else {
815 forced = 0;
816 }
817 }
818
819 if (i < 4 && slots[i])
820 scalar_only = false;
821 }
822 if (forced)
823 return 0;
824
825 /* Just check every possible combination of bank swizzle.
826 * Not very efficent, but works on the first try in most of the cases. */
827 for (i = 0; i < 4; i++)
828 if (!slots[i] || !slots[i]->bank_swizzle_force)
829 bank_swizzle[i] = SQ_ALU_VEC_012;
830 else
831 bank_swizzle[i] = slots[i]->bank_swizzle;
832
833 bank_swizzle[4] = SQ_ALU_SCL_210;
834 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
835
836 if (max_slots == 4) {
837 for (i = 0; i < max_slots; i++) {
838 if (bank_swizzle[i] == SQ_ALU_VEC_210)
839 return -1;
840 }
841 }
842 init_bank_swizzle(&bs);
843 if (scalar_only == false) {
844 for (i = 0; i < 4; i++) {
845 if (slots[i]) {
846 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
847 if (r)
848 break;
849 }
850 }
851 } else
852 r = 0;
853
854 if (!r && slots[4] && max_slots == 5) {
855 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
856 }
857 if (!r) {
858 for (i = 0; i < max_slots; i++) {
859 if (slots[i])
860 slots[i]->bank_swizzle = bank_swizzle[i];
861 }
862 return 0;
863 }
864
865 if (scalar_only) {
866 bank_swizzle[4]++;
867 } else {
868 for (i = 0; i < max_slots; i++) {
869 if (!slots[i] || !slots[i]->bank_swizzle_force) {
870 bank_swizzle[i]++;
871 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
872 break;
873 else
874 bank_swizzle[i] = SQ_ALU_VEC_012;
875 }
876 }
877 }
878 }
879
880 /* Couldn't find a working swizzle. */
881 return -1;
882 }
883
884 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
885 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
886 {
887 struct r600_bytecode_alu *prev[5];
888 int gpr[5], chan[5];
889 int i, j, r, src, num_src;
890 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
891
892 r = assign_alu_units(bc, alu_prev, prev);
893 if (r)
894 return r;
895
896 for (i = 0; i < max_slots; ++i) {
897 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
898 gpr[i] = prev[i]->dst.sel;
899 /* cube writes more than PV.X */
900 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
901 chan[i] = 0;
902 else
903 chan[i] = prev[i]->dst.chan;
904 } else
905 gpr[i] = -1;
906 }
907
908 for (i = 0; i < max_slots; ++i) {
909 struct r600_bytecode_alu *alu = slots[i];
910 if(!alu)
911 continue;
912
913 num_src = r600_bytecode_get_num_operands(bc, alu);
914 for (src = 0; src < num_src; ++src) {
915 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
916 continue;
917
918 if (bc->chip_class < CAYMAN) {
919 if (alu->src[src].sel == gpr[4] &&
920 alu->src[src].chan == chan[4]) {
921 alu->src[src].sel = V_SQ_ALU_SRC_PS;
922 alu->src[src].chan = 0;
923 continue;
924 }
925 }
926
927 for (j = 0; j < 4; ++j) {
928 if (alu->src[src].sel == gpr[j] &&
929 alu->src[src].chan == j) {
930 alu->src[src].sel = V_SQ_ALU_SRC_PV;
931 alu->src[src].chan = chan[j];
932 break;
933 }
934 }
935 }
936 }
937
938 return 0;
939 }
940
941 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
942 {
943 switch(value) {
944 case 0:
945 *sel = V_SQ_ALU_SRC_0;
946 break;
947 case 1:
948 *sel = V_SQ_ALU_SRC_1_INT;
949 break;
950 case -1:
951 *sel = V_SQ_ALU_SRC_M_1_INT;
952 break;
953 case 0x3F800000: /* 1.0f */
954 *sel = V_SQ_ALU_SRC_1;
955 break;
956 case 0x3F000000: /* 0.5f */
957 *sel = V_SQ_ALU_SRC_0_5;
958 break;
959 case 0xBF800000: /* -1.0f */
960 *sel = V_SQ_ALU_SRC_1;
961 *neg ^= 1;
962 break;
963 case 0xBF000000: /* -0.5f */
964 *sel = V_SQ_ALU_SRC_0_5;
965 *neg ^= 1;
966 break;
967 default:
968 *sel = V_SQ_ALU_SRC_LITERAL;
969 break;
970 }
971 }
972
973 /* compute how many literal are needed */
974 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
975 uint32_t literal[4], unsigned *nliteral)
976 {
977 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
978 unsigned i, j;
979
980 for (i = 0; i < num_src; ++i) {
981 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
982 uint32_t value = alu->src[i].value;
983 unsigned found = 0;
984 for (j = 0; j < *nliteral; ++j) {
985 if (literal[j] == value) {
986 found = 1;
987 break;
988 }
989 }
990 if (!found) {
991 if (*nliteral >= 4)
992 return -EINVAL;
993 literal[(*nliteral)++] = value;
994 }
995 }
996 }
997 return 0;
998 }
999
1000 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1001 struct r600_bytecode_alu *alu,
1002 uint32_t literal[4], unsigned nliteral)
1003 {
1004 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1005 unsigned i, j;
1006
1007 for (i = 0; i < num_src; ++i) {
1008 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1009 uint32_t value = alu->src[i].value;
1010 for (j = 0; j < nliteral; ++j) {
1011 if (literal[j] == value) {
1012 alu->src[i].chan = j;
1013 break;
1014 }
1015 }
1016 }
1017 }
1018 }
1019
1020 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1021 struct r600_bytecode_alu *alu_prev)
1022 {
1023 struct r600_bytecode_alu *prev[5];
1024 struct r600_bytecode_alu *result[5] = { NULL };
1025
1026 uint32_t literal[4], prev_literal[4];
1027 unsigned nliteral = 0, prev_nliteral = 0;
1028
1029 int i, j, r, src, num_src;
1030 int num_once_inst = 0;
1031 int have_mova = 0, have_rel = 0;
1032 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1033
1034 r = assign_alu_units(bc, alu_prev, prev);
1035 if (r)
1036 return r;
1037
1038 for (i = 0; i < max_slots; ++i) {
1039 struct r600_bytecode_alu *alu;
1040
1041 /* check number of literals */
1042 if (prev[i]) {
1043 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1044 return 0;
1045 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1046 return 0;
1047 if (is_alu_mova_inst(bc, prev[i])) {
1048 if (have_rel)
1049 return 0;
1050 have_mova = 1;
1051 }
1052 num_once_inst += is_alu_once_inst(bc, prev[i]);
1053 }
1054 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1055 return 0;
1056
1057 /* Let's check used slots. */
1058 if (prev[i] && !slots[i]) {
1059 result[i] = prev[i];
1060 continue;
1061 } else if (prev[i] && slots[i]) {
1062 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1063 /* Trans unit is still free try to use it. */
1064 if (is_alu_any_unit_inst(bc, slots[i])) {
1065 result[i] = prev[i];
1066 result[4] = slots[i];
1067 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1068 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1069 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1070 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1071 return 0;
1072
1073 result[i] = slots[i];
1074 result[4] = prev[i];
1075 } else
1076 return 0;
1077 } else
1078 return 0;
1079 } else if(!slots[i]) {
1080 continue;
1081 } else {
1082 if (max_slots == 5 && slots[i] && prev[4] &&
1083 slots[i]->dst.sel == prev[4]->dst.sel &&
1084 slots[i]->dst.chan == prev[4]->dst.chan &&
1085 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1086 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1087 return 0;
1088
1089 result[i] = slots[i];
1090 }
1091
1092 alu = slots[i];
1093 num_once_inst += is_alu_once_inst(bc, alu);
1094
1095 /* don't reschedule NOPs */
1096 if (is_nop_inst(bc, alu))
1097 return 0;
1098
1099 /* Let's check dst gpr. */
1100 if (alu->dst.rel) {
1101 if (have_mova)
1102 return 0;
1103 have_rel = 1;
1104 }
1105
1106 /* Let's check source gprs */
1107 num_src = r600_bytecode_get_num_operands(bc, alu);
1108 for (src = 0; src < num_src; ++src) {
1109 if (alu->src[src].rel) {
1110 if (have_mova)
1111 return 0;
1112 have_rel = 1;
1113 }
1114
1115 /* Constants don't matter. */
1116 if (!is_gpr(alu->src[src].sel))
1117 continue;
1118
1119 for (j = 0; j < max_slots; ++j) {
1120 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1121 continue;
1122
1123 /* If it's relative then we can't determin which gpr is really used. */
1124 if (prev[j]->dst.chan == alu->src[src].chan &&
1125 (prev[j]->dst.sel == alu->src[src].sel ||
1126 prev[j]->dst.rel || alu->src[src].rel))
1127 return 0;
1128 }
1129 }
1130 }
1131
1132 /* more than one PRED_ or KILL_ ? */
1133 if (num_once_inst > 1)
1134 return 0;
1135
1136 /* check if the result can still be swizzlet */
1137 r = check_and_set_bank_swizzle(bc, result);
1138 if (r)
1139 return 0;
1140
1141 /* looks like everything worked out right, apply the changes */
1142
1143 /* undo adding previus literals */
1144 bc->cf_last->ndw -= align(prev_nliteral, 2);
1145
1146 /* sort instructions */
1147 for (i = 0; i < max_slots; ++i) {
1148 slots[i] = result[i];
1149 if (result[i]) {
1150 LIST_DEL(&result[i]->list);
1151 result[i]->last = 0;
1152 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1153 }
1154 }
1155
1156 /* determine new last instruction */
1157 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1158
1159 /* determine new first instruction */
1160 for (i = 0; i < max_slots; ++i) {
1161 if (result[i]) {
1162 bc->cf_last->curr_bs_head = result[i];
1163 break;
1164 }
1165 }
1166
1167 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1168 bc->cf_last->prev2_bs_head = NULL;
1169
1170 return 0;
1171 }
1172
1173 /* we'll keep kcache sets sorted by bank & addr */
1174 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1175 struct r600_bytecode_kcache *kcache,
1176 unsigned bank, unsigned line)
1177 {
1178 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1179
1180 for (i = 0; i < kcache_banks; i++) {
1181 if (kcache[i].mode) {
1182 int d;
1183
1184 if (kcache[i].bank < bank)
1185 continue;
1186
1187 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1188 kcache[i].bank > bank) {
1189 /* try to insert new line */
1190 if (kcache[kcache_banks-1].mode) {
1191 /* all sets are in use */
1192 return -ENOMEM;
1193 }
1194
1195 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1196 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1197 kcache[i].bank = bank;
1198 kcache[i].addr = line;
1199 return 0;
1200 }
1201
1202 d = line - kcache[i].addr;
1203
1204 if (d == -1) {
1205 kcache[i].addr--;
1206 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1207 /* we are prepending the line to the current set,
1208 * discarding the existing second line,
1209 * so we'll have to insert line+2 after it */
1210 line += 2;
1211 continue;
1212 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1213 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1214 return 0;
1215 } else {
1216 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1217 return -ENOMEM;
1218 }
1219 } else if (d == 1) {
1220 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1221 return 0;
1222 } else if (d == 0)
1223 return 0;
1224 } else { /* free kcache set - use it */
1225 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1226 kcache[i].bank = bank;
1227 kcache[i].addr = line;
1228 return 0;
1229 }
1230 }
1231 return -ENOMEM;
1232 }
1233
1234 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1235 struct r600_bytecode_kcache *kcache,
1236 struct r600_bytecode_alu *alu)
1237 {
1238 int i, r;
1239
1240 for (i = 0; i < 3; i++) {
1241 unsigned bank, line, sel = alu->src[i].sel;
1242
1243 if (sel < 512)
1244 continue;
1245
1246 bank = alu->src[i].kc_bank;
1247 line = (sel-512)>>4;
1248
1249 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1250 return r;
1251 }
1252 return 0;
1253 }
1254
1255 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1256 struct r600_bytecode_alu *alu,
1257 struct r600_bytecode_kcache * kcache)
1258 {
1259 int i, j;
1260
1261 /* Alter the src operands to refer to the kcache. */
1262 for (i = 0; i < 3; ++i) {
1263 static const unsigned int base[] = {128, 160, 256, 288};
1264 unsigned int line, sel = alu->src[i].sel, found = 0;
1265
1266 if (sel < 512)
1267 continue;
1268
1269 sel -= 512;
1270 line = sel>>4;
1271
1272 for (j = 0; j < 4 && !found; ++j) {
1273 switch (kcache[j].mode) {
1274 case V_SQ_CF_KCACHE_NOP:
1275 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1276 R600_ERR("unexpected kcache line mode\n");
1277 return -ENOMEM;
1278 default:
1279 if (kcache[j].bank == alu->src[i].kc_bank &&
1280 kcache[j].addr <= line &&
1281 line < kcache[j].addr + kcache[j].mode) {
1282 alu->src[i].sel = sel - (kcache[j].addr<<4);
1283 alu->src[i].sel += base[j];
1284 found=1;
1285 }
1286 }
1287 }
1288 }
1289 return 0;
1290 }
1291
1292 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1293 {
1294 struct r600_bytecode_kcache kcache_sets[4];
1295 struct r600_bytecode_kcache *kcache = kcache_sets;
1296 int r;
1297
1298 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1299
1300 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1301 /* can't alloc, need to start new clause */
1302 if ((r = r600_bytecode_add_cf(bc))) {
1303 return r;
1304 }
1305 bc->cf_last->inst = type;
1306
1307 /* retry with the new clause */
1308 kcache = bc->cf_last->kcache;
1309 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1310 /* can't alloc again- should never happen */
1311 return r;
1312 }
1313 } else {
1314 /* update kcache sets */
1315 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1316 }
1317
1318 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1319 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1320 if (bc->chip_class < EVERGREEN)
1321 return -ENOMEM;
1322 bc->cf_last->eg_alu_extended = 1;
1323 }
1324
1325 return 0;
1326 }
1327
1328 static int insert_nop_r6xx(struct r600_bytecode *bc)
1329 {
1330 struct r600_bytecode_alu alu;
1331 int r, i;
1332
1333 for (i = 0; i < 4; i++) {
1334 memset(&alu, 0, sizeof(alu));
1335 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1336 alu.src[0].chan = i;
1337 alu.dst.chan = i;
1338 alu.last = (i == 3);
1339 r = r600_bytecode_add_alu(bc, &alu);
1340 if (r)
1341 return r;
1342 }
1343 return 0;
1344 }
1345
1346 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1347 static int load_ar_r6xx(struct r600_bytecode *bc)
1348 {
1349 struct r600_bytecode_alu alu;
1350 int r;
1351
1352 if (bc->ar_loaded)
1353 return 0;
1354
1355 /* hack to avoid making MOVA the last instruction in the clause */
1356 if ((bc->cf_last->ndw>>1) >= 110)
1357 bc->force_add_cf = 1;
1358
1359 memset(&alu, 0, sizeof(alu));
1360 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1361 alu.src[0].sel = bc->ar_reg;
1362 alu.last = 1;
1363 alu.index_mode = INDEX_MODE_LOOP;
1364 r = r600_bytecode_add_alu(bc, &alu);
1365 if (r)
1366 return r;
1367
1368 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1369 bc->ar_loaded = 1;
1370 return 0;
1371 }
1372
1373 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1374 static int load_ar(struct r600_bytecode *bc)
1375 {
1376 struct r600_bytecode_alu alu;
1377 int r;
1378
1379 if (bc->ar_handling)
1380 return load_ar_r6xx(bc);
1381
1382 if (bc->ar_loaded)
1383 return 0;
1384
1385 /* hack to avoid making MOVA the last instruction in the clause */
1386 if ((bc->cf_last->ndw>>1) >= 110)
1387 bc->force_add_cf = 1;
1388
1389 memset(&alu, 0, sizeof(alu));
1390 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1391 alu.src[0].sel = bc->ar_reg;
1392 alu.last = 1;
1393 r = r600_bytecode_add_alu(bc, &alu);
1394 if (r)
1395 return r;
1396
1397 bc->cf_last->r6xx_uses_waterfall = 1;
1398 bc->ar_loaded = 1;
1399 return 0;
1400 }
1401
1402 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1403 {
1404 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1405 struct r600_bytecode_alu *lalu;
1406 int i, r;
1407
1408 if (nalu == NULL)
1409 return -ENOMEM;
1410 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1411
1412 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1413 /* check if we could add it anyway */
1414 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1415 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1416 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1417 if (lalu->predicate) {
1418 bc->force_add_cf = 1;
1419 break;
1420 }
1421 }
1422 } else
1423 bc->force_add_cf = 1;
1424 }
1425
1426 /* cf can contains only alu or only vtx or only tex */
1427 if (bc->cf_last == NULL || bc->force_add_cf) {
1428 r = r600_bytecode_add_cf(bc);
1429 if (r) {
1430 free(nalu);
1431 return r;
1432 }
1433 }
1434 bc->cf_last->inst = type;
1435
1436 /* Check AR usage and load it if required */
1437 for (i = 0; i < 3; i++)
1438 if (nalu->src[i].rel && !bc->ar_loaded)
1439 load_ar(bc);
1440
1441 if (nalu->dst.rel && !bc->ar_loaded)
1442 load_ar(bc);
1443
1444 /* Setup the kcache for this ALU instruction. This will start a new
1445 * ALU clause if needed. */
1446 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1447 free(nalu);
1448 return r;
1449 }
1450
1451 if (!bc->cf_last->curr_bs_head) {
1452 bc->cf_last->curr_bs_head = nalu;
1453 }
1454 /* number of gpr == the last gpr used in any alu */
1455 for (i = 0; i < 3; i++) {
1456 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1457 bc->ngpr = nalu->src[i].sel + 1;
1458 }
1459 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1460 r600_bytecode_special_constants(nalu->src[i].value,
1461 &nalu->src[i].sel, &nalu->src[i].neg);
1462 }
1463 if (nalu->dst.sel >= bc->ngpr) {
1464 bc->ngpr = nalu->dst.sel + 1;
1465 }
1466 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1467 /* each alu use 2 dwords */
1468 bc->cf_last->ndw += 2;
1469 bc->ndw += 2;
1470
1471 /* process cur ALU instructions for bank swizzle */
1472 if (nalu->last) {
1473 uint32_t literal[4];
1474 unsigned nliteral;
1475 struct r600_bytecode_alu *slots[5];
1476 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1477 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1478 if (r)
1479 return r;
1480
1481 if (bc->cf_last->prev_bs_head) {
1482 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1483 if (r)
1484 return r;
1485 }
1486
1487 if (bc->cf_last->prev_bs_head) {
1488 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1489 if (r)
1490 return r;
1491 }
1492
1493 r = check_and_set_bank_swizzle(bc, slots);
1494 if (r)
1495 return r;
1496
1497 for (i = 0, nliteral = 0; i < max_slots; i++) {
1498 if (slots[i]) {
1499 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1500 if (r)
1501 return r;
1502 }
1503 }
1504 bc->cf_last->ndw += align(nliteral, 2);
1505
1506 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1507 * worst case */
1508 if ((bc->cf_last->ndw >> 1) >= 120) {
1509 bc->force_add_cf = 1;
1510 }
1511
1512 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1513 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1514 bc->cf_last->curr_bs_head = NULL;
1515 }
1516
1517 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1518 insert_nop_r6xx(bc);
1519
1520 return 0;
1521 }
1522
1523 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1524 {
1525 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1526 }
1527
1528 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1529 {
1530 switch (bc->chip_class) {
1531 case R600:
1532 return 8;
1533
1534 case R700:
1535 case EVERGREEN:
1536 case CAYMAN:
1537 return 16;
1538
1539 default:
1540 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1541 return 8;
1542 }
1543 }
1544
1545 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1546 {
1547 switch (bc->chip_class) {
1548 case R700:
1549 case R600:
1550 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1551 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1552 case EVERGREEN:
1553 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1554 case CAYMAN:
1555 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1556 default:
1557 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1558 return FALSE;
1559 }
1560 }
1561
1562 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1563 {
1564 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1565 int r;
1566
1567 if (nvtx == NULL)
1568 return -ENOMEM;
1569 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1570
1571 /* cf can contains only alu or only vtx or only tex */
1572 if (bc->cf_last == NULL ||
1573 last_inst_was_not_vtx_fetch(bc) ||
1574 bc->force_add_cf) {
1575 r = r600_bytecode_add_cf(bc);
1576 if (r) {
1577 free(nvtx);
1578 return r;
1579 }
1580 switch (bc->chip_class) {
1581 case R600:
1582 case R700:
1583 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1584 break;
1585 case EVERGREEN:
1586 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1587 break;
1588 case CAYMAN:
1589 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1590 break;
1591 default:
1592 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1593 return -EINVAL;
1594 }
1595 }
1596 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1597 /* each fetch use 4 dwords */
1598 bc->cf_last->ndw += 4;
1599 bc->ndw += 4;
1600 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1601 bc->force_add_cf = 1;
1602 return 0;
1603 }
1604
1605 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1606 {
1607 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1608 int r;
1609
1610 if (ntex == NULL)
1611 return -ENOMEM;
1612 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1613
1614 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1615 if (bc->cf_last != NULL &&
1616 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1617 struct r600_bytecode_tex *ttex;
1618 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1619 if (ttex->dst_gpr == ntex->src_gpr) {
1620 bc->force_add_cf = 1;
1621 break;
1622 }
1623 }
1624 /* slight hack to make gradients always go into same cf */
1625 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1626 bc->force_add_cf = 1;
1627 }
1628
1629 /* cf can contains only alu or only vtx or only tex */
1630 if (bc->cf_last == NULL ||
1631 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1632 bc->force_add_cf) {
1633 r = r600_bytecode_add_cf(bc);
1634 if (r) {
1635 free(ntex);
1636 return r;
1637 }
1638 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1639 }
1640 if (ntex->src_gpr >= bc->ngpr) {
1641 bc->ngpr = ntex->src_gpr + 1;
1642 }
1643 if (ntex->dst_gpr >= bc->ngpr) {
1644 bc->ngpr = ntex->dst_gpr + 1;
1645 }
1646 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1647 /* each texture fetch use 4 dwords */
1648 bc->cf_last->ndw += 4;
1649 bc->ndw += 4;
1650 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1651 bc->force_add_cf = 1;
1652 return 0;
1653 }
1654
1655 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1656 {
1657 int r;
1658 r = r600_bytecode_add_cf(bc);
1659 if (r)
1660 return r;
1661
1662 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1663 bc->cf_last->inst = inst;
1664 return 0;
1665 }
1666
1667 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1668 {
1669 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1670 }
1671
1672 /* common to all 3 families */
1673 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1674 {
1675 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1676 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1677 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1678 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1679 if (bc->chip_class < CAYMAN)
1680 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1681 id++;
1682 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1683 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1684 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1685 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1686 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1687 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1688 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1689 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1690 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1691 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1692 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1693 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1694 if (bc->chip_class < CAYMAN)
1695 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1696 id++;
1697 bc->bytecode[id++] = 0;
1698 return 0;
1699 }
1700
1701 /* common to all 3 families */
1702 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1703 {
1704 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1705 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1706 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1707 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1708 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1709 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1710 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1711 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1712 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1713 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1714 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1715 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1716 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1717 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1718 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1719 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1720 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1721 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1722 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1723 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1724 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1725 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1726 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1727 bc->bytecode[id++] = 0;
1728 return 0;
1729 }
1730
1731 /* r600 only, r700/eg bits in r700_asm.c */
1732 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1733 {
1734 /* don't replace gpr by pv or ps for destination register */
1735 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1736 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1737 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1738 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1739 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1740 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1741 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1742 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1743 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1744 S_SQ_ALU_WORD0_LAST(alu->last);
1745
1746 if (alu->is_op3) {
1747 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1748 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1749 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1750 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1751 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1752 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1753 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1754 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1755 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1756 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1757 } else {
1758 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1759 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1760 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1761 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1762 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1763 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1764 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1765 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1766 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1767 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1768 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1769 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1770 }
1771 return 0;
1772 }
1773
1774 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1775 {
1776 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1777 *bytecode++ = cf->inst |
1778 S_SQ_CF_WORD1_BARRIER(1) |
1779 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1780 }
1781
1782 /* common for r600/r700 - eg in eg_asm.c */
1783 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1784 {
1785 unsigned id = cf->id;
1786
1787 switch (cf->inst) {
1788 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1789 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1790 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1791 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1792 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1793 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1794 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1795 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1796
1797 bc->bytecode[id++] = cf->inst |
1798 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1799 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1800 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1801 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1802 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1803 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1804 break;
1805 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1806 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1807 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1808 if (bc->chip_class == R700)
1809 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1810 else
1811 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1812 break;
1813 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1814 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1815 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1816 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1817 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1818 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1819 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1820 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1821 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1822 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1823 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1824 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1825 cf->output.inst |
1826 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1827 break;
1828 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1829 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1830 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1831 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1832 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1833 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1834 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1835 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1836 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1837 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1838 cf->output.inst |
1839 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1840 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1841 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1842 break;
1843 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1844 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1845 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1846 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1847 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1848 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1849 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1850 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1851 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1852 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1853 bc->bytecode[id++] = cf->inst |
1854 S_SQ_CF_WORD1_BARRIER(1) |
1855 S_SQ_CF_WORD1_COND(cf->cond) |
1856 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1857
1858 break;
1859 default:
1860 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1861 return -EINVAL;
1862 }
1863 return 0;
1864 }
1865
1866 int r600_bytecode_build(struct r600_bytecode *bc)
1867 {
1868 struct r600_bytecode_cf *cf;
1869 struct r600_bytecode_alu *alu;
1870 struct r600_bytecode_vtx *vtx;
1871 struct r600_bytecode_tex *tex;
1872 uint32_t literal[4];
1873 unsigned nliteral;
1874 unsigned addr;
1875 int i, r;
1876
1877 if (bc->callstack[0].max > 0)
1878 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1879 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1880 bc->nstack = 1;
1881 }
1882
1883 /* first path compute addr of each CF block */
1884 /* addr start after all the CF instructions */
1885 addr = bc->cf_last->id + 2;
1886 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1887 if (bc->chip_class >= EVERGREEN) {
1888 switch (cf->inst) {
1889 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1890 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1891 /* fetch node need to be 16 bytes aligned*/
1892 addr += 3;
1893 addr &= 0xFFFFFFFCUL;
1894 break;
1895 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1896 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1897 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1898 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1899 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1900 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1901 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1902 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1903 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1904 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1905 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1906 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1907 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1908 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1909 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1910 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1911 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1912 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1913 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1914 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1915 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1916 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1917 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1918 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1919 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1920 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1921 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1922 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1923 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1924 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1925 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1926 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1927 break;
1928 default:
1929 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1930 return -EINVAL;
1931 }
1932 } else {
1933 switch (cf->inst) {
1934 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1935 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1936 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1937 /* fetch node need to be 16 bytes aligned*/
1938 addr += 3;
1939 addr &= 0xFFFFFFFCUL;
1940 break;
1941 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1942 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1943 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1944 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1945 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1946 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1947 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1948 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1949 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1950 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1951 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1952 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1953 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1954 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1955 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1956 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1957 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1958 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1959 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1960 break;
1961 default:
1962 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1963 return -EINVAL;
1964 }
1965 }
1966 cf->addr = addr;
1967 addr += cf->ndw;
1968 bc->ndw = cf->addr + cf->ndw;
1969 }
1970 free(bc->bytecode);
1971 bc->bytecode = calloc(1, bc->ndw * 4);
1972 if (bc->bytecode == NULL)
1973 return -ENOMEM;
1974 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1975 addr = cf->addr;
1976 if (bc->chip_class >= EVERGREEN) {
1977 r = eg_bytecode_cf_build(bc, cf);
1978 if (r)
1979 return r;
1980
1981 switch (cf->inst) {
1982 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1983 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1984 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1985 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1986 nliteral = 0;
1987 memset(literal, 0, sizeof(literal));
1988 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1989 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1990 if (r)
1991 return r;
1992 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1993 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1994
1995 switch(bc->chip_class) {
1996 case EVERGREEN: /* eg alu is same encoding as r700 */
1997 case CAYMAN:
1998 r = r700_bytecode_alu_build(bc, alu, addr);
1999 break;
2000 default:
2001 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2002 return -EINVAL;
2003 }
2004 if (r)
2005 return r;
2006 addr += 2;
2007 if (alu->last) {
2008 for (i = 0; i < align(nliteral, 2); ++i) {
2009 bc->bytecode[addr++] = literal[i];
2010 }
2011 nliteral = 0;
2012 memset(literal, 0, sizeof(literal));
2013 }
2014 }
2015 break;
2016 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2017 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2018 r = r600_bytecode_vtx_build(bc, vtx, addr);
2019 if (r)
2020 return r;
2021 addr += 4;
2022 }
2023 break;
2024 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2025 if (bc->chip_class == CAYMAN) {
2026 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2027 r = r600_bytecode_vtx_build(bc, vtx, addr);
2028 if (r)
2029 return r;
2030 addr += 4;
2031 }
2032 }
2033 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2034 r = r600_bytecode_tex_build(bc, tex, addr);
2035 if (r)
2036 return r;
2037 addr += 4;
2038 }
2039 break;
2040 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2041 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2042 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2043 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2044 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2045 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2046 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2047 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2048 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2049 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2050 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2051 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2052 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2053 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2054 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2055 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2056 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2057 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2058 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2059 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2060 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2061 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2062 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2063 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2064 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2065 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2066 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2067 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2068 break;
2069 default:
2070 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2071 return -EINVAL;
2072 }
2073 } else {
2074 r = r600_bytecode_cf_build(bc, cf);
2075 if (r)
2076 return r;
2077
2078 switch (cf->inst) {
2079 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2080 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2081 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2082 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2083 nliteral = 0;
2084 memset(literal, 0, sizeof(literal));
2085 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2086 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2087 if (r)
2088 return r;
2089 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2090 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2091
2092 switch(bc->chip_class) {
2093 case R600:
2094 r = r600_bytecode_alu_build(bc, alu, addr);
2095 break;
2096 case R700:
2097 r = r700_bytecode_alu_build(bc, alu, addr);
2098 break;
2099 default:
2100 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2101 return -EINVAL;
2102 }
2103 if (r)
2104 return r;
2105 addr += 2;
2106 if (alu->last) {
2107 for (i = 0; i < align(nliteral, 2); ++i) {
2108 bc->bytecode[addr++] = literal[i];
2109 }
2110 nliteral = 0;
2111 memset(literal, 0, sizeof(literal));
2112 }
2113 }
2114 break;
2115 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2116 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2117 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2118 r = r600_bytecode_vtx_build(bc, vtx, addr);
2119 if (r)
2120 return r;
2121 addr += 4;
2122 }
2123 break;
2124 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2125 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2126 r = r600_bytecode_tex_build(bc, tex, addr);
2127 if (r)
2128 return r;
2129 addr += 4;
2130 }
2131 break;
2132 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2133 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2134 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2135 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2136 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2137 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2138 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2139 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2140 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2141 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2142 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2143 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2144 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2145 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2146 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2147 break;
2148 default:
2149 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2150 return -EINVAL;
2151 }
2152 }
2153 }
2154 return 0;
2155 }
2156
2157 void r600_bytecode_clear(struct r600_bytecode *bc)
2158 {
2159 struct r600_bytecode_cf *cf = NULL, *next_cf;
2160
2161 free(bc->bytecode);
2162 bc->bytecode = NULL;
2163
2164 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2165 struct r600_bytecode_alu *alu = NULL, *next_alu;
2166 struct r600_bytecode_tex *tex = NULL, *next_tex;
2167 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2168
2169 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2170 free(alu);
2171 }
2172
2173 LIST_INITHEAD(&cf->alu);
2174
2175 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2176 free(tex);
2177 }
2178
2179 LIST_INITHEAD(&cf->tex);
2180
2181 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2182 free(vtx);
2183 }
2184
2185 LIST_INITHEAD(&cf->vtx);
2186
2187 free(cf);
2188 }
2189
2190 LIST_INITHEAD(&cf->list);
2191 }
2192
2193 void r600_bytecode_dump(struct r600_bytecode *bc)
2194 {
2195 struct r600_bytecode_cf *cf = NULL;
2196 struct r600_bytecode_alu *alu = NULL;
2197 struct r600_bytecode_vtx *vtx = NULL;
2198 struct r600_bytecode_tex *tex = NULL;
2199
2200 unsigned i, id;
2201 uint32_t literal[4];
2202 unsigned nliteral;
2203 char chip = '6';
2204
2205 switch (bc->chip_class) {
2206 case R700:
2207 chip = '7';
2208 break;
2209 case EVERGREEN:
2210 chip = 'E';
2211 break;
2212 case CAYMAN:
2213 chip = 'C';
2214 break;
2215 case R600:
2216 default:
2217 chip = '6';
2218 break;
2219 }
2220 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2221 fprintf(stderr, " %c\n", chip);
2222
2223 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2224 id = cf->id;
2225
2226 if (bc->chip_class >= EVERGREEN) {
2227 switch (cf->inst) {
2228 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2229 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2230 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2231 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2232 if (cf->eg_alu_extended) {
2233 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2234 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2235 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2236 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2237 id++;
2238 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2239 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2240 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2241 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2242 id++;
2243 }
2244
2245 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2246 fprintf(stderr, "ADDR:%d ", cf->addr);
2247 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2248 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2249 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2250 id++;
2251 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2252 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2253 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2254 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2255 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2256 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2257 break;
2258 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2259 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2260 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2261 fprintf(stderr, "ADDR:%d\n", cf->addr);
2262 id++;
2263 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2264 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2265 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2266 break;
2267 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2268 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2269 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2270 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2271 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2272 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2273 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2274 id++;
2275 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2276 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2277 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2278 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2279 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2280 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2281 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2282 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2283 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2284 break;
2285 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2286 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2287 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2288 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2289 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2290 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2291 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2292 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2293 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2294 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2295 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2296 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2297 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2298 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2299 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2300 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2301 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2302 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2303 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2304 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2305 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2306 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2307 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2308 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2309 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2310 id++;
2311 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2312 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2313 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2314 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2315 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2316 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2317 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2318 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2319 fprintf(stderr, "INST:%d ", cf->output.inst);
2320 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2321 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2322 break;
2323 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2324 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2325 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2326 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2327 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2328 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2329 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2330 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2331 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2332 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2333 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2334 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2335 id++;
2336 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2337 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2338 fprintf(stderr, "COND:%X ", cf->cond);
2339 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2340 break;
2341 default:
2342 R600_ERR("Unknown instruction %0x\n", cf->inst);
2343 }
2344 } else {
2345 switch (cf->inst) {
2346 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2347 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2348 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2349 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2350 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2351 fprintf(stderr, "ADDR:%d ", cf->addr);
2352 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2353 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2354 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2355 id++;
2356 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2357 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2358 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2359 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2360 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2361 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2362 break;
2363 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2364 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2365 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2366 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2367 fprintf(stderr, "ADDR:%d\n", cf->addr);
2368 id++;
2369 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2370 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2371 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2372 break;
2373 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2374 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2375 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2376 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2377 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2378 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2379 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2380 id++;
2381 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2382 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2383 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2384 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2385 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2386 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2387 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2388 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2389 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2390 break;
2391 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2392 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2393 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2394 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2395 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2396 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2397 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2398 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2399 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2400 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2401 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2402 id++;
2403 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2404 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2405 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2406 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2407 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2408 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2409 fprintf(stderr, "INST:%d ", cf->output.inst);
2410 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2411 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2412 break;
2413 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2414 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2415 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2416 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2417 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2418 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2419 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2420 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2421 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2422 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2423 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2424 id++;
2425 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2426 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2427 fprintf(stderr, "COND:%X ", cf->cond);
2428 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2429 break;
2430 default:
2431 R600_ERR("Unknown instruction %0x\n", cf->inst);
2432 }
2433 }
2434
2435 id = cf->addr;
2436 nliteral = 0;
2437 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2438 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2439
2440 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2441 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2442 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2443 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2444 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2445 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2446 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2447 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2448 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2449 fprintf(stderr, "IM:%d) ", alu->index_mode);
2450 fprintf(stderr, "LAST:%d)\n", alu->last);
2451 id++;
2452 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2453 fprintf(stderr, "INST:0x%x ", alu->inst);
2454 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2455 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2456 fprintf(stderr, "REL:%d ", alu->dst.rel);
2457 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2458 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2459 if (alu->is_op3) {
2460 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2461 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2462 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2463 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2464 } else {
2465 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2466 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2467 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2468 fprintf(stderr, "OMOD:%d ", alu->omod);
2469 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
2470 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
2471 }
2472
2473 id++;
2474 if (alu->last) {
2475 for (i = 0; i < nliteral; i++, id++) {
2476 float *f = (float*)(bc->bytecode + id);
2477 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
2478 }
2479 id += nliteral & 1;
2480 nliteral = 0;
2481 }
2482 }
2483
2484 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2485 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2486 fprintf(stderr, "INST:0x%x ", tex->inst);
2487 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2488 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2489 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2490 id++;
2491 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2492 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2493 fprintf(stderr, "REL:%d ", tex->dst_rel);
2494 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2495 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2496 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2497 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2498 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2499 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2500 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2501 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2502 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2503 id++;
2504 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2505 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2506 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2507 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2508 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2509 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2510 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2511 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2512 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2513 id++;
2514 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2515 id++;
2516 }
2517
2518 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2519 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2520 fprintf(stderr, "INST:%d ", vtx->inst);
2521 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2522 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2523 id++;
2524 /* This assumes that no semantic fetches exist */
2525 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2526 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2527 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2528 if (bc->chip_class < CAYMAN)
2529 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2530 else
2531 fprintf(stderr, "SEL_Y:%d) ", 0);
2532 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2533 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2534 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2535 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2536 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2537 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2538 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2539 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2540 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2541 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2542 id++;
2543 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2544 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2545 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2546 /* XXX */
2547 id++;
2548 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2549 id++;
2550 }
2551 }
2552
2553 fprintf(stderr, "--------------------------------------\n");
2554 }
2555
2556 static void r600_vertex_data_type(enum pipe_format pformat,
2557 unsigned *format,
2558 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2559 {
2560 const struct util_format_description *desc;
2561 unsigned i;
2562
2563 *format = 0;
2564 *num_format = 0;
2565 *format_comp = 0;
2566 *endian = ENDIAN_NONE;
2567
2568 desc = util_format_description(pformat);
2569 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2570 goto out_unknown;
2571 }
2572
2573 /* Find the first non-VOID channel. */
2574 for (i = 0; i < 4; i++) {
2575 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2576 break;
2577 }
2578 }
2579
2580 *endian = r600_endian_swap(desc->channel[i].size);
2581
2582 switch (desc->channel[i].type) {
2583 /* Half-floats, floats, ints */
2584 case UTIL_FORMAT_TYPE_FLOAT:
2585 switch (desc->channel[i].size) {
2586 case 16:
2587 switch (desc->nr_channels) {
2588 case 1:
2589 *format = FMT_16_FLOAT;
2590 break;
2591 case 2:
2592 *format = FMT_16_16_FLOAT;
2593 break;
2594 case 3:
2595 case 4:
2596 *format = FMT_16_16_16_16_FLOAT;
2597 break;
2598 }
2599 break;
2600 case 32:
2601 switch (desc->nr_channels) {
2602 case 1:
2603 *format = FMT_32_FLOAT;
2604 break;
2605 case 2:
2606 *format = FMT_32_32_FLOAT;
2607 break;
2608 case 3:
2609 *format = FMT_32_32_32_FLOAT;
2610 break;
2611 case 4:
2612 *format = FMT_32_32_32_32_FLOAT;
2613 break;
2614 }
2615 break;
2616 default:
2617 goto out_unknown;
2618 }
2619 break;
2620 /* Unsigned ints */
2621 case UTIL_FORMAT_TYPE_UNSIGNED:
2622 /* Signed ints */
2623 case UTIL_FORMAT_TYPE_SIGNED:
2624 switch (desc->channel[i].size) {
2625 case 8:
2626 switch (desc->nr_channels) {
2627 case 1:
2628 *format = FMT_8;
2629 break;
2630 case 2:
2631 *format = FMT_8_8;
2632 break;
2633 case 3:
2634 case 4:
2635 *format = FMT_8_8_8_8;
2636 break;
2637 }
2638 break;
2639 case 10:
2640 if (desc->nr_channels != 4)
2641 goto out_unknown;
2642
2643 *format = FMT_2_10_10_10;
2644 break;
2645 case 16:
2646 switch (desc->nr_channels) {
2647 case 1:
2648 *format = FMT_16;
2649 break;
2650 case 2:
2651 *format = FMT_16_16;
2652 break;
2653 case 3:
2654 case 4:
2655 *format = FMT_16_16_16_16;
2656 break;
2657 }
2658 break;
2659 case 32:
2660 switch (desc->nr_channels) {
2661 case 1:
2662 *format = FMT_32;
2663 break;
2664 case 2:
2665 *format = FMT_32_32;
2666 break;
2667 case 3:
2668 *format = FMT_32_32_32;
2669 break;
2670 case 4:
2671 *format = FMT_32_32_32_32;
2672 break;
2673 }
2674 break;
2675 default:
2676 goto out_unknown;
2677 }
2678 break;
2679 default:
2680 goto out_unknown;
2681 }
2682
2683 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2684 *format_comp = 1;
2685 }
2686
2687 *num_format = 0;
2688 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2689 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2690 if (!desc->channel[i].normalized) {
2691 if (desc->channel[i].pure_integer)
2692 *num_format = 1;
2693 else
2694 *num_format = 2;
2695 }
2696 }
2697 return;
2698 out_unknown:
2699 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2700 }
2701
2702 int r600_vertex_elements_build_fetch_shader(struct r600_context *rctx, struct r600_vertex_element *ve)
2703 {
2704 static int dump_shaders = -1;
2705
2706 struct r600_bytecode bc;
2707 struct r600_bytecode_vtx vtx;
2708 struct pipe_vertex_element *elements = ve->elements;
2709 const struct util_format_description *desc;
2710 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2711 unsigned format, num_format, format_comp, endian;
2712 uint32_t *bytecode;
2713 int i, r;
2714
2715 /* Vertex element offsets need special handling. If the offset is
2716 * bigger than what we can put in the fetch instruction we need to
2717 * alter the vertex resource offset. In order to simplify code we
2718 * will bind one resource per element in such cases. It's a worst
2719 * case scenario. */
2720 for (i = 0; i < ve->count; i++) {
2721 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2722 if (ve->vbuffer_offset[i]) {
2723 ve->vbuffer_need_offset = 1;
2724 }
2725 }
2726
2727 memset(&bc, 0, sizeof(bc));
2728 r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
2729
2730 for (i = 0; i < ve->count; i++) {
2731 if (elements[i].instance_divisor > 1) {
2732 struct r600_bytecode_alu alu;
2733
2734 memset(&alu, 0, sizeof(alu));
2735 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2736 alu.src[0].sel = 0;
2737 alu.src[0].chan = 3;
2738
2739 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2740 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2741
2742 alu.dst.sel = i + 1;
2743 alu.dst.chan = 3;
2744 alu.dst.write = 1;
2745 alu.last = 1;
2746
2747 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2748 r600_bytecode_clear(&bc);
2749 return r;
2750 }
2751 }
2752 }
2753
2754 for (i = 0; i < ve->count; i++) {
2755 unsigned vbuffer_index;
2756 r600_vertex_data_type(ve->elements[i].src_format,
2757 &format, &num_format, &format_comp, &endian);
2758 desc = util_format_description(ve->elements[i].src_format);
2759 if (desc == NULL) {
2760 r600_bytecode_clear(&bc);
2761 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2762 return -EINVAL;
2763 }
2764
2765 /* see above for vbuffer_need_offset explanation */
2766 vbuffer_index = elements[i].vertex_buffer_index;
2767 memset(&vtx, 0, sizeof(vtx));
2768 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2769 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2770 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2771 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2772 vtx.mega_fetch_count = 0x1F;
2773 vtx.dst_gpr = i + 1;
2774 vtx.dst_sel_x = desc->swizzle[0];
2775 vtx.dst_sel_y = desc->swizzle[1];
2776 vtx.dst_sel_z = desc->swizzle[2];
2777 vtx.dst_sel_w = desc->swizzle[3];
2778 vtx.data_format = format;
2779 vtx.num_format_all = num_format;
2780 vtx.format_comp_all = format_comp;
2781 vtx.srf_mode_all = 1;
2782 vtx.offset = elements[i].src_offset;
2783 vtx.endian = endian;
2784
2785 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2786 r600_bytecode_clear(&bc);
2787 return r;
2788 }
2789 }
2790
2791 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2792
2793 if ((r = r600_bytecode_build(&bc))) {
2794 r600_bytecode_clear(&bc);
2795 return r;
2796 }
2797
2798 if (dump_shaders == -1)
2799 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2800
2801 if (dump_shaders) {
2802 fprintf(stderr, "--------------------------------------------------------------\n");
2803 r600_bytecode_dump(&bc);
2804 fprintf(stderr, "______________________________________________________________\n");
2805 }
2806
2807 ve->fs_size = bc.ndw*4;
2808
2809 ve->fetch_shader = (struct r600_resource*)
2810 pipe_buffer_create(rctx->context.screen,
2811 PIPE_BIND_CUSTOM,
2812 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2813 if (ve->fetch_shader == NULL) {
2814 r600_bytecode_clear(&bc);
2815 return -ENOMEM;
2816 }
2817
2818 bytecode = rctx->ws->buffer_map(ve->fetch_shader->buf, rctx->cs, PIPE_TRANSFER_WRITE);
2819 if (bytecode == NULL) {
2820 r600_bytecode_clear(&bc);
2821 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2822 return -ENOMEM;
2823 }
2824
2825 if (R600_BIG_ENDIAN) {
2826 for (i = 0; i < ve->fs_size / 4; ++i) {
2827 bytecode[i] = bswap_32(bc.bytecode[i]);
2828 }
2829 } else {
2830 memcpy(bytecode, bc.bytecode, ve->fs_size);
2831 }
2832
2833 rctx->ws->buffer_unmap(ve->fetch_shader->buf);
2834 r600_bytecode_clear(&bc);
2835
2836 if (rctx->chip_class >= EVERGREEN)
2837 evergreen_fetch_shader(&rctx->context, ve);
2838 else
2839 r600_fetch_shader(&rctx->context, ve);
2840
2841 return 0;
2842 }