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r600g: add doubles support for CAYMAN
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
34
35 #include "sb/sb_public.h"
36
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
39
40 static inline unsigned int r600_bytecode_get_num_operands(
41 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
42 {
43 return r600_isa_alu(alu->op)->src_count;
44 }
45
46 int r700_bytecode_alu_build(struct r600_bytecode *bc,
47 struct r600_bytecode_alu *alu, unsigned id);
48
49 static struct r600_bytecode_cf *r600_bytecode_cf(void)
50 {
51 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
52
53 if (cf == NULL)
54 return NULL;
55 LIST_INITHEAD(&cf->list);
56 LIST_INITHEAD(&cf->alu);
57 LIST_INITHEAD(&cf->vtx);
58 LIST_INITHEAD(&cf->tex);
59 return cf;
60 }
61
62 static struct r600_bytecode_alu *r600_bytecode_alu(void)
63 {
64 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
65
66 if (alu == NULL)
67 return NULL;
68 LIST_INITHEAD(&alu->list);
69 return alu;
70 }
71
72 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
73 {
74 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
75
76 if (vtx == NULL)
77 return NULL;
78 LIST_INITHEAD(&vtx->list);
79 return vtx;
80 }
81
82 static struct r600_bytecode_tex *r600_bytecode_tex(void)
83 {
84 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
85
86 if (tex == NULL)
87 return NULL;
88 LIST_INITHEAD(&tex->list);
89 return tex;
90 }
91
92 static unsigned stack_entry_size(enum radeon_family chip) {
93 /* Wavefront size:
94 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
95 * Aruba/Sumo/Sumo2/redwood/juniper
96 * 32: R630/R730/R710/Palm/Cedar
97 * 16: R610/Rs780
98 *
99 * Stack row size:
100 * Wavefront Size 16 32 48 64
101 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
102 * Columns per Row (R9xx+) 8 4 4 4 */
103
104 switch (chip) {
105 /* FIXME: are some chips missing here? */
106 /* wavefront size 16 */
107 case CHIP_RV610:
108 case CHIP_RS780:
109 case CHIP_RV620:
110 case CHIP_RS880:
111 /* wavefront size 32 */
112 case CHIP_RV630:
113 case CHIP_RV635:
114 case CHIP_RV730:
115 case CHIP_RV710:
116 case CHIP_PALM:
117 case CHIP_CEDAR:
118 return 8;
119
120 /* wavefront size 64 */
121 default:
122 return 4;
123 }
124 }
125
126 void r600_bytecode_init(struct r600_bytecode *bc,
127 enum chip_class chip_class,
128 enum radeon_family family,
129 bool has_compressed_msaa_texturing)
130 {
131 static unsigned next_shader_id = 0;
132
133 bc->debug_id = ++next_shader_id;
134
135 if ((chip_class == R600) &&
136 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
137 bc->ar_handling = AR_HANDLE_RV6XX;
138 bc->r6xx_nop_after_rel_dst = 1;
139 } else {
140 bc->ar_handling = AR_HANDLE_NORMAL;
141 bc->r6xx_nop_after_rel_dst = 0;
142 }
143
144 LIST_INITHEAD(&bc->cf);
145 bc->chip_class = chip_class;
146 bc->family = family;
147 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
148 bc->stack.entry_size = stack_entry_size(family);
149 }
150
151 int r600_bytecode_add_cf(struct r600_bytecode *bc)
152 {
153 struct r600_bytecode_cf *cf = r600_bytecode_cf();
154
155 if (cf == NULL)
156 return -ENOMEM;
157 LIST_ADDTAIL(&cf->list, &bc->cf);
158 if (bc->cf_last) {
159 cf->id = bc->cf_last->id + 2;
160 if (bc->cf_last->eg_alu_extended) {
161 /* take into account extended alu size */
162 cf->id += 2;
163 bc->ndw += 2;
164 }
165 }
166 bc->cf_last = cf;
167 bc->ncf++;
168 bc->ndw += 2;
169 bc->force_add_cf = 0;
170 bc->ar_loaded = 0;
171 return 0;
172 }
173
174 int r600_bytecode_add_output(struct r600_bytecode *bc,
175 const struct r600_bytecode_output *output)
176 {
177 int r;
178
179 if (output->gpr >= bc->ngpr)
180 bc->ngpr = output->gpr + 1;
181
182 if (bc->cf_last && (bc->cf_last->op == output->op ||
183 (bc->cf_last->op == CF_OP_EXPORT &&
184 output->op == CF_OP_EXPORT_DONE)) &&
185 output->type == bc->cf_last->output.type &&
186 output->elem_size == bc->cf_last->output.elem_size &&
187 output->swizzle_x == bc->cf_last->output.swizzle_x &&
188 output->swizzle_y == bc->cf_last->output.swizzle_y &&
189 output->swizzle_z == bc->cf_last->output.swizzle_z &&
190 output->swizzle_w == bc->cf_last->output.swizzle_w &&
191 output->comp_mask == bc->cf_last->output.comp_mask &&
192 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
193
194 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
195 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
196
197 bc->cf_last->op = bc->cf_last->output.op = output->op;
198 bc->cf_last->output.gpr = output->gpr;
199 bc->cf_last->output.array_base = output->array_base;
200 bc->cf_last->output.burst_count += output->burst_count;
201 return 0;
202
203 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
204 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
205
206 bc->cf_last->op = bc->cf_last->output.op = output->op;
207 bc->cf_last->output.burst_count += output->burst_count;
208 return 0;
209 }
210 }
211
212 r = r600_bytecode_add_cf(bc);
213 if (r)
214 return r;
215 bc->cf_last->op = output->op;
216 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
217 bc->cf_last->barrier = 1;
218 return 0;
219 }
220
221 /* alu instructions that can ony exits once per group */
222 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
223 {
224 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
225 }
226
227 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
228 {
229 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
230 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
231 }
232
233 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
234 {
235 return r600_isa_alu(alu->op)->flags & AF_MOVA;
236 }
237
238 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
239 {
240 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
241 unsigned src;
242
243 if (alu->dst.rel) {
244 return 1;
245 }
246
247 for (src = 0; src < num_src; ++src) {
248 if (alu->src[src].rel) {
249 return 1;
250 }
251 }
252 return 0;
253 }
254
255 static int is_alu_64bit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
256 {
257 const struct alu_op_info *op = r600_isa_alu(alu->op);
258 return (op->flags & AF_64);
259 }
260
261 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
262 {
263 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
264 return !(slots & AF_S);
265 }
266
267 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
268 {
269 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
270 return !(slots & AF_V);
271 }
272
273 /* alu instructions that can execute on any unit */
274 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
275 {
276 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
277 return slots == AF_VS;
278 }
279
280 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
281 {
282 return alu->op == ALU_OP0_NOP;
283 }
284
285 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
286 struct r600_bytecode_alu *assignment[5])
287 {
288 struct r600_bytecode_alu *alu;
289 unsigned i, chan, trans;
290 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
291
292 for (i = 0; i < max_slots; i++)
293 assignment[i] = NULL;
294
295 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
296 chan = alu->dst.chan;
297 if (max_slots == 4)
298 trans = 0;
299 else if (is_alu_trans_unit_inst(bc, alu))
300 trans = 1;
301 else if (is_alu_vec_unit_inst(bc, alu))
302 trans = 0;
303 else if (assignment[chan])
304 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
305 else
306 trans = 0;
307
308 if (trans) {
309 if (assignment[4]) {
310 assert(0); /* ALU.Trans has already been allocated. */
311 return -1;
312 }
313 assignment[4] = alu;
314 } else {
315 if (assignment[chan]) {
316 assert(0); /* ALU.chan has already been allocated. */
317 return -1;
318 }
319 assignment[chan] = alu;
320 }
321
322 if (alu->last)
323 break;
324 }
325 return 0;
326 }
327
328 struct alu_bank_swizzle {
329 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
330 int hw_cfile_addr[4];
331 int hw_cfile_elem[4];
332 };
333
334 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
335 [SQ_ALU_VEC_012] = { 0, 1, 2 },
336 [SQ_ALU_VEC_021] = { 0, 2, 1 },
337 [SQ_ALU_VEC_120] = { 1, 2, 0 },
338 [SQ_ALU_VEC_102] = { 1, 0, 2 },
339 [SQ_ALU_VEC_201] = { 2, 0, 1 },
340 [SQ_ALU_VEC_210] = { 2, 1, 0 }
341 };
342
343 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
344 [SQ_ALU_SCL_210] = { 2, 1, 0 },
345 [SQ_ALU_SCL_122] = { 1, 2, 2 },
346 [SQ_ALU_SCL_212] = { 2, 1, 2 },
347 [SQ_ALU_SCL_221] = { 2, 2, 1 }
348 };
349
350 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
351 {
352 int i, cycle, component;
353 /* set up gpr use */
354 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
355 for (component = 0; component < NUM_OF_COMPONENTS; component++)
356 bs->hw_gpr[cycle][component] = -1;
357 for (i = 0; i < 4; i++)
358 bs->hw_cfile_addr[i] = -1;
359 for (i = 0; i < 4; i++)
360 bs->hw_cfile_elem[i] = -1;
361 }
362
363 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
364 {
365 if (bs->hw_gpr[cycle][chan] == -1)
366 bs->hw_gpr[cycle][chan] = sel;
367 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
368 /* Another scalar operation has already used the GPR read port for the channel. */
369 return -1;
370 }
371 return 0;
372 }
373
374 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
375 {
376 int res, num_res = 4;
377 if (bc->chip_class >= R700) {
378 num_res = 2;
379 chan /= 2;
380 }
381 for (res = 0; res < num_res; ++res) {
382 if (bs->hw_cfile_addr[res] == -1) {
383 bs->hw_cfile_addr[res] = sel;
384 bs->hw_cfile_elem[res] = chan;
385 return 0;
386 } else if (bs->hw_cfile_addr[res] == sel &&
387 bs->hw_cfile_elem[res] == chan)
388 return 0; /* Read for this scalar element already reserved, nothing to do here. */
389 }
390 /* All cfile read ports are used, cannot reference vector element. */
391 return -1;
392 }
393
394 static int is_gpr(unsigned sel)
395 {
396 return (sel <= 127);
397 }
398
399 /* CB constants start at 512, and get translated to a kcache index when ALU
400 * clauses are constructed. Note that we handle kcache constants the same way
401 * as (the now gone) cfile constants, is that really required? */
402 static int is_cfile(unsigned sel)
403 {
404 return (sel > 255 && sel < 512) ||
405 (sel > 511 && sel < 4607) || /* Kcache before translation. */
406 (sel > 127 && sel < 192); /* Kcache after translation. */
407 }
408
409 static int is_const(int sel)
410 {
411 return is_cfile(sel) ||
412 (sel >= V_SQ_ALU_SRC_0 &&
413 sel <= V_SQ_ALU_SRC_LITERAL);
414 }
415
416 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
417 struct alu_bank_swizzle *bs, int bank_swizzle)
418 {
419 int r, src, num_src, sel, elem, cycle;
420
421 num_src = r600_bytecode_get_num_operands(bc, alu);
422 for (src = 0; src < num_src; src++) {
423 sel = alu->src[src].sel;
424 elem = alu->src[src].chan;
425 if (is_gpr(sel)) {
426 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
427 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
428 /* Nothing to do; special-case optimization,
429 * second source uses first source’s reservation. */
430 continue;
431 else {
432 r = reserve_gpr(bs, sel, elem, cycle);
433 if (r)
434 return r;
435 }
436 } else if (is_cfile(sel)) {
437 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
438 if (r)
439 return r;
440 }
441 /* No restrictions on PV, PS, literal or special constants. */
442 }
443 return 0;
444 }
445
446 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
447 struct alu_bank_swizzle *bs, int bank_swizzle)
448 {
449 int r, src, num_src, const_count, sel, elem, cycle;
450
451 num_src = r600_bytecode_get_num_operands(bc, alu);
452 for (const_count = 0, src = 0; src < num_src; ++src) {
453 sel = alu->src[src].sel;
454 elem = alu->src[src].chan;
455 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
456 if (const_count >= 2)
457 /* More than two references to a constant in
458 * transcendental operation. */
459 return -1;
460 else
461 const_count++;
462 }
463 if (is_cfile(sel)) {
464 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
465 if (r)
466 return r;
467 }
468 }
469 for (src = 0; src < num_src; ++src) {
470 sel = alu->src[src].sel;
471 elem = alu->src[src].chan;
472 if (is_gpr(sel)) {
473 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
474 if (cycle < const_count)
475 /* Cycle for GPR load conflicts with
476 * constant load in transcendental operation. */
477 return -1;
478 r = reserve_gpr(bs, sel, elem, cycle);
479 if (r)
480 return r;
481 }
482 /* PV PS restrictions */
483 if (const_count && (sel == 254 || sel == 255)) {
484 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
485 if (cycle < const_count)
486 return -1;
487 }
488 }
489 return 0;
490 }
491
492 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
493 struct r600_bytecode_alu *slots[5])
494 {
495 struct alu_bank_swizzle bs;
496 int bank_swizzle[5];
497 int i, r = 0, forced = 1;
498 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
499 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
500
501 for (i = 0; i < max_slots; i++) {
502 if (slots[i]) {
503 if (slots[i]->bank_swizzle_force) {
504 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
505 } else {
506 forced = 0;
507 }
508 }
509
510 if (i < 4 && slots[i])
511 scalar_only = false;
512 }
513 if (forced)
514 return 0;
515
516 /* Just check every possible combination of bank swizzle.
517 * Not very efficent, but works on the first try in most of the cases. */
518 for (i = 0; i < 4; i++)
519 if (!slots[i] || !slots[i]->bank_swizzle_force)
520 bank_swizzle[i] = SQ_ALU_VEC_012;
521 else
522 bank_swizzle[i] = slots[i]->bank_swizzle;
523
524 bank_swizzle[4] = SQ_ALU_SCL_210;
525 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
526
527 init_bank_swizzle(&bs);
528 if (scalar_only == false) {
529 for (i = 0; i < 4; i++) {
530 if (slots[i]) {
531 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
532 if (r)
533 break;
534 }
535 }
536 } else
537 r = 0;
538
539 if (!r && max_slots == 5 && slots[4]) {
540 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
541 }
542 if (!r) {
543 for (i = 0; i < max_slots; i++) {
544 if (slots[i])
545 slots[i]->bank_swizzle = bank_swizzle[i];
546 }
547 return 0;
548 }
549
550 if (scalar_only) {
551 bank_swizzle[4]++;
552 } else {
553 for (i = 0; i < max_slots; i++) {
554 if (!slots[i] || !slots[i]->bank_swizzle_force) {
555 bank_swizzle[i]++;
556 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
557 break;
558 else if (i < max_slots - 1)
559 bank_swizzle[i] = SQ_ALU_VEC_012;
560 else
561 return -1;
562 }
563 }
564 }
565 }
566
567 /* Couldn't find a working swizzle. */
568 return -1;
569 }
570
571 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
572 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
573 {
574 struct r600_bytecode_alu *prev[5];
575 int gpr[5], chan[5];
576 int i, j, r, src, num_src;
577 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
578
579 r = assign_alu_units(bc, alu_prev, prev);
580 if (r)
581 return r;
582
583 for (i = 0; i < max_slots; ++i) {
584 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
585
586 if (is_alu_64bit_inst(bc, prev[i])) {
587 gpr[i] = -1;
588 continue;
589 }
590
591 gpr[i] = prev[i]->dst.sel;
592 /* cube writes more than PV.X */
593 if (is_alu_reduction_inst(bc, prev[i]))
594 chan[i] = 0;
595 else
596 chan[i] = prev[i]->dst.chan;
597 } else
598 gpr[i] = -1;
599 }
600
601 for (i = 0; i < max_slots; ++i) {
602 struct r600_bytecode_alu *alu = slots[i];
603 if(!alu)
604 continue;
605
606 if (is_alu_64bit_inst(bc, alu))
607 continue;
608 num_src = r600_bytecode_get_num_operands(bc, alu);
609 for (src = 0; src < num_src; ++src) {
610 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
611 continue;
612
613 if (bc->chip_class < CAYMAN) {
614 if (alu->src[src].sel == gpr[4] &&
615 alu->src[src].chan == chan[4] &&
616 alu_prev->pred_sel == alu->pred_sel) {
617 alu->src[src].sel = V_SQ_ALU_SRC_PS;
618 alu->src[src].chan = 0;
619 continue;
620 }
621 }
622
623 for (j = 0; j < 4; ++j) {
624 if (alu->src[src].sel == gpr[j] &&
625 alu->src[src].chan == j &&
626 alu_prev->pred_sel == alu->pred_sel) {
627 alu->src[src].sel = V_SQ_ALU_SRC_PV;
628 alu->src[src].chan = chan[j];
629 break;
630 }
631 }
632 }
633 }
634
635 return 0;
636 }
637
638 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
639 {
640 switch(value) {
641 case 0:
642 *sel = V_SQ_ALU_SRC_0;
643 break;
644 case 1:
645 *sel = V_SQ_ALU_SRC_1_INT;
646 break;
647 case -1:
648 *sel = V_SQ_ALU_SRC_M_1_INT;
649 break;
650 case 0x3F800000: /* 1.0f */
651 *sel = V_SQ_ALU_SRC_1;
652 break;
653 case 0x3F000000: /* 0.5f */
654 *sel = V_SQ_ALU_SRC_0_5;
655 break;
656 case 0xBF800000: /* -1.0f */
657 *sel = V_SQ_ALU_SRC_1;
658 *neg ^= 1;
659 break;
660 case 0xBF000000: /* -0.5f */
661 *sel = V_SQ_ALU_SRC_0_5;
662 *neg ^= 1;
663 break;
664 default:
665 *sel = V_SQ_ALU_SRC_LITERAL;
666 break;
667 }
668 }
669
670 /* compute how many literal are needed */
671 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
672 uint32_t literal[4], unsigned *nliteral)
673 {
674 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
675 unsigned i, j;
676
677 for (i = 0; i < num_src; ++i) {
678 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
679 uint32_t value = alu->src[i].value;
680 unsigned found = 0;
681 for (j = 0; j < *nliteral; ++j) {
682 if (literal[j] == value) {
683 found = 1;
684 break;
685 }
686 }
687 if (!found) {
688 if (*nliteral >= 4)
689 return -EINVAL;
690 literal[(*nliteral)++] = value;
691 }
692 }
693 }
694 return 0;
695 }
696
697 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
698 struct r600_bytecode_alu *alu,
699 uint32_t literal[4], unsigned nliteral)
700 {
701 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
702 unsigned i, j;
703
704 for (i = 0; i < num_src; ++i) {
705 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
706 uint32_t value = alu->src[i].value;
707 for (j = 0; j < nliteral; ++j) {
708 if (literal[j] == value) {
709 alu->src[i].chan = j;
710 break;
711 }
712 }
713 }
714 }
715 }
716
717 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
718 struct r600_bytecode_alu *alu_prev)
719 {
720 struct r600_bytecode_alu *prev[5];
721 struct r600_bytecode_alu *result[5] = { NULL };
722
723 uint32_t literal[4], prev_literal[4];
724 unsigned nliteral = 0, prev_nliteral = 0;
725
726 int i, j, r, src, num_src;
727 int num_once_inst = 0;
728 int have_mova = 0, have_rel = 0;
729 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
730
731 r = assign_alu_units(bc, alu_prev, prev);
732 if (r)
733 return r;
734
735 for (i = 0; i < max_slots; ++i) {
736 if (prev[i]) {
737 if (prev[i]->pred_sel)
738 return 0;
739 if (is_alu_once_inst(bc, prev[i]))
740 return 0;
741 }
742 if (slots[i]) {
743 if (slots[i]->pred_sel)
744 return 0;
745 if (is_alu_once_inst(bc, slots[i]))
746 return 0;
747 }
748 }
749
750 for (i = 0; i < max_slots; ++i) {
751 struct r600_bytecode_alu *alu;
752
753 if (num_once_inst > 0)
754 return 0;
755
756 /* check number of literals */
757 if (prev[i]) {
758 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
759 return 0;
760 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
761 return 0;
762 if (is_alu_mova_inst(bc, prev[i])) {
763 if (have_rel)
764 return 0;
765 have_mova = 1;
766 }
767
768 if (alu_uses_rel(bc, prev[i])) {
769 if (have_mova) {
770 return 0;
771 }
772 have_rel = 1;
773 }
774
775 num_once_inst += is_alu_once_inst(bc, prev[i]);
776 }
777 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
778 return 0;
779
780 /* Let's check used slots. */
781 if (prev[i] && !slots[i]) {
782 result[i] = prev[i];
783 continue;
784 } else if (prev[i] && slots[i]) {
785 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
786 /* Trans unit is still free try to use it. */
787 if (is_alu_any_unit_inst(bc, slots[i])) {
788 result[i] = prev[i];
789 result[4] = slots[i];
790 } else if (is_alu_any_unit_inst(bc, prev[i])) {
791 if (slots[i]->dst.sel == prev[i]->dst.sel &&
792 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
793 (prev[i]->dst.write == 1 || prev[i]->is_op3))
794 return 0;
795
796 result[i] = slots[i];
797 result[4] = prev[i];
798 } else
799 return 0;
800 } else
801 return 0;
802 } else if(!slots[i]) {
803 continue;
804 } else {
805 if (max_slots == 5 && slots[i] && prev[4] &&
806 slots[i]->dst.sel == prev[4]->dst.sel &&
807 slots[i]->dst.chan == prev[4]->dst.chan &&
808 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
809 (prev[4]->dst.write == 1 || prev[4]->is_op3))
810 return 0;
811
812 result[i] = slots[i];
813 }
814
815 alu = slots[i];
816 num_once_inst += is_alu_once_inst(bc, alu);
817
818 /* don't reschedule NOPs */
819 if (is_nop_inst(bc, alu))
820 return 0;
821
822 if (is_alu_mova_inst(bc, alu)) {
823 if (have_rel) {
824 return 0;
825 }
826 have_mova = 1;
827 }
828
829 if (alu_uses_rel(bc, alu)) {
830 if (have_mova) {
831 return 0;
832 }
833 have_rel = 1;
834 }
835
836 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
837 alu->op == ALU_OP0_SET_CF_IDX1)
838 return 0; /* data hazard with MOVA */
839
840 /* Let's check source gprs */
841 num_src = r600_bytecode_get_num_operands(bc, alu);
842 for (src = 0; src < num_src; ++src) {
843
844 /* Constants don't matter. */
845 if (!is_gpr(alu->src[src].sel))
846 continue;
847
848 for (j = 0; j < max_slots; ++j) {
849 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
850 continue;
851
852 /* If it's relative then we can't determin which gpr is really used. */
853 if (prev[j]->dst.chan == alu->src[src].chan &&
854 (prev[j]->dst.sel == alu->src[src].sel ||
855 prev[j]->dst.rel || alu->src[src].rel))
856 return 0;
857 }
858 }
859 }
860
861 /* more than one PRED_ or KILL_ ? */
862 if (num_once_inst > 1)
863 return 0;
864
865 /* check if the result can still be swizzlet */
866 r = check_and_set_bank_swizzle(bc, result);
867 if (r)
868 return 0;
869
870 /* looks like everything worked out right, apply the changes */
871
872 /* undo adding previus literals */
873 bc->cf_last->ndw -= align(prev_nliteral, 2);
874
875 /* sort instructions */
876 for (i = 0; i < max_slots; ++i) {
877 slots[i] = result[i];
878 if (result[i]) {
879 LIST_DEL(&result[i]->list);
880 result[i]->last = 0;
881 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
882 }
883 }
884
885 /* determine new last instruction */
886 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
887
888 /* determine new first instruction */
889 for (i = 0; i < max_slots; ++i) {
890 if (result[i]) {
891 bc->cf_last->curr_bs_head = result[i];
892 break;
893 }
894 }
895
896 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
897 bc->cf_last->prev2_bs_head = NULL;
898
899 return 0;
900 }
901
902 /* we'll keep kcache sets sorted by bank & addr */
903 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
904 struct r600_bytecode_kcache *kcache,
905 unsigned bank, unsigned line, unsigned index_mode)
906 {
907 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
908
909 for (i = 0; i < kcache_banks; i++) {
910 if (kcache[i].mode) {
911 int d;
912
913 if (kcache[i].bank < bank)
914 continue;
915
916 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
917 kcache[i].bank > bank) {
918 /* try to insert new line */
919 if (kcache[kcache_banks-1].mode) {
920 /* all sets are in use */
921 return -ENOMEM;
922 }
923
924 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
925 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
926 kcache[i].bank = bank;
927 kcache[i].addr = line;
928 kcache[i].index_mode = index_mode;
929 return 0;
930 }
931
932 d = line - kcache[i].addr;
933
934 if (d == -1) {
935 kcache[i].addr--;
936 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
937 /* we are prepending the line to the current set,
938 * discarding the existing second line,
939 * so we'll have to insert line+2 after it */
940 line += 2;
941 continue;
942 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
943 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
944 return 0;
945 } else {
946 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
947 return -ENOMEM;
948 }
949 } else if (d == 1) {
950 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
951 return 0;
952 } else if (d == 0)
953 return 0;
954 } else { /* free kcache set - use it */
955 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
956 kcache[i].bank = bank;
957 kcache[i].addr = line;
958 kcache[i].index_mode = index_mode;
959 return 0;
960 }
961 }
962 return -ENOMEM;
963 }
964
965 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
966 struct r600_bytecode_kcache *kcache,
967 struct r600_bytecode_alu *alu)
968 {
969 int i, r;
970
971 for (i = 0; i < 3; i++) {
972 unsigned bank, line, sel = alu->src[i].sel, index_mode;
973
974 if (sel < 512)
975 continue;
976
977 bank = alu->src[i].kc_bank;
978 line = (sel-512)>>4;
979 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
980
981 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
982 return r;
983 }
984 return 0;
985 }
986
987 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
988 struct r600_bytecode_alu *alu,
989 struct r600_bytecode_kcache * kcache)
990 {
991 int i, j;
992
993 /* Alter the src operands to refer to the kcache. */
994 for (i = 0; i < 3; ++i) {
995 static const unsigned int base[] = {128, 160, 256, 288};
996 unsigned int line, sel = alu->src[i].sel, found = 0;
997
998 if (sel < 512)
999 continue;
1000
1001 sel -= 512;
1002 line = sel>>4;
1003
1004 for (j = 0; j < 4 && !found; ++j) {
1005 switch (kcache[j].mode) {
1006 case V_SQ_CF_KCACHE_NOP:
1007 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1008 R600_ERR("unexpected kcache line mode\n");
1009 return -ENOMEM;
1010 default:
1011 if (kcache[j].bank == alu->src[i].kc_bank &&
1012 kcache[j].addr <= line &&
1013 line < kcache[j].addr + kcache[j].mode) {
1014 alu->src[i].sel = sel - (kcache[j].addr<<4);
1015 alu->src[i].sel += base[j];
1016 found=1;
1017 }
1018 }
1019 }
1020 }
1021 return 0;
1022 }
1023
1024 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1025 struct r600_bytecode_alu *alu,
1026 unsigned type)
1027 {
1028 struct r600_bytecode_kcache kcache_sets[4];
1029 struct r600_bytecode_kcache *kcache = kcache_sets;
1030 int r;
1031
1032 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1033
1034 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1035 /* can't alloc, need to start new clause */
1036 if ((r = r600_bytecode_add_cf(bc))) {
1037 return r;
1038 }
1039 bc->cf_last->op = type;
1040
1041 /* retry with the new clause */
1042 kcache = bc->cf_last->kcache;
1043 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1044 /* can't alloc again- should never happen */
1045 return r;
1046 }
1047 } else {
1048 /* update kcache sets */
1049 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1050 }
1051
1052 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1053 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1054 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1055 if (bc->chip_class < EVERGREEN)
1056 return -ENOMEM;
1057 bc->cf_last->eg_alu_extended = 1;
1058 }
1059
1060 return 0;
1061 }
1062
1063 static int insert_nop_r6xx(struct r600_bytecode *bc)
1064 {
1065 struct r600_bytecode_alu alu;
1066 int r, i;
1067
1068 for (i = 0; i < 4; i++) {
1069 memset(&alu, 0, sizeof(alu));
1070 alu.op = ALU_OP0_NOP;
1071 alu.src[0].chan = i;
1072 alu.dst.chan = i;
1073 alu.last = (i == 3);
1074 r = r600_bytecode_add_alu(bc, &alu);
1075 if (r)
1076 return r;
1077 }
1078 return 0;
1079 }
1080
1081 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1082 static int load_ar_r6xx(struct r600_bytecode *bc)
1083 {
1084 struct r600_bytecode_alu alu;
1085 int r;
1086
1087 if (bc->ar_loaded)
1088 return 0;
1089
1090 /* hack to avoid making MOVA the last instruction in the clause */
1091 if ((bc->cf_last->ndw>>1) >= 110)
1092 bc->force_add_cf = 1;
1093
1094 memset(&alu, 0, sizeof(alu));
1095 alu.op = ALU_OP1_MOVA_GPR_INT;
1096 alu.src[0].sel = bc->ar_reg;
1097 alu.src[0].chan = bc->ar_chan;
1098 alu.last = 1;
1099 alu.index_mode = INDEX_MODE_LOOP;
1100 r = r600_bytecode_add_alu(bc, &alu);
1101 if (r)
1102 return r;
1103
1104 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1105 bc->ar_loaded = 1;
1106 return 0;
1107 }
1108
1109 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1110 static int load_ar(struct r600_bytecode *bc)
1111 {
1112 struct r600_bytecode_alu alu;
1113 int r;
1114
1115 if (bc->ar_handling)
1116 return load_ar_r6xx(bc);
1117
1118 if (bc->ar_loaded)
1119 return 0;
1120
1121 /* hack to avoid making MOVA the last instruction in the clause */
1122 if ((bc->cf_last->ndw>>1) >= 110)
1123 bc->force_add_cf = 1;
1124
1125 memset(&alu, 0, sizeof(alu));
1126 alu.op = ALU_OP1_MOVA_INT;
1127 alu.src[0].sel = bc->ar_reg;
1128 alu.src[0].chan = bc->ar_chan;
1129 alu.last = 1;
1130 r = r600_bytecode_add_alu(bc, &alu);
1131 if (r)
1132 return r;
1133
1134 bc->cf_last->r6xx_uses_waterfall = 1;
1135 bc->ar_loaded = 1;
1136 return 0;
1137 }
1138
1139 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1140 const struct r600_bytecode_alu *alu, unsigned type)
1141 {
1142 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1143 struct r600_bytecode_alu *lalu;
1144 int i, r;
1145
1146 if (nalu == NULL)
1147 return -ENOMEM;
1148 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1149
1150 if (alu->is_op3) {
1151 /* will fail later since alu does not support it. */
1152 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1153 }
1154
1155 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1156 /* check if we could add it anyway */
1157 if (bc->cf_last->op == CF_OP_ALU &&
1158 type == CF_OP_ALU_PUSH_BEFORE) {
1159 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1160 if (lalu->execute_mask) {
1161 bc->force_add_cf = 1;
1162 break;
1163 }
1164 }
1165 } else
1166 bc->force_add_cf = 1;
1167 }
1168
1169 /* cf can contains only alu or only vtx or only tex */
1170 if (bc->cf_last == NULL || bc->force_add_cf) {
1171 r = r600_bytecode_add_cf(bc);
1172 if (r) {
1173 free(nalu);
1174 return r;
1175 }
1176 }
1177 bc->cf_last->op = type;
1178
1179 /* Load index register if required */
1180 if (bc->chip_class >= EVERGREEN) {
1181 for (i = 0; i < 3; i++)
1182 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1183 egcm_load_index_reg(bc, 0, true);
1184 }
1185
1186 /* Check AR usage and load it if required */
1187 for (i = 0; i < 3; i++)
1188 if (nalu->src[i].rel && !bc->ar_loaded)
1189 load_ar(bc);
1190
1191 if (nalu->dst.rel && !bc->ar_loaded)
1192 load_ar(bc);
1193
1194 /* Setup the kcache for this ALU instruction. This will start a new
1195 * ALU clause if needed. */
1196 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1197 free(nalu);
1198 return r;
1199 }
1200
1201 if (!bc->cf_last->curr_bs_head) {
1202 bc->cf_last->curr_bs_head = nalu;
1203 }
1204 /* number of gpr == the last gpr used in any alu */
1205 for (i = 0; i < 3; i++) {
1206 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1207 bc->ngpr = nalu->src[i].sel + 1;
1208 }
1209 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1210 r600_bytecode_special_constants(nalu->src[i].value,
1211 &nalu->src[i].sel, &nalu->src[i].neg);
1212 }
1213 if (nalu->dst.sel >= bc->ngpr) {
1214 bc->ngpr = nalu->dst.sel + 1;
1215 }
1216 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1217 /* each alu use 2 dwords */
1218 bc->cf_last->ndw += 2;
1219 bc->ndw += 2;
1220
1221 /* process cur ALU instructions for bank swizzle */
1222 if (nalu->last) {
1223 uint32_t literal[4];
1224 unsigned nliteral;
1225 struct r600_bytecode_alu *slots[5];
1226 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1227 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1228 if (r)
1229 return r;
1230
1231 if (bc->cf_last->prev_bs_head) {
1232 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1233 if (r)
1234 return r;
1235 }
1236
1237 if (bc->cf_last->prev_bs_head) {
1238 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1239 if (r)
1240 return r;
1241 }
1242
1243 r = check_and_set_bank_swizzle(bc, slots);
1244 if (r)
1245 return r;
1246
1247 for (i = 0, nliteral = 0; i < max_slots; i++) {
1248 if (slots[i]) {
1249 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1250 if (r)
1251 return r;
1252 }
1253 }
1254 bc->cf_last->ndw += align(nliteral, 2);
1255
1256 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1257 * worst case */
1258 if ((bc->cf_last->ndw >> 1) >= 120) {
1259 bc->force_add_cf = 1;
1260 }
1261
1262 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1263 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1264 bc->cf_last->curr_bs_head = NULL;
1265 }
1266
1267 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1268 insert_nop_r6xx(bc);
1269
1270 return 0;
1271 }
1272
1273 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1274 {
1275 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1276 }
1277
1278 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1279 {
1280 switch (bc->chip_class) {
1281 case R600:
1282 return 8;
1283
1284 case R700:
1285 case EVERGREEN:
1286 case CAYMAN:
1287 return 16;
1288
1289 default:
1290 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1291 return 8;
1292 }
1293 }
1294
1295 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1296 {
1297 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1298 (bc->chip_class == CAYMAN ||
1299 bc->cf_last->op != CF_OP_TEX));
1300 }
1301
1302 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1303 {
1304 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1305 int r;
1306
1307 if (nvtx == NULL)
1308 return -ENOMEM;
1309 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1310
1311 /* Load index register if required */
1312 if (bc->chip_class >= EVERGREEN) {
1313 if (vtx->buffer_index_mode)
1314 egcm_load_index_reg(bc, 0, false);
1315 }
1316
1317 /* cf can contains only alu or only vtx or only tex */
1318 if (bc->cf_last == NULL ||
1319 last_inst_was_not_vtx_fetch(bc) ||
1320 bc->force_add_cf) {
1321 r = r600_bytecode_add_cf(bc);
1322 if (r) {
1323 free(nvtx);
1324 return r;
1325 }
1326 switch (bc->chip_class) {
1327 case R600:
1328 case R700:
1329 case EVERGREEN:
1330 bc->cf_last->op = CF_OP_VTX;
1331 break;
1332 case CAYMAN:
1333 bc->cf_last->op = CF_OP_TEX;
1334 break;
1335 default:
1336 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1337 free(nvtx);
1338 return -EINVAL;
1339 }
1340 }
1341 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1342 /* each fetch use 4 dwords */
1343 bc->cf_last->ndw += 4;
1344 bc->ndw += 4;
1345 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1346 bc->force_add_cf = 1;
1347
1348 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1349 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1350
1351 return 0;
1352 }
1353
1354 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1355 {
1356 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1357 int r;
1358
1359 if (ntex == NULL)
1360 return -ENOMEM;
1361 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1362
1363 /* Load index register if required */
1364 if (bc->chip_class >= EVERGREEN) {
1365 if (tex->sampler_index_mode || tex->resource_index_mode)
1366 egcm_load_index_reg(bc, 1, false);
1367 }
1368
1369 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1370 if (bc->cf_last != NULL &&
1371 bc->cf_last->op == CF_OP_TEX) {
1372 struct r600_bytecode_tex *ttex;
1373 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1374 if (ttex->dst_gpr == ntex->src_gpr) {
1375 bc->force_add_cf = 1;
1376 break;
1377 }
1378 }
1379 /* slight hack to make gradients always go into same cf */
1380 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1381 bc->force_add_cf = 1;
1382 }
1383
1384 /* cf can contains only alu or only vtx or only tex */
1385 if (bc->cf_last == NULL ||
1386 bc->cf_last->op != CF_OP_TEX ||
1387 bc->force_add_cf) {
1388 r = r600_bytecode_add_cf(bc);
1389 if (r) {
1390 free(ntex);
1391 return r;
1392 }
1393 bc->cf_last->op = CF_OP_TEX;
1394 }
1395 if (ntex->src_gpr >= bc->ngpr) {
1396 bc->ngpr = ntex->src_gpr + 1;
1397 }
1398 if (ntex->dst_gpr >= bc->ngpr) {
1399 bc->ngpr = ntex->dst_gpr + 1;
1400 }
1401 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1402 /* each texture fetch use 4 dwords */
1403 bc->cf_last->ndw += 4;
1404 bc->ndw += 4;
1405 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1406 bc->force_add_cf = 1;
1407 return 0;
1408 }
1409
1410 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1411 {
1412 int r;
1413 r = r600_bytecode_add_cf(bc);
1414 if (r)
1415 return r;
1416
1417 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1418 bc->cf_last->op = op;
1419 return 0;
1420 }
1421
1422 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1423 {
1424 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1425 }
1426
1427 /* common to all 3 families */
1428 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1429 {
1430 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1431 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1432 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1433 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1434 if (bc->chip_class < CAYMAN)
1435 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1436 id++;
1437 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1438 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1439 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1440 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1441 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1442 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1443 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1444 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1445 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1446 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1447 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1448 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1449 if (bc->chip_class >= EVERGREEN)
1450 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1451 if (bc->chip_class < CAYMAN)
1452 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1453 id++;
1454 bc->bytecode[id++] = 0;
1455 return 0;
1456 }
1457
1458 /* common to all 3 families */
1459 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1460 {
1461 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1462 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1463 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1464 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1465 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1466 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1467 if (bc->chip_class >= EVERGREEN)
1468 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1469 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1470 id++;
1471 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1472 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1473 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1474 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1475 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1476 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1477 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1478 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1479 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1480 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1481 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1482 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1483 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1484 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1485 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1486 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1487 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1488 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1489 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1490 bc->bytecode[id++] = 0;
1491 return 0;
1492 }
1493
1494 /* r600 only, r700/eg bits in r700_asm.c */
1495 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1496 {
1497 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1498
1499 /* don't replace gpr by pv or ps for destination register */
1500 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1501 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1502 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1503 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1504 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1505 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1506 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1507 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1508 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1509 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1510 S_SQ_ALU_WORD0_LAST(alu->last);
1511
1512 if (alu->is_op3) {
1513 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1514 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1515 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1516 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1517 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1518 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1519 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1520 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1521 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1522 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1523 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1524 } else {
1525 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1526 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1527 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1528 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1529 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1530 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1531 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1532 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1533 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1534 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1535 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1536 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1537 }
1538 return 0;
1539 }
1540
1541 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1542 {
1543 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1544 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1545 S_SQ_CF_WORD1_BARRIER(1) |
1546 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1547 }
1548
1549 /* common for r600/r700 - eg in eg_asm.c */
1550 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1551 {
1552 unsigned id = cf->id;
1553 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1554 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1555
1556
1557 if (cf->op == CF_NATIVE) {
1558 bc->bytecode[id++] = cf->isa[0];
1559 bc->bytecode[id++] = cf->isa[1];
1560 } else if (cfop->flags & CF_ALU) {
1561 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1562 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1563 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1564 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1565
1566 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1567 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1568 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1569 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1570 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1571 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1572 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1573 } else if (cfop->flags & CF_FETCH) {
1574 if (bc->chip_class == R700)
1575 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1576 else
1577 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1578 } else if (cfop->flags & CF_EXP) {
1579 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1580 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1581 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1582 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1583 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1584 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1585 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1586 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1587 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1588 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1589 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1590 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1591 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1592 } else if (cfop->flags & CF_MEM) {
1593 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1594 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1595 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1596 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1597 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1598 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1599 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1600 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1601 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1602 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1603 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1604 } else {
1605 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1606 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1607 S_SQ_CF_WORD1_BARRIER(1) |
1608 S_SQ_CF_WORD1_COND(cf->cond) |
1609 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1610 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1611 }
1612 return 0;
1613 }
1614
1615 int r600_bytecode_build(struct r600_bytecode *bc)
1616 {
1617 struct r600_bytecode_cf *cf;
1618 struct r600_bytecode_alu *alu;
1619 struct r600_bytecode_vtx *vtx;
1620 struct r600_bytecode_tex *tex;
1621 uint32_t literal[4];
1622 unsigned nliteral;
1623 unsigned addr;
1624 int i, r;
1625
1626 if (!bc->nstack) // If not 0, Stack_size already provided by llvm
1627 bc->nstack = bc->stack.max_entries;
1628
1629 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1630 bc->nstack = 1;
1631 }
1632
1633 /* first path compute addr of each CF block */
1634 /* addr start after all the CF instructions */
1635 addr = bc->cf_last->id + 2;
1636 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1637 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1638 addr += 3;
1639 addr &= 0xFFFFFFFCUL;
1640 }
1641 cf->addr = addr;
1642 addr += cf->ndw;
1643 bc->ndw = cf->addr + cf->ndw;
1644 }
1645 free(bc->bytecode);
1646 bc->bytecode = calloc(4, bc->ndw);
1647 if (bc->bytecode == NULL)
1648 return -ENOMEM;
1649 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1650 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1651 addr = cf->addr;
1652 if (bc->chip_class >= EVERGREEN)
1653 r = eg_bytecode_cf_build(bc, cf);
1654 else
1655 r = r600_bytecode_cf_build(bc, cf);
1656 if (r)
1657 return r;
1658 if (cfop->flags & CF_ALU) {
1659 nliteral = 0;
1660 memset(literal, 0, sizeof(literal));
1661 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1662 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1663 if (r)
1664 return r;
1665 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1666 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1667
1668 switch(bc->chip_class) {
1669 case R600:
1670 r = r600_bytecode_alu_build(bc, alu, addr);
1671 break;
1672 case R700:
1673 case EVERGREEN: /* eg alu is same encoding as r700 */
1674 case CAYMAN:
1675 r = r700_bytecode_alu_build(bc, alu, addr);
1676 break;
1677 default:
1678 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1679 return -EINVAL;
1680 }
1681 if (r)
1682 return r;
1683 addr += 2;
1684 if (alu->last) {
1685 for (i = 0; i < align(nliteral, 2); ++i) {
1686 bc->bytecode[addr++] = literal[i];
1687 }
1688 nliteral = 0;
1689 memset(literal, 0, sizeof(literal));
1690 }
1691 }
1692 } else if (cf->op == CF_OP_VTX) {
1693 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1694 r = r600_bytecode_vtx_build(bc, vtx, addr);
1695 if (r)
1696 return r;
1697 addr += 4;
1698 }
1699 } else if (cf->op == CF_OP_TEX) {
1700 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1701 assert(bc->chip_class >= EVERGREEN);
1702 r = r600_bytecode_vtx_build(bc, vtx, addr);
1703 if (r)
1704 return r;
1705 addr += 4;
1706 }
1707 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1708 r = r600_bytecode_tex_build(bc, tex, addr);
1709 if (r)
1710 return r;
1711 addr += 4;
1712 }
1713 }
1714 }
1715 return 0;
1716 }
1717
1718 void r600_bytecode_clear(struct r600_bytecode *bc)
1719 {
1720 struct r600_bytecode_cf *cf = NULL, *next_cf;
1721
1722 free(bc->bytecode);
1723 bc->bytecode = NULL;
1724
1725 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1726 struct r600_bytecode_alu *alu = NULL, *next_alu;
1727 struct r600_bytecode_tex *tex = NULL, *next_tex;
1728 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1729
1730 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1731 free(alu);
1732 }
1733
1734 LIST_INITHEAD(&cf->alu);
1735
1736 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1737 free(tex);
1738 }
1739
1740 LIST_INITHEAD(&cf->tex);
1741
1742 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1743 free(vtx);
1744 }
1745
1746 LIST_INITHEAD(&cf->vtx);
1747
1748 free(cf);
1749 }
1750
1751 LIST_INITHEAD(&cf->list);
1752 }
1753
1754 static int print_swizzle(unsigned swz)
1755 {
1756 const char * swzchars = "xyzw01?_";
1757 assert(swz<8 && swz != 6);
1758 return fprintf(stderr, "%c", swzchars[swz]);
1759 }
1760
1761 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1762 unsigned need_brackets)
1763 {
1764 int o = 0;
1765 if (rel && index_mode >= 5 && sel < 128)
1766 o += fprintf(stderr, "G");
1767 if (rel || need_brackets) {
1768 o += fprintf(stderr, "[");
1769 }
1770 o += fprintf(stderr, "%d", sel);
1771 if (rel) {
1772 if (index_mode == 0 || index_mode == 6)
1773 o += fprintf(stderr, "+AR");
1774 else if (index_mode == 4)
1775 o += fprintf(stderr, "+AL");
1776 }
1777 if (rel || need_brackets) {
1778 o += fprintf(stderr, "]");
1779 }
1780 return o;
1781 }
1782
1783 static int print_dst(struct r600_bytecode_alu *alu)
1784 {
1785 int o = 0;
1786 unsigned sel = alu->dst.sel;
1787 char reg_char = 'R';
1788 if (sel > 128 - 4) { /* clause temporary gpr */
1789 sel -= 128 - 4;
1790 reg_char = 'T';
1791 }
1792
1793 if (alu->dst.write || alu->is_op3) {
1794 o += fprintf(stderr, "%c", reg_char);
1795 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1796 } else {
1797 o += fprintf(stderr, "__");
1798 }
1799 o += fprintf(stderr, ".");
1800 o += print_swizzle(alu->dst.chan);
1801 return o;
1802 }
1803
1804 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1805 {
1806 int o = 0;
1807 struct r600_bytecode_alu_src *src = &alu->src[idx];
1808 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1809
1810 if (src->neg)
1811 o += fprintf(stderr,"-");
1812 if (src->abs)
1813 o += fprintf(stderr,"|");
1814
1815 if (sel < 128 - 4) {
1816 o += fprintf(stderr, "R");
1817 } else if (sel < 128) {
1818 o += fprintf(stderr, "T");
1819 sel -= 128 - 4;
1820 } else if (sel < 160) {
1821 o += fprintf(stderr, "KC0");
1822 need_brackets = 1;
1823 sel -= 128;
1824 } else if (sel < 192) {
1825 o += fprintf(stderr, "KC1");
1826 need_brackets = 1;
1827 sel -= 160;
1828 } else if (sel >= 512) {
1829 o += fprintf(stderr, "C%d", src->kc_bank);
1830 need_brackets = 1;
1831 sel -= 512;
1832 } else if (sel >= 448) {
1833 o += fprintf(stderr, "Param");
1834 sel -= 448;
1835 need_chan = 0;
1836 } else if (sel >= 288) {
1837 o += fprintf(stderr, "KC3");
1838 need_brackets = 1;
1839 sel -= 288;
1840 } else if (sel >= 256) {
1841 o += fprintf(stderr, "KC2");
1842 need_brackets = 1;
1843 sel -= 256;
1844 } else {
1845 need_sel = 0;
1846 need_chan = 0;
1847 switch (sel) {
1848 case V_SQ_ALU_SRC_PS:
1849 o += fprintf(stderr, "PS");
1850 break;
1851 case V_SQ_ALU_SRC_PV:
1852 o += fprintf(stderr, "PV");
1853 need_chan = 1;
1854 break;
1855 case V_SQ_ALU_SRC_LITERAL:
1856 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value);
1857 break;
1858 case V_SQ_ALU_SRC_0_5:
1859 o += fprintf(stderr, "0.5");
1860 break;
1861 case V_SQ_ALU_SRC_M_1_INT:
1862 o += fprintf(stderr, "-1");
1863 break;
1864 case V_SQ_ALU_SRC_1_INT:
1865 o += fprintf(stderr, "1");
1866 break;
1867 case V_SQ_ALU_SRC_1:
1868 o += fprintf(stderr, "1.0");
1869 break;
1870 case V_SQ_ALU_SRC_0:
1871 o += fprintf(stderr, "0");
1872 break;
1873 default:
1874 o += fprintf(stderr, "??IMM_%d", sel);
1875 break;
1876 }
1877 }
1878
1879 if (need_sel)
1880 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
1881
1882 if (need_chan) {
1883 o += fprintf(stderr, ".");
1884 o += print_swizzle(src->chan);
1885 }
1886
1887 if (src->abs)
1888 o += fprintf(stderr,"|");
1889
1890 return o;
1891 }
1892
1893 static int print_indent(int p, int c)
1894 {
1895 int o = 0;
1896 while (p++ < c)
1897 o += fprintf(stderr, " ");
1898 return o;
1899 }
1900
1901 void r600_bytecode_disasm(struct r600_bytecode *bc)
1902 {
1903 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
1904 static int index = 0;
1905 struct r600_bytecode_cf *cf = NULL;
1906 struct r600_bytecode_alu *alu = NULL;
1907 struct r600_bytecode_vtx *vtx = NULL;
1908 struct r600_bytecode_tex *tex = NULL;
1909
1910 unsigned i, id, ngr = 0, last;
1911 uint32_t literal[4];
1912 unsigned nliteral;
1913 char chip = '6';
1914
1915 switch (bc->chip_class) {
1916 case R700:
1917 chip = '7';
1918 break;
1919 case EVERGREEN:
1920 chip = 'E';
1921 break;
1922 case CAYMAN:
1923 chip = 'C';
1924 break;
1925 case R600:
1926 default:
1927 chip = '6';
1928 break;
1929 }
1930 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1931 bc->ndw, bc->ngpr, bc->nstack);
1932 fprintf(stderr, "shader %d -- %c\n", index++, chip);
1933
1934 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1935 id = cf->id;
1936 if (cf->op == CF_NATIVE) {
1937 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
1938 bc->bytecode[id + 1]);
1939 } else {
1940 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1941 if (cfop->flags & CF_ALU) {
1942 if (cf->eg_alu_extended) {
1943 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
1944 bc->bytecode[id + 1], "ALU_EXT");
1945 id += 2;
1946 }
1947 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1948 bc->bytecode[id + 1], cfop->name);
1949 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
1950 for (i = 0; i < 4; ++i) {
1951 if (cf->kcache[i].mode) {
1952 int c_start = (cf->kcache[i].addr << 4);
1953 int c_end = c_start + (cf->kcache[i].mode << 4);
1954 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
1955 i, cf->kcache[i].bank, c_start, c_end,
1956 cf->kcache[i].index_mode ? " " : "",
1957 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
1958 }
1959 }
1960 fprintf(stderr, "\n");
1961 } else if (cfop->flags & CF_FETCH) {
1962 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1963 bc->bytecode[id + 1], cfop->name);
1964 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
1965 fprintf(stderr, "\n");
1966 } else if (cfop->flags & CF_EXP) {
1967 int o = 0;
1968 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
1969 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1970 bc->bytecode[id + 1], cfop->name);
1971 o += print_indent(o, 43);
1972 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1973 if (cf->output.burst_count > 1) {
1974 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1975 cf->output.array_base + cf->output.burst_count - 1);
1976
1977 o += print_indent(o, 55);
1978 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1979 cf->output.gpr + cf->output.burst_count - 1);
1980 } else {
1981 o += fprintf(stderr, "%d ", cf->output.array_base);
1982 o += print_indent(o, 55);
1983 o += fprintf(stderr, "R%d.", cf->output.gpr);
1984 }
1985
1986 o += print_swizzle(cf->output.swizzle_x);
1987 o += print_swizzle(cf->output.swizzle_y);
1988 o += print_swizzle(cf->output.swizzle_z);
1989 o += print_swizzle(cf->output.swizzle_w);
1990
1991 print_indent(o, 67);
1992
1993 fprintf(stderr, " ES:%X ", cf->output.elem_size);
1994 if (!cf->barrier)
1995 fprintf(stderr, "NO_BARRIER ");
1996 if (cf->end_of_program)
1997 fprintf(stderr, "EOP ");
1998 fprintf(stderr, "\n");
1999 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2000 int o = 0;
2001 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2002 "WRITE_IND_ACK"};
2003 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2004 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2005 o += print_indent(o, 43);
2006 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2007 if (cf->output.burst_count > 1) {
2008 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2009 cf->output.array_base + cf->output.burst_count - 1);
2010 o += print_indent(o, 55);
2011 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2012 cf->output.gpr + cf->output.burst_count - 1);
2013 } else {
2014 o += fprintf(stderr, "%d ", cf->output.array_base);
2015 o += print_indent(o, 55);
2016 o += fprintf(stderr, "R%d.", cf->output.gpr);
2017 }
2018 for (i = 0; i < 4; ++i) {
2019 if (cf->output.comp_mask & (1 << i))
2020 o += print_swizzle(i);
2021 else
2022 o += print_swizzle(7);
2023 }
2024
2025 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND)
2026 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2027
2028 o += print_indent(o, 67);
2029
2030 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2031 if (cf->output.array_size != 0xFFF)
2032 fprintf(stderr, "AS:%i ", cf->output.array_size);
2033 if (!cf->barrier)
2034 fprintf(stderr, "NO_BARRIER ");
2035 if (cf->end_of_program)
2036 fprintf(stderr, "EOP ");
2037 fprintf(stderr, "\n");
2038 } else {
2039 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2040 bc->bytecode[id + 1], cfop->name);
2041 fprintf(stderr, "@%d ", cf->cf_addr);
2042 if (cf->cond)
2043 fprintf(stderr, "CND:%X ", cf->cond);
2044 if (cf->pop_count)
2045 fprintf(stderr, "POP:%X ", cf->pop_count);
2046 if (cf->count && (cfop->flags & CF_EMIT))
2047 fprintf(stderr, "STREAM%d ", cf->count);
2048 if (cf->end_of_program)
2049 fprintf(stderr, "EOP ");
2050 fprintf(stderr, "\n");
2051 }
2052 }
2053
2054 id = cf->addr;
2055 nliteral = 0;
2056 last = 1;
2057 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2058 const char *omod_str[] = {"","*2","*4","/2"};
2059 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2060 int o = 0;
2061
2062 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2063 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2064 if (last)
2065 o += fprintf(stderr, "%4d ", ++ngr);
2066 else
2067 o += fprintf(stderr, " ");
2068 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2069 alu->update_pred ? 'P':' ',
2070 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2071
2072 o += fprintf(stderr, "%s%s%s ", aop->name,
2073 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2074
2075 o += print_indent(o,60);
2076 o += print_dst(alu);
2077 for (i = 0; i < aop->src_count; ++i) {
2078 o += fprintf(stderr, i == 0 ? ", ": ", ");
2079 o += print_src(alu, i);
2080 }
2081
2082 if (alu->bank_swizzle) {
2083 o += print_indent(o,75);
2084 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2085 }
2086
2087 fprintf(stderr, "\n");
2088 id += 2;
2089
2090 if (alu->last) {
2091 for (i = 0; i < nliteral; i++, id++) {
2092 float *f = (float*)(bc->bytecode + id);
2093 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2094 print_indent(o, 60);
2095 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2096 }
2097 id += nliteral & 1;
2098 nliteral = 0;
2099 }
2100 last = alu->last;
2101 }
2102
2103 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2104 int o = 0;
2105 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2106 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2107
2108 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2109
2110 o += print_indent(o, 50);
2111
2112 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2113 o += print_swizzle(tex->dst_sel_x);
2114 o += print_swizzle(tex->dst_sel_y);
2115 o += print_swizzle(tex->dst_sel_z);
2116 o += print_swizzle(tex->dst_sel_w);
2117
2118 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2119 o += print_swizzle(tex->src_sel_x);
2120 o += print_swizzle(tex->src_sel_y);
2121 o += print_swizzle(tex->src_sel_z);
2122 o += print_swizzle(tex->src_sel_w);
2123
2124 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2125 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2126
2127 if (tex->sampler_index_mode)
2128 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2129
2130 if (tex->lod_bias)
2131 fprintf(stderr, "LB:%d ", tex->lod_bias);
2132
2133 fprintf(stderr, "CT:%c%c%c%c ",
2134 tex->coord_type_x ? 'N' : 'U',
2135 tex->coord_type_y ? 'N' : 'U',
2136 tex->coord_type_z ? 'N' : 'U',
2137 tex->coord_type_w ? 'N' : 'U');
2138
2139 if (tex->offset_x)
2140 fprintf(stderr, "OX:%d ", tex->offset_x);
2141 if (tex->offset_y)
2142 fprintf(stderr, "OY:%d ", tex->offset_y);
2143 if (tex->offset_z)
2144 fprintf(stderr, "OZ:%d ", tex->offset_z);
2145
2146 id += 4;
2147 fprintf(stderr, "\n");
2148 }
2149
2150 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2151 int o = 0;
2152 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2153 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2154 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2155
2156 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2157
2158 o += print_indent(o, 50);
2159
2160 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2161 o += print_swizzle(vtx->dst_sel_x);
2162 o += print_swizzle(vtx->dst_sel_y);
2163 o += print_swizzle(vtx->dst_sel_z);
2164 o += print_swizzle(vtx->dst_sel_w);
2165
2166 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2167 o += print_swizzle(vtx->src_sel_x);
2168
2169 if (vtx->offset)
2170 fprintf(stderr, " +%db", vtx->offset);
2171
2172 o += print_indent(o, 55);
2173
2174 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2175
2176 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2177
2178 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2179 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2180
2181 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2182 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2183
2184 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2185 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2186 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2187 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2188 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2189
2190 id += 4;
2191 }
2192 }
2193
2194 fprintf(stderr, "--------------------------------------\n");
2195 }
2196
2197 void r600_vertex_data_type(enum pipe_format pformat,
2198 unsigned *format,
2199 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2200 {
2201 const struct util_format_description *desc;
2202 unsigned i;
2203
2204 *format = 0;
2205 *num_format = 0;
2206 *format_comp = 0;
2207 *endian = ENDIAN_NONE;
2208
2209 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2210 *format = FMT_10_11_11_FLOAT;
2211 *endian = r600_endian_swap(32);
2212 return;
2213 }
2214
2215 desc = util_format_description(pformat);
2216 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2217 goto out_unknown;
2218 }
2219
2220 /* Find the first non-VOID channel. */
2221 for (i = 0; i < 4; i++) {
2222 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2223 break;
2224 }
2225 }
2226
2227 *endian = r600_endian_swap(desc->channel[i].size);
2228
2229 switch (desc->channel[i].type) {
2230 /* Half-floats, floats, ints */
2231 case UTIL_FORMAT_TYPE_FLOAT:
2232 switch (desc->channel[i].size) {
2233 case 16:
2234 switch (desc->nr_channels) {
2235 case 1:
2236 *format = FMT_16_FLOAT;
2237 break;
2238 case 2:
2239 *format = FMT_16_16_FLOAT;
2240 break;
2241 case 3:
2242 case 4:
2243 *format = FMT_16_16_16_16_FLOAT;
2244 break;
2245 }
2246 break;
2247 case 32:
2248 switch (desc->nr_channels) {
2249 case 1:
2250 *format = FMT_32_FLOAT;
2251 break;
2252 case 2:
2253 *format = FMT_32_32_FLOAT;
2254 break;
2255 case 3:
2256 *format = FMT_32_32_32_FLOAT;
2257 break;
2258 case 4:
2259 *format = FMT_32_32_32_32_FLOAT;
2260 break;
2261 }
2262 break;
2263 default:
2264 goto out_unknown;
2265 }
2266 break;
2267 /* Unsigned ints */
2268 case UTIL_FORMAT_TYPE_UNSIGNED:
2269 /* Signed ints */
2270 case UTIL_FORMAT_TYPE_SIGNED:
2271 switch (desc->channel[i].size) {
2272 case 8:
2273 switch (desc->nr_channels) {
2274 case 1:
2275 *format = FMT_8;
2276 break;
2277 case 2:
2278 *format = FMT_8_8;
2279 break;
2280 case 3:
2281 case 4:
2282 *format = FMT_8_8_8_8;
2283 break;
2284 }
2285 break;
2286 case 10:
2287 if (desc->nr_channels != 4)
2288 goto out_unknown;
2289
2290 *format = FMT_2_10_10_10;
2291 break;
2292 case 16:
2293 switch (desc->nr_channels) {
2294 case 1:
2295 *format = FMT_16;
2296 break;
2297 case 2:
2298 *format = FMT_16_16;
2299 break;
2300 case 3:
2301 case 4:
2302 *format = FMT_16_16_16_16;
2303 break;
2304 }
2305 break;
2306 case 32:
2307 switch (desc->nr_channels) {
2308 case 1:
2309 *format = FMT_32;
2310 break;
2311 case 2:
2312 *format = FMT_32_32;
2313 break;
2314 case 3:
2315 *format = FMT_32_32_32;
2316 break;
2317 case 4:
2318 *format = FMT_32_32_32_32;
2319 break;
2320 }
2321 break;
2322 default:
2323 goto out_unknown;
2324 }
2325 break;
2326 default:
2327 goto out_unknown;
2328 }
2329
2330 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2331 *format_comp = 1;
2332 }
2333
2334 *num_format = 0;
2335 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2336 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2337 if (!desc->channel[i].normalized) {
2338 if (desc->channel[i].pure_integer)
2339 *num_format = 1;
2340 else
2341 *num_format = 2;
2342 }
2343 }
2344 return;
2345 out_unknown:
2346 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2347 }
2348
2349 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2350 unsigned count,
2351 const struct pipe_vertex_element *elements)
2352 {
2353 struct r600_context *rctx = (struct r600_context *)ctx;
2354 struct r600_bytecode bc;
2355 struct r600_bytecode_vtx vtx;
2356 const struct util_format_description *desc;
2357 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2358 unsigned format, num_format, format_comp, endian;
2359 uint32_t *bytecode;
2360 int i, j, r, fs_size;
2361 struct r600_fetch_shader *shader;
2362 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2363 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2364
2365 assert(count < 32);
2366
2367 memset(&bc, 0, sizeof(bc));
2368 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2369 rctx->screen->has_compressed_msaa_texturing);
2370
2371 bc.isa = rctx->isa;
2372
2373 for (i = 0; i < count; i++) {
2374 if (elements[i].instance_divisor > 1) {
2375 if (rctx->b.chip_class == CAYMAN) {
2376 for (j = 0; j < 4; j++) {
2377 struct r600_bytecode_alu alu;
2378 memset(&alu, 0, sizeof(alu));
2379 alu.op = ALU_OP2_MULHI_UINT;
2380 alu.src[0].sel = 0;
2381 alu.src[0].chan = 3;
2382 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2383 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2384 alu.dst.sel = i + 1;
2385 alu.dst.chan = j;
2386 alu.dst.write = j == 3;
2387 alu.last = j == 3;
2388 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2389 r600_bytecode_clear(&bc);
2390 return NULL;
2391 }
2392 }
2393 } else {
2394 struct r600_bytecode_alu alu;
2395 memset(&alu, 0, sizeof(alu));
2396 alu.op = ALU_OP2_MULHI_UINT;
2397 alu.src[0].sel = 0;
2398 alu.src[0].chan = 3;
2399 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2400 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2401 alu.dst.sel = i + 1;
2402 alu.dst.chan = 3;
2403 alu.dst.write = 1;
2404 alu.last = 1;
2405 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2406 r600_bytecode_clear(&bc);
2407 return NULL;
2408 }
2409 }
2410 }
2411 }
2412
2413 for (i = 0; i < count; i++) {
2414 r600_vertex_data_type(elements[i].src_format,
2415 &format, &num_format, &format_comp, &endian);
2416
2417 desc = util_format_description(elements[i].src_format);
2418 if (desc == NULL) {
2419 r600_bytecode_clear(&bc);
2420 R600_ERR("unknown format %d\n", elements[i].src_format);
2421 return NULL;
2422 }
2423
2424 if (elements[i].src_offset > 65535) {
2425 r600_bytecode_clear(&bc);
2426 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2427 return NULL;
2428 }
2429
2430 memset(&vtx, 0, sizeof(vtx));
2431 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2432 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2433 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2434 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2435 vtx.mega_fetch_count = 0x1F;
2436 vtx.dst_gpr = i + 1;
2437 vtx.dst_sel_x = desc->swizzle[0];
2438 vtx.dst_sel_y = desc->swizzle[1];
2439 vtx.dst_sel_z = desc->swizzle[2];
2440 vtx.dst_sel_w = desc->swizzle[3];
2441 vtx.data_format = format;
2442 vtx.num_format_all = num_format;
2443 vtx.format_comp_all = format_comp;
2444 vtx.offset = elements[i].src_offset;
2445 vtx.endian = endian;
2446
2447 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2448 r600_bytecode_clear(&bc);
2449 return NULL;
2450 }
2451 }
2452
2453 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2454
2455 if ((r = r600_bytecode_build(&bc))) {
2456 r600_bytecode_clear(&bc);
2457 return NULL;
2458 }
2459
2460 if (rctx->screen->b.debug_flags & DBG_FS) {
2461 fprintf(stderr, "--------------------------------------------------------------\n");
2462 fprintf(stderr, "Vertex elements state:\n");
2463 for (i = 0; i < count; i++) {
2464 fprintf(stderr, " ");
2465 util_dump_vertex_element(stderr, elements+i);
2466 fprintf(stderr, "\n");
2467 }
2468
2469 if (!sb_disasm) {
2470 r600_bytecode_disasm(&bc);
2471
2472 fprintf(stderr, "______________________________________________________________\n");
2473 } else {
2474 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2475 }
2476 }
2477
2478 fs_size = bc.ndw*4;
2479
2480 /* Allocate the CSO. */
2481 shader = CALLOC_STRUCT(r600_fetch_shader);
2482 if (!shader) {
2483 r600_bytecode_clear(&bc);
2484 return NULL;
2485 }
2486
2487 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2488 (struct pipe_resource**)&shader->buffer);
2489 if (!shader->buffer) {
2490 r600_bytecode_clear(&bc);
2491 FREE(shader);
2492 return NULL;
2493 }
2494
2495 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2496 bytecode += shader->offset / 4;
2497
2498 if (R600_BIG_ENDIAN) {
2499 for (i = 0; i < fs_size / 4; ++i) {
2500 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2501 }
2502 } else {
2503 memcpy(bytecode, bc.bytecode, fs_size);
2504 }
2505 rctx->b.ws->buffer_unmap(shader->buffer->cs_buf);
2506
2507 r600_bytecode_clear(&bc);
2508 return shader;
2509 }
2510
2511 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2512 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2513 {
2514 /* WORD0 */
2515 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2516 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2517 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2518 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2519 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2520 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2521 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2522 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2523 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2524 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2525 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2526
2527 /* WORD1 */
2528 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2529 if (alu->bank_swizzle)
2530 alu->bank_swizzle_force = alu->bank_swizzle;
2531 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2532 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2533 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2534 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2535 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2536 {
2537 alu->is_op3 = 1;
2538 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2539 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2540 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2541 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2542 alu->op = r600_isa_alu_by_opcode(bc->isa,
2543 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2544
2545 }
2546 else /*ALU_DWORD1_OP2*/
2547 {
2548 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2549 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2550 alu->op = r600_isa_alu_by_opcode(bc->isa,
2551 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2552 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2553 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2554 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2555 alu->execute_mask =
2556 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2557 }
2558 }
2559
2560 #if 0
2561 void r600_bytecode_export_read(struct r600_bytecode *bc,
2562 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2563 {
2564 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2565 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2566 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2567 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2568
2569 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2570 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2571 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2572 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2573 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2574 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2575 output->op = r600_isa_cf_by_opcode(bc->isa,
2576 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2577 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2578 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2579 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2580 }
2581 #endif